bsp: all Renesas bsp support the nano one-click switch. (#10629)

* bsp: all Renesas bsp support the nano one-click switch.

* fix pr conflicts.
This commit is contained in:
Yuqiang Wang
2025-08-25 10:33:41 +08:00
committed by GitHub
parent 88d0eb0080
commit a9f0d2368c
176 changed files with 1551 additions and 505 deletions
+22 -2
View File
@@ -1,3 +1,4 @@
CONFIG_SOC_R7FA6M5BH=y
#
# RT-Thread Kernel
@@ -210,6 +211,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
# CONFIG_FINSH_USING_WORD_OPERATION is not set
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -387,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
# CONFIG_PKG_USING_ESP_HOSTED is not set
#
# Wi-Fi
@@ -494,6 +497,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QMODBUS is not set
# CONFIG_PKG_USING_PNET is not set
# CONFIG_PKG_USING_OPENER is not set
# CONFIG_PKG_USING_FREEMQTT is not set
# end of IoT - internet of things
#
@@ -721,6 +725,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_RMP is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# end of system packages
#
@@ -844,6 +849,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# HC32 DDL Drivers
#
# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
# end of HC32 DDL Drivers
#
@@ -857,6 +864,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
# end of NXP HAL & SDK Drivers
#
# NUVOTON Drivers
#
# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
# GD32 Drivers
#
# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
# end of GD32 Drivers
# end of HAL & SDK Drivers
#
@@ -1374,7 +1396,6 @@ CONFIG_SOC_SERIES_R7FA6M5=y
#
# Hardware Drivers Config
#
CONFIG_SOC_R7FA6M5BH=y
#
# Onboard Peripheral Drivers
@@ -1395,7 +1416,6 @@ CONFIG_BSP_USING_UART4=y
CONFIG_BSP_UART4_RX_BUFSIZE=256
CONFIG_BSP_UART4_TX_BUFSIZE=0
# CONFIG_BSP_USING_HW_I2C is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_SCI is not set
# CONFIG_BSP_USING_ADC is not set
+11 -1
View File
@@ -11,7 +11,17 @@ PKGS_DIR := packages
ENV_DIR := /
config SOC_R7FA6M5BH
bool
select SOC_SERIES_R7FA6M5
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
source "$(BSP_DIR)/board/Kconfig"
if !RT_USING_NANO
rsource "$(BSP_DIR)/board/Kconfig"
endif
+1 -32
View File
@@ -1,19 +1,12 @@
menu "Hardware Drivers Config"
config SOC_R7FA6M5BH
bool
select SOC_SERIES_R7FA6M5
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
rsource "../../libraries/HAL_Drivers/Kconfig"
rsource "../../libraries/HAL_Drivers/drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
@@ -89,30 +82,6 @@ menu "Hardware Drivers Config"
default n
endif
menuconfig BSP_USING_SOFT_I2C
bool "Enable software I2C bus"
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
default n
if BSP_USING_SOFT_I2C
config BSP_USING_SOFT_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 Bus (software simulation)"
default n
if BSP_USING_I2C1
comment "Please refer to the 'bsp_io.h' file to configure the pins"
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number (hex)"
range 0x0000 0xFFFF
default 0x050C
config BSP_I2C1_SDA_PIN
hex "i2c1 sda pin number (hex)"
range 0x0000 0xFFFF
default 0x050B
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
+10 -2
View File
@@ -1,6 +1,8 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#define SOC_R7FA6M5BH
/* RT-Thread Kernel */
/* klibc options */
@@ -308,6 +310,14 @@
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -392,8 +402,6 @@
/* Hardware Drivers Config */
#define SOC_R7FA6M5BH
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
@@ -10,7 +10,11 @@
#include <rtthread.h>
#include "hal_data.h"
#ifdef RT_USING_NANO
#include <drv_gpio.h>
#else
#include <rtdevice.h>
#endif /* RT_USING_NANO */
#define LED_PIN BSP_IO_PORT_04_PIN_00 /* RED LED pins */
+9 -63
View File
@@ -1,72 +1,18 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
import os
cwd = GetCurrentDir()
group = []
src = ['drv_common.c']
path = [cwd]
# add the general drivers.
src = Split("""
drv_common.c
""")
if GetDepend(['RT_USING_NANO']):
group = group + SConscript(os.path.join(cwd, 'nano', 'SConscript'))
else:
group = group + SConscript(os.path.join(cwd, 'drivers', 'SConscript'))
if GetDepend(['BSP_USING_UART']):
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c']
else:
print("\nThe current project does not support serial-v1\n")
Return('group')
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_ONCHIP_RTC']):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_HW_I2C']):
src += ['drv_i2c.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['BSP_USING_SOFT_SPI']):
src += ['drv_soft_spi.c']
if GetDepend(['BSP_USING_SCI']):
src += ['drv_sci.c']
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['BSP_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['BSP_USING_ONCHIP_FLASH']):
src += ['drv_flash.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['BSP_USING_TIM']):
src += ['drv_hwtimer.c']
if GetDepend(['BSP_USING_ETH']):
src += ['drv_eth.c']
if GetDepend(['BSP_USING_CAN']) or GetDepend('BSP_USING_CANFD'):
src += ['drv_can.c']
if GetDepend(['BSP_USING_SDHI']):
src += ['drv_sdhi.c']
if GetDepend(['BSP_USING_LCD']):
src += ['drv_lcd.c']
path = [cwd]
path += [cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
group = group + DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
@@ -0,0 +1,70 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = []
if GetDepend(['BSP_USING_UART']):
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c']
else:
print("\nThe current project does not support serial-v1\n")
Return('group')
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_ONCHIP_RTC']):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_HW_I2C']):
src += ['drv_i2c.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['BSP_USING_SOFT_SPI']):
src += ['drv_soft_spi.c']
if GetDepend(['BSP_USING_SCI']):
src += ['drv_sci.c']
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['BSP_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['BSP_USING_ONCHIP_FLASH']):
src += ['drv_flash.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['BSP_USING_TIM']):
src += ['drv_hwtimer.c']
if GetDepend(['BSP_USING_ETH']):
src += ['drv_eth.c']
if GetDepend(['BSP_USING_CAN']) or GetDepend('BSP_USING_CANFD'):
src += ['drv_can.c']
if GetDepend(['BSP_USING_SDHI']):
src += ['drv_sdhi.c']
if GetDepend(['BSP_USING_LCD']):
src += ['drv_lcd.c']
path = [cwd]
path += [cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-08-17 CYFS first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
struct rt_adc_dev
{
struct rt_adc_ops ops;
struct rt_adc_device adc_device;
};
struct ra_adc_map
{
const char *device_name;
const adc_cfg_t *g_cfg;
const adc_ctrl_t *g_ctrl;
const adc_channel_cfg_t *g_channel_cfg;
};
#endif
#endif
#ifdef __cplusplus
}
#endif
@@ -0,0 +1,48 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-08-17 CYFS first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_CAN0)
#ifndef CAN0_CONFIG
#define CAN0_CONFIG \
{ \
.name = "can0", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
.p_api_ctrl = &g_can0_ctrl, \
.p_cfg = &g_can0_cfg, \
}
#endif /* CAN0_CONFIG */
#endif /* BSP_USING_CAN0 */
#if defined(BSP_USING_CAN1)
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
.p_api_ctrl = &g_can1_ctrl, \
.p_cfg = &g_can1_cfg, \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-08-17 CYFS first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC
struct ra_dac_map
{
char name;
const struct st_dac_cfg *g_cfg;
const struct st_dac_instance_ctrl *g_ctrl;
};
struct ra_dac_dev
{
rt_dac_device_t ra_dac_device_t;
struct ra_dac_map *ra_dac_map_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif
@@ -0,0 +1,68 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-08-17 CYFS first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
enum
{
#ifdef BSP_USING_PWM0
BSP_PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
BSP_PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
BSP_PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
BSP_PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
BSP_PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
BSP_PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
BSP_PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
BSP_PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
BSP_PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
BSP_PWM9_INDEX,
#endif
BSP_PWMS_NUM
};
#define PWM_DRV_INITIALIZER(num) \
{ \
.name = "pwm"#num , \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */
@@ -0,0 +1,58 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-08-17 CYFS first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.p_api_ctrl = &g_uart0_ctrl, \
.p_cfg = &g_uart0_cfg, \
}
#endif /* UART0_CONFIG */
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.p_api_ctrl = &g_uart1_ctrl, \
.p_cfg = &g_uart1_cfg, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.p_api_ctrl = &g_uart9_ctrl, \
.p_cfg = &g_uart9_cfg, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#ifdef __cplusplus
}
#endif
#endif

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