Merge pull request #3708 from thread-liu/add_stm32mp1_library

[add] STM32MP157A Discovery bsp
2026-03-27 09:32:28 +08:00 · 2020-06-21 14:38:53 +08:00
parent 6bcf52b755 8c44edf8a2
commit a57279956e
258 changed files with 989637 additions and 13 deletions
--- a/.travis.yml
+++ b/.travis.yml
@@ -119,6 +119,7 @@ env:
  - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='stm32/stm32l496-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32mp157a-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
--- a/bsp/stm32/README.md
+++ b/bsp/stm32/README.md
@@ -53,6 +53,8 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32l475-st-discovery](stm32l475-st-discovery) | ST 官方 stm32l475-discovery 开发板 |
 | [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-nucleo 开发板 |
 | [stm32l496-ali-developer](stm32l496-ali-developer) | 诺行 STM32L496 Ali Developer Kit 开发板 |
+| **MP1 系列** |  |
+| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-ST-Discovery Kit 开发板 |

 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

--- a/bsp/stm32/libraries/HAL_Drivers/Kconfig
+++ b/bsp/stm32/libraries/HAL_Drivers/Kconfig
@@ -30,7 +30,7 @@ config BSP_USING_CRC
    select RT_HWCRYPTO_USING_CRC
    # "Crypto device frame dose not support above 8-bits granularity"
    # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
-    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7)
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
    default n 

 config BSP_USING_RNG
@@ -38,7 +38,7 @@ config BSP_USING_RNG
    select RT_USING_HWCRYPTO
    select RT_HWCRYPTO_USING_RNG
    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
-                SOC_SERIES_STM32H7)
+                SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
    default n
    
 config BSP_USING_UDID
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_REQUEST_SPI1_RX
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_REQUEST_SPI4_RX
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA2_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART5_RX_DMA_INSTANCE            DMA2_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_REQUEST_UART5_RX
+#define UART5_RX_DMA_IRQ                 DMA2_Stream0_IRQn
+#endif
+    
+/* DMA2 stream1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI1_TX_DMA_CHANNEL              DMA_REQUEST_SPI1_RX
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_REQUEST_SPI4_TX
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_MC_AHB2ENSETR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_REQUEST_SPI5_RX
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_REQUEST_SPI5_TX
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA2_Stream5_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_TX_DMA_INSTANCE            DMA2_Stream5
+#define UART4_TX_DMA_CHANNEL             DMA_REQUEST_UART4_TX
+#define UART4_TX_DMA_IRQ                 DMA2_Stream5_IRQn    
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA2_Stream6_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_RX_DMA_INSTANCE            DMA2_Stream6
+#define UART4_RX_DMA_CHANNEL             DMA_REQUEST_UART4_RX
+#define UART4_RX_DMA_IRQ                 DMA2_Stream6_IRQn        
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA2_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART5_TX_DMA_INSTANCE            DMA2_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_REQUEST_UART5_TX
+#define UART5_TX_DMA_IRQ                 DMA2_Stream7_IRQn
+#endif
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .request = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .request = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .request = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .request = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .request = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .request = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .request = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .request = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .request = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .request = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .request = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .request = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c
@@ -29,10 +29,14 @@ void rt_hw_systick_init(void)
 {
 #if defined (SOC_SERIES_STM32H7)
    HAL_SYSTICK_Config((HAL_RCCEx_GetD1SysClockFreq()) / RT_TICK_PER_SECOND);
+#elif defined (SOC_SERIES_STM32MP1)
+	HAL_SYSTICK_Config(HAL_RCC_GetSystemCoreClockFreq() / RT_TICK_PER_SECOND);
 #else
    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
 #endif
+#if !defined (SOC_SERIES_STM32MP1)
    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+#endif
    NVIC_SetPriority(SysTick_IRQn, 0xFF);
 }

--- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h
@@ -104,6 +104,9 @@ extern "C" {
 #include "h7/sdio_config.h"
 #include "h7/pwm_config.h"
 #include "h7/usbd_config.h"
+#elif  defined(SOC_SERIES_STM32MP1)
+#include "mp1/dma_config.h"
+#include "mp1/uart_config.h"
 #endif

 #ifdef __cplusplus
--- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
@@ -22,7 +22,7 @@ extern "C" {
 	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
-	|| defined(SOC_SERIES_STM32H7)
+	|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */

@@ -36,7 +36,7 @@ struct dma_config {
 #endif

 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
-    || defined(SOC_SERIES_STM32H7)
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
    rt_uint32_t request;
 #endif
 };
--- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
@@ -7,6 +7,7 @@
 * Date           Author            Notes
 * 2018-11-06     balanceTWK        first version
 * 2019-04-23     WillianChan       Fix GPIO serial number disorder
+ * 2020-06-16     thread-liu        add STM32MP1
 */

 #include <board.h>
@@ -235,6 +236,23 @@ static const struct pin_irq_map pin_irq_map[] =
    {GPIO_PIN_13, EXTI4_15_IRQn},
    {GPIO_PIN_14, EXTI4_15_IRQn},
    {GPIO_PIN_15, EXTI4_15_IRQn}, 
+#elif defined(SOC_SERIES_STM32MP1)
+    {GPIO_PIN_0, EXTI0_IRQn},
+    {GPIO_PIN_1, EXTI1_IRQn},
+    {GPIO_PIN_2, EXTI2_IRQn},
+    {GPIO_PIN_3, EXTI3_IRQn},
+    {GPIO_PIN_4, EXTI4_IRQn},
+    {GPIO_PIN_5, EXTI5_IRQn},
+    {GPIO_PIN_6, EXTI6_IRQn},
+    {GPIO_PIN_7, EXTI7_IRQn},
+    {GPIO_PIN_8, EXTI8_IRQn},
+    {GPIO_PIN_9, EXTI9_IRQn},
+    {GPIO_PIN_10, EXTI10_IRQn},
+    {GPIO_PIN_11, EXTI11_IRQn},
+    {GPIO_PIN_12, EXTI12_IRQn},
+    {GPIO_PIN_13, EXTI13_IRQn},
+    {GPIO_PIN_14, EXTI14_IRQn},
+    {GPIO_PIN_15, EXTI15_IRQn}, 
 #else
    {GPIO_PIN_0, EXTI0_IRQn},
    {GPIO_PIN_1, EXTI1_IRQn},
@@ -619,7 +637,7 @@ rt_inline void pin_irq_hdr(int irqno)
    }
 }

-#if defined(SOC_SERIES_STM32G0)
+#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1)
 void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
 {
    pin_irq_hdr(bit2bitno(GPIO_Pin));
@@ -670,6 +688,103 @@ void EXTI4_15_IRQHandler(void)
    rt_interrupt_leave();
 }

+#elif defined(SOC_STM32MP157A)
+void EXTI0_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+   rt_interrupt_leave();
+}
+
+void EXTI1_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
+   rt_interrupt_leave();
+}
+
+void EXTI2_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+   rt_interrupt_leave();
+}
+
+void EXTI3_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+   rt_interrupt_leave();
+}
+
+void EXTI4_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
+   rt_interrupt_leave();
+}
+
+void EXTI5_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
+   rt_interrupt_leave();
+}
+
+void EXTI6_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
+   rt_interrupt_leave();
+}
+
+void EXTI7_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
+   rt_interrupt_leave();
+}
+
+void EXTI8_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+   rt_interrupt_leave();
+}
+
+void EXTI9_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
+   rt_interrupt_leave();
+}
+
+void EXTI10_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+   rt_interrupt_leave();
+}
+
+void EXTI11_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+   rt_interrupt_leave();
+}
+
+void EXTI12_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+   rt_interrupt_leave();
+}
+
+void EXTI13_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+   rt_interrupt_leave();
+}
+
+void EXTI14_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+   rt_interrupt_leave();
+}
+
+void EXTI15_IRQHandler(void) {
+   rt_interrupt_enter(); 
+   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+   rt_interrupt_leave();
+}
+
 #else

 void EXTI0_IRQHandler(void)
--- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
@@ -6,6 +6,7 @@
 * Change Logs:
 * Date           Author            Notes
 * 2018-11-06     balanceTWK        first version
+ * 2020-06-16     thread-liu        add stm32mp1 
 */

 #ifndef __DRV_GPIO_H__
@@ -16,7 +17,11 @@

 #define __STM32_PORT(port)  GPIO##port##_BASE

+#if defined(SOC_SERIES_STM32MP1)
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN)
+#else
 #define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+#endif

 #define __STM32_PIN(index, gpio, gpio_index)                                \
    {                                                                       \
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
@@ -243,7 +243,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
    UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
-    || defined(SOC_SERIES_STM32G4)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
    uart->handle.Instance->TDR = c;
 #else
    uart->handle.Instance->DR = c;
@@ -264,7 +264,7 @@ static int stm32_getc(struct rt_serial_device *serial)
    {
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
-    || defined(SOC_SERIES_STM32G4)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
        ch = uart->handle.Instance->RDR & 0xff;
 #else
        ch = uart->handle.Instance->DR & 0xff;
@@ -367,7 +367,7 @@ static void uart_isr(struct rt_serial_device *serial)
        }
 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
    && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
-    && !defined(SOC_SERIES_STM32G4)
+    && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1)
        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
        {
            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
@@ -873,7 +873,10 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)

 #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
        /* enable DMAMUX clock for L4+ and G4 */
-        __HAL_RCC_DMAMUX1_CLK_ENABLE();
+        __HAL_RCC_DMAMUX1_CLK_ENABLE();   
+#elif defined(SOC_SERIES_STM32MP1)
+    __HAL_RCC_DMAMUX_CLK_ENABLE();
+    __HAL_RCC_DMA2_CLK_ENABLE();
 #endif

 #endif
@@ -895,7 +898,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
    DMA_Handle->Instance                 = dma_config->Instance;
    DMA_Handle->Init.Channel             = dma_config->channel;
 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
-    || defined(SOC_SERIES_STM32H7)
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
    DMA_Handle->Instance                 = dma_config->Instance;
    DMA_Handle->Init.Request             = dma_config->request;
 #endif
@@ -916,7 +919,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
    }

    DMA_Handle->Init.Priority            = DMA_PRIORITY_MEDIUM;
-#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
    DMA_Handle->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
 #endif
    if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h
@@ -23,7 +23,8 @@ int rt_hw_usart_init(void);
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) \
    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
-#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7)
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */

@@ -31,7 +32,8 @@ int rt_hw_usart_init(void);
    || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
    || defined(SOC_SERIES_STM32G4)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
-#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7)
+#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
+    || defined(SOC_SERIES_STM32MP1)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_IT
 #endif

--- a/bsp/stm32/libraries/Kconfig
+++ b/bsp/stm32/libraries/Kconfig
@@ -55,3 +55,8 @@ config SOC_SERIES_STM32H7
    bool
    select ARCH_ARM_CORTEX_M7
    select SOC_FAMILY_STM32
+
+config SOC_SERIES_STM32MP1
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_STM32
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h
@@ -0,0 +1,228 @@
+/**
+  ******************************************************************************
+  * @file    stm32mp1xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32MP1xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32MP1xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx
+  * @{
+  */
+
+#ifndef __STM32MP1xx_H
+#define __STM32MP1xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target STM32MP1 device used in your
+   application
+  */
+
+#if !defined (STM32MP1)
+#define STM32MP1
+#endif /* STM32MP1 */
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32MP1xx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32MP1xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32MP1xx_CMSIS_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(CORE_CM4)
+#if defined(STM32MP15xx)  /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+  #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Axx)
+  #include "stm32mp157axx_cm4.h"
+#elif defined(STM32MP157Cxx)
+  #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Dxx)
+  #include "stm32mp157dxx_cm4.h"
+#elif defined(STM32MP157Fxx)
+  #include "stm32mp157fxx_cm4.h"
+#elif defined(STM32MP153Axx)
+  #include "stm32mp153axx_cm4.h"
+#elif defined(STM32MP153Cxx)
+  #include "stm32mp153cxx_cm4.h"
+#elif defined(STM32MP153Dxx)
+  #include "stm32mp153dxx_cm4.h"
+#elif defined(STM32MP153Fxx)
+  #include "stm32mp153fxx_cm4.h"
+#elif defined(STM32MP151Axx)
+  #include "stm32mp151axx_cm4.h"
+#elif defined(STM32MP151Cxx)
+  #include "stm32mp151cxx_cm4.h"
+#elif defined(STM32MP151Dxx)
+  #include "stm32mp151dxx_cm4.h"
+#elif defined(STM32MP151Fxx)
+  #include "stm32mp151fxx_cm4.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+#if defined(CORE_CA7)
+#if defined(STM32MP15xx)  /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+  #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Axx)
+  #include "stm32mp157axx_ca7.h"
+#elif defined(STM32MP157Cxx)
+  #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Dxx)
+  #include "stm32mp157dxx_ca7.h"
+#elif defined(STM32MP157Fxx)
+  #include "stm32mp157fxx_ca7.h"
+#elif defined(STM32MP153Axx)
+  #include "stm32mp153axx_ca7.h"
+#elif defined(STM32MP153Cxx)
+  #include "stm32mp153cxx_ca7.h"
+#elif defined(STM32MP153Dxx)
+  #include "stm32mp153dxx_ca7.h"
+#elif defined(STM32MP153Fxx)
+  #include "stm32mp153fxx_ca7.h"
+#elif defined(STM32MP151Axx)
+  #include "stm32mp151axx_ca7.h"
+#elif defined(STM32MP151Cxx)
+  #include "stm32mp151cxx_ca7.h"
+#elif defined(STM32MP151Dxx)
+  #include "stm32mp151dxx_ca7.h"
+#elif defined(STM32MP151Fxx)
+  #include "stm32mp151fxx_ca7.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32mp1xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32MP1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h
@@ -0,0 +1,106 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32mp1xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32MP1XX_H
+#define __SYSTEM_STM32MP1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup STM32MP1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32MP1xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Core1 Clock Frequency  */
+extern uint32_t SystemCore1Clock;         /*!< System Core1 Clock Frequency  */
+extern uint32_t SystemCore2Clock;         /*!< System Core2 Clock Frequency  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32MP1XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html
@@ -0,0 +1,206 @@
+<!DOCTYPE html>
+<html><head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><title>Release Notes for STM32MP1xx CMSIS</title>
+
+<style>
+div.Section1 {
+page: Section1;
+font-family: Arial,Helvetica,sans-serif;
+}
+h1 {
+font-size: 24pt;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+text-align: center;
+color: #3366ff;
+}
+h2 {
+margin: 12pt 0in 3pt;
+page-break-after: avoid;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+background-color: #3366ff;
+color: white;
+padding-left: 5px;
+font-size: 16pt;
+}
+h3 {
+margin-left: 0in;
+font-weight: bold;
+font-family: Arial,Helvetica,sans-serif;
+background-color: #3366ff;
+width: 200px;
+margin-right: 500pt;
+color: white;
+padding-left: 5px;
+padding-top: 2px;
+padding-bottom: 2px;
+font-size: 12pt;
+}
+h4 {
+font-family: Arial,Helvetica,sans-serif;
+font-weight: bold;
+text-decoration: underline;
+font-size: 12pt;
+}
+p {
+margin: 0px 0px 0px 0in;
+font-family: Arial,Helvetica,sans-serif;
+padding-top: 3px;
+padding-bottom: 3px;
+font-size: 12pt;
+}
+ul {
+font-family: Arial,Helvetica,sans-serif;
+margin-top: 3px;
+margin-bottom: 3px;
+font-size: 10pt;
+}
+caption {
+margin-top: 10px;
+font-family: Arial,Helvetica,sans-serif;
+font-size: 11pt;
+}
+hr {
+width: 100%;
+}
+.guidance {
+background-color: #e5b8b7;
+font-style: italic;
+font-family: Arial,Helvetica,sans-serif;
+padding-top: 3px;
+padding-bottom: 3px;
+margin-top: 3px;
+margin-bottom: 3px;
+font-size: 10pt;
+}
+.guidance_title {
+font-style: normal;
+font-weight: bold;
+text-decoration: underline;
+font-family: Arial,Helvetica,sans-serif;
+font-size: 10pt;
+}
+.tickets {
+border: 1pt solid #9cc2e5;
+font-family: Arial,Helvetica,sans-serif;
+margin-bottom: 3px;
+margin-top: 3px;
+font-size: 10pt;
+}
+.tickets th {
+border: 1pt solid #9cc2e5;
+font-size: 12pt;
+background-color: #39a9dc;
+color: white;
+text-align: center;
+}
+.tickets td {
+border: 1pt solid #9cc2e5;
+min-height: 32px;
+}
+tr:nth-child(even) {background-color: #cee2f2;}
+tr:nth-child(even) {background-color: #e8f1f9;}
+.topic1 {
+margin-top: 3px;
+margin-bottom: 3px;
+margin-left: 40px;
+}
+.topic2 {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+.topic3 {
+margin-top: 3px;
+margin-bottom: 3px;
+margin-left: 20px;
+}
+#purpose {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+#identification {
+margin-top: 3px;
+margin-bottom: 3px;
+}
+</style></head>
+<body link="blue" vlink="blue">
+<script type="text/javascript">
+var toggle_hist_disp = true;
+function toggle_history()
+{
+if (toggle_hist_disp)
+{
+toggle_hist_disp = false;
+var filter_off_text = document.createTextNode("Hide History");
+document.getElementById('filter_hist').innerHTML = "";
+document.getElementById('filter_hist').appendChild(filter_off_text);
+document.getElementById("history").hidden = false;
+}
+else
+{
+toggle_hist_disp = true;
+var filter_on_text = document.createTextNode("Show History");
+document.getElementById('filter_hist').innerHTML = "";
+document.getElementById('filter_hist').appendChild(filter_on_text);
+document.getElementById("history").hidden = true;
+}
+}</script><a href="../../../../../Release_Notes.html">Back to Release page</a>
+<div style="width: 1034px;" class="Section1">
+<div id="header">
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for<o:p></o:p> STM32MP1xx CMSIS Device</span></h1>
+<p style="text-align: center;">Copyright 2019
+STMicroelectronics</p>
+<p style="text-align: center;"><img style="width: 104px; height: 77px;" id="st_logo" alt="&lt;ST logo&gt; image" src="../../../../../_htmresc/st_logo.png"></p>
+</div>
+<div id="license" class="topic1">
+<h2>License</h2>
+<p>This software component is licensed by ST under BSD 3-Clause
+license, the "License"; You may not use this component except in
+compliance with the License. You may obtain a copy of the License at:</p>
+<p style="text-align: center; color: white;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank">https://opensource.org/licenses/BSD-3-Clause</a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a></p>
+</div>
+<div id="release_container" class="topic1">
+<div class="topic2" id="identification">
+<h3 style="width: 230px;">V1.2.0 / 03-Feb-2020</h3>
+</div>
+<div style="margin-left: 20px; width: 974px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>Header files:&nbsp;</li><ul><li>Add new Part Number for 800MHz</li><li>Update license with BSD 3-Clause template</li><li>Rework CMSIS for RTC/TAMP, GPIO and TIM</li><li>Rename TIM Break source bit definition</li></ul></ul><ul><li>Update Linker Template&nbsp;file for KEIL and IAR:</li><ul><li>Add OpenAMP region ( region present by default, to comment if needed )</li></ul></ul><br>
+</div>
+<div class="topic3" id="contents">
+<h4>Contents</h4>
+<ul>
+<li>CMSIS devices files for:</li><ul><li>STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">151D</span>xx ,STM32MP<span style="font-weight: bold;">151F</span>xx</li><li>STM32MP<span style="font-weight: bold;">153C</span>xx ,STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">153D</span>xx ,STM32MP<span style="font-weight: bold;">153F</span>xx</li><li>STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx, STM32MP<span style="font-weight: bold;">157D</span>xx ,STM32MP<span style="font-weight: bold;">157F</span>xx</li></ul></ul><ul>
+</ul>
+</div>
+</div>
+<div style="margin-left: 40px;"><button id="filter_hist" onclick="toggle_history()">Show
+History</button><br>
+</div>
+<div id="history" class="topic1" hidden="">
+<h2>Update History</h2>
+<br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-Sept-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>Header files:&nbsp;</li><ul><li>Update FMC bit definition</li><li>Update ETH&nbsp;bit definition</li><li>update EXTI_EXTICR&nbsp;bit definition</li><li>Update I2C&nbsp;bit definition</li><li>Update SPI&nbsp;bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, SPI_I2SCFGR)&nbsp;</li><li>TMPSENS IP renamed DTS</li><li>Update FDCAN TXBC&nbsp;bit definition</li><li>Update DAC_DHR8RD&nbsp;bit definition</li><li>Add CRYP in STM32MP151Cx and STM32MP153Cx</li><li>Update TIM / LPTIM&nbsp;bit definition + add missing macros</li></ul><li>Update system_stm32mp1xx.c</li><ul><li>Update SystemCoreClock</li></ul><li>Update startup file for KEIL and IAR</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Contents</h4>
+<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
+<br>
+</div><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 22-January-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>First official release for <span style="font-weight: bold;">STM32MP15xx</span> devices<br>
+</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Contents</h4>
+<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
+<br>
+</div><br><br>
+</div>
+<div id="product_doc" class="topic1">
+<hr>
+<p style="text-align: center;">For complete
+documentation on&nbsp;<span style="background-color: white;">STM32
+Microcontrollers</span>, visit: <span style="background-color: white;"><a href="http://www.st.com/STM32" target="_blank">www.st.com/STM32</a></span></p>
+</div>
+</div>
+</body></html>
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/linker/stm32mp15xx_m4.sct
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/linker/stm32mp15xx_m4.sct
@@ -0,0 +1,27 @@
+; *************************************************************
+; *** Scatter-Loading Description                           ***
+; *************************************************************
+
+LR_VECTORS 0x00000000 0x00000400  {    ; load region size_region
+  .isr_vector +0 {
+    startup*.o (RESET, +First)
+  }
+}
+
+LR_IROM1 0x10000000 0x00020000  {      ; load region size_region
+  ER_IROM1 0x10000000 0x00020000  {    ; load address = execution address
+    *(InRoot$$Sections)
+    .ANY (+RO)
+    .ANY (+XO)
+  }
+  RW_IRAM1 0x10020000 0x00020000  {    ; RW data
+    .ANY (+RW +ZI)
+  }
+
+; *****   Create region for OPENAMP                               *****
+; ***     These 4 lines can be commented if OPENAMP is not used     ***
+  .resource_table +0 ALIGN 4 {         ; resource table
+    *(.resource_table)
+  }
+  __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
+}
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s
@@ -0,0 +1,439 @@
+;******************************************************************************
+;* File Name          : startup_stm32mp15xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32MP15xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;****************************************************************************** 
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD     WWDG1_IRQHandler                     ;
+                DCD     PVD_AVD_IRQHandler                   ;
+                DCD     TAMP_IRQHandler                      ;
+                DCD     RTC_WKUP_ALARM_IRQHandler            ;
+                DCD     RESERVED4_IRQHandler                 ;
+                DCD     RCC_IRQHandler                       ;
+                DCD     EXTI0_IRQHandler                     ;
+                DCD     EXTI1_IRQHandler                     ;
+                DCD     EXTI2_IRQHandler                     ;
+                DCD     EXTI3_IRQHandler                     ;
+                DCD     EXTI4_IRQHandler                     ;
+                DCD     DMA1_Stream0_IRQHandler              ;
+                DCD     DMA1_Stream1_IRQHandler              ;
+                DCD     DMA1_Stream2_IRQHandler              ;
+                DCD     DMA1_Stream3_IRQHandler              ;
+                DCD     DMA1_Stream4_IRQHandler              ;
+                DCD     DMA1_Stream5_IRQHandler              ;
+                DCD     DMA1_Stream6_IRQHandler              ;
+                DCD     ADC1_IRQHandler                      ;
+                DCD     FDCAN1_IT0_IRQHandler                ;
+                DCD     FDCAN2_IT0_IRQHandler                ;
+                DCD     FDCAN1_IT1_IRQHandler                ;
+                DCD     FDCAN2_IT1_IRQHandler                ;
+                DCD     EXTI5_IRQHandler                     ;
+                DCD     TIM1_BRK_IRQHandler                  ;
+                DCD     TIM1_UP_IRQHandler                   ;
+                DCD     TIM1_TRG_COM_IRQHandler              ;
+                DCD     TIM1_CC_IRQHandler                   ;
+                DCD     TIM2_IRQHandler                      ;
+                DCD     TIM3_IRQHandler                      ;
+                DCD     TIM4_IRQHandler                      ;
+                DCD     I2C1_EV_IRQHandler                   ;
+                DCD     I2C1_ER_IRQHandler                   ;
+                DCD     I2C2_EV_IRQHandler                   ;
+                DCD     I2C2_ER_IRQHandler                   ;
+                DCD     SPI1_IRQHandler                      ;
+                DCD     SPI2_IRQHandler                      ;
+                DCD     USART1_IRQHandler                    ;
+                DCD     USART2_IRQHandler                    ;
+                DCD     USART3_IRQHandler                    ;
+                DCD     EXTI10_IRQHandler                    ;
+                DCD     RTC_TIMESTAMP_IRQHandler             ;
+                DCD     EXTI11_IRQHandler                    ;
+                DCD     TIM8_BRK_IRQHandler                  ;
+                DCD     TIM8_UP_IRQHandler                   ;
+                DCD     TIM8_TRG_COM_IRQHandler              ;
+                DCD     TIM8_CC_IRQHandler                   ;
+                DCD     DMA1_Stream7_IRQHandler              ;
+                DCD     FMC_IRQHandler                       ;
+                DCD     SDMMC1_IRQHandler                    ;
+                DCD     TIM5_IRQHandler                      ;
+                DCD     SPI3_IRQHandler                      ;
+                DCD     UART4_IRQHandler                     ;
+                DCD     UART5_IRQHandler                     ;
+                DCD     TIM6_IRQHandler                      ;
+                DCD     TIM7_IRQHandler                      ;
+                DCD     DMA2_Stream0_IRQHandler              ;
+                DCD     DMA2_Stream1_IRQHandler              ;
+                DCD     DMA2_Stream2_IRQHandler              ;
+                DCD     DMA2_Stream3_IRQHandler              ;
+                DCD     DMA2_Stream4_IRQHandler              ;
+                DCD     ETH1_IRQHandler                      ;
+                DCD     ETH1_WKUP_IRQHandler                 ;
+                DCD     FDCAN_CAL_IRQHandler                 ;
+                DCD     EXTI6_IRQHandler                     ;
+                DCD     EXTI7_IRQHandler                     ;
+                DCD     EXTI8_IRQHandler                     ;
+                DCD     EXTI9_IRQHandler                     ;
+                DCD     DMA2_Stream5_IRQHandler              ;
+                DCD     DMA2_Stream6_IRQHandler              ;
+                DCD     DMA2_Stream7_IRQHandler              ;
+                DCD     USART6_IRQHandler                    ;
+                DCD     I2C3_EV_IRQHandler                   ;
+                DCD     I2C3_ER_IRQHandler                   ;
+                DCD     USBH_OHCI_IRQHandler                 ;
+                DCD     USBH_EHCI_IRQHandler                 ;
+                DCD     EXTI12_IRQHandler                    ;
+                DCD     EXTI13_IRQHandler                    ;
+                DCD     DCMI_IRQHandler                      ;
+                DCD     CRYP1_IRQHandler                     ;
+                DCD     HASH1_IRQHandler                     ;
+                DCD     FPU_IRQHandler                       ;
+                DCD     UART7_IRQHandler                     ;
+                DCD     UART8_IRQHandler                     ;
+                DCD     SPI4_IRQHandler                      ;
+                DCD     SPI5_IRQHandler                      ;
+                DCD     SPI6_IRQHandler                      ;
+                DCD     SAI1_IRQHandler                      ;
+                DCD     LTDC_IRQHandler                      ;
+                DCD     LTDC_ER_IRQHandler                   ;
+                DCD     ADC2_IRQHandler                      ;
+                DCD     SAI2_IRQHandler                      ;
+                DCD     QUADSPI_IRQHandler                   ;
+                DCD     LPTIM1_IRQHandler                    ;
+                DCD     CEC_IRQHandler                       ;
+                DCD     I2C4_EV_IRQHandler                   ;
+                DCD     I2C4_ER_IRQHandler                   ;
+                DCD     SPDIF_RX_IRQHandler                  ;
+                DCD     OTG_IRQHandler                       ;
+                DCD     RESERVED99_IRQHandler                ;
+                DCD     IPCC_RX0_IRQHandler                  ;
+                DCD     IPCC_TX0_IRQHandler                  ;
+                DCD     DMAMUX1_OVR_IRQHandler               ;
+                DCD     IPCC_RX1_IRQHandler                  ;
+                DCD     IPCC_TX1_IRQHandler                  ;
+                DCD     CRYP2_IRQHandler                     ;
+                DCD     HASH2_IRQHandler                     ;
+                DCD     I2C5_EV_IRQHandler                   ;
+                DCD     I2C5_ER_IRQHandler                   ;
+                DCD     GPU_IRQHandler                       ;
+                DCD     DFSDM1_FLT0_IRQHandler               ;
+                DCD     DFSDM1_FLT1_IRQHandler               ;
+                DCD     DFSDM1_FLT2_IRQHandler               ;
+                DCD     DFSDM1_FLT3_IRQHandler               ;
+                DCD     SAI3_IRQHandler                      ;
+                DCD     DFSDM1_FLT4_IRQHandler               ;
+                DCD     TIM15_IRQHandler                     ;
+                DCD     TIM16_IRQHandler                     ;
+                DCD     TIM17_IRQHandler                     ;
+                DCD     TIM12_IRQHandler                     ;
+                DCD     MDIOS_IRQHandler                     ;
+                DCD     EXTI14_IRQHandler                    ;
+                DCD     MDMA_IRQHandler                      ;
+                DCD     DSI_IRQHandler                       ;
+                DCD     SDMMC2_IRQHandler                    ;
+                DCD     HSEM_IT2_IRQHandler                  ;
+                DCD     DFSDM1_FLT5_IRQHandler               ;
+                DCD     EXTI15_IRQHandler                    ;
+                DCD     nCTIIRQ1_IRQHandler                  ;
+                DCD     nCTIIRQ2_IRQHandler                  ;
+                DCD     TIM13_IRQHandler                     ;
+                DCD     TIM14_IRQHandler                     ;
+                DCD     DAC_IRQHandler                       ;
+                DCD     RNG1_IRQHandler                      ;
+                DCD     RNG2_IRQHandler                      ;
+                DCD     I2C6_EV_IRQHandler                   ; 
+                DCD     I2C6_ER_IRQHandler                   ;
+                DCD     SDMMC3_IRQHandler                    ;
+                DCD     LPTIM2_IRQHandler                    ;
+                DCD     LPTIM3_IRQHandler                    ;
+                DCD     LPTIM4_IRQHandler                    ;
+                DCD     LPTIM5_IRQHandler                    ;
+                DCD     ETH1_LPI_IRQHandler                  ;
+                DCD     RESERVED143_IRQHandler               ;
+                DCD     MPU_SEV_IRQHandler                   ;
+                DCD     RCC_WAKEUP_IRQHandler                ;
+                DCD     SAI4_IRQHandler                      ;
+                DCD     DTS_IRQHandler                       ;
+                DCD     RESERVED148_IRQHandler               ;
+                DCD     WAKEUP_PIN_IRQHandler                ;
+
+                SPACE    (73 * 4)                            ; Interrupts 151 .. 224 are left out
+__Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
+
+
+                AREA     |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
+                ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
+                ENDP
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  WWDG1_IRQHandler                  ; Window WatchDog 1
+                Set_Default_Handler  PVD_AVD_IRQHandler                ; PVD and AVD through EXTI Line detection                   
+                Set_Default_Handler  TAMP_IRQHandler                   ; Tamper and TimeStamps through the EXTI line
+                Set_Default_Handler  RTC_WKUP_ALARM_IRQHandler         ; RTC Wakeup and Alarm through the EXTI line
+                Set_Default_Handler  RESERVED4_IRQHandler              ; Reserved
+                Set_Default_Handler  RCC_IRQHandler                    ; RCC                                             
+                Set_Default_Handler  EXTI0_IRQHandler                  ; EXTI Line0                                             
+                Set_Default_Handler  EXTI1_IRQHandler                  ; EXTI Line1                                             
+                Set_Default_Handler  EXTI2_IRQHandler                  ; EXTI Line2                                             
+                Set_Default_Handler  EXTI3_IRQHandler                  ; EXTI Line3                                             
+                Set_Default_Handler  EXTI4_IRQHandler                  ; EXTI Line4               
+                Set_Default_Handler  DMA1_Stream0_IRQHandler           ; DMA1 Stream 0              
+                Set_Default_Handler  DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                                 
+                Set_Default_Handler  DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                                 
+                Set_Default_Handler  DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                                 
+                Set_Default_Handler  DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                                 
+                Set_Default_Handler  DMA1_Stream5_IRQHandler           ; DMA1 Stream 5              
+                Set_Default_Handler  DMA1_Stream6_IRQHandler           ; DMA1 Stream 6               
+                Set_Default_Handler  ADC1_IRQHandler                   ; ADC1                                          
+                Set_Default_Handler  FDCAN1_IT0_IRQHandler             ; FDCAN1 Interrupt line 0              
+                Set_Default_Handler  FDCAN2_IT0_IRQHandler             ; FDCAN2 Interrupt line 0
+                Set_Default_Handler  FDCAN1_IT1_IRQHandler             ; FDCAN1 Interrupt line 1
+                Set_Default_Handler  FDCAN2_IT1_IRQHandler             ; FDCAN2 Interrupt line 1
+                Set_Default_Handler  EXTI5_IRQHandler                  ; External Line5 interrupts through AIEC
+                Set_Default_Handler  TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                Set_Default_Handler  TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                Set_Default_Handler  TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                Set_Default_Handler  TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                Set_Default_Handler  TIM2_IRQHandler                   ; TIM2                                            
+                Set_Default_Handler  TIM3_IRQHandler                   ; TIM3                                            
+                Set_Default_Handler  TIM4_IRQHandler                   ; TIM4                                            
+                Set_Default_Handler  I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                Set_Default_Handler  I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                Set_Default_Handler  I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                Set_Default_Handler  I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                Set_Default_Handler  SPI1_IRQHandler                   ; SPI1                                            
+                Set_Default_Handler  SPI2_IRQHandler                   ; SPI2                                            
+                Set_Default_Handler  USART1_IRQHandler                 ; USART1                                          
+                Set_Default_Handler  USART2_IRQHandler                 ; USART2                                          
+                Set_Default_Handler  USART3_IRQHandler                 ; USART3                                          
+                Set_Default_Handler  EXTI10_IRQHandler                 ; External Line10 interrupts through AIEC
+                Set_Default_Handler  RTC_TIMESTAMP_IRQHandler          ; RTC TimeStamp through EXTI Line
+                Set_Default_Handler  EXTI11_IRQHandler                 ; External Line11 interrupts through AIEC
+                Set_Default_Handler  TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                Set_Default_Handler  TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                Set_Default_Handler  TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                Set_Default_Handler  TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                Set_Default_Handler  DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                Set_Default_Handler  FMC_IRQHandler                    ; FMC                             
+                Set_Default_Handler  SDMMC1_IRQHandler                 ; SDMMC1
+                Set_Default_Handler  TIM5_IRQHandler                   ; TIM5                            
+                Set_Default_Handler  SPI3_IRQHandler                   ; SPI3                            
+                Set_Default_Handler  UART4_IRQHandler                  ; UART4                           
+                Set_Default_Handler  UART5_IRQHandler                  ; UART5                           
+                Set_Default_Handler  TIM6_IRQHandler                   ; TIM6
+                Set_Default_Handler  TIM7_IRQHandler                   ; TIM7           
+                Set_Default_Handler  DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                   
+                Set_Default_Handler  DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                   
+                Set_Default_Handler  DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                   
+                Set_Default_Handler  DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                   
+                Set_Default_Handler  DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                   
+                Set_Default_Handler  ETH1_IRQHandler                   ; Ethernet                        
+                Set_Default_Handler  ETH1_WKUP_IRQHandler              ; Ethernet Wakeup through EXTI line              
+                Set_Default_Handler  FDCAN_CAL_IRQHandler              ; FDCAN Calibration
+                Set_Default_Handler  EXTI6_IRQHandler                  ; EXTI Line6 interrupts through AIEC
+                Set_Default_Handler  EXTI7_IRQHandler                  ; EXTI Line7 interrupts through AIEC
+                Set_Default_Handler  EXTI8_IRQHandler                  ; EXTI Line8 interrupts through AIEC
+                Set_Default_Handler  EXTI9_IRQHandler                  ; EXTI Line9 interrupts through AIEC
+                Set_Default_Handler  DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                   
+                Set_Default_Handler  DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                   
+                Set_Default_Handler  DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                   
+                Set_Default_Handler  USART6_IRQHandler                 ; USART6                           
+                Set_Default_Handler  I2C3_EV_IRQHandler                ; I2C3 event                             
+                Set_Default_Handler  I2C3_ER_IRQHandler                ; I2C3 error                             
+                Set_Default_Handler  USBH_OHCI_IRQHandler              ; USB Host OHCI
+                Set_Default_Handler  USBH_EHCI_IRQHandler              ; USB Host EHCI
+                Set_Default_Handler  EXTI12_IRQHandler                 ; EXTI Line12 interrupts through AIEC
+                Set_Default_Handler  EXTI13_IRQHandler                 ; EXTI Line13 interrupts through AIEC
+                Set_Default_Handler  DCMI_IRQHandler                   ; DCMI                            
+                Set_Default_Handler  CRYP1_IRQHandler                  ; Crypto1 global interrupt
+                Set_Default_Handler  HASH1_IRQHandler                  ; Crypto Hash1 interrupt
+                Set_Default_Handler  FPU_IRQHandler                    ; FPU
+                Set_Default_Handler  UART7_IRQHandler                  ; UART7
+                Set_Default_Handler  UART8_IRQHandler                  ; UART8
+                Set_Default_Handler  SPI4_IRQHandler                   ; SPI4
+                Set_Default_Handler  SPI5_IRQHandler                   ; SPI5
+                Set_Default_Handler  SPI6_IRQHandler                   ; SPI6
+                Set_Default_Handler  SAI1_IRQHandler                   ; SAI1
+                Set_Default_Handler  LTDC_IRQHandler                   ; LTDC
+                Set_Default_Handler  LTDC_ER_IRQHandler                ; LTDC error
+                Set_Default_Handler  ADC2_IRQHandler                   ; ADC2
+                Set_Default_Handler  SAI2_IRQHandler                   ; SAI2
+                Set_Default_Handler  QUADSPI_IRQHandler                ; QUADSPI
+                Set_Default_Handler  LPTIM1_IRQHandler                 ; LPTIM1 global interrupt
+                Set_Default_Handler  CEC_IRQHandler                    ; HDMI_CEC
+                Set_Default_Handler  I2C4_EV_IRQHandler                ; I2C4 Event                             
+                Set_Default_Handler  I2C4_ER_IRQHandler                ; I2C4 Error 
+                Set_Default_Handler  SPDIF_RX_IRQHandler               ; SPDIF_RX
+                Set_Default_Handler  OTG_IRQHandler                    ; USB On The Go HS global interrupt
+                Set_Default_Handler  RESERVED99_IRQHandler             ; Reserved
+                Set_Default_Handler  IPCC_RX0_IRQHandler               ; Mailbox RX0 Free interrupt
+                Set_Default_Handler  IPCC_TX0_IRQHandler               ; Mailbox TX0 Free interrupt
+                Set_Default_Handler  DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                Set_Default_Handler  IPCC_RX1_IRQHandler               ; Mailbox RX1 Free interrupt
+                Set_Default_Handler  IPCC_TX1_IRQHandler               ; Mailbox TX1 Free interrupt
+                Set_Default_Handler  CRYP2_IRQHandler                  ; Crypto2 global interrupt
+                Set_Default_Handler  HASH2_IRQHandler                  ; Crypto Hash2 interrupt
+                Set_Default_Handler  I2C5_EV_IRQHandler                ; I2C5 Event Interrupt
+                Set_Default_Handler  I2C5_ER_IRQHandler                ; I2C5 Error Interrupt
+                Set_Default_Handler  GPU_IRQHandler                    ; GPU Global Interrupt
+                Set_Default_Handler  DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                Set_Default_Handler  DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                Set_Default_Handler  DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                Set_Default_Handler  DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                Set_Default_Handler  SAI3_IRQHandler                   ; SAI3 global Interrupt
+                Set_Default_Handler  DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                Set_Default_Handler  TIM15_IRQHandler                  ; TIM15 global Interrupt
+                Set_Default_Handler  TIM16_IRQHandler                  ; TIM16 global Interrupt
+                Set_Default_Handler  TIM17_IRQHandler                  ; TIM17 global Interrupt
+                Set_Default_Handler  TIM12_IRQHandler                  ; TIM12 global Interrupt
+                Set_Default_Handler  MDIOS_IRQHandler                  ; MDIOS global Interrupt
+                Set_Default_Handler  EXTI14_IRQHandler                 ; EXTI Line14 interrupts through AIEC
+                Set_Default_Handler  MDMA_IRQHandler                   ; MDMA global Interrupt
+                Set_Default_Handler  DSI_IRQHandler                    ; DSI global Interrupt
+                Set_Default_Handler  SDMMC2_IRQHandler                 ; SDMMC2 global Interrupt
+                Set_Default_Handler  HSEM_IT2_IRQHandler               ; HSEM global Interrupt
+                Set_Default_Handler  DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                Set_Default_Handler  EXTI15_IRQHandler                 ; EXTI Line15 interrupts through AIEC
+                Set_Default_Handler  nCTIIRQ1_IRQHandler               ; Cortex-M4 CTI interrupt 1
+                Set_Default_Handler  nCTIIRQ2_IRQHandler               ; Cortex-M4 CTI interrupt 2
+                Set_Default_Handler  TIM13_IRQHandler                  ; TIM13 global interrupt
+                Set_Default_Handler  TIM14_IRQHandler                  ; TIM14 global interrupt
+                Set_Default_Handler  DAC_IRQHandler                    ; DAC1 and DAC2 underrun error interrupts
+                Set_Default_Handler  RNG1_IRQHandler                   ; RNG1 interrupt
+                Set_Default_Handler  RNG2_IRQHandler                   ; RNG2 interrupt
+                Set_Default_Handler  I2C6_EV_IRQHandler                ; I2C6 Event Interrupt
+                Set_Default_Handler  I2C6_ER_IRQHandler                ; I2C6 Error Interrupt
+                Set_Default_Handler  SDMMC3_IRQHandler                 ; SDMMC3 global Interrupt
+                Set_Default_Handler  LPTIM2_IRQHandler                 ; LPTIM2 global interrupt
+                Set_Default_Handler  LPTIM3_IRQHandler                 ; LPTIM3 global interrupt
+                Set_Default_Handler  LPTIM4_IRQHandler                 ; LPTIM4 global interrupt
+                Set_Default_Handler  LPTIM5_IRQHandler                 ; LPTIM5 global interrupt
+                Set_Default_Handler  ETH1_LPI_IRQHandler               ; Reserved
+                Set_Default_Handler  RESERVED143_IRQHandler            ; Reserved
+                Set_Default_Handler  MPU_SEV_IRQHandler                ; MPU Send Event through AIEC
+                Set_Default_Handler  RCC_WAKEUP_IRQHandler             ; RCC Wake up interrupt
+                Set_Default_Handler  SAI4_IRQHandler                   ; SAI4 global interrupt
+                Set_Default_Handler  DTS_IRQHandler                    ; Temperature sensor interrupt
+                Set_Default_Handler  RESERVED148_IRQHandler            ; Reserved
+                Set_Default_Handler  WAKEUP_PIN_IRQHandler             ; Interrupt for all 6 wake-up pins
+
+                ALIGN
+
+
+; User setup Stack & Heap
+
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
+                ENDIF
+
+                END
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld
@@ -0,0 +1,202 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32MP1 series
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the License; You may not use this file except in compliance with the 
+** License. You may obtain a copy of the License at:
+**                       opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x10040000;    /* end of RAM */
+
+_Min_Heap_Size  = 0x200;  /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  m_interrupts (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000298
+  m_text       (RX)  : ORIGIN = 0x10000000, LENGTH = 0x00020000
+  m_data       (RW)  : ORIGIN = 0x10020000, LENGTH = 0x00020000
+  m_ipc_shm    (RW)  : ORIGIN = 0x10040000, LENGTH = 0x00008000
+}
+
+ /* Symbols needed for OpenAMP to enable rpmsg */
+__OPENAMP_region_start__  = ORIGIN(m_ipc_shm);
+__OPENAMP_region_end__ = ORIGIN(m_ipc_shm)+LENGTH(m_ipc_shm);
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into ROM memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+ 
+
+  /* The program code and other data into ROM memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } > m_text
+
+  /* Constant data into ROM memory*/
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab   : { 
+  	. = ALIGN(4);
+  	*(.ARM.extab* .gnu.linkonce.armextab.*)
+  	. = ALIGN(4);
+  } > m_text
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } > m_text
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } > m_text
+
+  /* Used by the startup to initialize data */
+  __DATA_ROM = .;
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections */
+  .data :  AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (_edata - _sdata);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  .resource_table :
+  {
+    . = ALIGN(4);
+    KEEP (*(.resource_table*))
+    . = ALIGN(4);
+  } > m_data
+  
+
+  /* Uninitialized data section into RAM memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } > m_data
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } > m_data
+
+  
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+}
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_text_start__ = 0x00000000;
+define symbol __ICFEDIT_region_text_end__   = 0x00008000;
+define symbol __ICFEDIT_region_data_start__ = 0x00008000;
+define symbol __ICFEDIT_region_data_end__   = 0x00010000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region text_region   = mem:[from __ICFEDIT_region_text_start__   to __ICFEDIT_region_text_end__];
+define region data_region   = mem:[from __ICFEDIT_region_data_start__   to __ICFEDIT_region_data_end__];
+
+keep { section .resource_table };
+".resource_table" :  place in data_region {section .resource_table};
+
+/* Create region for OPENAMP */
+/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
+define symbol __OPENAMP_region_start__ = 0x10040000;
+define symbol __OPENAMP_region_size__   = 0x8000;
+export symbol __OPENAMP_region_start__;
+export symbol __OPENAMP_region_size__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit};
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in text_region   { readonly };
+place in data_region   { readwrite,
+                         block CSTACK, block HEAP};
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_text_start__ = 0x10000000;
+define symbol __ICFEDIT_region_text_end__   = 0x1001FFFF;
+define symbol __ICFEDIT_region_data_start__ = 0x10020000;
+define symbol __ICFEDIT_region_data_end__   = 0x1003FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region text_region   = mem:[from __ICFEDIT_region_text_start__   to __ICFEDIT_region_text_end__];
+define region data_region   = mem:[from __ICFEDIT_region_data_start__   to __ICFEDIT_region_data_end__];
+
+keep { section .resource_table };
+".resource_table" :  place in data_region {section .resource_table};
+
+/* Create region for OPENAMP */
+/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
+define symbol __OPENAMP_region_start__ = 0x10040000;
+define symbol __OPENAMP_region_size__   = 0x8000;
+export symbol __OPENAMP_region_start__;
+export symbol __OPENAMP_region_size__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit};
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in text_region   { readonly };
+place in data_region   { readwrite,
+                         block CSTACK, block HEAP};
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/startup_stm32mp15xx.s
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/startup_stm32mp15xx.s
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c
@@ -0,0 +1,290 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32mp1xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32mp1xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock frequency, it can
+  *                                  be used by the user application to setup
+  *                                  the SysTick timer or configure other
+  *                                  parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  *
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32mp1xx_system
+  * @{
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32mp1xx_hal.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Defines
+  * @{
+  */
+
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x400. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) each time HAL_RCC_ClockConfig() is called to configure the system clock
+         frequency
+         Note: If you use this function to configure the system clock;
+               then there is no need to call the first functions listed above,
+               since SystemCoreClock variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = HSI_VALUE;
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) 
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32MP1xx_System_Private_Functions
+  * @{
+  */
+
+  /**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+#if defined (CORE_CM4)
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+   SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#if defined (VECT_TAB_SRAM)
+  SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif
+  /* Disable all interrupts and events */
+  CLEAR_REG(EXTI_C2->IMR1);
+  CLEAR_REG(EXTI_C2->IMR2);
+  CLEAR_REG(EXTI_C2->IMR3);
+  CLEAR_REG(EXTI_C2->EMR1);
+  CLEAR_REG(EXTI_C2->EMR2);
+  CLEAR_REG(EXTI_C2->EMR3);
+#else
+#error Please #define CORE_CM4
+#endif	                         
+}
+
+/**
+   * @brief Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock frequency (Hz),
+  *         it can be used by the user application to setup the SysTick timer or
+  *         configure other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called to
+  *         update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the
+  *             HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the
+  *             HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the
+  *             CSI_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
+  *             HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
+  *             multiplied/divided by the PLL3 factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *             (default value 64 MHz) but the real value may vary depending
+  *             on the variations in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *              (default value 24 MHz), user has to ensure that HSE_VALUE is
+  *              same as the real frequency of the crystal used. Otherwise, this
+  *              function may have wrong result.
+  *
+  *         (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+  *              (default value 4 MHz)but the real value may vary depending
+  *              on the variations in voltage and temperature.
+  *
+  *         - The result of this function could be not correct when using
+  *           fractional value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t   pllsource, pll3m, pll3fracen;
+  float fracn1, pll3vco;
+
+  switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
+  {
+  case 0x00:  /* HSI used as system clock source */
+    SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
+    break;
+
+  case 0x01:  /* HSE used as system clock source */
+    SystemCoreClock = HSE_VALUE;
+    break;
+
+  case 0x02:  /* CSI used as system clock source */
+    SystemCoreClock = CSI_VALUE;
+    break;
+
+  case 0x03:  /* PLL3_P used as system clock source */
+    pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
+    pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
+    pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
+    fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
+    pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF));
+
+    if (pll3m != 0U)
+    {
+      switch (pllsource)
+      {
+        case 0x00:  /* HSI used as PLL clock source */
+          pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
+          break;
+
+        case 0x01:  /* HSE used as PLL clock source */
+          pll3vco *= (float)(HSE_VALUE / pll3m);
+          break;
+
+        case 0x02:  /* CSI used as PLL clock source */
+          pll3vco *= (float)(CSI_VALUE / pll3m);
+          break;
+
+        case 0x03:  /* No clock source for PLL */
+          pll3vco = 0;
+          break;
+       }
+      SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
+    }
+    else
+    {
+      SystemCoreClock = 0U;
+    }
+    break;
+  }
+
+  /* Compute mcu_ck */
+  SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
+}
+
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32mp15xx.s before jump to main.
+  *         This function configures the external SRAM mounted on Eval boards
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_armcc.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_armcc.h
--- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_armclang.h
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Include/cmsis_armclang.h
--- a/Show More
+++ b/Show More