[BSP] add bsp for st's new platform stm32h7s7-st-disco.

[drv] STM32H7RSxx_HAL bsp fixed and update. [add] bsp stm32h7s7-dk README.md
2026-11-14 16:02:37 +08:00 · 2024-04-16 22:48:01 -04:00
1 parent 8ebecf7441
commit a3979fa8d9
@@ -125,6 +125,17 @@ extern "C" {
 #include "h7/sdio_config.h"
 #include "h7/pwm_config.h"
 #include "h7/usbd_config.h"
+
+#elif  defined(SOC_SERIES_STM32H7RS)
+#include "h7/dma_config.h"
+#include "h7/uart_config.h"
+#include "h7/spi_config.h"
+#include "h7/adc_config.h"
+#include "h7/dac_config.h"
+#include "h7/tim_config.h"
+#include "h7/pwm_config.h"
+#include "h7/usbd_config.h"
+
 #elif defined(SOC_SERIES_STM32U5)
 #include "u5/dma_config.h"
 #include "u5/uart_config.h"
@@ -22,7 +22,7 @@ extern "C" {
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\
    || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \
    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
-    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
+    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -35,6 +35,14 @@
 #define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))

 #if defined(GPIOZ)
+#define __STM32_PORT_MAX 16u
+#elif defined(GPIOP)
+#define __STM32_PORT_MAX 15u
+#elif defined(GPIOO)
+#define __STM32_PORT_MAX 14u
+#elif defined(GPION)
+#define __STM32_PORT_MAX 13u
+#elif defined(GPIOM)
 #define __STM32_PORT_MAX 12u
 #elif defined(GPIOK)
 #define __STM32_PORT_MAX 11u
@@ -84,7 +92,8 @@ static const struct pin_irq_map pin_irq_map[] =
        {GPIO_PIN_13, EXTI4_15_IRQn},
        {GPIO_PIN_14, EXTI4_15_IRQn},
        {GPIO_PIN_15, EXTI4_15_IRQn},
-#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) \
+                || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
        {GPIO_PIN_0, EXTI0_IRQn},
        {GPIO_PIN_1, EXTI1_IRQn},
        {GPIO_PIN_2, EXTI2_IRQn},
@@ -575,7 +584,7 @@ void EXTI4_15_IRQHandler(void)
    rt_interrupt_leave();
 }

-#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5)
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS)
 void EXTI0_IRQHandler(void)
 {
    rt_interrupt_enter();
@@ -798,6 +807,22 @@ int rt_hw_pin_init(void)
    __HAL_RCC_GPIOK_CLK_ENABLE();
 #endif

+#if defined(__HAL_RCC_GPIOM_CLK_ENABLE)
+    __HAL_RCC_GPIOM_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPION_CLK_ENABLE)
+    __HAL_RCC_GPION_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOO_CLK_ENABLE)
+    __HAL_RCC_GPIOO_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOP_CLK_ENABLE)
+    __HAL_RCC_GPIOP_CLK_ENABLE();
+#endif
+
    return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
 }

@@ -317,7 +317,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)  \
-    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
+    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
    uart->handle.Instance->TDR = c;
 #else
    uart->handle.Instance->DR = c;
@@ -339,7 +339,7 @@ static int stm32_getc(struct rt_serial_device *serial)
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
-    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
+    || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
        ch = uart->handle.Instance->RDR & uart->DR_mask;
 #else
        ch = uart->handle.Instance->DR & uart->DR_mask;
@@ -477,7 +477,7 @@ static void uart_isr(struct rt_serial_device *serial)
 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
    && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
    && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
-    && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5)
+    && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS)
 #ifdef SOC_SERIES_STM32F3
        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
        {
@@ -32,7 +32,7 @@ int rt_hw_usart_init(void);
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \
    || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \
-    || defined(SOC_SERIES_STM32H5)
+    || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
 #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
    || defined(SOC_SERIES_STM32MP1)
@@ -42,6 +42,9 @@ static uint32_t _systick_ms = 1;
 /* SysTick configuration */
 void rt_hw_systick_init(void)
 {
+	// Updates the variable SystemCoreClock
+    SystemCoreClockUpdate();
+
    HAL_SYSTICK_Config(SystemCoreClock / RT_TICK_PER_SECOND);

    NVIC_SetPriority(SysTick_IRQn, 0xFF);
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7rsxx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M7 Device System Source File for STM32H7RSxx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32H7RSxx_system
+  * @{
+  */
+
+#ifndef SYSTEM_STM32H7RSXX_H
+#define SYSTEM_STM32H7RSXX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32H7RSxx_System_Includes
+  * @{
+  */
+#include <stdint.h>
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7RSxx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;        /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7RSxx_System_Exported_Functions
+  * @{
+  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H7RSXX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
@@ -0,0 +1,126 @@
+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for STM32H7RSxx CMSIS</title>
+  <style type="text/css">
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<center>
+<h1 id="release-notes-for">Release Notes for</h1>
+<h1 id="stm32h7rsxx-cmsis"><mark>STM32H7RSxx CMSIS</mark></h1>
+<p>Copyright © 2024 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+</center>
+<h1 id="purpose">Purpose</h1>
+<p>This driver provides the CMSIS device for the stm32H7RSxx products. This covers</p>
+<ul>
+<li>STM32H7S7xx devices</li>
+<li>STM32H7S3xx devices</li>
+<li>STM32H7R7xx devices</li>
+<li>STM32H7R3xx devices</li>
+</ul>
+<p>This driver is composed of the description of the registers under “Include” directory.</p>
+<p>Various template files are provided to easily build an application. They can be adapted to fit applications requirements.</p>
+<ul>
+<li>Templates/system_stm32h7rsxx.c contains the initialization code referred as SystemInit.</li>
+<li>Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.</li>
+<li>Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.</li>
+</ul>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history">Update History</h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-February-2024</strong></label>
+<div>
+<h2 id="first-release">First release</h2>
+<h3 id="first-official-release-of-stm32h7rsxx-firmware-package-supporting-stm32h7rsxx-devices">First official Release of <strong>STM32H7RSxx</strong> Firmware package supporting <strong>STM32H7RSxx</strong> devices</h3>
+<h2 id="contents">Contents</h2>
+<ul>
+<li>Support of STM32H7Rx/Sx devices</li>
+</ul>
+<p><br />
+</p>
+<p>Notes: linker file mapping vs HW boards</p>
+<table>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Board</th>
+<th>Internal Flash (boot)</th>
+<th style="text-align: left;">External memories (Appli)</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td style="text-align: left;">STM32H7S78-DK</td>
+<td>stm32h7s7xx_flash.*</td>
+<td style="text-align: left;">stm32h7rsxx_RAMxspi1_ROMxspi2.*</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">NUCLEO-H7S3L8</td>
+<td>stm32h7s3xx_flash.*</td>
+<td style="text-align: left;">stm32h7rsxx_ROMxspi2.*</td>
+</tr>
+</tbody>
+</table>
+<p><br />
+</p>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38a</li>
+<li>STM32CubeIDE V1.15.0 (GCC12)</li>
+</ul>
+<p><br />
+</p>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32H7R3xx/STM32H7R7xx/STM32H7S3xx/STM32H7S7xx devices</li>
+</ul>
+<p><br />
+</p>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="dependencies">Dependencies</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="notes">Notes</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+<div class="columns">
+<div class="column" style="width:95%;">
+<p>For complete documentation on STM32H7Rx/Sx,</p>
+<p>visit: <span style="font-color: blue;"><a href="https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h7r3-7s3.html">stm32h7-series/stm32h7r3-7s3</a></span></p>
+<p>visit: <span style="font-color: blue;"><a href="https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h7r7-7s7.html">stm32h7-series/stm32h7r7-7s7</a></span></p>
+<p><em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em></p>
+</div><div class="column" style="width:5%;">
+<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
+</div>
+</div>
+</footer>
+</body>
+</html>
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x08000000 0x08010000  {    ; load region size_region
+  ER_ROM 0x08000000 0x08010000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x24050000 0x00022000  {    ; load region size_region
+  ER_ROM 0x24050000 0x00022000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00050000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24050000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x08000000 0x08010000  {    ; load region size_region
+  ER_ROM 0x08000000 0x08010000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x24050000 0x00022000  {    ; load region size_region
+  ER_ROM 0x24050000 0x00022000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00050000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24050000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,37 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x70000000 0x08000000  {    ; load region size_region
+  ER_ROM 0x70000000 0x08000000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_EXTRAM 0x90000000 0x2000000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400 {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x90000000 0x08000000  {    ; load region size_region
+  ER_ROM 0x90000000 0x08000000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,37 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x90000000 0x08000000  {    ; load region size_region
+  ER_ROM 0x90000000 0x08000000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_EXTRAM 0x70000000 0x2000000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x70000000 0x08000000  {    ; load region size_region
+  ER_ROM 0x70000000 0x08000000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,23 @@
+; *************************************************************
+; MDK-ARM ExtFlashLoader Linker Control File (scatter-loading)
+; *************************************************************
+PRG 0 PI            ; Programming Functions
+{
+  PrgCode +0           ; Code
+  {
+    * (+RO)
+  }
+  PrgData +0           ; Data
+  {
+    * (+ZI,+RW)
+  }
+
+}
+
+DSCR +0x1000
+{
+  DevDscr +0
+  {
+    FlashDev.o
+  }
+}
@@ -0,0 +1,26 @@
+; *************************************************************
+; STM32CubeProgrammer ExtFlashLoader Linker Control File (scatter-loading)
+; *************************************************************
+
+;0x20000004 is the address where the flashloader is loaded
+FLASH_LOADER 0x20000004 PI   ; FlashLoader Functions
+{
+  PrgCode +0          ; Code
+  {
+    * (+RO)
+  }
+;  0x0401FFFC+0x20000004=0x24020000 where data and bss is loaded
+  PrgData +0x0401FFFC          ; Data
+  {
+    * (+RW,+ZI)
+  }
+}
+
+;reserved for device information
+DEVICE_INFO 0               ; Device Info
+{
+  DevInfo 0           ; Info structure
+  {
+    stm32_device_info.o
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x08000000 0x08010000  {    ; load region size_region
+  ER_ROM 0x08000000 0x08010000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x24050000 0x00022000  {    ; load region size_region
+  ER_ROM 0x24050000 0x00022000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00050000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24050000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x08000000 0x08010000  {    ; load region size_region
+  ER_ROM 0x08000000 0x08010000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00072000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24072000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,34 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LOAD_FLASH 0x24050000 0x00022000  {    ; load region size_region
+  ER_ROM 0x24050000 0x00022000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  ER_ITCM 0x00000000 0x00010000  {  ;
+  }
+
+  RW_DTCM 0x20000000 0x00010000  {  ; RW data
+   *(STACK)
+   *(HEAP)
+  }
+
+  RW_SRAMAHB 0x30000000 0x8000  {
+  }
+
+  RW_BKPSRAM 0x38800000 0x1000  {
+  }
+
+  RW_RAM 0x24000000  0x00050000-0x400  {
+   .ANY (+RW +ZI)
+  }
+
+  RW_NONCACHEABLEBUFFER  0x24050000-0x400 0x400  {
+   *(noncacheable_buffer)
+  }
+}
@@ -0,0 +1,159 @@
+/*
+*****************************************************************************
+**  File        : linker.ld
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Generate 2 segment for Loader code and device info */
+PHDRS {Loader PT_LOAD FLAGS(5) ; SgInfo PT_LOAD ; }
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1)-1;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+	RAM_D1 (xrw)      : ORIGIN = 0x20000004, LENGTH = 64K-4
+	RAM_D2 (xrw)      : ORIGIN = 0x24020000, LENGTH = 128K
+}
+
+/* Define output sections */
+
+SECTIONS
+{
+
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+  	. = . + 0x1FC;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM_D1 :Loader
+
+ .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_D1
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >RAM_D1 :Loader
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >RAM_D1 :Loader
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >RAM_D1 :Loader
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >RAM_D1 :Loader
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM_D1 :Loader
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM_D2 :Loader
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM_D1 :Loader
+
+  .stm32_device_info :
+  {
+	KEEP(*stm32_device_info.o ( .rodata* ))
+
+  } :SgInfo
+
+
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM_D1 :Loader
+
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM_D1 :Loader
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24050000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x24071FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24050000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x24071FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,61 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__     = 0x70000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x70000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x77FFFFFF;
+define symbol NONCACHEABLEBUFFER_size      = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+define symbol __region_EXTRAM_start__ = 0x90000000;
+define symbol __region_EXTRAM_end__   = 0x91FFFFFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+export symbol __region_EXTRAM_start__;
+export symbol __region_EXTRAM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region EXTRAM_region   = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region    { readonly };
+place in RAM_region    { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region   { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x90000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x90000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x97FFFFFF;
+define symbol NONCACHEABLEBUFFER_size      = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,62 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x90000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x90000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x97FFFFFF;
+define symbol NONCACHEABLEBUFFER_size      = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+define symbol __region_EXTRAM_start__ = 0x70000000;
+define symbol __region_EXTRAM_end__   = 0x71FFFFFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+export symbol __region_EXTRAM_start__;
+export symbol __region_EXTRAM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region EXTRAM_region   = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region    { readonly };
+place in RAM_region    { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region   { block CSTACK, block HEAP };
@@ -0,0 +1,56 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x70000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x70000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x77FFFFFF;
+define symbol NONCACHEABLEBUFFER_size      = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region    { readonly };
+place in RAM_region    { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region   { block CSTACK, block HEAP };
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x00000040;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x0000EFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0000F000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0000FFFF;
+define symbol __ICFEDIT_region_DTCM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_DTCM_end__    = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x8;    /* not used defined the min size */
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+define region IRAM_region_2 =   mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region DTCM_region   =   mem:[from __ICFEDIT_region_DTCM_start__ to __ICFEDIT_region_DTCM_end__];
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+do not initialize { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
+place at start of IRAM_region { readonly };
+place in IRAM_region          { block RamTop with fixed order { readwrite, block CSTACK, block HEAP }};
+place in IRAM_region_2        { zi};
+place at start of DTCM_region { section RAMBUFFER_END };
+place at end of DTCM_region   { section RAMBUFFER_START };
@@ -0,0 +1,22 @@
+
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20010000;
+
+define symbol __ICFEDIT_region_RAM2_start__   = 0x24020000;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x24040000;
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define memory mem with size = 4G;
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM2_region  = mem:[from __ICFEDIT_region_RAM2_start__   to __ICFEDIT_region_RAM2_end__];
+define region Info_region  = mem:[from 0   to 0x3000];
+
+define block RAM_BLOCK with fixed order {readonly code, readonly data, readwrite };
+define block StorageInfo_BLOCK with fixed order { readonly data object stm32_device_Info.o};
+
+place in RAM_region    { block RAM_BLOCK};
+place in RAM2_region   { zi };
+place in Info_region   { block StorageInfo_BLOCK };
+
+do not initialize  { section .info, readwrite };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24050000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x24071FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24050000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x24071FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x24071FFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24050000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x400;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x24071FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
@@ -0,0 +1,47 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c
+STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
+    src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c']
+    src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c']
+    src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c']
+
+
+path = [cwd + '/STM32H7RSxx_HAL_Driver/Inc',
+    cwd + '/CMSIS/Device/ST/STM32H7RSxx/Include']
+
+CPPDEFINES = ['USE_HAL_DRIVER']
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
+
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ASSERT_H */
@@ -0,0 +1,150 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7rsxx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7RSxx_HAL_CRC_EX_H
+#define STM32H7RSxx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7rsxx_hal_def.h"
+
+/** @addtogroup STM32H7RSxx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
+#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
+#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__ CRC handle
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+  * @{
+  */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7RSxx_HAL_CRC_EX_H */
@@ -0,0 +1,129 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7rsxx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYP HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7RSxx_HAL_CRYP_EX_H
+#define STM32H7RSxx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7rsxx_hal_def.h"
+
+/** @addtogroup STM32H7RSxx_HAL_Driver
+  * @{
+  */
+#if defined (CRYP)
+/** @addtogroup CRYPEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+  * @{
+  */
+
+/**
+  * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout);
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output,
+                                              uint32_t ID, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout);
+#endif /* USE_HAL_SAES_ONLY */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* CRYP */
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7RSxx_HAL_CRYP_EX_H */
@@ -0,0 +1,199 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7rsxx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7RSxx_HAL_DEF_H
+#define STM32H7RSxx_HAL_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7rsxx.h"
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <math.h>
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if !defined(UNUSED)
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+  do{                                                    \
+    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+    (__DMA_HANDLE__).Parent = (__HANDLE__);              \
+  } while(0)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__)            \
+  do{                                     \
+    if((__HANDLE__)->Lock == HAL_LOCKED)  \
+    {                                     \
+      return HAL_BUSY;                    \
+    }                                     \
+    else                                  \
+    {                                     \
+      (__HANDLE__)->Lock = HAL_LOCKED;    \
+    }                                     \
+  }while (0)
+
+#define __HAL_UNLOCK(__HANDLE__)          \
+  do{                                     \
+    (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+  }while (0)
+#endif /* USE_RTOS */
+
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak  __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed  __attribute__((packed))
+#endif /* packed */
+#elif defined (__GNUC__) /* GNU Compiler */
+#ifndef __weak
+#define __weak  __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed  __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
+#define ALIGN_32BYTES(buf)  buf __attribute__((aligned(32)))
+
+/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */
+/* This alignment is required for double-word DMA transfers */
+#define ALIGN_8BYTES(buf)  buf __attribute__((aligned(8)))
+
+/* Legacy macros to get variable 4-bytes aligned */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END  __attribute__((aligned(4)))
+#endif /* __ALIGN_END */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+/* ARM Compiler V6
+   ---------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined (__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC  __ramfunc
+
+#elif defined (__GNUC__)
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC  __attribute__((section(".RamFunc")))
+
+#endif /* __ARMCC_VERSION */
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__)
+/* ARM V6 & GNU Compiler
+   ---------------------
+*/
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined (__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif /* __ARMCC_VERSION || __GNUC__ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7RSxx_HAL_DEF_H */