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[BSP]Add nrf5x SPI BSP

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This commit is contained in:
ShermanShao11
2020-05-25 19:42:33 +08:00
parent fc44e8f0ae
commit a17867878d
5 changed files with 442 additions and 7 deletions
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bsp/nrf5x/libraries/drivers/SConscript
+3
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@@ -17,6 +17,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
if GetDepend(['BSP_USING_QSPI_FLASH']):
src += ['drv_qspi_flash.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
bsp/nrf5x/libraries/drivers/drv_spi.c
+281
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File diff suppressed because it is too large Load Diff
bsp/nrf5x/libraries/drivers/drv_spi.h
+77
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@@ -0,0 +1,77 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-05-19 Sherman first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
#ifdef BSP_USING_SPI
#include "nrfx_spi.h"
/**
* @brief Attach the spi device to SPI bus, this function must be used after initialization.
* @param bus_name spi bus name "spi0"/"spi1"/"spi2"
* @param device_name spi device name "spi0x"/"spi1x"/"spi2x"
* @param ss_pin spi ss pin number
* @retval RT_ERROR / RT_EOK
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t ss_pin);
//SPI bus config
#ifdef BSP_USING_SPI0
#define NRFX_SPI0_CONFIG \
{ \
.bus_name = "spi0", \
.spi = NRFX_SPI_INSTANCE(0) \
}
#endif
#ifdef BSP_USING_SPI1
#define NRFX_SPI1_CONFIG \
{ \
.bus_name = "spi1", \
.spi = NRFX_SPI_INSTANCE(1) \
}
#endif
#ifdef BSP_USING_SPI2
#define NRFX_SPI2_CONFIG \
{ \
.bus_name = "spi2", \
.spi = NRFX_SPI_INSTANCE(2) \
}
#endif
struct nrfx_drv_spi_config
{
char *bus_name;
nrfx_spi_t spi;
};
struct nrfx_drv_spi
{
nrfx_spi_t spi; /* nrfx spi driver instance. */
nrfx_spi_config_t spi_config; /* nrfx spi config Configuration */
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
};
struct nrfx_drv_spi_pin_config
{
rt_uint8_t sck_pin;
rt_uint8_t mosi_pin;
rt_uint8_t miso_pin;
rt_uint8_t ss_pin;
};
#endif /* BSP_USING_SPI */
#endif /*__DRV_SPI_H_*/
bsp/nrf5x/nrf52840/board/Kconfig
+73 -1
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@@ -80,6 +80,79 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_SPI
bool "Enable SPI"
select RT_USING_PIN
default y
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 bus"
default y
if BSP_USING_SPI0
config BSP_SPI0_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI0_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI0_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI0_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
config BSP_USING_SPI1
bool "Enable SPI1 bus"
default n
if BSP_USING_SPI1
config BSP_SPI1_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI1_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI1_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI1_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
config BSP_USING_SPI2
bool "Enable SPI2 bus"
default n
if BSP_USING_SPI2
config BSP_SPI2_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI2_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI2_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI2_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
endif
config BSP_USING_ON_CHIP_FLASH
select PKG_USING_FAL
bool "Enable on-chip FLASH"
@@ -87,7 +160,6 @@ menu "On-chip Peripheral Drivers"
menu "On-chip flash config"
config MCU_FLASH_START_ADDRESS
hex "MCU FLASH START ADDRESS"
default 0x00000000
bsp/nrf5x/nrf52840/board/sdk_config.h
+8 -6
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@@ -3556,27 +3556,27 @@
// <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
//==========================================================
#ifndef NRFX_SPI_ENABLED
#define NRFX_SPI_ENABLED 0
#define NRFX_SPI_ENABLED 1
#endif
// <q> NRFX_SPI0_ENABLED - Enable SPI0 instance
#ifndef NRFX_SPI0_ENABLED
#define NRFX_SPI0_ENABLED 0
#define NRFX_SPI0_ENABLED 1
#endif
// <q> NRFX_SPI1_ENABLED - Enable SPI1 instance
#ifndef NRFX_SPI1_ENABLED
#define NRFX_SPI1_ENABLED 0
#define NRFX_SPI1_ENABLED 1
#endif
// <q> NRFX_SPI2_ENABLED - Enable SPI2 instance
#ifndef NRFX_SPI2_ENABLED
#define NRFX_SPI2_ENABLED 0
#define NRFX_SPI2_ENABLED 1
#endif
// <o> NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration.
@@ -11694,9 +11694,11 @@
#endif
// </e>
// </h>
// </h>
//==========================================================
#ifndef NRFX_SYSTICK_ENABLED
#define NRFX_SYSTICK_ENABLED 1
#endif
// <<< end of configuration section >>>
#endif //SDK_CONFIG_H