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Merge pull request #1524 from TanekLiang/imxrt-update-new-sdk

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[bsp][imxrt1052-evk] update sdk to EVKB
This commit is contained in:
Bernard Xiong
2018-06-11 21:51:16 +08:00
committed by GitHub
parent 22d5e3c3a9 7154956a4a
commit a0fc4f3953
137 changed files with 10139 additions and 8335 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/imxrt1052-evk/.config
+74 -24
View File
@@ -84,6 +84,7 @@ CONFIG_FINSH_CMD_SIZE=80
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
@@ -129,6 +130,7 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_I2C=y
CONFIG_RT_USING_I2C_BITOPS=y
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
CONFIG_RT_USING_RTC=y
@@ -144,6 +146,7 @@ CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
@@ -157,7 +160,6 @@ CONFIG_RT_USING_SPI=y
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
# CONFIG_HAVE_SYS_SIGNALS is not set
#
# Network stack
@@ -199,6 +201,8 @@ CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
@@ -238,20 +242,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# RT-Thread online packages
#
#
# system packages
#
#
# RT-Thread GUI Engine
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
#
# IoT - internet of things
#
@@ -260,6 +250,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@@ -281,6 +272,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_ONENET is not set
#
# security packages
@@ -299,6 +291,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
@@ -307,7 +300,32 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_IPERF is not set
#
# system packages
#
#
# RT-Thread GUI Engine
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_GUIENGINE_V200 is not set
# CONFIG_PKG_USING_GUIENGINE_LATEST_VERSION is not set
# CONFIG_GUIENGINE_IMAGE_LODEPNG is not set
# CONFIG_GUIENGINE_IMAGE_PNG is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
#
# miscellaneous packages
@@ -316,16 +334,48 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_SAMPLES is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_MDNS is not set
# CONFIG_PKG_USING_UPNP is not set
# CONFIG_PKG_USING_WLAN_WICED_SRC is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RT_AT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
CONFIG_SOC_IMXRT1052=y
CONFIG_BOARD_USING_HYPERFLASH=y
# CONFIG_BOARD_USING_QSPIFLASH is not set
CONFIG_BOARD_RT1050_EVK=y
# CONFIG_BOARD_RT1050_FIRE is not set
# CONFIG_BOARD_RT1050_ShareBoard is not set
# CONFIG_BOARD_RT1050_ATK is not set
# CONFIG_BOARD_RT1050_SeeedStudio is not set
#
# RT1050 Bsp Config
@@ -365,14 +415,14 @@ CONFIG_LPSPI4_SDI_GPIO_1=y
# CONFIG_RT_USING_SPI_FLASH is not set
#
# Select i2c bus drivers
# Select iic bus drivers
#
CONFIG_LPI2C_CLOCK_SOURCE_DIVIDER=4
CONFIG_RT_USING_I2C1=y
# CONFIG_RT_USING_I2C1_BITOPS is not set
# CONFIG_RT_USING_I2C2 is not set
# CONFIG_RT_USING_I2C3 is not set
# CONFIG_RT_USING_I2C4 is not set
CONFIG_RT_USING_HW_I2C1=y
CONFIG_HW_I2C1_BADURATE_100kHZ=y
# CONFIG_HW_I2C1_BADURATE_400kHZ is not set
# CONFIG_RT_USING_HW_I2C2 is not set
# CONFIG_RT_USING_HW_I2C3 is not set
# CONFIG_RT_USING_HW_I2C4 is not set
#
# Select lcd driver
bsp/imxrt1052-evk/Libraries/MIMXRT1052.h
+2817 -259
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File diff suppressed because it is too large Load Diff
bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h
+67 -445
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File diff suppressed because it is too large Load Diff
bsp/imxrt1052-evk/Libraries/SConscript
+1 -1
View File
@@ -12,7 +12,7 @@ src += Glob('common/chip/*.c')
src += [cwd + '/system_MIMXRT1052.c']
CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/Include']
CPPDEFINES = ['CPU_MIMXRT1052DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_adc.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c
+18 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,11 @@
#include "fsl_adc_etc.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.adc_etc"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -90,7 +99,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
/* Set ADC_ETC_CTRL register. */
tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask);
ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
| ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
;
if (config->enableTSCBypass)
{
tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
@@ -124,6 +137,9 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
config->enableTSCBypass = true;
config->enableTSC0Trigger = false;
config->enableTSC1Trigger = false;
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
config->TSC0triggerPriority = 0U;
config->TSC1triggerPriority = 0U;
config->clockPreDivider = 0U;
bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h
+20 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -87,6 +91,17 @@ typedef enum _adc_etc_interrupt_enable
kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
} adc_etc_interrupt_enable_t;
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
/*!
* @brief DMA mode selection.
*/
typedef enum _adc_etc_dma_mode_selection
{
kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
} adc_etc_dma_mode_selection_t;
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
/*!
* @brief ADC_ETC configuration.
*/
@@ -96,6 +111,9 @@ typedef struct _adc_etc_config
Otherwise TSC would trigger ADC through ADC_ETC. */
bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.aipstz"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -68,7 +72,7 @@ typedef enum _aipstz_peripheral_access_control {
kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
kAIPSTZ_PeripheralWriteProtected = (1U << 1),
kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 2)
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
} aipstz_peripheral_access_control_t;
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/
bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -29,6 +33,12 @@
*/
#include "fsl_aoi.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.aoi"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c
+11 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.bee"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h
+5 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.c
+23 -13
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,7 +37,13 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
#endif
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
#define L2CACHE_8WAYS_MASK 0xFFU
#define L2CACHE_16WAYS_MASK 0xFFFFU
@@ -126,7 +136,7 @@ static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t reg
/* Set the opeartion for all ways/entries of the cache. */
*(uint32_t *)regAddr = mask;
/* Waiting for until the operation is complete. */
while ((*(uint32_t *)regAddr & mask) && timeout)
while ((*(volatile uint32_t *)regAddr & mask) && timeout)
{
__ASM("nop");
timeout--;
@@ -397,7 +407,7 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
}
}
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
{
@@ -420,41 +430,41 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_InvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateICacheByRange(address, size_byte);
}
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_InvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateDCacheByRange(address, size_byte);
}
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanDCacheByRange(address, size_byte);
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_CleanByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_CleanInvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}
bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.h
+12 -8
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,15 +51,15 @@
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
#endif
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
* Definitions
******************************************************************************/
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
/*! @brief Number of level 2 cache controller ways. */
typedef enum _l2cache_way_num
@@ -133,7 +137,7 @@ typedef struct _l2cache_config
/* ------------------------ other settings -------------------------------------- */
l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
} l2cache_config_t;
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
* API
******************************************************************************/
@@ -286,7 +290,7 @@ static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32
}
/*@}*/
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
/*!
* @name Control for L2 pl310 cache
*@{
@@ -414,7 +418,7 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/*@}*/
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*!
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.c
+208 -133
View File
File diff suppressed because it is too large Load Diff
bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.h
+745 -537
View File
File diff suppressed because it is too large Load Diff
bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_cmp.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cmp"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_common.c
+45 -15
View File
@@ -1,10 +1,13 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,6 +42,12 @@ typedef struct _mem_align_control_block
uint16_t offset; /*!< offset from aligned adress to real address */
} mem_align_cb_t;
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.common"
#endif
#ifndef __GIC_PRIO_BITS
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
@@ -99,30 +109,50 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 = 1u << intNumber;
}
#else
{
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
SYSCON->STARTERCLR[index] = 1u << intNumber;
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 &= ~(1u << intNumber);
}
#else
{
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
bsp/imxrt1052-evk/Libraries/drivers/fsl_common.h
+73 -17
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -65,14 +69,16 @@
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */
/*! @brief Status group numbers. */
enum _status_groups
@@ -140,6 +146,7 @@ enum _status_groups
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
@@ -175,6 +182,13 @@ typedef int32_t status_t;
#include "fsl_reset.h"
#endif
/*
* Macro guard for whether to use default weak IRQ implementation in drivers
*/
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
#endif
/*! @name Min/max macros */
/* @{ */
#if !defined(MIN)
@@ -273,13 +287,6 @@ _Pragma("diag_suppress=Pm120")
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
/* @} */
/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */
void *SDK_Malloc(size_t size, size_t alignbytes);
void SDK_Free(void *ptr);
/* @} */
/*! @name Non-cacheable region definition macros */
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
@@ -339,6 +346,37 @@ void SDK_Free(void *ptr);
#endif
/* @} */
/*! @name Time sensitive region */
/* @{ */
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
#elif(defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
#else
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#else
#error Toolchain not supported.
#endif
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
/* @} */
/*******************************************************************************
* API
******************************************************************************/
@@ -511,6 +549,24 @@ void SDK_Free(void *ptr);
void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
/*!
* @brief Allocate memory with given alignment and aligned size.
*
* This is provided to support the dynamically allocated memory
* used in cache-able region.
* @param size The length required to malloc.
* @param alignbytes The alignment size.
* @retval The allocated memory.
*/
void *SDK_Malloc(size_t size, size_t alignbytes);
/*!
* @brief Free memory.
*
* @param ptr The memory to be release.
*/
void SDK_Free(void *ptr);
#if defined(__cplusplus)
}
#endif
bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c
+11 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.csi"
#endif
/* Two frame buffer loaded to CSI register at most. */
#define CSI_MAX_ACTIVE_FRAME_NUM 2
bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h
+5 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.c
+13 -4
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_dcdc.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -330,13 +340,12 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
void DCDC_BootIntoDCM(DCDC_Type *base)
{
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) |
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) |
DCDC_REG2_DCM_SET_CTRL_MASK;
}
void DCDC_BootIntoCCM(DCDC_Type *base)
{
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) |
DCDC_REG2_DCM_SET_CTRL_MASK;
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
}
bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.h
+5 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c
+11 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dcp"
#endif
/*! Compile time sizeof() check */
#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h
+5 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dmamux"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.c
+16 -3
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.edma"
#endif
#define EDMA_TRANSFER_ENABLED_MASK 0x80U
/*******************************************************************************
@@ -711,8 +721,10 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
*/
if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
{
/* Clear the DREQ bits for the dynamic scatter gather */
tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
/* Enable scatter/gather also in the TCD registers. */
csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
/* Must write the CSR register one-time, because the transfer maybe finished anytime. */
tcdRegs->CSR = csr;
/*
@@ -727,6 +739,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
*/
if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
{
tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
return kStatus_Success;
}
/*
bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.h
+33 -8
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -52,7 +56,7 @@
#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
/*! @brief Get the pointer of DCHPRIn */
#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
/*! @brief eDMA transfer configuration */
typedef enum _edma_transfer_size
@@ -60,6 +64,7 @@ typedef enum _edma_transfer_size
kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
} edma_transfer_size_t;
@@ -242,7 +247,24 @@ typedef struct _edma_tcd
/*! @brief Callback for eDMA */
struct _edma_handle;
/*! @brief Define callback function for eDMA. */
/*! @brief Define callback function for eDMA.
*
* This callback function is called in the EDMA interrupt handle.
* In normal mode, run into callback function means the transfer users need is done.
* In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not
* all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
*
* @param handle EDMA handle pointer, users shall not touch the values inside.
* @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to
* change in EDMA callback function.
* @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
* gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the
* load of core is different, it will be different if the new tcd loaded into EDMA registers while
* this callback called. If true, it always means new tcd still not loaded into registers, while
* false means new tcd already loaded into registers.
* @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It
* tells user how many tcds are finished between the last callback and this.
*/
typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
/*! @brief eDMA transfer handle structure */
@@ -702,7 +724,7 @@ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
* @brief Gets the remaining major loop count from the eDMA current channel TCD.
*
* This function checks the TCD (Task Control Descriptor) status for a specified
* eDMA channel and returns the the number of major loop count that has not finished.
* eDMA channel and returns the number of major loop count that has not finished.
*
* @param base eDMA peripheral base address.
* @param channel eDMA channel number.
@@ -774,7 +796,10 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
/*!
* @brief Installs the TCDs memory pool into the eDMA handle.
*
* This function is called after the EDMA_CreateHandle to use scatter/gather feature.
* This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
* while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
* (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
* Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
*
* @param handle eDMA handle pointer.
* @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
@@ -786,7 +811,7 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t
* @brief Installs a callback function for the eDMA transfer.
*
* This callback is called in the eDMA IRQ handler. Use the callback to do something after
* the current major loop transfer completes.
* the current major loop transfer completes. This function will be called every time one tcd finished transfer.
*
* @param handle eDMA handle pointer.
* @param callback eDMA callback function pointer.
@@ -824,8 +849,8 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
* @brief Submits the eDMA transfer request.
*
* This function submits the eDMA transfer request according to the transfer configuration structure.
* If submitting the transfer request repeatedly, this function packs an unprocessed request as
* a TCD and enables scatter/gather feature to process it in the next time.
* In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
* The tcd pools is setup by call function EDMA_InstallTCDMemory before.
*
* @param handle eDMA handle pointer.
* @param config Pointer to eDMA transfer configuration structure.
bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.c
+11 -5
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_elcdif.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.elcdif"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -286,10 +296,6 @@ status_t ELCDIF_UpdateLut(
for (i = 0; i < count; i++)
{
*regLutData = lutData[i];
for (volatile uint32_t j = 0; j < 0x80; j++)
{
}
}
return kStatus_Success;
bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.h
+5 -1
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.enc"
#endif
#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK)
#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK)
bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h
+22 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -303,6 +307,22 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base);
*/
void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config);
/*!
* @brief Enable watchdog for ENC module.
*
* @param base ENC peripheral base address
* @param enable Enables or disables the watchdog
*/
void ENC_EnableWatchdog(ENC_Type *base, bool enable);
/*!
* @brief Set initial position value for ENC module.
*
* @param base ENC peripheral base address
* @param value Positive initial value
*/
void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value);
/* @} */
/*!
bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c
+92 -120
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -36,6 +40,12 @@
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.enet"
#endif
/*! @brief IPv4 PTP message IP version offset. */
#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
/*! @brief IPv4 PTP message UDP protocol offset. */
@@ -99,7 +109,9 @@
/*! @brief NanoSecond in one second. */
#define ENET_NANOSECOND_ONE_SECOND 1000000000U
/*! @brief Define a common clock cycle delays used for time stamp capture. */
#define ENET_1588TIME_DELAY_COUNT 38U
#ifndef ENET_1588TIME_DELAY_COUNT
#define ENET_1588TIME_DELAY_COUNT 10U
#endif
/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
#define ENET_HTONS(n) __REV16(n)
@@ -793,6 +805,12 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config
#else
rxBuffer = buffCfg->rxBufferAlign;
#endif
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Invalidate rx buffers before DMA transfer data into them. */
DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign));
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
for (count = 0; count < buffCfg->rxBdNumber; count++)
{
/* Set data buffer and the length. */
@@ -1172,24 +1190,18 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
else
{
/* A frame on one buffer or several receive buffers are both considered. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* A frame on one buffer or several receive buffers are both considered. */
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
enet_ptp_time_data_t ptpTimestamp;
bool isPtpEventMessage = false;
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
bool isPtpEventMessage = false;
/* Parse the PTP message according to the header message. */
isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
@@ -1205,11 +1217,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
{
/* Copy the frame to user's buffer without FCS. */
len = curBuffDescrip->length - offset;
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy(data + offset, (void *)address, len);
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* Store the PTP 1588 timestamp for received PTP event frame. */
@@ -1240,11 +1247,7 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
{
break;
}
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]);
offset += handle->rxBuffSizeAlign[0];
@@ -1254,13 +1257,13 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
/* Get the current buffer descriptor. */
curBuffDescrip = handle->rxBdCurrent[0];
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
}
@@ -1345,8 +1348,10 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data, length);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -1372,15 +1377,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
{
handle->txBdCurrent[0]++;
}
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
ENET_ActiveSend(base, 0);
@@ -1414,15 +1410,19 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
}
/* update the size left to be transmit. */
sizeleft = length - len;
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
if (sizeleft > handle->txBuffSizeAlign[0])
{
/* Data copy. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Data length update. */
curBuffDescrip->length = handle->txBuffSizeAlign[0];
len += handle->txBuffSizeAlign[0];
@@ -1434,24 +1434,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
}
else
{
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, sizeleft);
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
DCACHE_CleanByRange(address, sizeleft);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
/* Active the transmit buffer descriptor. */
ENET_ActiveSend(base, 0);
@@ -1638,25 +1629,19 @@ status_t ENET_ReadFrameMultiRing(
else
{
/* A frame on one buffer or several receive buffers are both considered. */
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
enet_ptp_time_data_t ptpTimestamp;
bool isPtpEventMessage = false;
/* Parse the PTP message according to the header message. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
@@ -1671,11 +1656,6 @@ status_t ENET_ReadFrameMultiRing(
{
/* Copy the frame to user's buffer without FCS. */
len = curBuffDescrip->length - offset;
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy(data + offset, (void *)address, len);
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* Store the PTP 1588 timestamp for received PTP event frame. */
@@ -1706,11 +1686,6 @@ status_t ENET_ReadFrameMultiRing(
{
break;
}
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]);
offset += handle->rxBuffSizeAlign[ringId];
@@ -1722,13 +1697,13 @@ status_t ENET_ReadFrameMultiRing(
/* Get the current buffer descriptor. */
curBuffDescrip = handle->rxBdCurrent[ringId];
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
}
@@ -1778,6 +1753,11 @@ status_t ENET_SendFrameMultiRing(
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data, length);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -1803,15 +1783,7 @@ status_t ENET_SendFrameMultiRing(
{
handle->txBdCurrent[ringId]++;
}
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
ENET_ActiveSend(base, ringId);
@@ -1845,53 +1817,41 @@ status_t ENET_SendFrameMultiRing(
}
/* update the size left to be transmit. */
sizeleft = length - len;
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
if (sizeleft > handle->txBuffSizeAlign[ringId])
{
/* Data copy. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Data length update. */
curBuffDescrip->length = handle->txBuffSizeAlign[ringId];
len += handle->txBuffSizeAlign[ringId];
/* Sets the control flag. */
curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor*/
ENET_ActiveSend(base, ringId);
}
else
{
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, sizeleft);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
DCACHE_CleanByRange(address, sizeleft);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, sizeleft);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
ENET_ActiveSend(base, ringId);
@@ -1900,9 +1860,6 @@ status_t ENET_SendFrameMultiRing(
/* Get the current buffer descriptor address. */
curBuffDescrip = handle->txBdCurrent[ringId];
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache invalidate maintain. */
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
} while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
return kStatus_ENET_TxFrameBusy;
@@ -2155,7 +2112,7 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt
switch (ENET_HTONS(ptpType))
{ /* Ethernet layer 2. */
case ENET_ETHERNETL2:
if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType)
if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType)
{
isPtpMsg = true;
if (!isFastEnabled)
@@ -2488,6 +2445,7 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false);
if (isPtpEventMessage)
{
/* Only store tx timestamp for ptp event message. */
do
{
/* Increase current buffer descriptor to the next one. */
@@ -2523,6 +2481,9 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
ptpTimeData.timeStamp.second = handle->msTimerSecond - 1;
}
/* Save transmit time stamp nanosecond. */
ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp;
/* Enable the interrupt. */
EnableGlobalIRQ(primask);
@@ -2533,7 +2494,6 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
/* Get the current transmit buffer descriptor. */
curBuffDescrip = handle->txBdDirtyTime[ringId];
/* Get the control status data, If the buffer descriptor has not been processed break out. */
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
{
@@ -2542,6 +2502,18 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
} while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]);
return kStatus_ENET_TxFrameFail;
}
else
{
/* Only increase current buffer descriptor to the next one. */
if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
{
handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId];
}
else
{
handle->txBdDirtyTime[ringId]++;
}
}
return kStatus_Success;
}
bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.h
+30 -23
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,7 +50,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief Defines the driver version. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */
/*@}*/
/*! @name ENET DESCRIPTOR QUEUE */
@@ -194,7 +198,7 @@ typedef enum _enet_mii_mode
*
* Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode".
*/
typedef enum _enet_mii_speed
typedef enum _enet_mii_speed
{
kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */
kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */
@@ -204,21 +208,21 @@ typedef enum _enet_mii_speed
} enet_mii_speed_t;
/*! @brief Defines the half or full duplex for the MII data interface. */
typedef enum _enet_mii_duplex
typedef enum _enet_mii_duplex
{
kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
kENET_MiiFullDuplex /*!< Full duplex mode. */
} enet_mii_duplex_t;
/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
typedef enum _enet_mii_write
typedef enum _enet_mii_write
{
kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */
kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */
} enet_mii_write_t;
/*! @brief Defines the read operation for the MII management frame. */
typedef enum _enet_mii_read
typedef enum _enet_mii_read
{
kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */
kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */
@@ -226,7 +230,8 @@ typedef enum _enet_mii_read
#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */
typedef enum _enet_mii_extend_opcode {
typedef enum _enet_mii_extend_opcode
{
kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */
kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */
kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */
@@ -245,7 +250,7 @@ typedef enum _enet_mii_extend_opcode {
* configure rxFifoFullThreshold and txFifoWatermark
* in the enet_config_t.
*/
typedef enum _enet_special_control_flag
typedef enum _enet_special_control_flag
{
kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */
kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */
@@ -268,7 +273,7 @@ typedef enum _enet_special_control_flag
* members. Members usually map to interrupt enable bits in one or more
* peripheral registers.
*/
typedef enum _enet_interrupt_enable
typedef enum _enet_interrupt_enable
{
kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */
kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */
@@ -302,7 +307,7 @@ typedef enum _enet_interrupt_enable
} enet_interrupt_enable_t;
/*! @brief Defines the common interrupt event for callback use. */
typedef enum _enet_event
typedef enum _enet_event
{
kENET_RxEvent, /*!< Receive event. */
kENET_TxEvent, /*!< Transmit event. */
@@ -314,7 +319,7 @@ typedef enum _enet_event
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
/*! @brief Defines certain idle slope for bandwidth fraction. */
typedef enum _enet_idle_slope
typedef enum _enet_idle_slope
{
kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */
kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */
@@ -339,7 +344,7 @@ typedef enum _enet_idle_slope
#endif /* FSL_FEATURE_ENET_HAS_AVB */
/*! @brief Defines the transmit accelerator configuration. */
typedef enum _enet_tx_accelerator
typedef enum _enet_tx_accelerator
{
kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */
kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */
@@ -347,7 +352,7 @@ typedef enum _enet_tx_accelerator
} enet_tx_accelerator_t;
/*! @brief Defines the receive accelerator configuration. */
typedef enum _enet_rx_accelerator
typedef enum _enet_rx_accelerator
{
kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */
kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */
@@ -358,7 +363,7 @@ typedef enum _enet_rx_accelerator
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/*! @brief Defines the ENET PTP message related constant. */
typedef enum _enet_ptp_event_type
typedef enum _enet_ptp_event_type
{
kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */
kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
@@ -367,7 +372,7 @@ typedef enum _enet_ptp_event_type
} enet_ptp_event_type_t;
/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */
typedef enum _enet_ptp_timer_channel
typedef enum _enet_ptp_timer_channel
{
kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */
kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */
@@ -481,14 +486,16 @@ typedef struct _enet_data_error_stats
*/
typedef struct _enet_buffer_config
{
uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */
uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */
uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */
volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */
volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */
uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */
uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */
uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */
uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */
uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */
volatile enet_rx_bd_struct_t
*rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */
volatile enet_tx_bd_struct_t
*txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */
uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */
uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */
} enet_buffer_config_t;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c
+12 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_ewm.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.ewm"
#endif
/*******************************************************************************
* Code
******************************************************************************/
bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h
+6 -2
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.c
+226 -302
View File
File diff suppressed because it is too large Load Diff
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.h
+56 -30
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,7 +48,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexCAN driver version 2.2.0. */
#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/*! @brief FlexCAN Frame ID helper macro. */
@@ -68,24 +72,26 @@
(FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
(((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
(((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \
(((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
(((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
(((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
(((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
(((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
(((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
(((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
(((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
(((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
(((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
(((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
(FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
(((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
( \
((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
<< 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
(((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
@@ -119,9 +125,10 @@
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \
*/
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
@@ -130,9 +137,10 @@
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \
*/
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
@@ -363,11 +371,11 @@ typedef struct _flexcan_fd_frame
uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
uint32_t srr : 1; /*!< Substitute Remote request. */
uint32_t : 1;
uint32_t code : 4; /*!< Message Buffer Code. */
uint32_t code : 4; /*!< Message Buffer Code. */
uint32_t : 1;
uint32_t esi : 1; /*!< Error State Indicator. */
uint32_t brs : 1; /*!< Bit Rate Switch. */
uint32_t edl : 1; /*!< Extended Data Length. */
uint32_t esi : 1; /*!< Error State Indicator. */
uint32_t brs : 1; /*!< Bit Rate Switch. */
uint32_t edl : 1; /*!< Extended Data Length. */
};
struct
{
@@ -395,6 +403,23 @@ typedef struct _flexcan_fd_frame
} flexcan_fd_frame_t;
#endif
/*! @brief FlexCAN protocol timing characteristic configuration structure. */
typedef struct _flexcan_timing_config
{
uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
uint8_t rJumpwidth; /*!< Re-sync Jump Width. */
uint8_t phaseSeg1; /*!< Phase Segment 1. */
uint8_t phaseSeg2; /*!< Phase Segment 2. */
uint8_t propSeg; /*!< Propagation Segment. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */
uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */
uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */
uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */
uint8_t fpropSeg; /*!< Fast Propagation Segment. */
#endif
} flexcan_timing_config_t;
/*! @brief FlexCAN module configuration structure. */
typedef struct _flexcan_config
{
@@ -412,18 +437,9 @@ typedef struct _flexcan_config
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
bool enableDoze; /*!< Enable or Disable Doze Mode. */
#endif
flexcan_timing_config_t timingConfig; /* Protocol timing . */
} flexcan_config_t;
/*! @brief FlexCAN protocol timing characteristic configuration structure. */
typedef struct _flexcan_timing_config
{
uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
uint8_t rJumpwidth; /*!< Re-sync Jump Width. */
uint8_t phaseSeg1; /*!< Phase Segment 1. */
uint8_t phaseSeg2; /*!< Phase Segment 2. */
uint8_t propSeg; /*!< Propagation Segment. */
} flexcan_timing_config_t;
/*!
* @brief FlexCAN Receive Message Buffer configuration structure
*
@@ -510,6 +526,14 @@ extern "C" {
* @{
*/
/*!
* @brief Get the FlexCAN instance from peripheral base address.
*
* @param base FlexCAN peripheral base address.
* @return FlexCAN instance.
*/
uint32_t FLEXCAN_GetInstance(CAN_Type *base);
/*!
* @brief Initializes a FlexCAN instance.
*
@@ -525,6 +549,7 @@ extern "C" {
* flexcanConfig.enableSelfWakeup = false;
* flexcanConfig.enableIndividMask = false;
* flexcanConfig.enableDoze = false;
* flexcanConfig.timingConfig = timingConfig;
* FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL);
* @endcode
*
@@ -556,6 +581,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
* flexcanConfig->enableSelfWakeup = false;
* flexcanConfig->enableIndividMask = false;
* flexcanConfig->enableDoze = false;
* flexcanConfig.timingConfig = timingConfig;
*
* @param config Pointer to the FlexCAN configuration structure.
*/
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.c
+20 -11
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,12 +38,25 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio"
#endif
/*< @brief user configurable flexio handle count. */
#define FLEXIO_HANDLE_COUNT 2
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to flexio bases for each instance. */
FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to flexio clocks for each instance. */
const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*< @brief pointer to array of FLEXIO handle. */
static void *s_flexioHandle[FLEXIO_HANDLE_COUNT];
@@ -50,14 +67,6 @@ static void *s_flexioType[FLEXIO_HANDLE_COUNT];
/*< @brief pointer to array of FLEXIO Isr. */
static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to flexio clocks for each instance. */
const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointers to flexio bases for each instance. */
FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
/*******************************************************************************
* Codes
******************************************************************************/
@@ -178,7 +187,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
{
base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
| FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth)
#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
| FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) |
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.h
+28 -7
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -43,8 +47,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO driver version 2.0.1. */
#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief FlexIO driver version 2.0.2. */
#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief Calculate FlexIO timer trigger.*/
@@ -185,11 +189,11 @@ typedef enum _flexio_shifter_mode
kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */
kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */
kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE
#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
programmable state attributes. */
#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */
#if defined(FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE) && FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing
programmable logic look up table. */
#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */
@@ -290,7 +294,7 @@ typedef struct _flexio_shifter_config
flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */
/* Shifter. */
flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */
#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/
#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */
@@ -301,6 +305,16 @@ typedef struct _flexio_shifter_config
/*! @brief typedef for FlexIO simulated driver interrupt handler.*/
typedef void (*flexio_isr_t)(void *base, void *handle);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to flexio bases for each instance. */
extern FLEXIO_Type *const s_flexioBases[];
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to flexio clocks for each instance. */
extern const clock_ip_name_t s_flexioClocks[];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* API
******************************************************************************/
@@ -357,6 +371,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
*/
void FLEXIO_Deinit(FLEXIO_Type *base);
/*!
* @brief Get instance number for FLEXIO module.
*
* @param base FLEXIO peripheral base address.
*/
uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
/* @} */
/*!
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.c
+13 -11
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master"
#endif
/*! @brief FLEXIO I2C transfer state */
enum _flexio_i2c_master_transfer_states
{
@@ -45,18 +55,10 @@ enum _flexio_i2c_master_transfer_states
kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
};
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
extern const clock_ip_name_t s_flexioClocks[];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
extern FLEXIO_Type *const s_flexioBases[];
/*******************************************************************************
* Prototypes
******************************************************************************/
extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
/*!
* @brief Set up master transfer, send slave address and decide the initial
* transfer state.
@@ -97,7 +99,7 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
* Codes
******************************************************************************/
uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
{
return FLEXIO_GetInstance(base->flexioBase);
}
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.h
+8 -4
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,8 +48,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2C master driver version 2.1.2. */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @brief FlexIO I2C master driver version 2.1.5. */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*@}*/
/*! @brief FlexIO I2C transfer status*/
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.c
+13 -11
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_flexio_i2s.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@@ -43,8 +53,6 @@ enum _sai_transfer_state
* Prototypes
******************************************************************************/
extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
/*!
* @brief Receive a piece of data in non-blocking way.
*
@@ -68,17 +76,11 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
extern const clock_ip_name_t s_flexioClocks[];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
extern FLEXIO_Type *const s_flexioBases[];
/*******************************************************************************
* Code
******************************************************************************/
uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
{
return FLEXIO_GetInstance(base->flexioBase);
}
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.h
+8 -4
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,8 +48,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S driver version 2.1.1. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @brief FlexIO I2S driver version 2.1.4. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*@}*/
/*! @brief FlexIO I2S transfer status */
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.c
+13 -3
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,11 +34,17 @@
#include "fsl_flexio_i2s_edma.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
/* Used for 32byte aligned */
#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU)
#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU)
/*<! Structure definition for flexio_i2s_edma_private_handle_t. The structure is private. */
typedef struct _flexio_i2s_edma_private_handle
bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.h
+14 -3
View File
@@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,12 @@
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S EDMA driver version 2.1.4. */
#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*@}*/
typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;
/*! @brief FlexIO I2S eDMA transfer callback function for finish and error */
@@ -155,7 +165,8 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
* @brief Performs a non-blocking FlexIO I2S receive using eDMA.
*
* @note This interface returned immediately after transfer initiates. Users should call
* FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.
* FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is
* finished.
*
* @param base FlexIO I2S peripheral base address.
* @param handle FlexIO I2S DMA handle pointer.

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