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feat: libcpu/risc-v: unify mmu related works
These changes are designed to standardize the memory management across 'virt64' and 'c906', ensuring efficient handling of address spaces and page tables. Changes: - Creation of ASID management files (`asid.c`) for both 'c906' and 'virt64' architectures, which is essential for maintaining stability. - Extensive updates to the MMU configuration and handling in `mmu.c` and `mmu.h` files. - Addition of functions to manage ASID allocation and switching of page tables. - For c906, accommodated the early memory setup to the one from virt64. Signed-off-by: Shell <smokewood@qq.com>
This commit is contained in:
Shell
Meco Man
@@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-07-12 RT-Thread first version.
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*/
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#define DBG_TAG "hw.asid"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <rtthread.h>
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#include <board.h>
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#include <cache.h>
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#include <mm_aspace.h>
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#include <mm_page.h>
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#include <mmu.h>
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#include <riscv_mmu.h>
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#include <tlb.h>
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static rt_uint8_t ASID_BITS = 0;
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static rt_uint32_t next_asid;
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static rt_uint64_t global_asid_generation;
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#define ASID_MASK ((1 << ASID_BITS) - 1)
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#define ASID_FIRST_GENERATION (1 << ASID_BITS)
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#define MAX_ASID ASID_FIRST_GENERATION
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void rt_hw_asid_init(void)
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{
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unsigned int satp_reg = read_csr(satp);
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satp_reg |= (((rt_uint64_t)0xffff) << PPN_BITS);
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write_csr(satp, satp_reg);
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unsigned short valid_asid_bit = ((read_csr(satp) >> PPN_BITS) & 0xffff);
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// The maximal value of ASIDLEN, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57
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for (unsigned i = 0; i < 16; i++)
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{
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if (!(valid_asid_bit & 0x1))
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{
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break;
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}
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valid_asid_bit >>= 1;
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ASID_BITS++;
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}
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global_asid_generation = ASID_FIRST_GENERATION;
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next_asid = 1;
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}
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static rt_uint64_t _asid_acquire(rt_aspace_t aspace)
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{
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if ((aspace->asid ^ global_asid_generation) >> ASID_BITS) // not same generation
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{
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if (next_asid != MAX_ASID)
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{
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aspace->asid = global_asid_generation | next_asid;
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next_asid++;
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}
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else
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{
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// scroll to next generation
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global_asid_generation += ASID_FIRST_GENERATION;
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next_asid = 1;
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rt_hw_tlb_invalidate_all_local();
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aspace->asid = global_asid_generation | next_asid;
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next_asid++;
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}
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}
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return aspace->asid & ASID_MASK;
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}
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void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl)
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{
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rt_uint64_t asid = _asid_acquire(aspace);
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write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
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(asid << PPN_BITS) |
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((rt_ubase_t)pgtbl >> PAGE_OFFSET_BIT));
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asm volatile("sfence.vma x0,%0"::"r"(asid):"memory");
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}
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+85
-165
File diff suppressed because it is too large
Load Diff
@@ -30,7 +30,7 @@ struct mem_desc
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{
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rt_size_t vaddr_start;
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rt_size_t vaddr_end;
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rt_size_t paddr_start;
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rt_ubase_t paddr_start;
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rt_size_t attr;
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struct rt_varea varea;
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};
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@@ -43,8 +43,8 @@ struct mem_desc
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#define GET_PPN(pte) \
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(__PARTBIT(pte, PTE_PPN_SHIFT, PHYSICAL_ADDRESS_WIDTH_BITS - PTE_PPN_SHIFT))
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#define GET_PADDR(pte) (GET_PPN(pte) << PAGE_OFFSET_BIT)
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#define VPN_TO_PPN(vaddr, pv_off) (((rt_size_t)(vaddr)) + (pv_off))
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#define PPN_TO_VPN(paddr, pv_off) (((rt_size_t)(paddr)) - (pv_off))
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#define VPN_TO_PPN(vaddr, pv_off) (((rt_uintptr_t)(vaddr)) + (pv_off))
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#define PPN_TO_VPN(paddr, pv_off) (((rt_uintptr_t)(paddr)) - (pv_off))
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#define COMBINEVADDR(l1_off, l2_off, l3_off) \
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(((l1_off) << VPN2_SHIFT) | ((l2_off) << VPN1_SHIFT) | \
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((l3_off) << VPN0_SHIFT))
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@@ -57,11 +57,11 @@ struct mem_desc
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#define MMU_MAP_ERROR_CONFLICT -4
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void *rt_hw_mmu_tbl_get(void);
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int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_size_t size,
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rt_size_t *vtable, rt_size_t pv_off);
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int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_ubase_t size,
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rt_ubase_t *vtable, rt_ubase_t pv_off);
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void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr);
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void rt_hw_mmu_kernel_map_init(rt_aspace_t aspace, rt_size_t vaddr_start,
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rt_size_t size);
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void rt_hw_mmu_kernel_map_init(rt_aspace_t aspace, rt_ubase_t vaddr_start,
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rt_ubase_t size);
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void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
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size_t attr);
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void rt_hw_mmu_unmap(rt_aspace_t aspace, void *v_addr, size_t size);
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@@ -20,10 +20,10 @@
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void mmu_enable_user_page_access(void)
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{
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set_csr(sstatus,SSTATUS_SUM);
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set_csr(sstatus, SSTATUS_SUM);
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}
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void mmu_disable_user_page_access(void)
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{
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clear_csr(sstatus,SSTATUS_SUM);
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clear_csr(sstatus, SSTATUS_SUM);
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -20,29 +20,30 @@
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#undef PAGE_SIZE
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/* C-SKY extend */
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#define PTE_SEC (1UL << 59) /* Security */
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#define PTE_SHARE (1UL << 60) /* Shareable */
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#define PTE_BUF (1UL << 61) /* Bufferable */
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#define PTE_CACHE (1UL << 62) /* Cacheable */
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#define PTE_SO (1UL << 63) /* Strong Order */
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#define PTE_SEC (1UL << 59) /* Security */
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#define PTE_SHARE (1UL << 60) /* Shareable */
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#define PTE_BUF (1UL << 61) /* Bufferable */
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#define PTE_CACHE (1UL << 62) /* Cacheable */
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#define PTE_SO (1UL << 63) /* Strong Order */
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
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#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define VPN0_BIT 9
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#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
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#define VPN1_BIT 9
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#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
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#define VPN2_BIT 9
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
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#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define VPN0_BIT 9
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#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
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#define VPN1_BIT 9
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#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
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#define VPN2_BIT 9
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#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define PPN0_BIT 9
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#define PPN0_BIT 9
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#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT)
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#define PPN1_BIT 9
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#define PPN1_BIT 9
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#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT)
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#define PPN2_BIT 26
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#define PPN2_BIT 26
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#define PPN_BITS (PPN0_BIT + PPN1_BIT + PPN2_BIT)
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#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT)
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#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT)
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@@ -52,71 +53,79 @@
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#define PHYSICAL_ADDRESS_WIDTH_BITS 56
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#define PAGE_ATTR_NEXT_LEVEL (0)
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#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
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#define PAGE_ATTR_READONLY (PTE_R)
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#define PAGE_ATTR_XN (PTE_W | PTE_R)
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#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
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#define PAGE_ATTR_NEXT_LEVEL (0)
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#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
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#define PAGE_ATTR_READONLY (PTE_R)
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#define PAGE_ATTR_XN (PTE_W | PTE_R)
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#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
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#define PAGE_ATTR_USER (PTE_U)
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#define PAGE_ATTR_USER (PTE_U)
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#define PAGE_ATTR_SYSTEM (0)
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#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
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#define PAGE_ATTR_DEV (PTE_SO)
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#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
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#define PAGE_ATTR_DEV (PTE_SO)
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#define PAGE_DEFAULT_ATTR_LEAF (PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define PAGE_DEFAULT_ATTR_NEXT (PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
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#define PAGE_DEFAULT_ATTR_LEAF \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
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PAGE_ATTR_RWX | PTE_V)
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#define PAGE_DEFAULT_ATTR_NEXT \
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(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
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#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
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#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
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#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
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#define PTE_WRAP(attr) (attr | PTE_A | PTE_D)
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/**
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* encoding of SATP (Supervisor Address Translation and Protection register)
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*/
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#define SATP_MODE_OFFSET 60
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#define SATP_MODE_BARE 0
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define SATP_MODE_OFFSET 60
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#define SATP_MODE_BARE 0
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define PPN_BITS 44
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#define ARCH_VADDR_WIDTH 39
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#define SATP_MODE SATP_MODE_SV39
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#define ARCH_VADDR_WIDTH 39
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#define SATP_MODE SATP_MODE_SV39
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#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_ROCB \
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PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_READONLY | PTE_V)
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#define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_EARLY \
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PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
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#define MMU_MAP_TRACE(attr) (attr)
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#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_U_ROCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_READONLY | PTE_V)
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#define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V)
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#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
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#define MMU_MAP_TRACE(attr) (attr)
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#define PTE_XWR_MASK 0xe
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#define PTE_XWR_MASK 0xe
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#define ARCH_PAGE_SIZE PAGE_SIZE
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
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#define ARCH_INDEX_WIDTH 9
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#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
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#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
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#define ARCH_PAGE_SIZE PAGE_SIZE
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
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#define ARCH_INDEX_WIDTH 9
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#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
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#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
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#define ARCH_MAP_FAILED ((void *)0x8000000000000000)
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#define ARCH_MAP_FAILED ((void *)0x8000000000000000)
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void mmu_set_pagetable(rt_ubase_t addr);
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void mmu_enable_user_page_access(void);
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void mmu_disable_user_page_access(void);
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#define RT_HW_MMU_PROT_READ 1
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#define RT_HW_MMU_PROT_WRITE 2
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#define RT_HW_MMU_PROT_READ 1
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#define RT_HW_MMU_PROT_WRITE 2
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#define RT_HW_MMU_PROT_EXECUTE 4
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#define RT_HW_MMU_PROT_KERNEL 8
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#define RT_HW_MMU_PROT_USER 16
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#define RT_HW_MMU_PROT_CACHE 32
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#define RT_HW_MMU_PROT_KERNEL 8
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#define RT_HW_MMU_PROT_USER 16
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#define RT_HW_MMU_PROT_CACHE 32
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void rt_hw_asid_init(void);
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struct rt_aspace;
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void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl);
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/**
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* @brief Remove permission from attribution
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@@ -20,7 +20,7 @@
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#define HANDLE_FAULT(ret) \
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if (__builtin_expect((ret) != SBI_SUCCESS, 0)) \
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LOG_W("%s failed\n", __FUNCTION__);
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LOG_W("%s failed", __FUNCTION__);
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static inline void rt_hw_tlb_invalidate_all(void)
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{
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@@ -0,0 +1,85 @@
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/*
|
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* Copyright (c) 2006-2024, RT-Thread Development Team
|
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*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
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*
|
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* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-07-12 RT-Thread first version.
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*/
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#define DBG_TAG "hw.asid"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <rtthread.h>
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#include <board.h>
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#include <cache.h>
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#include <mm_aspace.h>
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#include <mm_page.h>
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#include <mmu.h>
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#include <riscv_mmu.h>
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#include <tlb.h>
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static rt_uint8_t ASID_BITS = 0;
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static rt_uint32_t next_asid;
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static rt_uint64_t global_asid_generation;
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#define ASID_MASK ((1 << ASID_BITS) - 1)
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#define ASID_FIRST_GENERATION (1 << ASID_BITS)
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#define MAX_ASID ASID_FIRST_GENERATION
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void rt_hw_asid_init(void)
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{
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unsigned int satp_reg = read_csr(satp);
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satp_reg |= (((rt_uint64_t)0xffff) << PPN_BITS);
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write_csr(satp, satp_reg);
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unsigned short valid_asid_bit = ((read_csr(satp) >> PPN_BITS) & 0xffff);
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|
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// The maximal value of ASIDLEN, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57
|
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for (unsigned i = 0; i < 16; i++)
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{
|
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if (!(valid_asid_bit & 0x1))
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{
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break;
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}
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valid_asid_bit >>= 1;
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ASID_BITS++;
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}
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global_asid_generation = ASID_FIRST_GENERATION;
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next_asid = 1;
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}
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static rt_uint64_t _asid_acquire(rt_aspace_t aspace)
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{
|
||||
if ((aspace->asid ^ global_asid_generation) >> ASID_BITS) // not same generation
|
||||
{
|
||||
if (next_asid != MAX_ASID)
|
||||
{
|
||||
aspace->asid = global_asid_generation | next_asid;
|
||||
next_asid++;
|
||||
}
|
||||
else
|
||||
{
|
||||
// scroll to next generation
|
||||
global_asid_generation += ASID_FIRST_GENERATION;
|
||||
next_asid = 1;
|
||||
rt_hw_tlb_invalidate_all_local();
|
||||
|
||||
aspace->asid = global_asid_generation | next_asid;
|
||||
next_asid++;
|
||||
}
|
||||
}
|
||||
|
||||
return aspace->asid & ASID_MASK;
|
||||
}
|
||||
|
||||
void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl)
|
||||
{
|
||||
rt_uint64_t asid = _asid_acquire(aspace);
|
||||
write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
|
||||
(asid << PPN_BITS) |
|
||||
((rt_ubase_t)pgtbl >> PAGE_OFFSET_BIT));
|
||||
asm volatile("sfence.vma x0,%0"::"r"(asid):"memory");
|
||||
}
|
||||
|
||||
+47
-27
@@ -43,6 +43,16 @@ static void *current_mmu_table = RT_NULL;
|
||||
volatile __attribute__((aligned(4 * 1024)))
|
||||
rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
|
||||
|
||||
#ifdef ARCH_USING_ASID
|
||||
void rt_hw_aspace_switch(rt_aspace_t aspace)
|
||||
{
|
||||
uintptr_t page_table = (uintptr_t)rt_kmem_v2p(aspace->page_table);
|
||||
current_mmu_table = aspace->page_table;
|
||||
|
||||
rt_hw_asid_switch_pgtbl(aspace, page_table);
|
||||
}
|
||||
|
||||
#else /* !ARCH_USING_ASID */
|
||||
void rt_hw_aspace_switch(rt_aspace_t aspace)
|
||||
{
|
||||
uintptr_t page_table = (uintptr_t)rt_kmem_v2p(aspace->page_table);
|
||||
@@ -53,6 +63,11 @@ void rt_hw_aspace_switch(rt_aspace_t aspace)
|
||||
rt_hw_tlb_invalidate_all_local();
|
||||
}
|
||||
|
||||
void rt_hw_asid_init(void)
|
||||
{
|
||||
}
|
||||
#endif /* ARCH_USING_ASID */
|
||||
|
||||
void *rt_hw_mmu_tbl_get()
|
||||
{
|
||||
return current_mmu_table;
|
||||
@@ -246,8 +261,7 @@ void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size)
|
||||
MM_PGTBL_UNLOCK(aspace);
|
||||
|
||||
// when unmapped == 0, region not exist in pgtbl
|
||||
if (!unmapped || unmapped > size)
|
||||
break;
|
||||
if (!unmapped || unmapped > size) break;
|
||||
|
||||
size -= unmapped;
|
||||
v_addr += unmapped;
|
||||
@@ -260,7 +274,8 @@ static inline void _init_region(void *vaddr, size_t size)
|
||||
rt_ioremap_start = vaddr;
|
||||
rt_ioremap_size = size;
|
||||
rt_mpr_start = rt_ioremap_start - rt_mpr_size;
|
||||
LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start, rt_mpr_start);
|
||||
LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start,
|
||||
rt_mpr_start);
|
||||
}
|
||||
#else
|
||||
static inline void _init_region(void *vaddr, size_t size)
|
||||
@@ -270,11 +285,11 @@ static inline void _init_region(void *vaddr, size_t size)
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SMART) && defined(ARCH_REMAP_KERNEL)
|
||||
#define KERN_SPACE_START ((void *)KERNEL_VADDR_START)
|
||||
#define KERN_SPACE_SIZE (0xfffffffffffff000UL - KERNEL_VADDR_START + 0x1000)
|
||||
#define KERN_SPACE_START ((void *)KERNEL_VADDR_START)
|
||||
#define KERN_SPACE_SIZE (0xfffffffffffff000UL - KERNEL_VADDR_START + 0x1000)
|
||||
#else
|
||||
#define KERN_SPACE_START ((void *)0x1000)
|
||||
#define KERN_SPACE_SIZE ((size_t)USER_VADDR_START - 0x1000)
|
||||
#define KERN_SPACE_START ((void *)0x1000)
|
||||
#define KERN_SPACE_SIZE ((size_t)USER_VADDR_START - 0x1000)
|
||||
#endif
|
||||
|
||||
int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_ubase_t size,
|
||||
@@ -393,6 +408,7 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s: failed at %p", __func__, vaddr);
|
||||
paddr = (uintptr_t)ARCH_MAP_FAILED;
|
||||
}
|
||||
return (void *)paddr;
|
||||
@@ -467,25 +483,25 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
|
||||
size_t attr;
|
||||
switch (mdesc->attr)
|
||||
{
|
||||
case NORMAL_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case NORMAL_NOCACHE_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case DEVICE_MEM:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
break;
|
||||
default:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
case NORMAL_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case NORMAL_NOCACHE_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case DEVICE_MEM:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
break;
|
||||
default:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
}
|
||||
|
||||
struct rt_mm_va_hint hint = {.flags = MMF_MAP_FIXED,
|
||||
.limit_start = aspace->start,
|
||||
.limit_range_size = aspace->size,
|
||||
.map_size = mdesc->vaddr_end -
|
||||
mdesc->vaddr_start + 1,
|
||||
.prefer = (void *)mdesc->vaddr_start};
|
||||
struct rt_mm_va_hint hint = {
|
||||
.flags = MMF_MAP_FIXED,
|
||||
.limit_start = aspace->start,
|
||||
.limit_range_size = aspace->size,
|
||||
.map_size = mdesc->vaddr_end - mdesc->vaddr_start + 1,
|
||||
.prefer = (void *)mdesc->vaddr_start};
|
||||
|
||||
if (mdesc->paddr_start == (rt_uintptr_t)ARCH_MAP_FAILED)
|
||||
mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
|
||||
@@ -495,6 +511,8 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
|
||||
mdesc++;
|
||||
}
|
||||
|
||||
rt_hw_asid_init();
|
||||
|
||||
rt_hw_aspace_switch(&rt_kernel_space);
|
||||
rt_page_cleanup();
|
||||
}
|
||||
@@ -520,16 +538,18 @@ void rt_hw_mem_setup_early(void)
|
||||
{
|
||||
if (pv_off & (1ul << (ARCH_INDEX_WIDTH * 2 + ARCH_PAGE_SHIFT)))
|
||||
{
|
||||
LOG_E("%s: not aligned virtual address. pv_offset %p", __func__, pv_off);
|
||||
LOG_E("%s: not aligned virtual address. pv_offset %p", __func__,
|
||||
pv_off);
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/**
|
||||
* identical mapping,
|
||||
* PC are still at lower region before relocating to high memory
|
||||
*/
|
||||
for (size_t i = 0; i < __SIZE(PPN0_BIT); i++)
|
||||
{
|
||||
early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V);
|
||||
early_pgtbl[i] = COMBINEPTE(ps, MMU_MAP_EARLY);
|
||||
ps += L1_PAGE_SIZE;
|
||||
}
|
||||
|
||||
@@ -543,7 +563,7 @@ void rt_hw_mem_setup_early(void)
|
||||
rt_ubase_t ve_idx = GET_L1(vs + 0x80000000);
|
||||
for (size_t i = vs_idx; i < ve_idx; i++)
|
||||
{
|
||||
early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V);
|
||||
early_pgtbl[i] = COMBINEPTE(ps, MMU_MAP_EARLY);
|
||||
ps += L1_PAGE_SIZE;
|
||||
}
|
||||
|
||||
|
||||
@@ -11,10 +11,10 @@
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <riscv.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <riscv.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "riscv_mmu.h"
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -19,22 +19,23 @@
|
||||
#undef PAGE_SIZE
|
||||
|
||||
#define PAGE_OFFSET_SHIFT 0
|
||||
#define PAGE_OFFSET_BIT 12
|
||||
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
|
||||
#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
|
||||
#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
|
||||
#define VPN0_BIT 9
|
||||
#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
|
||||
#define VPN1_BIT 9
|
||||
#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
|
||||
#define VPN2_BIT 9
|
||||
#define PAGE_OFFSET_BIT 12
|
||||
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
|
||||
#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
|
||||
#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
|
||||
#define VPN0_BIT 9
|
||||
#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
|
||||
#define VPN1_BIT 9
|
||||
#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
|
||||
#define VPN2_BIT 9
|
||||
|
||||
#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
|
||||
#define PPN0_BIT 9
|
||||
#define PPN0_BIT 9
|
||||
#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT)
|
||||
#define PPN1_BIT 9
|
||||
#define PPN1_BIT 9
|
||||
#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT)
|
||||
#define PPN2_BIT 26
|
||||
#define PPN2_BIT 26
|
||||
#define PPN_BITS (PPN0_BIT + PPN1_BIT + PPN2_BIT)
|
||||
|
||||
#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT)
|
||||
#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT)
|
||||
@@ -44,12 +45,12 @@
|
||||
|
||||
#define PHYSICAL_ADDRESS_WIDTH_BITS 56
|
||||
|
||||
#define PAGE_ATTR_NEXT_LEVEL (0)
|
||||
#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
|
||||
#define PAGE_ATTR_READONLY (PTE_R)
|
||||
#define PAGE_ATTR_NEXT_LEVEL (0)
|
||||
#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
|
||||
#define PAGE_ATTR_READONLY (PTE_R)
|
||||
#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
|
||||
|
||||
#define PAGE_ATTR_USER (PTE_U)
|
||||
#define PAGE_ATTR_USER (PTE_U)
|
||||
#define PAGE_ATTR_SYSTEM (0)
|
||||
|
||||
#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G)
|
||||
@@ -62,44 +63,49 @@
|
||||
/**
|
||||
* encoding of SATP (Supervisor Address Translation and Protection register)
|
||||
*/
|
||||
#define SATP_MODE_OFFSET 60
|
||||
#define SATP_MODE_BARE 0
|
||||
#define SATP_MODE_SV39 8
|
||||
#define SATP_MODE_SV48 9
|
||||
#define SATP_MODE_SV57 10
|
||||
#define SATP_MODE_SV64 11
|
||||
#define SATP_MODE_OFFSET 60
|
||||
#define SATP_MODE_BARE 0
|
||||
#define SATP_MODE_SV39 8
|
||||
#define SATP_MODE_SV48 9
|
||||
#define SATP_MODE_SV57 10
|
||||
#define SATP_MODE_SV64 11
|
||||
|
||||
#define ARCH_VADDR_WIDTH 39
|
||||
#define SATP_MODE SATP_MODE_SV39
|
||||
#define ARCH_VADDR_WIDTH 39
|
||||
#define SATP_MODE SATP_MODE_SV39
|
||||
|
||||
#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RW (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RW (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_EARLY (PAGE_ATTR_RWX | PTE_G | PTE_V)
|
||||
|
||||
#define PTE_XWR_MASK 0xe
|
||||
#define PTE_XWR_MASK 0xe
|
||||
|
||||
#define ARCH_PAGE_SIZE PAGE_SIZE
|
||||
#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
|
||||
#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
|
||||
#define ARCH_INDEX_WIDTH 9
|
||||
#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
|
||||
#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
|
||||
#define ARCH_PAGE_SIZE PAGE_SIZE
|
||||
#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
|
||||
#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
|
||||
#define ARCH_INDEX_WIDTH 9
|
||||
#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
|
||||
#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
|
||||
|
||||
#define ARCH_MAP_FAILED ((void *)-1)
|
||||
#define ARCH_MAP_FAILED ((void *)-1)
|
||||
|
||||
void mmu_set_pagetable(rt_ubase_t addr);
|
||||
void mmu_enable_user_page_access(void);
|
||||
void mmu_disable_user_page_access(void);
|
||||
|
||||
#define RT_HW_MMU_PROT_READ 1
|
||||
#define RT_HW_MMU_PROT_WRITE 2
|
||||
#define RT_HW_MMU_PROT_READ 1
|
||||
#define RT_HW_MMU_PROT_WRITE 2
|
||||
#define RT_HW_MMU_PROT_EXECUTE 4
|
||||
#define RT_HW_MMU_PROT_KERNEL 8
|
||||
#define RT_HW_MMU_PROT_USER 16
|
||||
#define RT_HW_MMU_PROT_CACHE 32
|
||||
#define RT_HW_MMU_PROT_KERNEL 8
|
||||
#define RT_HW_MMU_PROT_USER 16
|
||||
#define RT_HW_MMU_PROT_CACHE 32
|
||||
|
||||
void rt_hw_asid_init(void);
|
||||
struct rt_aspace;
|
||||
void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl);
|
||||
|
||||
/**
|
||||
* @brief Remove permission from attribution
|
||||
|
||||
Reference in New Issue
Block a user