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[bsp] add core-v-mcu bsp (#6705)

Browse Source 
* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>
This commit is contained in:
Yaochenger
2022-12-08 15:01:37 -05:00
committed by GitHub
co-authored by 1516081466@qq.com
parent ab9a80c408
commit 9d8da76543
137 changed files with 24743 additions and 0 deletions
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bsp/core-v-mcu/Libraries/Kconfig
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config SOC_RISCV_FAMILY_Core_V
bool
config SOC_RISCV_SERIES_Core_V
bool
select ARCH_RISCV
select SOC_RISCV_FAMILY_Core_V
bsp/core-v-mcu/Libraries/core_v_drivers/SConscript
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import rtconfig
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Split("""
source/udma_uart_driver.c
""")
if GetDepend('SOC_RISCV_FAMILY_Core_V'):
if GetDepend('BSP_USING_UART'):
src += ['source/drv_usart.c']
path = [
cwd + '/include']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
bsp/core-v-mcu/Libraries/core_v_drivers/include/camera.h
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#ifndef __CAMERA_H__
#define __CAMERA_H__
//#include <FreeRTOS.h>
#include <queue.h>
#include "himax.h"
typedef struct {
volatile uint32_t *rx_saddr; // 0x00
volatile uint32_t rx_size; // 0x04
volatile uint32_t rx_cfg; // 0x08
volatile uint32_t rx_initcfg;// 0x0C
volatile uint32_t *tx_saddr; // 0x10
volatile uint32_t tx_size; // 0x14
volatile uint32_t tx_cfg; // 0x18
volatile uint32_t tx_initcfg;// 0x1C
volatile uint32_t cfg_glob; // 0x20
volatile uint32_t cfg_ll; // 0x24
volatile uint32_t cfg_ur; // 0x28
volatile uint32_t cfg_size; // 0x2C
volatile uint32_t cfg_filter;// 0x30
volatile uint32_t vsync_pol; // 0x34
} camera_struct_t;
typedef struct {
uint16_t addr;
uint8_t data;
}reg_cfg_t;
#endif
bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_log.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_usart.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun the first version
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
/* corev config class */
struct corev_uart_config
{
const char *name;
};
/* corevs uart dirver class */
struct corev_uart
{
struct corev_uart_config *config;
struct rt_serial_device serial;
};
extern void uart_rx_isr (void *id);
int rt_hw_usart_init(void);
#endif
bsp/core-v-mcu/Libraries/core_v_drivers/include/himax.h
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/*
* Copyright (C) 2018 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Copyright (C) 2018 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HIMAX_H__
#define __HIMAX_H__
/*
* HIMAX camera macros
*/
// Register address
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define FRAME_COUNT 0x0005
#define PIXEL_ORDER 0x0006
// R&W registers
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define SW_RESET 0x0103
#define GRP_PARAM_HOLD 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Binning mode control
#define READOUT_X 0x0383
#define READOUT_Y 0x0387
#define BINNING_MODE 0x0390
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_CFG 0x1000
#define BLC_TGT 0x1003
#define BLI_EN 0x1006
#define BLC2_TGT 0x1007
// Sensor reserved
#define DPC_CTRL 0x1008
#define SINGLE_THR_HOT 0x100B
#define SINGLE_THR_COLD 0x100C
// VSYNC,HSYNC and pixel shift register
#define VSYNC_HSYNC_PIXEL_SHIFT_EN 0x1012
// Automatic exposure gain control
#define AE_CTRL 0x2100
#define AE_TARGET_MEAN 0x2101
#define AE_MIN_MEAN 0x2102
#define CONVERGE_IN_TH 0x2103
#define CONVERGE_OUT_TH 0x2104
#define MAX_INTG_H 0x2105
#define MAX_INTG_L 0x2106
#define MIN_INTG 0x2107
#define MAX_AGAIN_FULL 0x2108
#define MAX_AGAIN_BIN2 0x2109
#define MIN_AGAIN 0x210A
#define MAX_DGAIN 0x210B
#define MIN_DGAIN 0x210C
#define DAMPING_FACTOR 0x210D
#define FS_CTRL 0x210E
#define FS_60HZ_H 0x210F
#define FS_60HZ_L 0x2110
#define FS_50HZ_H 0x2111
#define FS_50HZ_L 0x2112
#define FS_HYST_TH 0x2113
// Motion detection control
#define MD_CTRL 0x2150
#define I2C_CLEAR 0x2153
#define WMEAN_DIFF_TH_H 0x2155
#define WMEAN_DIFF_TH_M 0x2156
#define WMEAN_DIFF_TH_L 0x2157
#define MD_THH 0x2158
#define MD_THM1 0x2159
#define MD_THM2 0x215A
#define MD_THL 0x215B
// Sensor timing control
#define QVGA_WIN_EN 0x3010
#define SIX_BIT_MODE_EN 0x3011
#define PMU_AUTOSLEEP_FRAMECNT 0x3020
#define ADVANCE_VSYNC 0x3022
#define ADVANCE_HSYNC 0x3023
#define EARLY_GAIN 0x3035
// IO and clock control
#define BIT_CONTROL 0x3059
#define OSC_CLK_DIV 0x3060
#define ANA_Register_11 0x3061
#define IO_DRIVE_STR 0x3062
#define IO_DRIVE_STR2 0x3063
#define ANA_Register_14 0x3064
#define OUTPUT_PIN_STATUS_CONTROL 0x3065
#define ANA_Register_17 0x3067
#define PCLK_POLARITY 0x3068
/*
* Useful value of Himax registers
*/
#define HIMAX_RESET 0x01
#define Pclk_rising_edge 0x00
#define Pclk_falling_edge 0x01
#define BYPASS_BIGEND 5
enum{
HIMAX_Standby = 0x0,
HIMAX_Streaming = 0x1, // I2C triggered streaming enable
HIMAX_Streaming2 = 0x3, // Output N frames
HIMAX_Streaming3 = 0x5 // Hardware Trigger
};
#endif
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_cam_driver.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_cam_reg_defs.h"
typedef enum {
kCamReset,
kCamID,
kCamInit,
kCamFrame
} udma_cam_control_type_t;
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} cam_cmd_t;
uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam);
void cam_open (uint8_t cam_id);
// helper functions
void _himaxRegWrite(unsigned int addr, unsigned char value);
#endif /* DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_ */
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_i2cm_driver.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
#define SEMAPHORE_WAIT_TIME_IN_MS 10
typedef enum {
kI2cmReset
} udma_i2cm_control_type_t;
typedef enum {
kI2cmCmdStart = 0x00,
kI2cmCmdStop = 0x20,
kI2cmCmdRdAck = 0x40,
kI2cmCmdRdNack = 0x60,
kI2cmCmdWr = 0x80,
kI2cmCmdWait = 0xA0,
kI2cmCmdRpt = 0xC0,
kI2cmCmdCfg = 0xE0,
kI2cmCmdWaitEvt = 0x10,
} i2cm_cmd_t;
uint16_t udma_i2cm_open (uint8_t i2c_id, uint32_t i2c_clk_freq);
uint16_t udma_i2cm_close (uint8_t i2c_id);
uint16_t udma_i2cm_control(uint8_t i2c_id, udma_i2cm_control_type_t control_type, void* pparam);
uint8_t udma_i2cm_write(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t write_len, uint8_t* write_data, bool more_follows);
uint8_t udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
uint8_t udma_i2cm_16read8(uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
// helper functions
uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr);
uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr);
uint8_t _udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
uint8_t _udma_i2cm_send_stop(uint8_t i2c_id);
#endif /* DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_ */
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_qspi_driver.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kQSPImReset
} udma_qspim_control_type_t;
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} spim_cmd_t;
uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t spi_clk_freq);
uint16_t udma_qspim_close (uint8_t qspim_id);
uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam);
void udma_qspim_write(uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd);
uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs);
void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs);
uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs);
// helper functions
#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_sdio_driver.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kSDIOmReset
} udma_sdio_control_type_t;
/*
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} spim_cmd_t;
*/
uint16_t udma_sdio_open (uint8_t sdio_id);
uint16_t udma_sdio_close (uint8_t sdio_id);
uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam);
uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf);
void udma_sdio_write(uint8_t sdio_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
void udma_sdio_read(uint8_t sdio_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_flash_erase(uint8_t sdio_id, uint8_t cs, uint32_t addr, uint8_t cmd);
uint32_t udma_flash_readid(uint8_t sdio_id, uint8_t cs);
void udma_flash_read(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
void udma_flash_write(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
uint32_t udma_flash_reset_enable(uint8_t sdio_id, uint8_t cs);
uint32_t udma_flash_reset_memory(uint8_t sdio_id, uint8_t cs);
uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
void udma_sdio_clearDataSetup(uint8_t sdio_id);
// helper functions
#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_uart_driver.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __UDMA_UART_DRIVER_H_
#define __UDMA_UART_DRIVER_H_
#include "stdint.h"
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kUartDataValid
} udma_uart_control_type_t;
uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate);
uint16_t udma_uart_close (uint8_t uart_id);
uint16_t udma_uart_write(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_uart_getchar(uint8_t uart_id);
uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam);
#endif //__UDMA_UART_DRIVER_H_
bsp/core-v-mcu/Libraries/core_v_drivers/source/drv_usart.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun the first version
*/
#include "board.h"
#include <rtdevice.h>
#include <drv_usart.h>
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_uart_reg_defs.h"
#include "udma_uart_driver.h"
#include <string.h>
#include "core-v-mcu-config.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.uart"
#include <drv_log.h>
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
!defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
extern char u1buffer[128], u0buffer[128];
extern int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
extern UdmaUart_t *puart0 ;
extern UdmaUart_t *puart1 ;
enum
{
UART1_INDEX,
};
struct corev_uart_config uart_config[1] =
{
{
"uart1"
}
};
struct corev_uart uart_obj[1] = {0};
static rt_err_t corev_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
return RT_EOK;
}
static rt_err_t corev_control(struct rt_serial_device *serial, int cmd, void *arg)
{
return RT_EOK;
}
uint16_t rt_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->status_b.tx_busy) {
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1;
return 0;
}
static int corev_putc(struct rt_serial_device *serial, char c)
{
char put_data =c;
struct corev_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct corev_uart *)serial->parent.user_data;
rt_writeraw(0, 1,&put_data);
return 1;
}
static int corev_getc(struct rt_serial_device *serial)
{
signed char ch;
struct corev_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct corev_uart *)serial->parent.user_data;
ch = -1;
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + 0 * UDMA_CH_SIZE);
if (puart->valid_b.rx_data_valid == 1) {
ch = puart->data_b.rx_data & 0xff;
}
return (int)ch;
}
rt_size_t corevdma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
return RT_EOK;
}
void uart_isr(struct rt_serial_device *serial)
{
struct corev_uart *uart = (struct corev_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
static const struct rt_uart_ops corev_uart_ops =
{
corev_configure,
corev_control,
corev_putc,
corev_getc,
corevdma_transmit
};
void uart_rx_isr (void *id){
rt_interrupt_enter();
if (id == 6) {
while (*(int*)0x1a102130) {
u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
u1wrptr &= 0x7f;
}
}
if (id == 2) {//use this uart
while (puart0->valid) {
uart_isr(&(uart_obj[UART1_INDEX].serial));
}
}
rt_interrupt_leave();
}
int rt_hw_usart_init(void)
{
rt_size_t obj_num = 1;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &corev_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
,&uart_obj[i]);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_cam_driver.c
+240
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bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_i2cm_driver.c
+355
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bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_qspi_driver.c
+686
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bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_sdio_driver.c
+266
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bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_uart_driver.c
+217
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript
+31
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@@ -0,0 +1,31 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
src = Split("""
core_v_hal/source/hal_apb_i2cs.c
core_v_hal/source/hal_fc_event.c
core_v_hal/source/hal_fll.c
core_v_hal/source/hal_fll_pi.c
core_v_hal/source/hal_gpio.c
core_v_hal/source/hal_gpio_pulp.c
core_v_hal/source/hal_irq.c
core_v_hal/source/hal_pinmux.c
core_v_hal/source/hal_pinmux1.c
core_v_hal/source/hal_soc_eu.c
core_v_hal/source/hal_timer_irq.c
bmsis/core-v-mcu/source/core-v-mcu.c
bmsis/core-v-mcu/source/crt0.S
bmsis/core-v-mcu/source/vectors.S
""")
path = [
cwd + '/bmsis/core-v-mcu/include',
cwd + '/core_v_hal/include']
group = DefineGroup('core_v_hal_lib', src, depend = [''], CPPPATH = path)
Return('group')
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/bits.h
+58
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/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __BITS_H
#define __BITS_H
#include <stdbool.h>
/* Helper to pass a int as a pointer or vice-versa. */
#define POINTER_TO_UINT(x) ((uintptr_t) (x))
#define UINT_TO_POINTER(x) ((void *) (uintptr_t) (x))
#define POINTER_TO_INT(x) ((intptr_t) (x))
#define INT_TO_POINTER(x) ((void *) (intptr_t) (x))
#if !(defined (__CHAR_BIT__) && defined (__SIZEOF_LONG__))
# error Missing required predefined macros for BITS_PER_LONG calculation
#endif
#define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__)
/* Create a contiguous bitmask starting at bit position @l and ending at
* position @h.
*/
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
/* KB, MB, GB */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)
#define GB(x) (MB(x) << 10)
/* KHZ, MHZ */
#define KHZ(x) ((x) * 1000)
#define MHZ(x) (KHZ(x) * 1000)
#ifndef BIT
#if defined(_ASMLANGUAGE)
#define BIT(n) (1 << (n))
#else
#define BIT(n) (1UL << (n))
#endif
#endif
/**
* @brief Macro sets or clears bit depending on boolean value
*
* @param var Variable to be altered
* @param bit Bit number
* @param set Value 0 clears bit, any other value sets bit
*/
#define WRITE_BIT(var, bit, set) \
((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
#define BIT_MASK(n) (BIT(n) - 1)
#endif
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-config.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-events.h
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/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
#include "core-v-mcu-properties.h"
/* Events offsets. */
#define UDMA_EVENT_OFFSET_RX (0U)
#define UDMA_EVENT_OFFSET_TX (1U)
#define EVENT_UART_RX (2U)
#define EVENT_UART_ERR (3U)
#define UDMA_EVENT_OFFSET_SPI_CMD (2)
#define UDMA_EVENT_OFFSET_SPI_EOT (3)
/* Number of events per peripheral. */
#define UDMA_CHANNEL_NB_EVENTS_LOG2 (2)
#define UDMA_CHANNEL_NB_EVENTS (1 << UDMA_CHANNEL_NB_EVENTS_LOG2)
/* Number of SW events. */
#define NB_SW_EVENTS (8)
/*! @brief FC events (aka IRQ lines)*/
#define FC_EVENT_SW(id) (id & (NB_SW_EVENTS - 1))
#define FC_EVENT_DMA_EVT (8)
#define FC_EVENT_DMA (9)
#define FC_EVENT_TIMER0 (10) /* Timer low. */
#define SYSTICK_IRQN FC_EVENT_TIMER0
#define FC_EVENT_TIMER1 (11) /* Timer high. */
/* #define FC_EVENT_EU_HWCE (12) */
/*
* SoC event unit events: Many events get implicitely muxed into this interrupt.
* A user that gets such an interrupt has to check the event unit's registers to
* see what happened
*/
#define FC_EVENT_SOC_EVENT (27)
/* #define FC_EVENT_MPU_ERROR (28) */
/*
* Event queue error: If we don't process event unit events quickly enough
* internal fifos can overflow and we get this error interrupt
*/
#define FC_EVENT_FC_QUEUE_ERROR (29)
#define FC_EVENT_HP0 runn (30)
#define FC_EVENT_HP1 (31)
/*! @name SoC events */
/*! @brief Number of FC_Events. */
#define SOC_EU_NB_FC_EVENTS (168)
/*! @brief UDMA events */
/* SPIM */
#define SOC_EVENT_UDMA_SPIM_RX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_SPIM_TX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
#define SOC_EVENT_UDMA_SPIM_CMD(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_CMD)
#define SOC_EVENT_UDMA_SPIM_EOT(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_EOT)
/* HYPER */
/* #define SOC_EVENT_UDMA_HYPER_RX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
/* #define SOC_EVENT_UDMA_HYPER_TX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
/* UART */
#define SOC_EVENT_UDMA_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_UART_TX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
#define SOC_EVENT_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_RX)
#define SOC_EVENT_UART_ERR(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_ERR)
/* I2C */
#define SOC_EVENT_UDMA_I2C_RX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_I2C_TX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
/* DMACPY */
/* #define SOC_EVENT_UDMA_DMACPY_RX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
/* #define SOC_EVENT_UDMA_DMACPY_TX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
/* I2S */
#define SOC_EVENT_UDMA_I2S_RX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_I2S_TX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
/* CPI */
#define SOC_EVENT_UDMA_CAM_RX(id) ((UDMA_CAM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
/* UDMA EOT & error events. */
//#define SOC_EVENT_UDMA_I2C_ERROR(id) (26 + id)
/*! @brief PMU events, no pmu*/
/* #define SOC_EVENT_PMU_CLUSTER_POWER (31) */
/* #define SOC_EVENT_PMU_CLUSTER_CG (35) */
/* #define SOC_EVENT_PMU_DLC_BRIDGE_PICL (36) */
/* #define SOC_EVENT_PMU_DLC_BRIDGE_SCU (37) */
/* #define SOC_EVENT_PWM(id) (38 + id) */
#define SOC_EVENT_GPIO (139)
#define SOC_EVENT_HWPE0 (140)
#define SOC_EVENT_HWPE1 (141)
/* #define SOC_EVENT_RTC_APB (43) */
/* #define SOC_EVENT_RTC (44) */
#define SOC_EVENT_SW(id) (160 + (id & (NB_SW_EVENTS - 1)))
#define SOC_EVENT_REF32K_CLK_RISE (168)
/* @brief Cluster events */
#define CL_EVENT_SW(id) (id & (NB_SW_EVENTS - 1))
#define CL_EVENT_DMA0 (8)
#define CL_EVENT_DMA1 (9)
#define CL_EVENT_TIMER0_LO (10)
#define CL_EVENT_TIMER0_HI (11)
#define CL_EVENT_ACC0 (12)
#define CL_EVENT_ACC1 (13)
#define CL_EVENT_ACC2 (14)
#define CL_EVENT_ACC3 (15)
#define CL_EVENT_BAR (16)
#define CL_EVENT_MUTEX (17)
#define CL_EVENT_DISPATCH (18)
/* #define CL_EVENT_CLUSTER0 (22) */
/* #define CL_EVENT_CLUSTER1 (23) */
#define CL_EVENT_SOC_EVT (30) /* adapted */
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-memory-map.h
+127
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/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
#include "core-v-mcu-properties.h"
/* Memories */
/* FC memory. */
#define FC_TCDM_ADDR (0x1B000000)
#if (ARCHI_HAS_FC_ALIAS)
#define FC_TCDM_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_FC_ALIAS */
/* L2 memory */
#define L2_SHARED_ADDR (0x1C000000)
#if (ARCHI_HAS_L2_ALIAS)
#define L2_SHARED_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_L2_ALIAS */
/* L1 cluster memory */
#define CL_L1_ADDR (0x10000000)
#if (ARCHI_HAS_CL_L1_ALIAS)
#define CL_L1_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_CL_L1_ALIAS */
/* L1 cluster TS */
#if (ARCHI_HAS_CL_L1_TS)
#define L2_PRIV0_TS_ADDR (0x10100000)
#endif /* ARCHI_HAS_CL_L1_TS */
/* ROM memory (8 KiB)*/
#define ROM_ADDR (0x1A000000)
#define ROM_SIZE (0x00002000)
/* Cluster */
#define ARCHI_CLUSTER_ADDR (0x00000000)
#define ARCHI_CLUSTER_SIZE (0x00400000)
#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
#define ARCHI_CLUSTER_PERIPHERALS_OFFSET (0x00200000)
/* Cluster peripherals */
#define ARCHI_TIMER_SIZE (0x00000800)
#define ARCHI_CLUSTER_CTRL_OFFSET (0x00000000)
#define ARCHI_TIMER_OFFSET (0x00000400)
#define ARCHI_EU_OFFSET (0x00000800)
#define ARCHI_HWCE_OFFSET (0x00001000)
#define ARCHI_ICACHE_CTRL_OFFSET (0x00001400)
#define ARCHI_MCHAN_EXT_OFFSET (0x00001800)
#define ARCHI_CLUSTER_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
#define ARCHI_CLUSTER_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_CLUSTER_CTRL_OFFSET)
#define ARCHI_CLUSTER_TIMER_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET)
#define ARCHI_ICACHE_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_ICACHE_CTRL_OFFSET)
#define ARCHI_EU_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET)
#define ARCHI_HWCE_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_HWCE_OFFSET)
#define ARCHI_MCHAN_EXT_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_MCHAN_EXT_OFFSET)
#define ARCHI_DEMUX_PERIPHERALS_OFFSET (0x204000)
#define ARCHI_EU_DEMUX_OFFSET (0x00000)
#define ARCHI_MCHAN_DEMUX_OFFSET (0x00400)
#define ARCHI_DEMUX_PERIPHERALS_ADDR (ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_DEMUX_PERIPHERALS_OFFSET)
#define ARCHI_EU_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET)
#define ARCHI_MCHAN_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET)
/* SoC peripherals */
#define SOC_PERIPHERALS_ADDR (0x1A100000)
#define SOC_FLL_OFFSET (0x00000000)
#define CL_FLL_OFFSET (0x00000800)
#define GPIO_OFFSET (0x00001000)
#define UDMA_OFFSET (0x00002000)
#define APB_SOC_CTRL_OFFSET (0x00004000)
#define ADV_TIMER_OFFSET (0x00005000) /* PWM. */
#define SOC_EU_OFFSET (0x00006000)
#define FC_IRQ_OFFSET (0x00009800)
/* #define FC_IRQ_OFFSET (0x00009000) */ /* valid mirror address */
#define FC_TIMER_OFFSET (0x0000B000)
#define FC_HWPE_OFFSET (0x0000C000)
#define STDOUT_OFFSET (0x0000F000)
#define DEBUG_OFFSET (0x00010000)
#define SOC_FLL_ADDR (SOC_PERIPHERALS_ADDR + SOC_FLL_OFFSET)
#define CL_FLL_ADDR (SOC_PERIPHERALS_ADDR + CL_FLL_OFFSET)
#define GPIO_ADDR (SOC_PERIPHERALS_ADDR + GPIO_OFFSET)
#define UDMA_CTRL_ADDR (SOC_PERIPHERALS_ADDR + UDMA_OFFSET)
#define APB_SOC_CTRL_ADDR (SOC_PERIPHERALS_ADDR + APB_SOC_CTRL_OFFSET)
#define ADV_TIMER_ADDR (SOC_PERIPHERALS_ADDR + ADV_TIMER_OFFSET)
#define SOC_EU_ADDR (SOC_PERIPHERALS_ADDR + SOC_EU_OFFSET)
#define FC_IRQ_ADDR (SOC_PERIPHERALS_ADDR + FC_IRQ_OFFSET)
#define FC_TIMER_ADDR (SOC_PERIPHERALS_ADDR + FC_TIMER_OFFSET)
#define FC_HWPE_ADDR (SOC_PERIPHERALS_ADDR + FC_HWPE_OFFSET)
#define STDOUT_ADDR (SOC_PERIPHERALS_ADDR + STDOUT_OFFSET)
#define DEBUG_ADDR (SOC_PERIPHERALS_ADDR + DEBUG_OFFSET)
/* UDMA peripherals */
/* #define UDMA_GC_ADDR (UDMA_CTRL_ADDR + 0x780) */
/* UDMA base peripheral addr = UDMA base address + UDMA ctrl. */
#define UDMA_PERIPH_BASE_ADDR (UDMA_CTRL_ADDR + 0x80)
#define UDMA_SPIM(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_SPIM_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_HYPER(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_HYPER_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_UART(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_UART_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_I2C(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2C_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_DMACPY(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_DMACPY_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_I2S(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_CPI(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
//#include "pmsis/rtos/os_frontend_api/os.h"
//#include "pmsis/backend/implementation_specific_defines.h"
//#include "pmsis/backend/pmsis_backend_native_task_api.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Function declaration
******************************************************************************/
/*******************************************************************************
* API implementation
******************************************************************************/
//static inline int pmsis_kickoff(void *arg)
//{
// return __os_native_kickoff(arg);
//}
//static inline void pmsis_exit(int err)
//{
// __os_native_exit(err);
//}
//static inline void *pmsis_task_create(void (*entry)(void*),
// void *arg,
// char *name,
// int priority)
//{
// return __os_native_api_create_task(entry, arg, name, priority);
//}
//static inline void pmsis_task_suspend(void *task_handler)
//{
// __os_native_task_t *task = (__os_native_task_t *) task_handler;
// __os_native_task_suspend(task);
//}
//static inline void pi_yield()
//{
// __os_native_yield();
//}
//static inline int disable_irq(void)
//{
// hal_compiler_barrier();
// return __os_native_api_disable_irq();
//}
//static inline void restore_irq(int irq_enable)
//{
// hal_compiler_barrier();
// __os_native_api_restore_irq(irq_enable);
//}
//
//static inline int pi_sem_init(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// return __os_native_api_sem_init(sem);
//}
//
//static inline int pi_sem_deinit(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// return __os_native_api_sem_deinit(sem);
//}
//
//static inline void pi_sem_take(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// sem->take(sem->sem_object);
//}
//
//static inline void pi_sem_give(pi_sem_t *sem)
//{
// sem->give(sem->sem_object);
// hal_compiler_barrier();
//}
//static inline void pmsis_mutex_take(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// int irq_enabled;
// volatile int mutex_free=0;
// while (!mutex_free)
// {
// irq_enabled = disable_irq();
// hal_compiler_barrier();
// mutex_free = !((volatile uint32_t)mutex->mutex_object);
// hal_compiler_barrier();
// restore_irq(irq_enabled);
// }
// irq_enabled = disable_irq();
// mutex->mutex_object = (void*)1;
// restore_irq(irq_enabled);
//#else
// mutex->take(mutex->mutex_object);
//#endif
//}
//
//static inline void pmsis_mutex_release(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// mutex->mutex_object = (void*)0;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//#else
// mutex->release(mutex->mutex_object);
// hal_compiler_barrier();
//#endif
//}
//
//static inline int pmsis_mutex_init(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// mutex->mutex_object = (void*)0;
// return 0;
//#else
// return __os_native_api_mutex_init(mutex);
//#endif
//}
//
//static inline int pmsis_mutex_deinit(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// mutex->mutex_object = (void*)0;
// return 0;
//#else
// return __os_native_api_mutex_deinit(mutex);
//#endif
//}
//
//static inline void pmsis_spinlock_init(pmsis_spinlock_t *spinlock)
//{
// hal_compiler_barrier();
// spinlock->lock = 0;
//}
//
//static inline void pmsis_spinlock_take(pmsis_spinlock_t *spinlock)
//{
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// spinlock->lock = 1;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//}
//
//static inline void pmsis_spinlock_release(pmsis_spinlock_t *spinlock)
//{
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// spinlock->lock = 0;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//}
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis.h
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/*
* Copyright 2019 GreenWaves Technologies
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
#include <stddef.h>
#include <inttypes.h>
/* Debug helper. */
#ifdef DEBUG
#define DEBUG_PRINTF printf
#else
#define DEBUG_PRINTF(...) ((void) 0)
#endif /* DEBUG */
#if (!defined(HW_VERIF_ONLY))
/* Backend includes. */
//#include "pmsis/backend/implementation_specific_defines.h"
//#include "hal/include/hal_target.h"
/* pmsis_api includes. */
//#include "pmsis/device.h"
//#include "pmsis/task.h"
//#include "pmsis_types.h"
//#include "../../../pmsis_api/include/pmsis/rtos/rtos-orig.h"
//#include "pmsis/rtos/assert.h"
//#include "pmsis/mem_slab.h"
/* PMSIS includes. */
//#include "pmsis/implem/debug.h"
//#include "pmsis/implem/drivers/drivers_data.h"
//#include "hal/include/hal_pmsis_drivers.h"
#include "hal_fc_event.h"
#include "hal_fll_pi.h"
#include "hal_i2c_internal.h"
#include "hal_uart_internal.h"
//#include "pmsis/rtos/os/pmsis_task.h"
//#include "pmsis/rtos/os/pmsis_freq.h"
//#include "target/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h"
//#include "hal/include/hal_native_task_api.h"
#if defined(FEATURE_CLUSTER)
//#include "pmsis/implem/cluster/cluster.h"
#endif /* FEATURE_CLUSTER */
#endif /* HW_VERIF_ONLY */
/* Hal includes. */
//#include "pmsis/implem/hal/hal.h"
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-properties.h
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/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
/* PULP defs */
#define PULP
#define ARCHI_FPGA_FREQUENCY 5000000
/* hardware modules */
#define ARCHI_NUM_TIMER 1
#define ARCHI_NUM_FLL 2
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
#define ARCHI_NB_FLL 3
#define __RT_FLL_CL 2
#define __RT_FLL_PERIPH 1
#define __RT_FLL_FC 0
#define __RT_FREQ_DOMAIN_FC 0
#define __RT_FREQ_DOMAIN_CL 2
#define __RT_FREQ_DOMAIN_PERIPH 1
#define RT_FREQ_NB_DOMAIN 3
/* Cores & cluster */
/* FC */
#define ARCHI_FC_CID (32)
/* Cluster */
#define ARCHI_HAS_CLUSTER (1)
#define ARCHI_CL_CID(id) (id)
#define ARCHI_CLUSTER_NB_PE (8) /* Processing elements. */
/* Memories */
/* FC memory */
#define ARCHI_HAS_FC_TCDM (1)
#define ARCHI_HAS_FC_ALIAS (1)
#define FC_TCDM_SIZE (0x00004000) /* 16kB. */
/* L2 memory */
#define ARCHI_HAS_L2_ALIAS (0)
#define L2_SHARED_SIZE (0x00080000) /* 512kB. */
/* L1 cluster memory */
#define ARCHI_HAS_CL_L1_ALIAS (1)
#define CL_L1_SIZE (0x00010000) /* 64kB. */
/* L1 cluster TS */
#define ARCHI_HAS_CL_L1_TS (1)
/* TODO: fix this table */
/* UDMA peripherals */
// #define UDMA_HAS_SPIM (1)
// #define UDMA_HAS_HYPER (0)
// #define UDMA_HAS_UART (1)
// #define UDMA_HAS_I2C (1)
// #define UDMA_HAS_DMACPY (0)
// #define UDMA_HAS_I2S (1)
// #define UDMA_HAS_CPI (1)
/* TODO: fix this table */
/* Number of UDMA peripherals */
// #define UDMA_NB_SPIM (2)
// #define UDMA_NB_HYPER (0)
// #define UDMA_NB_UART (1)
// #define UDMA_NB_I2C (2)
// #define UDMA_NB_DMACPY (0)
// #define UDMA_NB_I2S (1)
// #define UDMA_NB_CPI (1)
/* TODO: fix this table */
/* #define UDMA_NB_PERIPH ((UDMA_HAS_SPIM ? UDMA_NB_SPIM) + \ */
/* (UDMA_HAS_HYPER ? UDMA_NB_HYPER) + \ */
/* (UDMA_HAS_UART ? UDMA_NB_UART) + \ */
/* (UDMA_HAS_I2C ? UDMA_NB_I2C) + \ */
/* (UDMA_HAS_DMACPY ? UDMA_NB_DMACPY) + \ */
/* (UDMA_HAS_I2S ? UDMA_NB_I2S) + \ */
/* (UDMA_HAS_CPI ? UDMA_NB_CPI)) */
#define UDMA_NB_PERIPH (10)
/* Size of each UDMA peripheral */
#define UDMA_PERIPH_SIZE_LOG2 (7)
#define UDMA_PERIPH_SIZE (1 << UDMA_PERIPH_SIZE_LOG2)
/* UDMA peripherals ID, this maps to PER_ID_* in udma_subsystem.sv */
//#define UDMA_SPIM_ID(id) (1 + (id))
/* #define UDMA_HYPER_ID(id) (3 + (id)) */
//#define UDMA_UART_ID(id) (0 + (id))
//#define UDMA_I2C_ID(id) (2 + (id))
/* #define UDMA_DMACPY_ID(id) (7 + (id)) */
//#define ARCHI_UDMA_FILTER_ID(id) (7 + (id))
////#define UDMA_I2S_ID(id) (5 + (id))
//#define UDMA_CPI_ID(id) (6 + (id))
//#define UDMA_SDIO_ID(id) (4 + (id))
/* Pads & GPIO. */
// #define ARCHI_NB_PAD (48)
// #define ARCHI_NB_GPIO (32)
/* PWM. */
/* #define ARCHI_NB_PWM (4) */
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pulp-mem-map.h
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
/*
* SOC PERIPHERALS
*/
#define PULP_SOC_PERIPHERALS_ADDR 0x1A100000
#define PULP_FC_TIMER_SIZE 0x00000800
#define PULP_FLL_OFFSET 0x00000000
#define PULP_GPIO_OFFSET 0x00001000
#define PULP_UDMA_OFFSET 0x00002000
#define PULP_APB_SOC_CTRL_OFFSET 0x00004000
#define PULP_ADV_TIMER_OFFSET 0x00005000
#define PULP_SOC_EU_OFFSET 0x00006000
#define PULP_FC_IRQ_OFFSET 0x00009800
/* #define PULP_FC_IRQ_OFFSET 0x00009000 */ /* this is a mirror of above */
#define PULP_FC_TIMER_OFFSET 0x0000B000
#define PULP_FC_HWPE_OFFSET 0x0000C000
#define PULP_STDOUT_OFFSET 0x0000F000
#define PULP_DEBUG_OFFSET 0x00010000
#define PULP_FLL_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET)
#define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET)
#define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET)
#define PULP_APB_SOC_CTRL_ADDR \
(PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET)
#define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET)
#define PULP_SOC_EU_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET)
#define PULP_FC_IRQ_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET)
/* #define PULP_FC_ITC_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_ITC_OFFSET) */
#define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET)
#define PULP_FC_HWPE_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET)
#define PULP_STDOUT_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET)
#define PULP_FLL_AREA_SIZE 0x00000010
/*
* CLUSTER
*/
#define PULP_CLUSTER_ADDR 0x00000000
#define PULP_CLUSTER_SIZE 0x00400000
#define PULP_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*PULP_CLUSTER_SIZE)
/*
* CLUSTER PERIPHERALS
*/
#define PULP_CLUSTER_PERIPHERALS_OFFSET 0x00200000
#define PULP_TIMER_OFFSET 0x00000400
#define PULP_CLUSTER_PERIPHERALS_ADDR \
(PULP_CLUSTER_ADDR + PULP_CLUSTER_PERIPHERALS_OFFSET)
#define PULP_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) \
(PULP_CLUSTER_GLOBAL_ADDR(cid) + PULP_CLUSTER_PERIPHERALS_OFFSET)
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-system.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: Platform system level functions */
#ifndef _CORE_V_MCU_SYSTEM_H
#define _CORE_V_MCU_SYSTEM_H
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOSConfig.h"
extern volatile uint32_t system_core_clock;
void system_init (void);
void system_core_clock_update (void);
#endif /* _CORE_V_MCU_SYSTEM_H */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-target.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Author: Robert Balas */
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
#include "core_pulp.h"
#include "core_utils.h"
#include "core-v-mcu-periph.h"
//#include "pmsis/targets/periph.h"
static inline void hal_compiler_barrier()
{
asm volatile ("" : : : "memory");
}
static inline void hal_write32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) = value;
asm volatile ("" : : : "memory");
}
static inline void hal_write8(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint8_t *)addr) = value;
asm volatile ("" : : : "memory");
}
static inline void hal_or32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) |= value;
asm volatile ("" : : : "memory");
}
static inline void hal_and32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) &= value;
asm volatile ("" : : : "memory");
}
static inline uint32_t hal_read32(volatile void *addr)
{
asm volatile ("" : : : "memory");
uint32_t ret = *((volatile uint32_t *)addr);
asm volatile ("" : : : "memory");
return ret;
}
static inline uint8_t hal_read8(volatile void *addr)
{
asm volatile ("" : : : "memory");
uint8_t ret = *((volatile uint8_t *)addr);
asm volatile ("" : : : "memory");
return ret;
}
static inline uint32_t pi_core_id()
{
return __native_core_id();
}
static inline uint32_t pi_cluster_id()
{
return __native_cluster_id();
}
static inline uint32_t pi_is_fc()
{
return __native_is_fc();
}
static inline uint32_t pi_nb_cluster_cores()
{
return ARCHI_CLUSTER_NB_PE;
}
static inline int pi_cl_cluster_nb_cores()
{
return ARCHI_CLUSTER_NB_PE;
}
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp_cluster.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_utils.h
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/*
* Copyright 2020 Greenwaves Technologies
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PMSIS_CORE_UTILS__
#define __PMSIS_CORE_UTILS__
#include "csr.h"
/** FC_CLUSTER_ID Definitions */
#define FC_CLUSTER_ID 32 /**< FC CLuster ID */
/**
\ingroup CMSIS_Core_IDFunctionInterface
\defgroup CMSIS_Core_IDFunctions ID Functions
\brief Functions that manage Cluster and Core ID.
@{
*/
static inline uint32_t __native_core_id() {
/* encoding of mhartid: {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
uint32_t mhartid = csr_read(MHARTID_ADDR);
return mhartid & 0x01f;
}
static inline uint32_t __native_cluster_id() {
/* encoding of mhartid {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
uint32_t mhartid = csr_read(MHARTID_ADDR);
return 0 ;//(mhartid >> 5) & 0x3f;
}
static inline uint32_t __native_is_fc() {
return ( __native_cluster_id() == FC_CLUSTER_ID);
}
#endif
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/csr.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: CSR access macros */
#ifndef __CSR_H
#define __CSR_H
#include "bits.h"
/* TODO: complete this */
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
/* TODO: complete this */
#define MSTATUS_IE BIT(3)
#define __CSR_EXPAND(x) #x
#define csr_read(csr) \
({ \
register unsigned long __val; \
asm volatile("csrr %0, " __CSR_EXPAND(csr) \
: "=r"(__val) \
: \
: "memory"); \
__val; \
})
#define csr_write(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrw " __CSR_EXPAND(csr) ", %0" \
: \
: "rK"(__val) \
: "memory"); \
})
/* TODO: I hope this properly does a memory barrier with the "memory" hint */
#define csr_read_clear(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})
#define csr_read_set(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})
#endif
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pmsis_gcc.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pulp_io.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: Register I/O access
*/
#ifndef __PULP_IO_H
#define __PULP_IO_H
#include <stdint.h>
/* generic I/O write */
static inline void writeb(uint8_t val, uintptr_t addr)
{
asm volatile("sb %0, 0(%1)"
:
: "r"(val), "r"((volatile uint8_t *)addr));
}
static inline void writeh(uint16_t val, uintptr_t addr)
{
asm volatile("sh %0, 0(%1)"
:
: "r"(val), "r"((volatile uint16_t *)addr));
}
static inline void writew(uint32_t val, uintptr_t addr)
{
asm volatile("sw %0, 0(%1)"
:
: "r"(val), "r"((volatile uint32_t *)addr));
}
static inline void writed(uint64_t val, uintptr_t addr)
{
asm volatile("sd %0, 0(%1)"
:
: "r"(val), "r"((volatile uint64_t *)addr));
}
/* generic I/O read */
static inline uint8_t readb(const uintptr_t addr)
{
uint8_t val;
asm volatile("lb %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint8_t *)addr));
return val;
}
static inline uint16_t readh(const uintptr_t addr)
{
uint16_t val;
asm volatile("lh %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint16_t *)addr));
return val;
}
static inline uint32_t readw(const uintptr_t addr)
{
uint32_t val;
asm volatile("lw %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint32_t *)addr));
return val;
}
static inline uint64_t readd(const uintptr_t addr)
{
uint64_t val;
asm volatile("ld %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint64_t *)addr));
return val;
}
#endif
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_core-v-mcu_metal.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef __SYSTEM_PULPISSIMO_RI5CY_METAL_H
#define __SYSTEM_PULPISSIMO_RI5CY_METAL_H
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOSConfig.h"
/* PULPissimo defs */
#define PULPISSIMO
#define ARCHI_FPGA_FREQUENCY 5000000
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
/* hardware modules */
#define ARCHI_NUM_TIMER 1
#define ARCHI_NUM_FLL 2
/* TODO: clean up those macros */
#define ARCHI_FPGA_FREQUENCY 5000000
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
#define ARCHI_NB_FLL 2
#define RT_FREQ_NB_DOMAIN 2
#define __RT_FLL_CL 2
#define __RT_FLL_PERIPH 1
#define __RT_FLL_FC 0
#define __RT_FREQ_DOMAIN_FC 0
#define __RT_FREQ_DOMAIN_CL 2
#define __RT_FREQ_DOMAIN_PERIPH 1
#define RT_FREQ_NB_DOMAIN 2
extern volatile uint32_t system_core_clock;
void pulp_sys_init (void);
void system_core_clock_update (void);
#endif /* __SYSTEM_PULPISSIMO_RI5CY_H */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_metal.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include "system_core-v-mcu_metal.h"
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_pmsis.h
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include "system_pulpissimo_ri5cy.h"
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/crt0.S
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/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause
*/
/* Copyright (c) 2017 SiFive Inc. All rights reserved.
* Copyright (c) 2019 ETH Zürich and University of Bologna
* This copyrighted material is made available to anyone wishing to use,
* modify, copy, or redistribute it subject to the terms and conditions
* of the FreeBSD License. This program is distributed in the hope that
* it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
* including the implied warranties of MERCHANTABILITY or FITNESS FOR
* A PARTICULAR PURPOSE. A copy of this license is available at
* http://www.opensource.org/licenses.
*/
/* entry point */
.section .text.start
.global _start
.type _start, @function
_start:
/* initialize global pointer */
.option push
.option norelax
1: auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
#if defined(ARCHI_HAS_CLUSTER)
/* TODO */
#endif
/* initialize stack pointer */
la sp, __stack_top
/*or a0, a0, 0*/
and a0, a0, 0
csrw mie, a0 // disable interrupts
csrr a0, mie
/* set vector table address */
la a0, __vector_start
or a0, a0, 1 /* enable vectored mode (hardcoded anyway for CV32E40P) */
csrw mtvec, a0
/* clear the bss segment */
la t0, __bss_start
la t1, __bss_end
/* TODO: optionally compile this out to speed simulation */
1:
sw zero,0(t0)
addi t0, t0, 4
bltu t0, t1, 1b
/* new-style constructors and destructors */
#if defined(__PULP_USE_LIBC)
la a0, __libc_fini_array
call atexit
call __libc_init_array
#endif
/* call main */
lw a0, 0(sp) /* a0 = argc */
addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
li a2, 0 /* a2 = envp = NULL */
call entry
tail exit
.size _start, .-_start
.global _init
.type _init, @function
.global _fini
.type _fini, @function
_init:
_fini:
/* These don't have to do anything since we use init_array/fini_array. Prevent
missing symbol error */
ret
.size _init, .-_init
.size _fini, .-_fini
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/vectors.S
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/*
* Copyright 2019 ETH Zürich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun Remove FreeRTOS related code and add RT-Thread code
*/
.extern IRQ_Handler
#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
.extern freertos_risc_v_ctxt_handler
#endif
#ifdef __HACK_FIRMWARE_OPT1 /* TODO: properly do this with weak symbols */
.extern TIMER1_IRQ_handler
#endif
.extern fc_soc_event_handler
.section .vectors, "ax"
.option norvc
vector_table:
j IRQ_Handler // irq0
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // irq3
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler //ctxt_handler // irq 7 mtime or timer
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ_Handler
j IRQ_Handler // irq 11 Machine (event Fifo)
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ16
j IRQ_Handler // IRQ17
j IRQ_Handler // IRQ18
j IRQ_Handler // IRQ19
j IRQ_Handler // IRQ20
j IRQ_Handler // IRQ21
j IRQ_Handler // IRQ22
j IRQ_Handler // IRQ23
j IRQ_Handler // IRQ24
j IRQ_Handler // IRQ25
j IRQ_Handler // IRQ26
j IRQ_Handler // IRQ27
j IRQ_Handler // IRQ28
j IRQ_Handler // IRQ29
j IRQ_Handler // IRQ30
j IRQ_Handler // IRQ30
/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
new vector table (which is at mtvec) */
/* .section .legacy_irq, "ax" */
/* j vector_table */
/* j __no_irq_handler */
/* j __no_irq_handler */
/* j __no_irq_handler */
.section .text.vecs
/* exception handling */
__no_irq_handler:
la a0, no_exception_handler_msg
jal ra, puts
j __no_irq_handler
sw_irq_handler:
csrr t0, mcause
slli t0, t0, 1 /* shift off the high bit */
srli t0, t0, 1
li t1, 2
beq t0, t1, handle_illegal_insn
li t1, 11
beq t0, t1, handle_ecall
li t1, 3
beq t0, t1, handle_ebreak
j handle_unknown
handle_ecall:
la a0, ecall_msg
jal ra, puts
j end_handler
handle_ebreak:
la a0, ebreak_msg
jal ra, puts
j end_handler
handle_illegal_insn:
la a0, illegal_insn_msg
jal ra, puts
j end_handler
handle_unknown:
la a0, unknown_msg
jal ra, puts
j end_handler
end_handler:
csrr a0, mepc
addi a0, a0, 4
csrw mepc, a0
mret
.section .rodata
illegal_insn_msg:
.string "illegal instruction exception handler entered\n"
ecall_msg:
.string "ecall exception handler entered\n"
ebreak_msg:
.string "ebreak exception handler entered\n"
unknown_msg:
.string "unknown exception handler entered\n"
no_exception_handler_msg:
.string "no exception handler installed\n"
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/adv_timer_unit_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/efpga_template_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_event_cntrl_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_gpio_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs.h
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/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __HAL_APB_I2CS_H__
#define __HAL_APB_I2CS_H__
#include "stdint.h"
#define MY_I2C_SLAVE_ADDRESS 0x62
#define MY_I2C_SLAVE_ADDRESS_7BIT (0x62 << 1)
#define I2C_MASTER_REG_DEV_ADDRESS 0x00
#define I2C_MASTER_REG_ENABLE 0x01
#define I2C_MASTER_REG_DEBOUNCE_LENGTH 0x02
#define I2C_MASTER_REG_SCL_DELAY_LENGTH 0x03
#define I2C_MASTER_REG_SDA_DELAY_LENGTH 0x04
#define I2C_MASTER_REG_MSG_I2C_APB 0x10
#define I2C_MASTER_REG_MSG_I2C_APB_STATUS 0x11
#define I2C_MASTER_REG_MSG_APB_I2C 0x12
#define I2C_MASTER_REG_MSG_APB_I2C_STATUS 0x13
#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_DATA_PORT 0x20
#define I2C_MASTER_REG_FIFO_I2C_APB_READ_DATA_PORT 0x21
#define I2C_MASTER_REG_FIFO_I2C_APB_FLUSH 0x22
#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_FLAGS 0x23
#define I2C_MASTER_REG_FIFO_I2C_APB_READ_FLAGS 0x24
#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_DATA_PORT 0x30
#define I2C_MASTER_REG_FIFO_APB_I2C_READ_DATA_PORT 0x31
#define I2C_MASTER_REG_FIFO_APB_I2C_FLUSH 0x32
#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_FLAGS 0x33
#define I2C_MASTER_REG_FIFO_APB_I2C_READ_FLAGS 0x34
#define I2C_MASTER_REG_INTERRUPT_STATUS 0x40
#define I2C_MASTER_REG_INTERRUPT_ENABLE 0x41
#define I2C_MASTER_REG_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT 0x42
#define I2C_MASTER_REG_INTERRUPT_APB_I2C_READ_FLAGS_SELECT 0x43
#define I2C_MASTER_REG_INTERRUPT_TO_APB_STATUS 0x50
#define I2C_MASTER_REG_INTERRUPT_TO_APB_ENABLE 0x51
#define I2C_MASTER_REG_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 0x52
#define I2C_MASTER_REG_INTERRUPT_I2C_APB_READ_FLAGS_SELECT 0x53
uint8_t hal_get_apb_i2cs_slave_address(void);
void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress);
uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus);
uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void);
void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData);
uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void);
uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void);
uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void);
uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void);
uint8_t hal_get_i2cs_msg_i2c_apb(void);
uint8_t hal_get_i2cs_msg_i2c_apb_status(void);
void hal_set_i2cs_msg_apb_i2c(uint8_t aData);
uint8_t hal_get_i2cs_msg_apb_i2c_status(void);
void hal_i2cs_fifo_i2c_apb_FIFO_flush(void);
void hal_i2cs_fifo_apb_i2c_FIFO_flush(void);
#endif // __HAL_APB_I2CS_H__
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc.h
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/*
* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Description: SoC configuration registers (apb_soc_ctrl)
* Authors: Germain Haugou (germain.haugou@iis.ee.ethz.ch)
* Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef HAL_INCLUDE_HAL_APB_SOC_H_
#define HAL_INCLUDE_HAL_APB_SOC_H_
#define APB_SOC_BOOT_OTHER 0
#define APB_SOC_BOOT_JTAG 1
#define APB_SOC_BOOT_SPI 2
#define APB_SOC_BOOT_ROM 3
#define APB_SOC_BOOT_PRELOAD 4
#define APB_SOC_BOOT_HYPER 5
#define APB_SOC_BOOT_SPIM 6
#define APB_SOC_BOOT_SPIM_QPI 7
#define APB_SOC_PLT_OTHER 0
#define APB_SOC_PLT_FPGA 1
#define APB_SOC_PLT_RTL 2
#define APB_SOC_PLT_VP 3
#define APB_SOC_PLT_CHIP 4
//PADs configuration is made of 8bits out of which only the first 6 are used
//bit0 enable pull UP
//bit1 enable pull DOWN
//bit2 enable ST
//bit3 enable SlewRate Limit
//bit4..5 Driving Strength
//bit6..7 not used
#define APB_SOC_BOOTADDR_OFFSET 0x04
#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0]
#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment
#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment
#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment
#define APB_SOC_PADFUN0_OFFSET 0x10
#define APB_SOC_PADCFG0_OFFSET 0x20
#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4)
#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
#define APB_SOC_PADFUN_SIZE 2
#define ARCHI_APB_SOC_PADFUN_NB 4
#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1)
#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24])
#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2)
#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
#define APB_SOC_PADCFG_SIZE 8
#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3)
#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet)
#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet)
#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment
#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment)
#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment
#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment)
#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment
#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed)
#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed)
#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment
#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment
#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment
#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment
#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment
#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment
#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
#define APB_SOC_PADS_CONFIG 0xC4
#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
#define APB_SOC_JTAG_REG_EXT_BIT 8
#define APB_SOC_JTAG_REG_EXT_WIDTH 4
#define APB_SOC_JTAG_REG_LOC_BIT 0
#define APB_SOC_JTAG_REG_LOC_WIDTH 4
#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2)
#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
#define APB_SOC_STATUS_EOC_BIT 31
#define APB_SOC_NB_CORE_BIT 16
#define APB_SOC_BYPASS_OFFSET 0x70
#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
#define APB_SOC_BYPASS_USER0_BIT 14
#define APB_SOC_BYPASS_USER1_BIT 15
#define APB_SOC_FLL_CTRL_OFFSET 0xD0
#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4
#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8
#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC
#define APB_SOC_FLL_CTRL_SOC_BIT 0
#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1
#define APB_SOC_FLL_CTRL_PERIPH_BIT 2
#define APB_SOC_RTC_OFFSET 0x1D0
#endif /* HAL_INCLUDE_HAL_APB_SOC_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc_ctrl_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc_ctrl_regs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_timer_unit_reg_defs.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fc_event.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_FC_EVENT_H_
#define HAL_INCLUDE_HAL_FC_EVENT_H_
#include "core-v-mcu-pmsis.h"
/*!
* @addtogroup FC_EventHandler
* @{
*/
/*******************************************************************************
* Variables, macros, structures,... definitions
******************************************************************************/
/*******************************************************************************
* APIs
******************************************************************************/
#define NB_SOC_EVENTS ( SOC_EU_NB_FC_EVENTS )
typedef void (*pi_fc_event_handler_t)(void* arg);
void pi_fc_event_handler_init(uint32_t fc_event_irq);
/*!
* @brief FC event handler.
*
* This function pops an event and executes the handler corresponding to the event.
*/
void fc_soc_event_handler(void);
//void pi_fc_event_handler_set(uint32_t event_id, pi_fc_event_handler_t event_handler, SemaphoreHandle_t semaphoreHandle);//This function based on freertos
void user_pi_fc_event_handler_set(uint32_t event_id,pi_fc_event_handler_t event_handler);
void pi_fc_event_handler_clear(uint32_t event_id);
void clear_fc_event_handler(uint32_t event_id);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/* @} */
#endif /* HAL_INCLUDE_HAL_FC_EVENT_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fll.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fll_pi.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_FLL_PI_H_
#define HAL_INCLUDE_HAL_FLL_PI_H_
//#include "pmsis/targets/target.h"
#include "core-v-mcu-target.h"
/*!
* @addtogroup fll
* @{
*/
#define DCDC_OPER_POINTS (4)
#define DCDC_DEFAULT_NV (1200)
#define DCDC_DEFAULT_MV (1200)
#define DCDC_DEFAULT_LV (1000)
#define DCDC_DEFAULT_RET (800)
#define DCDC_RANGE (5)
#define DCDC_RANGE_MASK (0x1F)
#define DCDC_BASE_VALUE (550)
#define DCDC_STEP (50)
#define MAX_DCDC_VARIATION ((int32_t) (0.1*32767))
/*******************************************************************************
* Definitions
******************************************************************************/
#define FLL_LV_MAX_FREQUENCY 150000000
#define FLL_NV_MAX_FREQUENCY 250000000
#define FLL_SOC_MIN_FREQUENCY 150000000
#define FLL_SOC_MAX_FREQUENCY 250000000
#define FLL_CLUSTER_MIN_FREQUENCY 87000000
#define FLL_CLUSTER_MAX_FREQUENCY 175000000
#define FLL_SOC_FV_SLOPE ((FLL_SOC_MAX_FREQUENCY - FLL_SOC_MIN_FREQUENCY) / (DCDC_DEFAULT_NV - DCDC_DEFAULT_LV))
#define FLL_CLUSTER_FV_SLOPE ((FLL_CLUSTER_MAX_FREQUENCY - FLL_CLUSTER_MIN_FREQUENCY) / (DCDC_DEFAULT_NV - DCDC_DEFAULT_LV))
typedef enum _fll_type
{
FLL_SOC = 0,
FLL_PERI = 1,
FLL_CLUSTER = 2
} fll_type_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief Initialize one FLL.
*
* @param which_fll SoC's or Cluster's fll.
* @param ret_state Retention state.
*
* @note .
*/
void pi_fll_init(fll_type_t which_fll, uint32_t ret_state);
/*!
* @brief Deinitalize one FLL.
*
* @param which_fll SoC's or Cluster's fll.
*
* @note .
*/
void pi_fll_deinit(fll_type_t which_fll);
/*!
* @brief Clean all FLL configuration.
*
* @note .
*/
void pi_fll_clear();
/*!
* @brief Set specific FLL to wanted frequency.
*
* @param which_fll SoC's or Cluster's fll.
* @param frequency The frequency value to set.
* @param check Check frequency.
*
* @note .
* @return check result of frequency.
*/
int pi_fll_set_frequency(fll_type_t which_fll, uint32_t frequency, int check);
/*!
* @brief Get specific FLL's frequency.
*
* @param which_fll SoC's or Cluster's fll.
*
* @note .
* @return frequency value.
*/
int pi_fll_get_frequency(fll_type_t which_fll, uint8_t real);
/*!
* @brief Calculate FC SOC domain's max frequency with certain voltage
*
* @param voltage Given voltage
*
* @return max frquency.
*/
static inline int pi_fll_soc_max_freq_at_V(int voltage)
{
return (FLL_SOC_MIN_FREQUENCY + (voltage - DCDC_DEFAULT_LV) * FLL_SOC_FV_SLOPE);
}
/*!
* @brief Calculate cluster domain's max frequency with certain voltage
*
* @param voltage Given voltage
*
* @return max frquency.
*/
static inline int pi_fll_cluster_max_freq_at_V(int voltage)
{
return (FLL_CLUSTER_MIN_FREQUENCY + (voltage - DCDC_DEFAULT_LV) * FLL_CLUSTER_FV_SLOPE);
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/* @} */
#endif /* HAL_INCLUDE_HAL_FLL_PI_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_GPIO_H_
#define HAL_INCLUDE_HAL_GPIO_H_
typedef enum {
CLEAR,
SET,
TOGGLE
}efpgaio_enum_typedef;
typedef struct {
uint8_t mode;
uint32_t int_type;
uint8_t in_val;
uint8_t out_val;
uint32_t int_en;
uint32_t number;
}gpio_hal_typedef;
void hal_write_gpio(uint8_t gpio_num, uint8_t value);
void hal_set_gpio(uint8_t gpio_num);
void hal_clr_gpio(uint8_t gpio_num);
void hal_toggle_gpio(uint8_t gpio_num);
void hal_gpio_int_ack (uint8_t int_gpio_num);
void hal_set_gpio_num(uint8_t gpio_num);
void hal_read_gpio_status(gpio_hal_typedef *hgpio);
void hal_read_gpio_status_raw(uint8_t gpio_num, uint32_t* register_value);
void hal_set_gpio_mode(uint8_t gpio_num, uint8_t gpio_mode);
void hal_set_gpio_interrupt(uint8_t gpio_num, uint8_t interrupt_type, uint8_t interrupt_enable);
void hal_enable_gpio_interrupt(uint8_t gpio_num);
void hal_disable_gpio_interrupt(uint8_t gpio_num);
void hal_efpgaio_output(uint8_t gpio_num, efpgaio_enum_typedef value);
void hal_efpgaio_outen(uint8_t gpio_num, efpgaio_enum_typedef value);
void hal_efpgaio_event(uint8_t gpio_num);
void hal_efpgaio_status(gpio_hal_typedef *efpgaio);
#endif /* HAL_INCLUDE_HAL_GPIO_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio_periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_internal.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_I2C_INTERNAL_H_
#define HAL_INCLUDE_HAL_I2C_INTERNAL_H_
#include "core-v-mcu-pmsis.h"
//#include "pmsis/task.h"
#include "hal_i2c_pi.h"
//#include "hal/include/hal_pmsis_hal.h"
//#include "pmsis/implem/hal/hal_pmsis_hal.h"
//#include "pmsis/implem/hal/hal.h"
#include "hal_soc_eu_periph.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Max length of a i2c request/data buffer. */
#define MAX_SIZE (0xFF)
/* Length of i2c cmd buffer. */
#define __PI_I2C_CMD_BUFF_SIZE (16)
/* Lenght of i2c stop command sequence. */
#define __PI_I2C_STOP_CMD_SIZE (3)
struct i2c_transfer_s
{
uint8_t *buffer;
uint32_t size;
pi_i2c_xfer_flags_e flags;
int8_t device_id;
udma_channel_e channel;
};
struct i2c_pending_transfer_s
{
uint32_t pending_buffer;
uint32_t pending_size;
uint32_t pending_repeat;
uint32_t pending_repeat_size;
pi_i2c_xfer_flags_e flags;
int8_t device_id;
udma_channel_e channel;
};
struct i2c_cb_args_s
{
struct pi_task *cb;
struct i2c_transfer_s transfer;
struct i2c_cb_args_s *next;
};
struct i2c_driver_fifo_s
{
/* Best to use only one queue since both RX & TX can be used at the same time. */
struct pi_task *hw_buffer[2]; /* RX + TX */
struct i2c_cb_args_s *fifo_head; /* Head of SW fifo waiting transfers. */
struct i2c_cb_args_s *fifo_tail; /* Tail of SW fifo waiting transfers. */
struct i2c_pending_transfer_s *pending; /* RX + TX. */
uint32_t cs; /* Chip select i2c device. */
uint32_t max_baudrate; /* Max baudrate for the selected i2c chip. */
uint32_t div; /* Clock divider for the selected i2c chip. */
uint32_t i2c_cmd_index; /* Number of commands in i2c_cmd_seq. */
uint8_t i2c_cmd_seq[__PI_I2C_CMD_BUFF_SIZE]; /* Command sequence. */
uint8_t i2c_stop_send; /* Set if a stop command sequence should be sent. */
uint8_t i2c_stop_seq[__PI_I2C_STOP_CMD_SIZE]; /* Command STOP sequence. */
};
/*******************************************************************************
* Driver data
*****************************************************************************/
/*******************************************************************************
* Function declaration
******************************************************************************/
/* Copy in UDMA. */
void __pi_i2c_copy(struct i2c_driver_fifo_s *fifo, struct i2c_transfer_s *transfer, struct pi_task *task);
/* Handler. */
void i2c_handler(void *arg);
/* Clock divider. */
uint32_t __pi_i2c_get_clk_div(uint32_t baudrate);
#endif /* HAL_INCLUDE_HAL_I2C_INTERNAL_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_periph.h
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/*
* Copyright (C) 2019 ETH Zurich, University of Bologna
* and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef HAL_INCLUDE_HAL_I2C_PERIPH_H_
#define HAL_INCLUDE_HAL_I2C_PERIPH_H_
#include "hal_udma_core_periph.h"
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer --
---------------------------------------------------------------------------- */
/** I2C_Type Register Layout Typedef */
typedef struct i2c
{
udma_channel_t rx; /**< UDMA RX channels struct. */
udma_channel_t tx; /**< UDMA RX channels struct. */
udma_channel_t cmd; /**< UDMA RX channels struct. */
volatile uint32_t status; /**< Status register. */
volatile uint32_t setup; /**< Configuration register. */
} i2c_t;
/* ----------------------------------------------------------------------------
-- I2C Register Bitfield Access --
---------------------------------------------------------------------------- */
/*! @name STATUS */
/* I2C bus busy status flag:
- 1'b0: no transfer on-going
- 1'b1: transfer on-going */
#define I2C_STATUS_BUSY_MASK (0x1)
#define I2C_STATUS_BUSY_SHIFT (0)
#define I2C_STATUS_BUSY(val) (((uint32_t)(((uint32_t)(val)) << I2C_STATUS_BUSY_SHIFT)) & I2C_STATUS_BUSY_MASK)
/* I2C arbitration lost status flag:
- 1'b0: no error
- 1'b1: arbitration lost error */
#define I2C_STATUS_ARB_LOST_MASK (0x2)
#define I2C_STATUS_ARB_LOST_SHIFT (1)
#define I2C_STATUS_ARB_LOST(val) (((uint32_t)(((uint32_t)(val)) << I2C_STATUS_ARB_LOST_SHIFT)) & I2C_STATUS_ARB_LOST_MASK)
/*! @name SETUP */
/* Reset command used to abort the on-going transfer and clear busy and arbitration lost status flags. */
#define I2C_SETUP_DO_RST_MASK (0x1)
#define I2C_SETUP_DO_RST_SHIFT (0)
#define I2C_SETUP_DO_RST(val) (((uint32_t)(((uint32_t)(val)) << I2C_SETUP_DO_RST_SHIFT)) & I2C_SETUP_DO_RST_MASK)
/*! @name STATUS */
typedef union
{
struct
{
/* I2C bus busy status flag:
- 1'b0: no transfer on-going
- 1'b1: transfer on-going */
uint32_t busy:1;
/* I2C arbitration lost status flag:
- 1'b0: no error
- 1'b1: arbitration lost error */
uint32_t arb_lost:1;
} field;
uint32_t word;
} i2c_status_t;
/*! @name SETUP */
typedef union
{
struct
{
/* Reset command used to abort the on-going transfer and clear busy and arbitration lost status flags. */
uint32_t do_rst:1;
} field;
uint32_t word;
} i2c_setup_t;
/* ----------------------------------------------------------------------------
-- CMD IDs and macros --
---------------------------------------------------------------------------- */
#define I2C_CMD_MASK (0xF0U)
#define I2C_CMD_SHIFT (4U)
#define I2C_CMD_START (((uint32_t)(((uint32_t)(0x0)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x00
#define I2C_CMD_WAIT_EV (((uint32_t)(((uint32_t)(0x1)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x10
#define I2C_CMD_STOP (((uint32_t)(((uint32_t)(0x2)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x20
#define I2C_CMD_RD_ACK (((uint32_t)(((uint32_t)(0x4)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x40
#define I2C_CMD_RD_NACK (((uint32_t)(((uint32_t)(0x6)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x60
#define I2C_CMD_WR (((uint32_t)(((uint32_t)(0x8)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x80
#define I2C_CMD_WAIT (((uint32_t)(((uint32_t)(0xA)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xA0
#define I2C_CMD_RPT (((uint32_t)(((uint32_t)(0xC)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xC0
#define I2C_CMD_CFG (((uint32_t)(((uint32_t)(0xE)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xE0
#endif /* HAL_INCLUDE_HAL_I2C_PERIPH_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_pi.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_irq.h
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Interrupt controller definitions */
/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Germain Haugou (germain.haugou@iis.ee.ethz.ch)
*/
#ifndef HAL_INCLUDE_HAL_IRQ_H_
#define HAL_INCLUDE_HAL_IRQ_H_
#include "bits.h"
#define IRQ_REG_MASK_OFFSET 0x000
#define IRQ_REG_MASK_SET_OFFSET 0x004
#define IRQ_REG_MASK_CLEAR_OFFSET 0x008
#define IRQ_REG_INT_OFFSET 0x00C
#define IRQ_REG_INT_SET_OFFSET 0x010
#define IRQ_REG_INT_CLEAR_OFFSET 0x014
#define IRQ_REG_ACK_OFFSET 0x018
#define IRQ_REG_ACK_SET_OFFSET 0x01C
#define IRQ_REG_ACK_CLEAR_OFFSET 0x020
#define IRQ_REG_FIFO_OFFSET 0x024
/* Interrupt line masks: these interrupts directly go to the core (after being
* serialized as reqest + id). We refer to these interrupts with the prefix IRQ.
* Events on the other we strictly use to refer to "interrupts/events" that are
* signaled through (muxed) EU SoC interrupts (IRQ_FC_EVT_SOC_EVT) and need
* additional handling by the user through the Event Unit.
*/
#define IRQ_FC_EVT_SW0 BIT(0)
#define IRQ_FC_EVT_SW1 BIT(1)
#define IRQ_FC_EVT_SW2 BIT(2)
#define IRQ_FC_EVT_SW3 BIT(3)
#define IRQ_FC_EVT_SW4 BIT(4)
#define IRQ_FC_EVT_SW5 BIT(5)
#define IRQ_FC_EVT_SW6 BIT(6)
#define IRQ_FC_EVT_SW7 BIT(7)
#define IRQ_FC_EVT_DMA_PE_EVT BIT(8)
#define IRQ_FC_EVT_DMA_PE_IRQ BIT(9)
#define IRQ_FC_EVT_TIMER0_LO BIT(10)
#define IRQ_FC_EVT_TIMER0_HI BIT(11)
#define IRQ_FC_EVT_PF BIT(12)
#define IRQ_FC_EVT_CLK_REF BIT(14)
#define IRQ_FC_EVT_GPIO BIT(15)
/* is not in PULPissimo */
/*#define IRQ_FC_EVT_RTC 16 */
#define IRQ_FC_EVT_ADV_TIMER0 BIT(17)
#define IRQ_FC_EVT_ADV_TIMER1 BIT(18)
#define IRQ_FC_EVT_ADV_TIMER2 BIT(19)
#define IRQ_FC_EVT_ADV_TIMER3 BIT(20)
/* is not in PULPissimo */
/* #define IRQ_FC_EVT_CLUSTER_NOT_BUSY 21 */
/* #define IRQ_FC_EVT_CLUSTER_POK 22 */
/* #define IRQ_FC_EVT_CLUSTER_CG_OK 23 */
/* #define IRQ_FC_EVT_PICL_OK 24 */
/* #define IRQ_FC_EVT_SCU_OK 25 */
/*
* SoC event unit events: Many events get implicitely muxed into this interrupt.
* A user that gets such an interrupt has to check the event unit's registers to
* see what happened
*/
#define IRQ_FC_EVT_SOC_EVT BIT(26)
/*
* Event queue error: If we don't process event unit events quickly enough
* internal fifos can overflow and we get this error interrupt
*/
#define IRQ_FC_EVT_QUIRQE_ERROR BIT(29)
/* High priority peripheral events: these are hardcoded to directly go to the
* core using a dedicated interrupt line
*/
#define IRQ_FC_EVT_PERIPH0 BIT(30)
#define IRQ_FC_EVT_PERIPH1 BIT(31)
/* TODO: doc */
void irq_mask(uint32_t mask);
void irq_enable(uint32_t mask);
void irq_disable(uint32_t mask);
uint32_t irq_clint_disable();
uint32_t irq_clint_enable();
void pulp_irq_init();
#endif /* HAL_INCLUDE_HAL_IRQ_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pinmux.h
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#ifndef HAL_INCLUDE_HAL_PINMUX_H_
#define HAL_INCLUDE_HAL_PINMUX_H_
void hal_setpullup(uint8_t io_num, uint8_t on);
void hal_setpinmux(uint8_t io_num, uint8_t mux_sel);
uint8_t hal_getpinmux(uint8_t io_num);
#endif /* HAL_INCLUDE_HAL_PINMUX_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pinmux1.h
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#ifndef HAL_INCLUDE_HAL_PINMUX1_H_
#define HAL_INCLUDE_HAL_PINMUX1_H_
/*
* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Driver to control and configure pad mux */
/* Author: Robert Balas (balasr@iis.ee.ethz.ch) */
#include <stdint.h>
#include "pulp_io.h"
#include "hal_apb_soc.h"
#include "core-v-mcu-pulp-mem-map.h"
#define PINMUX_FUNC_A 0
#define PINMUX_FUNC_B 1
#define PINMUX_FUNC_C 2
#define PINMUX_FUNC_D 3
/* This doesn't exist on PULP */
#define PINMUX_FUNC_E 4
#define PINMUX_FUNC_F 5
#define PINMUX_FUNC_G 6
#define PINMUX_FUNC_H 7
int pinmux_pin_set(int pin, uint32_t func);
int pinmux_pin_get(int pin, uint32_t *func);
#endif /* HAL_INCLUDE_HAL_PINMUX1_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_drivers-obs.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
#define HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
/* PMSIS api includes. */
/* Chips specifics. */
//#include "pmsis/chips/gap8/perf.h"
/* Drivers. */
//#include "pmsis/drivers/cpi.h"
//#include "pmsis/drivers/dmacpy.h"
//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
//#include "pmsis/drivers/gpio.h"
//#include "pmsis/drivers/hyperbus.h"
//#include "pmsis/drivers/i2c.h"
//#include "pmsis/drivers/i2s.h"
//#include "pmsis/drivers/pad.h"
//#include "pmsis/drivers/perf.h"
//#include "pmsis/drivers/pwm.h"
//#include "pmsis/drivers/rtc.h"
//#include "pmsis/drivers/spi.h"
#include "hal_fc_event.h"
#include "hal_fll_pi.h"
//#include "pmsis/implem/drivers/perf/perf.h"
//#include "pmsis/implem/drivers/pmu/pmu.h"
//#include "pmsis/implem/drivers/pwm/pwm_internal.h"
//#include "pmsis/implem/drivers/rtc/rtc_internal.h"
//#include "pmsis/implem/drivers/timer/timer.h"
//#include "pmsis/implem/drivers/udma/cpi/cpi_internal.h"
//#include "pmsis/implem/drivers/udma/dmacpy/dmacpy_internal.h"
//#include "pmsis/implem/drivers/udma/hyperbus/hyperbus_internal.h"
#include "hal_i2c_internal.h"
//#include "pmsis/implem/drivers/udma/i2s/i2s_internal.h"
#include "hal_uart_internal.h"
#endif /* HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_hal.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file shall be used for verification purpose only. */
#ifndef HAL_INCLUDE_HAL_PMSIS_HAL_H_
#define HAL_INCLUDE_HAL_PMSIS_HAL_H_
/* Hal includes. */
/* Event unit. */
//#include "event_unit/event_unit.h"
/* Efuse */
/* #include "efuse/pmsis_efuse.h" */
/* GPIO. */
#include "gpio/gpio.h"
/* PWM */
#include "pwm/pwm.h"
#include "pwm/pwm_ctrl.h"
/* RTC */
/* #include "rtc/rtc.h" */
/* Soc_ctrl. */
#include "soc_ctrl/soc_ctrl_pad.h"
/* Soc events generator. */
#include "soc_eu/soc_eu.h"
/* UDMA. */
#include "udma/udma_core.h"
/* #include "udma/udma_cpi.h" */
#include "udma/udma_ctrl.h"
/* #include "udma/udma_dmacpy.h" */
/* #include "udma/udma_hyper.h" */
#include "udma/udma_i2c.h"
#include "udma/udma_i2s.h"
#include "udma/udma_spim.h"
#include "udma/udma_uart.h"
/* Cluster. */
/* DMA. */
#include "dma/dma.h"
#endif /* HAL_INCLUDE_HAL_PMSIS_HAL_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types.h
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/*
* Copyright (C) 2018 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef HAL_INCLUDE_HAL_PMSIS_TYPES_H_
#define HAL_INCLUDE_HAL_PMSIS_TYPES_H_
#include "inttypes.h"
#include "sys/types.h"
/**
* @defgroup groupDrivers Drivers
*/
/// @cond IMPLEM
/**
* @ingroup PMSIS_OS
*/
/**
* @defgroup PMSISTypes PMSIS common types
*/
/**
* @addtogroup PMSISTypes
* @{
*/
/**@{*/
struct pi_device;
struct pmsis_event_kernel_wrap;
// device type placed at the top of conf
typedef enum {
PI_DEVICE_UNKWN_TYPE,
PI_DEVICE_CLUSTER_TYPE,
PI_DEVICE_HYPERBUS_TYPE,
PI_DEVICE_SPI_TYPE,
PI_DEVICE_CPI_TYPE,
PI_DEVICE_I2C_TYPE,
PI_DEVICE_GPIO_TYPE,
PI_DEVICE_PWM_TYPE
} pi_device_e;
typedef struct pi_task pi_task_t;
typedef void (*callback_t)(void *arg);
typedef struct spinlock {
int32_t *lock_ptr; // with test and set mask
int32_t *release_ptr; // standard pointer
} spinlock_t;
typedef struct pi_device_config {
const char *name; // to open, FIXME: device tree
// initialize the device struct (api+ init data) using init_conf
int (*init)(struct pi_device *device);
const void *init_conf;
} pi_device_config_t;
// device struct, it wont stay here
typedef struct pi_device {
struct pi_device_api *api; // function pointers
void *config; // driver conf: might be filled either using device tree or manually
void *data; // driver data
} pi_device_t;
typedef uint32_t (*device_rw_func)(struct pi_device *device, uintptr_t size,
const void *addr, const void *buffer);
typedef uint32_t (*device_ioctl_func)(struct pi_device *device,
uint32_t func_id,
void *arg);
typedef uint32_t (*device_rw_func_async)(struct pi_device *device,
uintptr_t size, const void *addr, const void *buffer, pi_task_t *async);
typedef uint32_t (*device_ioctl_func_async)(struct pi_device *device,
uint32_t func_id, void *arg, pi_task_t *async);
typedef int (*open_func)(struct pi_device *device);
typedef int (*close_func)(struct pi_device *device);
typedef int (*open_func_async)(struct pi_device *device,
pi_task_t *async);
typedef int (*close_func_async)(struct pi_device *device, pi_task_t *async);
// pmsis device minimal api: used for basic inheritance
typedef struct pi_device_api
{
int (*open)(struct pi_device *device);
int (*close)(struct pi_device *device);
int (*open_async)(struct pi_device *device, pi_task_t *async);
int (*close_async)(struct pi_device *device, pi_task_t *async);
ssize_t (*read)(struct pi_device *device, uint32_t ext_addr,
void *buffer, uint32_t size, pi_task_t *async);
ssize_t (*write)(struct pi_device *device, uint32_t ext_addr,
const void *buffer, uint32_t size, pi_task_t *async);
int (*ioctl)(struct pi_device *device, uint32_t func_id, void *arg);
int (*ioctl_async)(struct pi_device *device, uint32_t func_id,
void *arg, pi_task_t *async);
void *specific_api;
} pi_device_api_t;
#ifndef IMPLEM_MUTEX_OBJECT_TYPE
#define IMPLEM_MUTEX_OBJECT_TYPE \
void* mutex_object;
#endif
/** Memory slab allocator */
typedef struct pi_mem_slab pi_mem_slab_t;
/** Task types **/
typedef void (*__pmsis_mutex_func)(void *mutex_object);
typedef struct pmsis_mutex {
IMPLEM_MUTEX_OBJECT_TYPE
__pmsis_mutex_func take;
__pmsis_mutex_func release;
} pmsis_mutex_t, pi_mutex_t;
#ifndef IMPLEM_SEM_OBJECT_TYPE
#define IMPLEM_SEM_OBJECT_TYPE \
void* sem_object;
#endif
/** Task types **/
typedef void (*__pi_sem_func)(void *sem_object);
typedef struct pi_sem {
IMPLEM_SEM_OBJECT_TYPE
__pi_sem_func take;
__pi_sem_func give;
} pi_sem_t;
typedef struct pmsis_spinlock {
uint32_t lock;
} pmsis_spinlock_t;
struct pmsis_event_kernel_wrap {
void *__os_native_task;
void (*event_kernel_main)(struct pmsis_event_kernel_wrap*);
// real event kernel (might be just an api stub for pulpOS)
void *priv;
};
enum pi_task_id {
PI_TASK_CALLBACK_ID,
PI_TASK_NONE_ID,
};
/// @endcond
#endif /* HAL_INCLUDE_HAL_PMSIS_TYPES_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types_pi.h
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/*
* hal_pmsis_types.h
*
* Created on: Feb 20, 2021
* Author: qlblue
*/
#ifndef HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_
#define HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_
/*
* Copyright 2019 GreenWaves Technologies
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PMSIS_IMPLEM_PMSIS_TYPES_H__
#define __PMSIS_IMPLEM_PMSIS_TYPES_H__
//#include "pmsis/pmsis_types.h"
#include "hal_pmsis_types.h"
#ifndef PI_TASK_IMPLEM
#define PI_TASK_IMPLEM \
int8_t destroy;
#endif
#ifndef PI_TASK_IMPLEM_NB_DATA
#define PI_TASK_IMPLEM_NB_DATA 8
#endif /* PI_TASK_IMPLEM_NB_DATA */
typedef struct pi_task
{
// Warning, might be accessed inline in asm, and thus can not be moved
uintptr_t arg[4];
int32_t id;
uint32_t data[PI_TASK_IMPLEM_NB_DATA];
pi_sem_t wait_on;
struct pi_task *next;
volatile int8_t done;
int8_t core_id;
int8_t cluster_id;
PI_TASK_IMPLEM;
} pi_task_t;
#endif /* __PMSIS_IMPLEM_PMSIS_TYPES_H__ */
#endif /* HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_ctrl_periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_ctrl_periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_eu.h
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Germain Haugou (germain.haugou@iis.ee.ethz.ch)
*/
#ifndef HAL_INCLUDE_HAL_SOC_EU_H_
#define HAL_INCLUDE_HAL_SOC_EU_H_
/*
* SOC EVENTS
*/
/* Let's remove for the time being the SOC_EU* macros from the pulp-sdk and use
* the ones form pulp-runtime
*/
/*
#define SOC_EU_EVENT_PERIPH_EVT_NB 160
#define SOC_EU_EVENT_SW_NB (8)
#define SOC_EU_EVENT_NB_TOTAL 256
#define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
#define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT \
(1 << SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
#define SOC_EU_EVENT_UDMA_FIRST_EVT 0
#define SOC_EU_EVENT_UDMA_NB_EVT \
(SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT * EU_NB_PERIPH)
#define SOC_EU_EVENT_UDMA_NB_TGEN_EVT 6
#define SOC_EU_EVENT_PERIPH_FIRST_EVT(x) ((x)*SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT)
#define SOC_EU_EVENT_UART0_RX 0
#define SOC_EU_EVENT_UART0_TX 1
#define SOC_EU_EVENT_UART0_EOT 2
#define SOC_EU_EVENT_UART0_RX_DATA 3
#define SOC_EU_EVENT_SPIM0_RX 4
#define SOC_EU_EVENT_SPIM0_TX 5
#define SOC_EU_EVENT_SPIM0_CMD 6
#define SOC_EU_EVENT_SPIM0_EOT 7
#define SOC_EU_EVENT_I2C0_RX 8
#define SOC_EU_EVENT_I2C0_TX 9
#define SOC_EU_EVENT_I2C1_RX 12
#define SOC_EU_EVENT_I2C1_TX 13
#define SOC_EU_EVENT_SDIO0_RX 16
#define SOC_EU_EVENT_SDIO0_TX 17
#define SOC_EU_EVENT_I2S0_RX 20
#define SOC_EU_EVENT_I2S0_TX 21
#define SOC_EU_EVENT_CPI0_RX 24
#define SOC_EU_EVENT_FILTER0_RX 28
#define SOC_EU_EVENT_FILTER0_TX 29
#define SOC_EU_EVENT_CLUSTER_ON_OFF 31
#define SOC_EU_EVENT_MSP 37
#define SOC_EU_EVENT_ICU_MODE_CHANGED 37
#define SOC_EU_EVENT_ICU_OK 37
#define SOC_EU_EVENT_ICU_DELAYED 37
#define SOC_EU_EVENT_CLUSTER_CG_OK 35
#define SOC_EU_EVENT_PICL_OK 36
#define SOC_EU_EVENT_SCU_OK 37
#define SOC_EU_EVENT_PMU_FIRST_EVENT SOC_EU_EVENT_CLUSTER_ON_OFF
#define SOC_EU_EVENT_PMU_NB_EVENTS 7
#define SOC_EU_EVENT_GPIO 42
#define SOC_EU_EVENT_NB_I2S_CHANNELS 4
#define SOC_EU_EVENT_NB_UDMA_CHANNELS 19
#define SOC_EU_EVENT_FCHWPE0 140
#define SOC_EU_EVENT_FCHWPE1 141
#define SOC_EU_EVENT_SW_EVENT0 48
#define SOC_EU_EVENT_SW_EVENT1 49
#define SOC_EU_EVENT_SW_EVENT2 50
#define SOC_EU_EVENT_SW_EVENT3 51
#define SOC_EU_EVENT_SW_EVENT4 52
#define SOC_EU_EVENT_SW_EVENT5 53
#define SOC_EU_EVENT_SW_EVENT6 54
#define SOC_EU_EVENT_SW_EVENT7 55
#define SOC_EU_EVENT_NB 8
#define SOC_EU_EVENT_REF_CLK_RISE 56
*/
#define SOC_EU_EVENT 0x00
#define SOC_FC_FIRST_MASK 0x04
#define SOC_CL_FIRST_MASK 0x24
#define SOC_PR_FIRST_MASK 0x44
#define SOC_ERR_FIRST_MASK 0x64
#define SOC_TIMER_SEL_HI 0x84
#define SOC_TIMER_SEL_LO 0x88
#define SOC_EU_EVENT_0 0x1
#define SOC_EU_EVENT_1 0x2
#define SOC_EU_EVENT_2 0x4
#define SOC_EU_EVENT_3 0x8
#define SOC_EU_EVENT_4 0x10
#define SOC_EU_EVENT_5 0x20
#define SOC_EU_EVENT_6 0x40
#define SOC_EU_EVENT_7 0x80
#define SOC_TIMER_SEL_ENABLE_SHIFT 31
#define SOC_TIMER_SEL_EVT_SHIFT 0
#define SOC_TIMER_SEL_EVT_WIDTH 8
#define SOC_TIMER_SEL_EVT_MASK ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH))
// #define SOC_TIMER_SEL_EVT_MASK 0xff
#define SOC_TIMER_SEL_ENABLE_DISABLED 0
#define SOC_TIMER_SEL_ENABLE_ENABLED 1
#define SOC_TIMER_SEL_ENABLE_DIS (0 << SOC_TIMER_SEL_ENABLE_SHIFT)
#define SOC_TIMER_SEL_ENABLE_ENA (1 << SOC_TIMER_SEL_ENABLE_SHIFT)
#define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT)
// related to XX_FIRST_MASK registers
#define SOC_NB_EVENT_REGS 8
#define SOC_NB_EVENT_TARGETS 3
#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4)
#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4)
#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4)
/* TODO: doc */
void soc_eu_mask_set(uint32_t offset, uint32_t mask);
uint32_t soc_eu_mask_get(uint32_t offset);
void pulp_soc_eu_event_init();
#endif /* HAL_INCLUDE_HAL_SOC_EU_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_eu_periph.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_timer.h
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_timer_irq.h
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Author: Robert Balas (balasr@iis.ee.ethz.ch) */
#ifndef HAL_INCLUDE_HAL_TIMER_IRQ_H_
#define HAL_INCLUDE_HAL_TIMER_IRQ_H_
#include <stdint.h>
int timer_irq_init(uint32_t ticks);
int timer_irq_set_timeout(uint32_t ticks, bool idle);
uint32_t timer_irq_clock_elapsed();
uint32_t timer_irq_cycle_get_32();
#endif /* HAL_INCLUDE_HAL_TIMER_IRQ_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_internal.h
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef HAL_INCLUDE_HAL_UART_INTERNAL_H_
#define HAL_INCLUDE_HAL_UART_INTERNAL_H_
//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
#include "hal_uart_pi.h"
#include "core-v-mcu-pmsis.h"
//#include "pmsis/task.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define UART_TX_BUFFER_SIZE 16
#define UART_DEFAULT_PRE_ALLOC_EVT 5
#define NB_UART 1
#ifndef UART_DRIVER_DATA_IMPLEM_SPECIFC
#define UART_DRIVER_DATA_IMPLEM_SPECIFC
#endif
/*
* pi_task:
* data[0] = l2_buf
* data[1] = size
* data[2] = channel
* data[3] = repeat_size
* data[4] = device_id (used for delegation)
*/
struct uart_itf_data_s
{
struct pi_task *fifo_head[2]; /*!< 0 = RX | 1 = TX. */
struct pi_task *fifo_tail[2]; /*!< 0 = RX | 1 = TX. */
uint32_t nb_open; /*!< Number of times device has been opened. */
uint32_t device_id; /*!< Device ID. */
UART_DRIVER_DATA_IMPLEM_SPECIFC
};
/*******************************************************************************
* Driver data
*****************************************************************************/
/*******************************************************************************
* Function declaration
******************************************************************************/
/**
* \brief Initialize conf struct.
*
* This function initializes a config struct with default values.
*
* \param conf Pointer to struct pi_uart_conf.
*/
void __pi_uart_conf_init(struct pi_uart_conf *conf);
/**
* \brief Open a device.
*
* This function opens a device.
* A conf struct and a pointer to store UART driver info should be given.
*
* \para driver_data Pointer to store driver info.
* \param conf Pointer to struct pi_uart_conf.
*
* \retval 0 If operation is successfull.
* \retval ERRNO An error code otherwise.
*/
int32_t __pi_uart_open(struct uart_itf_data_s **driver_data,
struct pi_uart_conf *conf);
/**
* \brief Close a device.
*
* This function closes an opened device.
*
* \param driver_data Pointer to driver info.
*/
void __pi_uart_close(struct uart_itf_data_s *driver_data);
/**
* \brief Ioctl commands.
*
* This function allows to configure a device using ioctl commands.
*
* \param driver_data Pointer to driver info.
* \param cmd Ioctl command.
* \param arg Ioctl command arg.
*
* \retval -1 If wrong ioctl command.
* \retval Value Value depending on ioctl command.
*/
int32_t __pi_uart_ioctl(struct uart_itf_data_s *driver_data, uint32_t cmd,
void *arg);
/**
* \brief Transfer data.
*
* This function allows to send/receive data using the periph.
* The transfer is executed immediately if there is no current transfer or no
* pending transfer. Otherwise, the transfer is enqueued in a fifo.
*
* \param driver_data Pointer to driver info.
* \param l2_buf Address of data buffer.
* \param size Size of data buffer.
* \param channel Direction of transfer.
* \param task Event task used to notify end of transfer.
*
* \retval 0 If operation is successfull.
* \retval -1 Otherwise.
*/
int32_t __pi_uart_copy(struct uart_itf_data_s *driver_data, uint32_t l2_buf,
uint32_t size, udma_channel_e channel,
struct pi_task *task);
/**
* \brief Transfer data.
*
* This function allows to send data using the periph.
* The transfer is executed immediately if there is no current transfer or no
* pending transfer. Otherwise, the transfer is enqueued in a fifo.
*
* \param driver_data Pointer to driver info.
* \param buffer Pointer to data buffer.
* \param size Size of data buffer.
* \param task Event task used to notify end of transfer.
*
* \retval 0 If operation is successfull.
* \retval -1 Otherwise.
*/
static inline int __pi_uart_write(struct uart_itf_data_s *data, void *buffer,
uint32_t size, pi_task_t *callback)
{
return __pi_uart_copy(data, (uint32_t) buffer, size, TX_CHANNEL, callback);
}
/**
* \brief Transfer data.
*
* This function allows to receive data using the periph.
* The transfer is executed immediately if there is no current transfer or no
* pending transfer. Otherwise, the transfer is enqueued in a fifo.
*
* \param driver_data Pointer to driver info.
* \param buffer Pointer to data buffer.
* \param size Size of data buffer.
* \param task Event task used to notify end of transfer.
*
* \retval 0 If operation is successfull.
* \retval -1 Otherwise.
*/
static inline int __pi_uart_read(struct uart_itf_data_s *data, void *buffer,
uint32_t size, pi_task_t *callback)
{
return __pi_uart_copy(data, (uint32_t) buffer, size, RX_CHANNEL, callback);
}
#endif /* HAL_INCLUDE_HAL_UART_INTERNAL_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_periph.h
+154
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/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. */
/*
* Copyright (C) 2019 ETH Zurich, University of Bologna
* and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef HAL_INCLUDE_HAL_UART_PERIPH_H_
#define HAL_INCLUDE_HAL_UART_PERIPH_H_
#include "hal_udma_core_periph.h"
/* ----------------------------------------------------------------------------
-- UART Peripheral Access Layer --
---------------------------------------------------------------------------- */
/** UART_Type Register Layout Typedef */
typedef struct
{
udma_channel_t rx; /**< UDMA RX channels struct. */
udma_channel_t tx; /**< UDMA TX channels struct. */
volatile uint32_t status; /**< Status register */
volatile uint32_t setup; /**< Configuration register */
} uart_t;
/* ----------------------------------------------------------------------------
-- UART Register Bitfield Access --
---------------------------------------------------------------------------- */
/*! @name STATUS */
/* TX busy status flag */
#define UART_STATUS_TX_BUSY_MASK (0x1)
#define UART_STATUS_TX_BUSY_SHIFT (0)
#define UART_STATUS_TX_BUSY(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_TX_BUSY_SHIFT)) & UART_STATUS_TX_BUSY_MASK)
/* RX busy status flag */
#define UART_STATUS_RX_BUSY_MASK (0x2)
#define UART_STATUS_RX_BUSY_SHIFT (1)
#define UART_STATUS_RX_BUSY(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_BUSY_SHIFT)) & UART_STATUS_RX_BUSY_MASK)
/* RX parity error status flag */
#define UART_STATUS_RX_PE_MASK (0x4)
#define UART_STATUS_RX_PE_SHIFT (2)
#define UART_STATUS_RX_PE(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_PE_SHIFT)) & UART_STATUS_RX_PE_MASK)
/*! @name SETUP */
/* Set parity generation and check:
- 1'b0: disable
- 1'b1: enable */
#define UART_SETUP_PARITY_ENA_MASK (0x1)
#define UART_SETUP_PARITY_ENA_SHIFT (0)
#define UART_SETUP_PARITY_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_PARITY_ENA_SHIFT)) & UART_SETUP_PARITY_ENA_MASK)
/* Set character length:
- 2'b00: 5 bits
- 2'b01: 6 bits
- 2'b10: 7 bits
- 2'b11: 8 bits */
#define UART_SETUP_BIT_LENGTH_MASK (0x6)
#define UART_SETUP_BIT_LENGTH_SHIFT (1)
#define UART_SETUP_BIT_LENGTH(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_BIT_LENGTH_SHIFT)) & UART_SETUP_BIT_LENGTH_MASK)
/* Set stop bits length:
- 2'b0: 1 stop bit
- 2'b1: 2 stop bits */
#define UART_SETUP_STOP_BITS_MASK (0x8)
#define UART_SETUP_STOP_BITS_SHIFT (3)
#define UART_SETUP_STOP_BITS(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_STOP_BITS_SHIFT)) & UART_SETUP_STOP_BITS_MASK)
/* Set TX transceiver state:
- 1'b0: disable
- 1'b1: enable */
#define UART_SETUP_TX_ENA_MASK (0x100)
#define UART_SETUP_TX_ENA_SHIFT (8)
#define UART_SETUP_TX_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_TX_ENA_SHIFT)) & UART_SETUP_TX_ENA_MASK)
/* Set RX transceiver state:
- 1'b0: disable
- 1'b1: enable */
#define UART_SETUP_RX_ENA_MASK (0x200)
#define UART_SETUP_RX_ENA_SHIFT (9)
#define UART_SETUP_RX_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_RX_ENA_SHIFT)) & UART_SETUP_RX_ENA_MASK)
/* Sets the clock divider ratio for the baud rate generator. */
#define UART_SETUP_CLKDIV_MASK (0xffff0000)
#define UART_SETUP_CLKDIV_SHIFT (16)
#define UART_SETUP_CLKDIV(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_CLKDIV_SHIFT)) & UART_SETUP_CLKDIV_MASK)
/*! @name STATUS */
typedef union
{
struct
{
/* TX busy status flag */
uint32_t tx_busy:1;
/* RX busy status flag */
uint32_t rx_busy:1;
/* RX parity error status flag */
uint32_t rx_pe:1;
} field;
uint32_t word;
} uart_status_t;
/*! @name SETUP */
typedef union
{
struct
{
/* Set parity generation and check:
- 1'b0: disable
- 1'b1: enable */
uint32_t parity_ena:1;
/* Set character length:
- 2'b00: 5 bits
- 2'b01: 6 bits
- 2'b10: 7 bits
- 2'b11: 8 bits */
uint32_t bit_length:2;
/* Set stop bits length:
- 2'b0: 1 stop bit
- 2'b1: 2 stop bits */
uint32_t stop_bits:1;
uint32_t reserved_0:4;
/* Set TX transceiver state:
- 1'b0: disable
- 1'b1: enable */
uint32_t tx_ena:1;
/* Set RX transceiver state:
- 1'b0: disable
- 1'b1: enable */
uint32_t rx_ena:1;
uint32_t reserved_1:6;
/* Sets the clock divider ratio for the baud rate generator. */
uint32_t clkdiv:16;
} field;
uint32_t word;
} uart_setup_t;
#endif /* HAL_INCLUDE_HAL_UART_PERIPH_H_ */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_pi.h
+436
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_cam_reg_defs.h
+204
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_core_periph.h
+384
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_ctrl_reg_defs.h
+103
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/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __UDMA_CTRL_H_
#define __UDMA_CTRL_H_
//---------------------------------//
//
// Module: UDMA_CTRL
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t reg_cg;
struct {
__IO uint32_t periph_clk_enable : 32;
} reg_cg_b;
};
// Offset = 0x0004
union {
__IO uint32_t reg_cfg_evt;
struct {
__IO uint32_t cmp_event0 : 8;
__IO uint32_t cmp_event1 : 8;
__IO uint32_t cmp_event2 : 8;
__IO uint32_t cmp_event3 : 8;
} reg_cfg_evt_b;
};
// Offset = 0x0008
union {
__IO uint32_t reg_rst;
struct {
__IO uint32_t periph_reset : 32;
} reg_rst_b;
};
} UdmaCtrl_t;
#define REG_REG_CG 0x000
#define REG_REG_CG_PERIPH_CLK_ENABLE_LSB 0
#define REG_REG_CG_PERIPH_CLK_ENABLE_MASK 0xffffffff
#define REG_REG_CFG_EVT 0x004
#define REG_REG_CFG_EVT_CMP_EVENT3_LSB 24
#define REG_REG_CFG_EVT_CMP_EVENT3_MASK 0xff
#define REG_REG_CFG_EVT_CMP_EVENT2_LSB 16
#define REG_REG_CFG_EVT_CMP_EVENT2_MASK 0xff
#define REG_REG_CFG_EVT_CMP_EVENT1_LSB 8
#define REG_REG_CFG_EVT_CMP_EVENT1_MASK 0xff
#define REG_REG_CFG_EVT_CMP_EVENT0_LSB 0
#define REG_REG_CFG_EVT_CMP_EVENT0_MASK 0xff
#define REG_REG_RST 0x008
#define REG_REG_RST_PERIPH_RESET_LSB 0
#define REG_REG_RST_PERIPH_RESET_MASK 0xffffffff
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __UDMA_CTRL_H_
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_i2cm_reg_defs.h
+174
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/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __UDMA_I2CM_H_
#define __UDMA_I2CM_H_
//---------------------------------//
//
// Module: UDMA_I2CM
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t rx_saddr;
struct {
__IO uint32_t saddr : 12;
} rx_saddr_b;
};
// Offset = 0x0004
union {
__IO uint32_t rx_size;
struct {
__IO uint32_t size : 16;
} rx_size_b;
};
// Offset = 0x0008
union {
__IO uint32_t rx_cfg;
struct {
__IO uint32_t continuous : 1;
__IO uint32_t : 3;
__IO uint32_t en : 1;
__IO uint32_t pending : 1;
__IO uint32_t clr : 1;
} rx_cfg_b;
};
__I uint32_t unused0[1];
// Offset = 0x0010
union {
__IO uint32_t tx_saddr;
struct {
__IO uint32_t saddr : 12;
} tx_saddr_b;
};
// Offset = 0x0014
union {
__IO uint32_t tx_size;
struct {
__IO uint32_t size : 16;
} tx_size_b;
};
// Offset = 0x0018
union {
__IO uint32_t tx_cfg;
struct {
__IO uint32_t continuous : 1;
__IO uint32_t : 3;
__IO uint32_t en : 1;
__IO uint32_t pending : 1;
__IO uint32_t clr : 1;
} tx_cfg_b;
};
__I uint32_t unused1[1];
// Offset = 0x0020
union {
__IO uint32_t status;
struct {
__IO uint32_t busy : 1;
__IO uint32_t al : 1;
} status_b;
};
// Offset = 0x0024
union {
__IO uint32_t setup;
struct {
__IO uint32_t reset : 1;
} setup_b;
};
} UdmaI2cm_t;
#define REG_RX_SADDR 0x00
#define REG_RX_SADDR_SADDR_LSB 0
#define REG_RX_SADDR_SADDR_MASK 0xfff
#define REG_RX_SIZE 0x04
#define REG_RX_SIZE_SIZE_LSB 0
#define REG_RX_SIZE_SIZE_MASK 0xffff
#define REG_RX_CFG 0x08
#define REG_RX_CFG_CLR_LSB 6
#define REG_RX_CFG_CLR_MASK 0x1
#define REG_RX_CFG_PENDING_LSB 5
#define REG_RX_CFG_PENDING_MASK 0x1
#define REG_RX_CFG_EN_LSB 4
#define REG_RX_CFG_EN_MASK 0x1
#define REG_RX_CFG_CONTINUOUS_LSB 0
#define REG_RX_CFG_CONTINUOUS_MASK 0x1
#define REG_TX_SADDR 0x10
#define REG_TX_SADDR_SADDR_LSB 0
#define REG_TX_SADDR_SADDR_MASK 0xfff
#define REG_TX_SIZE 0x14
#define REG_TX_SIZE_SIZE_LSB 0
#define REG_TX_SIZE_SIZE_MASK 0xffff
#define REG_TX_CFG 0x18
#define REG_TX_CFG_CLR_LSB 6
#define REG_TX_CFG_CLR_MASK 0x1
#define REG_TX_CFG_PENDING_LSB 5
#define REG_TX_CFG_PENDING_MASK 0x1
#define REG_TX_CFG_EN_LSB 4
#define REG_TX_CFG_EN_MASK 0x1
#define REG_TX_CFG_CONTINUOUS_LSB 0
#define REG_TX_CFG_CONTINUOUS_MASK 0x1
#define REG_STATUS 0x20
#define REG_STATUS_AL_LSB 1
#define REG_STATUS_AL_MASK 0x1
#define REG_STATUS_BUSY_LSB 0
#define REG_STATUS_BUSY_MASK 0x1
#define REG_SETUP 0x24
#define REG_SETUP_RESET_LSB 0
#define REG_SETUP_RESET_MASK 0x1
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __UDMA_I2CM_H_
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_qspi_reg_defs.h
+213
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_sdio_reg_defs.h
+292
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_uart_reg_defs.h
+247
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/udma_camera_reg_defs.h
+204
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_apb_i2cs.c
+123
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#include "core-v-mcu-config.h"
#include "hal_apb_i2cs_reg_defs.h"
uint8_t hal_get_apb_i2cs_slave_address(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_dev_address_b.slave_addr;
}
void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
apbI2cSlave->i2cs_dev_address_b.slave_addr = aSlaveAddress;
}
uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
if( aStatus == 1 )
apbI2cSlave->i2cs_enable_b.ip_enable = 1;
else if( aStatus == 0 )
apbI2cSlave->i2cs_enable_b.ip_enable = 0;
return (uint8_t)apbI2cSlave->i2cs_enable_b.ip_enable;
}
uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_read_data_port;
}
void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
apbI2cSlave->i2cs_fifo_apb_i2c_write_data_port = aData;
}
uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_write_flags;
}
uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_read_flags;
}
uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_fifo_apb_i2c_read_flags;
}
uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_fifo_apb_i2c_write_flags;
}
uint8_t hal_get_i2cs_msg_i2c_apb(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
return (apbI2cSlave->i2cs_msg_i2c_apb);
}
uint8_t hal_get_i2cs_msg_i2c_apb_status(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_msg_i2c_apb_status;
}
void hal_set_i2cs_msg_apb_i2c(uint8_t aData)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
apbI2cSlave->i2cs_msg_apb_i2c = aData;
}
uint8_t hal_get_i2cs_msg_apb_i2c_status(void)
{
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
return (uint8_t )apbI2cSlave->i2cs_msg_apb_i2c_status;
}
void hal_i2cs_fifo_i2c_apb_FIFO_flush(void)
{
int i = 0;
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
apbI2cSlave->i2cs_fifo_i2c_apb_flush_b.enable = 1;
for( i=0; i<1000; i++);
apbI2cSlave->i2cs_fifo_i2c_apb_flush_b.enable = 0;
for( i=0; i<1000; i++);
}
void hal_i2cs_fifo_apb_i2c_FIFO_flush(void)
{
int i = 0;
ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
apbI2cSlave->i2cs_fifo_apb_i2c_flush_b.enable = 1;
for( i=0; i<1000; i++);
apbI2cSlave->i2cs_fifo_apb_i2c_flush_b.enable = 0;
for( i=0; i<1000; i++);
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fc_event.c
+119
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/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* hal_fc_event.c
*
* Created on: Feb 19, 2021
* Author: qlblue
*/
//#include "pmsis/implem/drivers/fc_event/fc_event.h"
#include "hal_fc_event.h"
//#include "pmsis/implem/hal/hal.h"
#include "hal_soc_eu_periph.h"
//#include "pmsis/implem/drivers/pmsis_it.h"
//#include "FreeRTOS.h"
//#include "semphr.h"
#include "rtthread.h"
#define unuse_freertos_in_event
/*******************************************************************************
* Variables, macros, structures,... definition
******************************************************************************/
/*******************************************************************************
* Function definition
******************************************************************************/
static void fc_event_null_event(void *arg);
static volatile pi_fc_event_handler_t fc_event_handlers[SOC_EU_NB_FC_EVENTS];
//static SemaphoreHandle_t fc_event_semaphores[SOC_EU_NB_FC_EVENTS];
static void fc_event_null_event(void *arg)
{
return;
}
void pi_fc_event_handler_init(uint32_t fc_event_irq)
{
/* TODO: fix this mess, that should be 8 32-bit writes */
/* open the mask for fc_soc_event irq */
for (int i = 0; i < SOC_EU_NB_FC_EVENTS; i++) {
pi_fc_event_handler_clear(i);
}
/* NVIC_SetVector(fc_event_irq, (uint32_t)__handler_wrapper_light_fc_event_handler);*/
//irqn_enable(fc_event_irq);
}
#if 0
void pi_fc_event_handler_set(uint32_t event_id,
pi_fc_event_handler_t event_handler,
SemaphoreHandle_t semaphoreHandle)
{
if (event_handler != NULL) {
fc_event_handlers[event_id] = event_handler;
}
if (semaphoreHandle != NULL) {
fc_event_semaphores[event_id] = semaphoreHandle;
}
}
#endif
void user_pi_fc_event_handler_set(uint32_t event_id,
pi_fc_event_handler_t event_handler)
{
if (event_handler != NULL) {
fc_event_handlers[event_id] = event_handler;
}
}
void pi_fc_event_handler_clear(uint32_t event_id)
{
fc_event_handlers[event_id] = (pi_fc_event_handler_t)fc_event_null_event;
//fc_event_semaphores[event_id] = NULL;// remove from project
}
/* TODO: Use Eric's FIRQ ABI */
void fc_soc_event_handler1 (uint32_t mcause)
{
uint32_t val = 0;
//static BaseType_t xHigherPriorityTaskWoken;
uint32_t event_id = *(uint32_t*)(0x1a106090); // new event fifo address
event_id &= 0xFF;
/* redirect to handler with jump table */
if (fc_event_handlers[event_id] != NULL) {
fc_event_handlers[event_id]((void *)event_id);
}
#if 0
if (fc_event_semaphores[event_id] != NULL) {
/* Unblock the task by releasing the semaphore. */
#ifdef unuse_freertos_in_event
SemaphoreHandle_t xSemaphoreHandle = fc_event_semaphores[event_id];
xSemaphoreGiveFromISR( xSemaphoreHandle, &xHigherPriorityTaskWoken );
//rt_schedule();
//portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
//__asm volatile( "ecall" );
#endif
}
#endif
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll.c
+208
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll_pi.c
+206
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio.c
+239
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bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio_pulp.c
+171
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/*
* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Driver to control and configure the PULP GPIO pins */
/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include <stdint.h>
#include <assert.h>
#include <hal_gpio_pulp.h>
#include <hal_pinmux1.h>
#include <bits.h>
#include <pulp_io.h>
#include "core-v-mcu-pulp-mem-map.h"
int gpio_pin_conf_pad(int pin, uint32_t flags)
{
assert(0 <= pin && pin < 32);
/* this is only correct if the static assert in gpio.h regarding padcfg*
* registers doesn't fail
*/
uintptr_t pad_conf_reg =
(((uintptr_t)pin & 0xf) >> 3) * 4 +
(uintptr_t)(PULP_GPIO_ADDR + GPIO_PADCFG0_OFFSET);
uint32_t pad_shift = (pin & 0x3) << 3; /* (0,1) (8,9) (16,17) (24,25) */
uint32_t val = (flags & GPIO_PULL_ENABLE) |
(flags & GPIO_DRIVE_STRENGTH_HIGH) << 1;
writew(val << pad_shift, pad_conf_reg);
return 0;
}
/* for now we only handle the gpio from 0-31 and ignore 32-63 */
int gpio_pin_configure(int pin, uint32_t flags)
{
/* check for misconfigurations */
assert(!((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)));
/* set pad mux to gpio */
pinmux_pin_set(pin, PINMUX_FUNC_B);
/* configure pad pull and drive */
gpio_pin_conf_pad(pin, flags);
/* configure direction */
uint32_t pads = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADDIR_OFFSET));
WRITE_BIT(pads, pin, flags & GPIO_OUTPUT);
writew(pads, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADDIR_OFFSET));
/* default value to prevent glitches */
if (flags & GPIO_OUTPUT_INIT_HIGH)
gpio_pin_set_raw(pin, 1);
if (flags & GPIO_OUTPUT_INIT_LOW)
gpio_pin_set_raw(pin, 0);
/* control pad clock gating: need to enable clock for inputs */
uint32_t en = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_GPIOEN_OFFSET));
WRITE_BIT(en, pin, GPIO_INPUT);
writew(en, (uintptr_t)(PULP_GPIO_ADDR + GPIO_GPIOEN_OFFSET));
return 0;
}
inline int gpio_port_get_raw(uint32_t *value)
{
/* this api is a bit dumb but the return value is mean to signal an
* error. This never happens in our implementation.
*/
*value = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADIN_OFFSET));
return 0;
}
inline int gpio_port_set_masked_raw(uint32_t mask, uint32_t value)
{
uint32_t outval =
readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
writew((outval & ~mask) | (value & mask),
(uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
return 0;
}
inline int gpio_port_set_bits_raw(uint32_t mask)
{
uint32_t outval =
readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
writew(outval | mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
return 0;
}
inline int gpio_port_clear_bits_raw(uint32_t mask)
{
uint32_t outval =
readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
writew(outval & ~mask,
(uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
return 0;
}
inline int gpio_port_toggle_bits(uint32_t mask)
{
uint32_t outval =
readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
writew(outval ^ mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
return 0;
}
inline int gpio_pin_get_raw(int pin)
{
assert(0 <= pin && pin < 32);
uint32_t value = 0;
int ret = gpio_port_get_raw(&value);
if (!ret)
ret = (value & BIT(pin)) != 0;
return ret;
}
inline int gpio_pin_set_raw(int pin, int value)
{
assert(0 <= pin && pin < 32);
if (value != 0)
gpio_port_set_bits_raw(BIT(pin));
else
gpio_port_clear_bits_raw(BIT(pin));
return 0;
}
inline int gpio_pin_toggle(int pin)
{
return gpio_port_toggle_bits(BIT(pin));
}
/* TODO: gpio interrupt handling and configuration */
/* static inline int gpio_pin_interrupt_configure() */
/* { */
/* } */
/* static inline int gpio_manage_callback(){ */
/* } */
/* static inline int gpio_enable_callback(){ */
/* } */
/* static inline int gpio_disable_callback(){ */
/* } */
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_irq.c
+73
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Driver to control and configure the PULP IRQ (apb_interrupt_control)*/
#include <csr.h>
#include <pulp_io.h>
#include <stdint.h>
#include "core-v-mcu-pulp-mem-map.h"
#include "hal_irq.h"
/* utility functions for PULPs external interrupt controller */
void irq_mask(uint32_t mask)
{
writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_OFFSET));
}
void irq_enable(uint32_t mask)
{
writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET));
}
void irq_disable(uint32_t mask)
{
writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET));
}
/* utility functions for the core level interrupt (CLINT) described in the
* RISC-V privileged specification */
uint32_t irq_clint_disable()
{
uint32_t val = csr_read_clear(CSR_MSTATUS, MSTATUS_IE);
return val;
}
uint32_t irq_clint_enable()
{
uint32_t val = 0;
val = csr_read(CSR_MSTATUS);
val = csr_read_set(CSR_MSTATUS, MSTATUS_IE);
//csr_write(CSR_MIE, BIT(25));
val = csr_read(CSR_MSTATUS);
return val;
}
/* TODO: make this a constructor? */
void irq_init()
{
/* the debug module could have enabled irq so we disable it during
* initialization
*/
irq_disable(0xffffffff);
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux.c
+46
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/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
//#include "FreeRTOS.h"
//#include "FreeRTOSConfig.h"
//#include "kernel/include/task.h" // Needed for configASSERT
#include "core-v-mcu-config.h"
#include "hal_apb_soc_ctrl_regs.h"
#include "hal_pinmux.h"
void hal_setpullup(uint8_t io_num, uint8_t on) {
SocCtrl_t* psoc_ctrl = SOC_CTRL_START_ADDR;
configASSERT (io_num < N_IO);
psoc_ctrl->io_ctrl_b[io_num].cfg = on;
}
void hal_setpinmux(uint8_t io_num, uint8_t mux_sel) {
SocCtrl_t* psoc_ctrl = SOC_CTRL_START_ADDR;
configASSERT (io_num < N_IO);
psoc_ctrl->io_ctrl_b[io_num].mux = mux_sel;
}
uint8_t hal_getpinmux(uint8_t io_num) {
SocCtrl_t* psoc_ctrl = SOC_CTRL_START_ADDR;
configASSERT (io_num < N_IO);
return psoc_ctrl->io_ctrl_b[io_num].mux;
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux1.c
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/*
* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Driver to control and configure pad mux */
#include <stdint.h>
#include <assert.h>
#include <hal_pinmux1.h>
#include <pulp_io.h>
#include "core-v-mcu-pulp-mem-map.h"
#include "hal_apb_soc.h"
/* TODO: we only support pin 0-31 */
int pinmux_pin_set(int pin, uint32_t func)
{
assert(0 <= pin && pin < 32);
uintptr_t padfun_reg =
((pin & 0xf) >> 4) * 4 +
(PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADFUN0_OFFSET);
uint32_t padfun_shift = (pin & 0x7) << 1; /* 16 pads a 2 bits per reg */
writew((func & 0x3) << padfun_shift, padfun_reg);
return 0;
}
int pinmux_pin_get(int pin, uint32_t *func)
{
assert(0 <= pin && pin < 32);
uintptr_t padfun_reg =
((pin & 0xf) >> 4) * 4 +
(PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADFUN0_OFFSET);
uint32_t padfun_shift = (pin & 0x7) << 1; /* 16 pads a 2 bits per reg */
uint32_t padfunval = readw(padfun_reg);
*func = (padfunval >> padfun_shift) & 0x3;
return 0;
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_soc_eu.c
+52
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Driver to control and configure the PULP event unit */
/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include <pulp_io.h>
#include <stdint.h>
#include "core-v-mcu-config.h"
#include "core-v-mcu-memory-map.h" //ToDo: this should be merged into config.h
#include "hal_soc_eu.h"
void soc_eu_mask_set(uint32_t offset, uint32_t mask)
{
writew(mask, (uintptr_t)(SOC_EU_ADDR + offset));
}
uint32_t soc_eu_mask_get(uint32_t offset)
{
return readw((uintptr_t)(SOC_EU_ADDR + offset));
}
/* void soc_eu_irq_mask_set(uint32_t mask) */
/* { */
/* writew(mask, PULP_SOC_EU_ADDR + ) */
/* } */
/* uint32_t soc_eu_irq_mask_get() */
/* { */
/* } */
void pulp_soc_eu_event_init()
{
/* deactivate all soc events */
for (int i = 0; i < SOC_NB_EVENT_REGS; i++) {
soc_eu_mask_set(SOC_FC_FIRST_MASK + i * 4, 0xffffffff);
}
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_timer_irq.c
+92
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/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Driver to configure PULP timer as periodic interrupt source */
/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Germain Haugou (germain.haugou@iis.ee.ethz.ch)
*/
#include <bits.h>
#include <pulp_io.h>
#include <stdint.h>
#include <stdbool.h>
#include "core-v-mcu-pulp-mem-map.h"
#include "hal_timer.h"
#include "hal_timer_irq.h"
//#include "FreeRTOSConfig.h"
/* TODO: used to measure elapsed time since last "visit" */
static uint32_t last_count;
int timer_irq_disable(){
writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_HI_OFFSET));
}
int timer_irq_init(uint32_t ticks)
{
/* TODO: enable soc_eu timer interrupt */
/* set the interrupt interval */
timer_irq_set_timeout(ticks, false);
/* We use only one of the 32-bit timer, leaving the other half available
* as an additional timer. We didn't opt for using both together as
* 64-bit timer.
*
* Enable timer, use 32khz ref clock as source. Timer will reset
* automatically to zero after causing an interrupt.
*/
/* use high timer for now as int actually gets to cpu */
#ifdef configMTIME_BASE_ADDRESS
writew(0xc000000f,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
#else
writew(TIMER_CFG_LO_ENABLE_MASK | TIMER_CFG_LO_RESET_MASK |
TIMER_CFG_LO_MODE_MASK |
TIMER_CFG_LO_IRQEN_MASK,
(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
#endif
return 0;
}
int timer_irq_set_timeout(uint32_t ticks, bool idle)
{
(void)idle;
/* fast reset, value doesn't matter */
writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_LO_OFFSET));
writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_LO_OFFSET));
writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_HI_OFFSET));
// writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_HI_OFFSET));
return 0;
}
/* TODO: implement */
uint32_t timer_irq_clock_elapsed()
{
return 0;
}
uint32_t timer_irq_cycle_get_32()
{
return readw((uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CNT_LO_OFFSET));
}
bsp/core-v-mcu/core-v-cv32e40p/.config
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bsp/core-v-mcu/core-v-cv32e40p/Kconfig
+21
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../Libraries/Kconfig"
source "board/Kconfig"

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