Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-03-27 17:45:13 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

[bsp] add core-v-mcu bsp (#6705)

Browse Source 
* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>
This commit is contained in:
Yaochenger
2022-12-09 04:01:37 +08:00
committed by GitHub
parent ab9a80c408
commit 9d8da76543
137 changed files with 24743 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
bsp/core-v-mcu/Libraries/Kconfig Normal file
View File

@@ -0,0 +1,7 @@
config SOC_RISCV_FAMILY_Core_V
bool
config SOC_RISCV_SERIES_Core_V
bool
select ARCH_RISCV
select SOC_RISCV_FAMILY_Core_V

21
bsp/core-v-mcu/Libraries/core_v_drivers/SConscript Normal file
View File

@@ -0,0 +1,21 @@
import rtconfig
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Split("""
source/udma_uart_driver.c
""")
if GetDepend('SOC_RISCV_FAMILY_Core_V'):
if GetDepend('BSP_USING_UART'):
src += ['source/drv_usart.c']
path = [
cwd + '/include']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

33
bsp/core-v-mcu/Libraries/core_v_drivers/include/camera.h Normal file
View File

@@ -0,0 +1,33 @@
#ifndef __CAMERA_H__
#define __CAMERA_H__
//#include <FreeRTOS.h>
#include <queue.h>
#include "himax.h"
typedef struct {
volatile uint32_t *rx_saddr; // 0x00
volatile uint32_t rx_size; // 0x04
volatile uint32_t rx_cfg; // 0x08
volatile uint32_t rx_initcfg;// 0x0C
volatile uint32_t *tx_saddr; // 0x10
volatile uint32_t tx_size; // 0x14
volatile uint32_t tx_cfg; // 0x18
volatile uint32_t tx_initcfg;// 0x1C
volatile uint32_t cfg_glob; // 0x20
volatile uint32_t cfg_ll; // 0x24
volatile uint32_t cfg_ur; // 0x28
volatile uint32_t cfg_size; // 0x2C
volatile uint32_t cfg_filter;// 0x30
volatile uint32_t vsync_pol; // 0x34
} camera_struct_t;
typedef struct {
uint16_t addr;
uint8_t data;
}reg_cfg_t;
#endif

27
bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_log.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

31
bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_usart.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun the first version
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
/* corev config class */
struct corev_uart_config
{
const char *name;
};
/* corevs uart dirver class */
struct corev_uart
{
struct corev_uart_config *config;
struct rt_serial_device serial;
};
extern void uart_rx_isr (void *id);
int rt_hw_usart_init(void);
#endif

144
bsp/core-v-mcu/Libraries/core_v_drivers/include/himax.h Normal file
View File

@@ -0,0 +1,144 @@
/*
* Copyright (C) 2018 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Copyright (C) 2018 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HIMAX_H__
#define __HIMAX_H__
/*
* HIMAX camera macros
*/
// Register address
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define FRAME_COUNT 0x0005
#define PIXEL_ORDER 0x0006
// R&W registers
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define SW_RESET 0x0103
#define GRP_PARAM_HOLD 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Binning mode control
#define READOUT_X 0x0383
#define READOUT_Y 0x0387
#define BINNING_MODE 0x0390
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_CFG 0x1000
#define BLC_TGT 0x1003
#define BLI_EN 0x1006
#define BLC2_TGT 0x1007
// Sensor reserved
#define DPC_CTRL 0x1008
#define SINGLE_THR_HOT 0x100B
#define SINGLE_THR_COLD 0x100C
// VSYNC,HSYNC and pixel shift register
#define VSYNC_HSYNC_PIXEL_SHIFT_EN 0x1012
// Automatic exposure gain control
#define AE_CTRL 0x2100
#define AE_TARGET_MEAN 0x2101
#define AE_MIN_MEAN 0x2102
#define CONVERGE_IN_TH 0x2103
#define CONVERGE_OUT_TH 0x2104
#define MAX_INTG_H 0x2105
#define MAX_INTG_L 0x2106
#define MIN_INTG 0x2107
#define MAX_AGAIN_FULL 0x2108
#define MAX_AGAIN_BIN2 0x2109
#define MIN_AGAIN 0x210A
#define MAX_DGAIN 0x210B
#define MIN_DGAIN 0x210C
#define DAMPING_FACTOR 0x210D
#define FS_CTRL 0x210E
#define FS_60HZ_H 0x210F
#define FS_60HZ_L 0x2110
#define FS_50HZ_H 0x2111
#define FS_50HZ_L 0x2112
#define FS_HYST_TH 0x2113
// Motion detection control
#define MD_CTRL 0x2150
#define I2C_CLEAR 0x2153
#define WMEAN_DIFF_TH_H 0x2155
#define WMEAN_DIFF_TH_M 0x2156
#define WMEAN_DIFF_TH_L 0x2157
#define MD_THH 0x2158
#define MD_THM1 0x2159
#define MD_THM2 0x215A
#define MD_THL 0x215B
// Sensor timing control
#define QVGA_WIN_EN 0x3010
#define SIX_BIT_MODE_EN 0x3011
#define PMU_AUTOSLEEP_FRAMECNT 0x3020
#define ADVANCE_VSYNC 0x3022
#define ADVANCE_HSYNC 0x3023
#define EARLY_GAIN 0x3035
// IO and clock control
#define BIT_CONTROL 0x3059
#define OSC_CLK_DIV 0x3060
#define ANA_Register_11 0x3061
#define IO_DRIVE_STR 0x3062
#define IO_DRIVE_STR2 0x3063
#define ANA_Register_14 0x3064
#define OUTPUT_PIN_STATUS_CONTROL 0x3065
#define ANA_Register_17 0x3067
#define PCLK_POLARITY 0x3068
/*
* Useful value of Himax registers
*/
#define HIMAX_RESET 0x01
#define Pclk_rising_edge 0x00
#define Pclk_falling_edge 0x01
#define BYPASS_BIGEND 5
enum{
HIMAX_Standby = 0x0,
HIMAX_Streaming = 0x1, // I2C triggered streaming enable
HIMAX_Streaming2 = 0x3, // Output N frames
HIMAX_Streaming3 = 0x5 // Hardware Trigger
};
#endif

61
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_cam_driver.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_cam_reg_defs.h"
typedef enum {
kCamReset,
kCamID,
kCamInit,
kCamFrame
} udma_cam_control_type_t;
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} cam_cmd_t;
uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam);
void cam_open (uint8_t cam_id);
// helper functions
void _himaxRegWrite(unsigned int addr, unsigned char value);
#endif /* DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_ */

61
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_i2cm_driver.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
#define SEMAPHORE_WAIT_TIME_IN_MS 10
typedef enum {
kI2cmReset
} udma_i2cm_control_type_t;
typedef enum {
kI2cmCmdStart = 0x00,
kI2cmCmdStop = 0x20,
kI2cmCmdRdAck = 0x40,
kI2cmCmdRdNack = 0x60,
kI2cmCmdWr = 0x80,
kI2cmCmdWait = 0xA0,
kI2cmCmdRpt = 0xC0,
kI2cmCmdCfg = 0xE0,
kI2cmCmdWaitEvt = 0x10,
} i2cm_cmd_t;
uint16_t udma_i2cm_open (uint8_t i2c_id, uint32_t i2c_clk_freq);
uint16_t udma_i2cm_close (uint8_t i2c_id);
uint16_t udma_i2cm_control(uint8_t i2c_id, udma_i2cm_control_type_t control_type, void* pparam);
uint8_t udma_i2cm_write(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t write_len, uint8_t* write_data, bool more_follows);
uint8_t udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
uint8_t udma_i2cm_16read8(uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
// helper functions
uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr);
uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr);
uint8_t _udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
uint8_t _udma_i2cm_send_stop(uint8_t i2c_id);
#endif /* DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_ */

64
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_qspi_driver.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kQSPImReset
} udma_qspim_control_type_t;
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} spim_cmd_t;
uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t spi_clk_freq);
uint16_t udma_qspim_close (uint8_t qspim_id);
uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam);
void udma_qspim_write(uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd);
uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs);
void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs);
uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs);
// helper functions
#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

69
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_sdio_driver.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
#define DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
#include <stdint.h>
#include <stdbool.h>
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kSDIOmReset
} udma_sdio_control_type_t;
/*
typedef enum {
kSPIm_Cfg = (0x0 << 28),
kSPIm_SOT = (0x1 << 28),
kSPIm_SendCmd = (0x2 << 28),
kSPIm_Dummy = (0x4 << 28),
kSPIm_Wait = (0x5 << 28),
kSPIm_TxData = (0x6 << 28),
kSPIm_RxData = (0x7 << 28),
kSPIm_Repeat = (0x8 << 28),
kSPIm_EOT = (0x9 << 28),
kSPIm_RepeatEnd = (0xa << 28),
kSPIm_RxCheck = (0xb << 28),
kSPIm_FDX = (0xc << 28),
kSPIm_UCA = (0xd << 28),
kSPIm_UCS = (0xe << 28)
} spim_cmd_t;
*/
uint16_t udma_sdio_open (uint8_t sdio_id);
uint16_t udma_sdio_close (uint8_t sdio_id);
uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam);
uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf);
void udma_sdio_write(uint8_t sdio_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
void udma_sdio_read(uint8_t sdio_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_flash_erase(uint8_t sdio_id, uint8_t cs, uint32_t addr, uint8_t cmd);
uint32_t udma_flash_readid(uint8_t sdio_id, uint8_t cs);
void udma_flash_read(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
void udma_flash_write(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
uint32_t udma_flash_reset_enable(uint8_t sdio_id, uint8_t cs);
uint32_t udma_flash_reset_memory(uint8_t sdio_id, uint8_t cs);
uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
void udma_sdio_clearDataSetup(uint8_t sdio_id);
// helper functions
#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

39
bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_uart_driver.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __UDMA_UART_DRIVER_H_
#define __UDMA_UART_DRIVER_H_
#include "stdint.h"
#include "hal_udma_ctrl_reg_defs.h"
typedef enum {
kUartDataValid
} udma_uart_control_type_t;
uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate);
uint16_t udma_uart_close (uint8_t uart_id);
uint16_t udma_uart_write(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
uint8_t udma_uart_getchar(uint8_t uart_id);
uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam);
#endif //__UDMA_UART_DRIVER_H_

162
bsp/core-v-mcu/Libraries/core_v_drivers/source/drv_usart.c Normal file
View File

@@ -0,0 +1,162 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun the first version
*/
#include "board.h"
#include <rtdevice.h>
#include <drv_usart.h>
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_uart_reg_defs.h"
#include "udma_uart_driver.h"
#include <string.h>
#include "core-v-mcu-config.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.uart"
#include <drv_log.h>
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
!defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
extern char u1buffer[128], u0buffer[128];
extern int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
extern UdmaUart_t *puart0 ;
extern UdmaUart_t *puart1 ;
enum
{
UART1_INDEX,
};
struct corev_uart_config uart_config[1] =
{
{
"uart1"
}
};
struct corev_uart uart_obj[1] = {0};
static rt_err_t corev_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
return RT_EOK;
}
static rt_err_t corev_control(struct rt_serial_device *serial, int cmd, void *arg)
{
return RT_EOK;
}
uint16_t rt_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->status_b.tx_busy) {
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1;
return 0;
}
static int corev_putc(struct rt_serial_device *serial, char c)
{
char put_data =c;
struct corev_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct corev_uart *)serial->parent.user_data;
rt_writeraw(0, 1,&put_data);
return 1;
}
static int corev_getc(struct rt_serial_device *serial)
{
signed char ch;
struct corev_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct corev_uart *)serial->parent.user_data;
ch = -1;
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + 0 * UDMA_CH_SIZE);
if (puart->valid_b.rx_data_valid == 1) {
ch = puart->data_b.rx_data & 0xff;
}
return (int)ch;
}
rt_size_t corevdma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
return RT_EOK;
}
void uart_isr(struct rt_serial_device *serial)
{
struct corev_uart *uart = (struct corev_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
static const struct rt_uart_ops corev_uart_ops =
{
corev_configure,
corev_control,
corev_putc,
corev_getc,
corevdma_transmit
};
void uart_rx_isr (void *id){
rt_interrupt_enter();
if (id == 6) {
while (*(int*)0x1a102130) {
u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
u1wrptr &= 0x7f;
}
}
if (id == 2) {//use this uart
while (puart0->valid) {
uart_isr(&(uart_obj[UART1_INDEX].serial));
}
}
rt_interrupt_leave();
}
int rt_hw_usart_init(void)
{
rt_size_t obj_num = 1;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &corev_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
,&uart_obj[i]);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */

240
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_cam_driver.c Normal file
View File

@@ -0,0 +1,240 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <drivers/include/camera.h>
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOS.h"
#include "semphr.h"
#include "target/core-v-mcu/include/core-v-mcu-config.h"
#include "hal/include/hal_fc_event.h"
#include "hal/include/hal_udma_ctrl_reg_defs.h"
#include "hal/include/hal_udma_cam_reg_defs.h"
#include <drivers/include/udma_cam_driver.h>
#include <drivers/include/udma_i2cm_driver.h>
#include "drivers/include/himax.h"
#include "drivers/include/camera.h"
reg_cfg_t himaxRegInit[] = {
{BLC_TGT, 0x08}, // BLC target :8 at 8 bit mode
{BLC2_TGT, 0x08}, // BLI target :8 at 8 bit mode
{0x3044, 0x0A}, // Increase CDS time for settling
{0x3045, 0x00}, // Make symetric for cds_tg and rst_tg
{0x3047, 0x0A}, // Increase CDS time for settling
{0x3050, 0xC0}, // Make negative offset up to 4x
{0x3051, 0x42},
{0x3052, 0x50},
{0x3053, 0x00},
{0x3054, 0x03}, // tuning sf sig clamping as lowest
{0x3055, 0xF7}, // tuning dsun
{0x3056, 0xF8}, // increase adc nonoverlap clk
{0x3057, 0x29}, // increase adc pwr for missing code
{0x3058, 0x1F}, // turn on dsun
{0x3059, 0x1E},
{0x3064, 0x00},
{0x3065, 0x04}, // pad pull 0
{BLC_CFG, 0x43}, // BLC_on, IIR
{0x1001, 0x43}, // BLC dithering en
{0x1002, 0x43}, // blc_darkpixel_thd
{0x0350, 0x00}, // Dgain Control
{BLI_EN, 0x01}, // BLI enable
{0x1003, 0x00}, // BLI Target [Def: 0x20]
{DPC_CTRL, 0x01}, // DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2
{0x1009, 0xA0}, // cluster hot pixel th
{0x100A, 0x60}, // cluster cold pixel th
{SINGLE_THR_HOT, 0x90}, // single hot pixel th
{SINGLE_THR_COLD, 0x40}, // single cold pixel th
{0x1012, 0x00}, // Sync. shift disable
{0x2000, 0x07},
{0x2003, 0x00},
{0x2004, 0x1C},
{0x2007, 0x00},
{0x2008, 0x58},
{0x200B, 0x00},
{0x200C, 0x7A},
{0x200F, 0x00},
{0x2010, 0xB8},
{0x2013, 0x00},
{0x2014, 0x58},
{0x2017, 0x00},
{0x2018, 0x9B},
{AE_CTRL, 0x01}, //Automatic Exposure Gain Control
{AE_TARGET_MEAN, 0x3C}, //AE target mean [Def: 0x3C]
{AE_MIN_MEAN, 0x0A}, //AE min target mean [Def: 0x0A]
{INTEGRATION_H, 0x00}, //Integration H [Def: 0x01]
{INTEGRATION_L, 0x60}, //Integration L [Def: 0x08]
{ANALOG_GAIN, 0x00}, //Analog Global Gain
{DAMPING_FACTOR, 0x20}, //Damping Factor [Def: 0x20]
{DIGITAL_GAIN_H, 0x01}, //Digital Gain High [Def: 0x01]
{DIGITAL_GAIN_L, 0x00}, //Digital Gain Low [Def: 0x00]
{0x2103, 0x03},
{0x2104, 0x05},
{0x2105, 0x01},
{0x2106, 0x54},
{0x2108, 0x03},
{0x2109, 0x04},
{0x210B, 0xC0},
{0x210E, 0x00}, //Flicker Control
{0x210F, 0x00},
{0x2110, 0x3C},
{0x2111, 0x00},
{0x2112, 0x32},
{0x2150, 0x30},
{0x0340, 0x02},
{0x0341, 0x16},
{0x0342, 0x01},
{0x0343, 0x78},
{0x3010, 0x01},
{0x0383, 0x01},
{0x0387, 0x01},
{0x0390, 0x00},
{0x3011, 0x70},
{0x3059, 0x02},
{0x3060, 0x01},
// {0x3060, 0x25}, //Clock gating and clock divisors
{0x3068, 0x20}, //PCLK0 polarity
{IMG_ORIENTATION, 0x01}, // change the orientation
{0x0104, 0x01},
{0x0100, 0x01},
//{0x0601, 0x11} //Test pattern walking ones
//{0x0601, 0x01} //Test pattern colour bar
};
SemaphoreHandle_t cam_semaphore_rx;
static uint8_t cam;
static void camISR() {
}
void cam_open (uint8_t cam_id)
{
int i = 0;
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
/* Enable reset and enable uart clock */
pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
//psdio_regs->clk_div_b.clk_div = 5;
//psdio_regs->clk_div_b.valid = 1;
hal_setpinmux(21, 0);
hal_setpinmux(22, 0);
hal_setpinmux(25, 0);
for(i=0; i<8; i++ )
{
//set pin muxes to sdio functionality
hal_setpinmux(29+i, 0);
}
/* See if already initialized */
if (cam_semaphore_rx != NULL ){
return;
}
/* Set semaphore */
SemaphoreHandle_t shSemaphoreHandle; // FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
shSemaphoreHandle = xSemaphoreCreateBinary();
configASSERT(shSemaphoreHandle);
xSemaphoreGive(shSemaphoreHandle);
cam_semaphore_rx = shSemaphoreHandle;
/* Set handlers. */
pi_fc_event_handler_set(SOC_EVENT_UDMA_CAM_RX(cam_id), camISR, cam_semaphore_rx);
/* Enable SOC events propagation to FC. */
hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_CAM_RX(cam_id));
/* configure */
cam = 0x48; // Himax address
udma_cam_control(kCamReset, NULL);
return;
}
uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam) {
short retval = 0;
uint16_t i;
SemaphoreHandle_t shSemaphoreHandle;
camera_struct_t *camera;
//camera = (camera_struct_t *)0x1A102300; // Peripheral 5?
camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
shSemaphoreHandle = cam_semaphore_rx;
switch (control_type) {
case kCamReset:
_himaxRegWrite(SW_RESET, HIMAX_RESET);
break;
case kCamID:
udma_i2cm_16read8(0, cam, MODEL_ID_H, 2, &retval, 0);
retval = (retval >> 8) & 0xff | (retval <<8);
break;
case kCamInit:
for(i=0; i<(sizeof(himaxRegInit)/sizeof(reg_cfg_t)); i++){
_himaxRegWrite(himaxRegInit[i].addr, himaxRegInit[i].data);
}
camera->cfg_ll = 0<<16 | 0;
camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
camera->cfg_size = 324;
camera->vsync_pol = 1;
camera->cfg_glob = (0 << 0) | // framedrop disabled
(000000 << 1) | // number of frames to drop
(0 << 7) | // Frame slice disabled
(004 << 8) | // Format binary 100 = ByPass little endian
(0000 << 11); // Shift value ignored in bypass
break;
case kCamFrame:
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
camera->rx_saddr = pparam;
camera->rx_size = (244*324);
camera->rx_cfg = 0x12; // start 16-bit transfers
camera->cfg_glob = camera->cfg_glob |
(1 << 31) ; // enable 1 == go
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
camera->cfg_glob = camera->cfg_glob &
(0x7fffffff) ; // enable 1 == go
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
}
return retval;
}
void _himaxRegWrite(unsigned int addr, unsigned char value){
uint8_t naddr;
uint16_t data;
naddr = (addr>>8) & 0xff;
data = (value << 8) | (addr & 0xff);
udma_i2cm_write (0, cam, naddr, 2, &data, 0);
// i2c_16write8(cam,addr,value);
}

355
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_i2cm_driver.c Normal file
View File

@@ -0,0 +1,355 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOS.h"
#include "semphr.h"
#include "target/core-v-mcu/include/core-v-mcu-config.h"
#include "hal/include/hal_fc_event.h"
#include "hal/include/hal_udma_ctrl_reg_defs.h"
#include "hal/include/hal_udma_i2cm_reg_defs.h"
#include <drivers/include/udma_i2cm_driver.h>
#define unuse_freertos_in_i2cm
SemaphoreHandle_t i2cm_semaphores_rx[N_I2CM];
SemaphoreHandle_t i2cm_semaphores_tx[N_I2CM];
void i2cmTXHandler(void *arg)
{
uint32_t lCounter = 0;
lCounter++;
}
void i2cmRXHandler(void *arg)
{
uint32_t lCounter = 0;
lCounter++;
}
static uint8_t aucclkdiv[2];
uint16_t udma_i2cm_open (uint8_t i2cm_id, uint32_t clk_freq) {
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
uint32_t clk_divisor;
/* See if already initialized */
if (i2cm_semaphores_rx[i2cm_id] != NULL || i2cm_semaphores_tx[i2cm_id] != NULL) {
return 1;
}
/* Enable reset and enable uart clock */
pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
pudma_ctrl->reg_cg |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
/* Set semaphore */
#ifndef unuse_freertos_in_i2cm
SemaphoreHandle_t shSemaphoreHandle; // FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
shSemaphoreHandle = xSemaphoreCreateBinary();
configASSERT(shSemaphoreHandle);
xSemaphoreGive(shSemaphoreHandle);
i2cm_semaphores_rx[i2cm_id] = shSemaphoreHandle;
shSemaphoreHandle = xSemaphoreCreateBinary();
configASSERT(shSemaphoreHandle);
xSemaphoreGive(shSemaphoreHandle);
i2cm_semaphores_tx[i2cm_id] = shSemaphoreHandle;
#endif
/* Set handlers. */
pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_RX(i2cm_id), i2cmRXHandler/*NULL*/, i2cm_semaphores_rx[i2cm_id]);
pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_TX(i2cm_id), i2cmTXHandler/*NULL*/, i2cm_semaphores_tx[i2cm_id]);
/* Enable SOC events propagation to FC. */
hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_RX(i2cm_id));
hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_TX(i2cm_id));
/* configure */
clk_divisor = 5000000/clk_freq;
aucclkdiv[0] = (clk_divisor >> 0) & 0xFF;
aucclkdiv[1] = (clk_divisor >> 8) & 0xFF;
return 0;
}
uint16_t udma_i2cm_control(uint8_t i2cm_id, udma_i2cm_control_type_t control_type, void* pparam) {
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
switch(control_type) {
case kI2cmReset:
pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
break;
default:
configASSERT(0);
}
return 0;
}
static uint8_t auccmd_rx[16];
uint8_t udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
_udma_i2cm_write_addr_plus_regaddr(i2cm_id, i2cm_addr, reg_addr);
return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
}
uint8_t udma_i2cm_16read8(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
_udma_i2cm_write_addr_plus_reg16addr(i2cm_id, i2cm_addr, reg_addr);
return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
}
static uint8_t auccmd_tx[32];
uint8_t udma_i2cm_write (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t write_len, uint8_t *write_data, bool more_follows) {
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
uint8_t* pcmd = auccmd_tx;
uint8_t* pdata = write_data;
SemaphoreHandle_t shSemaphoreHandleTx = i2cm_semaphores_tx[i2cm_id];
uint8_t lStatus = pdFALSE;
configASSERT(write_len < 256);
if( xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE ) // Wait for any prior transmission to complete
{
*pcmd++ = kI2cmCmdCfg;
*pcmd++ = aucclkdiv[1];
*pcmd++ = aucclkdiv[0];
*pcmd++ = kI2cmCmdStart; // Put Start transaction on I2C bus
*pcmd++ = kI2cmCmdRpt; // Set up for several writes: i2cm_CMD_RPT
*pcmd++ = (uint8_t)(write_len + 2); // I@CM_ADDR + REG_ADDR + data
*pcmd++ = kI2cmCmdWr; // Command to repeat: I2C CMD_WR
*pcmd++ = i2cm_addr & 0xfe; // Clear R/WRbar bit from i2c device's address to indicate write
*pcmd++ = reg_addr; // Target address for following data
for (int i = 0; i != write_len; i++) {
*pcmd++ = *pdata++;
}
pi2cm_regs->tx_saddr = auccmd_tx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA transaction is completed
xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandleTx );
if (!more_follows) {
_udma_i2cm_send_stop(i2cm_id);
}
lStatus = pdTRUE;
}
else
{
xSemaphoreGive( shSemaphoreHandleTx );
}
return lStatus;
}
uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr) {
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
uint8_t* pcmd = auccmd_tx;
uint8_t lStatus = pdFALSE;
SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
pi2cm_regs->tx_cfg_b.en = 0;
*pcmd++ = kI2cmCmdCfg;
*pcmd++ = aucclkdiv[1];
*pcmd++ = aucclkdiv[0];
*pcmd++ = kI2cmCmdStart; // Put Start transaction on I2C bus
*pcmd++ = kI2cmCmdWr; // Write device's address (next byte)
*pcmd++ = i2cm_addr & 0xfe; // Clear R/WRbar bit from i2c device's address to indicate write
*pcmd++ = kI2cmCmdWr; // I2C CMD_WR
pi2cm_regs->tx_saddr = auccmd_tx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA operation is completed
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
//pi2cm_regs->tx_cfg_b.en = 0;
pcmd = auccmd_tx;
*pcmd++ = reg_addr;
pi2cm_regs->tx_saddr = auccmd_tx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA operation is completed
xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandle );
lStatus = pdTRUE;
}
else
{
xSemaphoreGive( shSemaphoreHandle );
}
}
else
{
xSemaphoreGive( shSemaphoreHandle );
}
return lStatus;
}
uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr) {
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
uint8_t* pcmd = auccmd_tx;
uint8_t lStatus = pdFALSE;
SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
pi2cm_regs->tx_cfg_b.en = 0;
*pcmd++ = kI2cmCmdCfg;
*pcmd++ = aucclkdiv[1];
*pcmd++ = aucclkdiv[0];
*pcmd++ = kI2cmCmdStart; // Put Start transaction on I2C bus
*pcmd++ = kI2cmCmdWr; // Write device's address (next byte)
*pcmd++ = i2cm_addr & 0xfe; // Clear R/WRbar bit from i2c device's address to indicate write
*pcmd++ = kI2cmCmdRpt; // 2 byte register address
*pcmd++ = 2;
*pcmd++ = kI2cmCmdWr; // I2C CMD_WR
pi2cm_regs->tx_saddr = auccmd_tx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA operation is completed
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
//pi2cm_regs->tx_cfg_b.en = 0;
pcmd = auccmd_tx;
*pcmd++ = reg_addr & 0xff;
*pcmd++ = (reg_addr >> 8) & 0xff;
pi2cm_regs->tx_saddr = auccmd_tx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA operation is completed
xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandle );
lStatus = pdTRUE;
}
else
{
xSemaphoreGive( shSemaphoreHandle );
}
}
else
{
xSemaphoreGive( shSemaphoreHandle );
}
return lStatus;
}
uint8_t _udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
uint8_t* pcmd = auccmd_rx;
uint8_t lStatus = pdFALSE;
configASSERT(read_len < 256);
SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
pi2cm_regs->tx_cfg_b.en = 0;
*pcmd++ = kI2cmCmdCfg;
*pcmd++ = aucclkdiv[1];
*pcmd++ = aucclkdiv[0];
*pcmd++ = kI2cmCmdStart; // Put Start transaction on I2C bus
*pcmd++ = kI2cmCmdWr; // Write device's address (next byte)
*pcmd++ = i2cm_addr | 0x01; // Device's address with read bit set
if (read_len > 1) { // Do len-1 reads with ACK, and follow by 1 read with NACK
*pcmd++ = kI2cmCmdRpt; // Tell controller to repeat the following command
*pcmd++ = (uint8_t)(read_len - 1); // len-1 times
*pcmd++ = kI2cmCmdRdAck; // command to repeat is read with ack
}
*pcmd++ = kI2cmCmdRdNack; // Read last byte with NACK to indicate the end of the read
//
pi2cm_regs->rx_saddr = read_buffer;
pi2cm_regs->rx_size = read_len;
pi2cm_regs->rx_cfg_b.en = 1;
pi2cm_regs->tx_saddr = auccmd_rx;
pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_rx);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA operation is complete
shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandle );
shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandle );
if (!more_follows) {
_udma_i2cm_send_stop(i2cm_id);
}
lStatus = pdTRUE;
}
else
{
xSemaphoreGive( shSemaphoreHandle );
lStatus = pdFALSE;
}
}
else
{
xSemaphoreGive( shSemaphoreHandle );
lStatus = pdFALSE;
}
return lStatus;
}
static uint8_t auci2cm_stop_seq[] = {
kI2cmCmdStop, kI2cmCmdWait, 0x0
};
uint8_t _udma_i2cm_send_stop(uint8_t i2cm_id) {
UdmaI2cm_t* pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
uint8_t lStatus = pdFALSE;
if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
{
pi2cm_regs->tx_saddr = auci2cm_stop_seq;
pi2cm_regs->tx_size = sizeof(auci2cm_stop_seq);
pi2cm_regs->tx_cfg_b.en = 1;
// Block until UDMA transaction is completed
xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
xSemaphoreGive( shSemaphoreHandle );
lStatus = pdTRUE;
}
else
{
xSemaphoreGive( shSemaphoreHandle );
}
return lStatus;
}

686
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_qspi_driver.c Normal file
View File

File diff suppressed because it is too large Load Diff

266
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_sdio_driver.c Normal file
View File

@@ -0,0 +1,266 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOS.h"
#include "semphr.h"
#include "target/core-v-mcu/include/core-v-mcu-config.h"
#include "hal/include/hal_fc_event.h"
#include "hal/include/hal_udma_ctrl_reg_defs.h"
#include "hal/include/hal_udma_sdio_reg_defs.h"
#include <drivers/include/udma_sdio_driver.h>
#define BLOCK_SIZE 512
uint16_t udma_sdio_open (uint8_t sdio_id)
{
int i = 0;
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
UdmaSdio_t* psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
/* Enable reset and enable uart clock */
pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
pudma_ctrl->reg_cg |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
psdio_regs->clk_div_b.clk_div = 7;//5;
psdio_regs->clk_div_b.valid = 1;
//Restore pin muxes
for(i=0; i<6; i++ )
{
//set pin muxes to sdio functionality
hal_setpinmux(37+i, 0);
}
return 0;
}
uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam) {
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
UdmaSdio_t* psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
switch(control_type) {
case kSDIOmReset:
pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
break;
default:
configASSERT(0);
}
return 0;
}
void udma_sdio_clearDataSetup(uint8_t sdio_id)
{
UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
psdio_regs->data_setup = 0x00000000;
}
uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
{
uint8_t lSts = 0;
uint32_t lData = 0;
UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
psdio_regs->tx_cfg_b.clr = 1;
psdio_regs->tx_cfg_b.en = 0;
psdio_regs->tx_cfg_b.datasize = 2;
psdio_regs->tx_saddr = aBuf;
psdio_regs->tx_size = aBufLen;
lData = 0;
psdio_regs->data_setup = 0x00000000;
lData |= 1 << 0; //Data Enable - Enable data transfer for current command
lData |= 0 << 1; //RWN: Set transfer direction 1 read; 0 write
lData |= 1 << 2; //QUAD mode: Use quad mode.
lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
psdio_regs->data_setup = lData;
psdio_regs->tx_cfg_b.en = 1;
}
uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
{
uint8_t lSts = 0;
uint32_t lData = 0;
UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
psdio_regs->rx_cfg_b.clr = 1;
psdio_regs->rx_cfg_b.en = 0;
psdio_regs->rx_cfg_b.datasize = 2;
psdio_regs->rx_saddr = aBuf;
psdio_regs->rx_size = aBufLen;
lData = 0;
psdio_regs->data_setup = 0x00000000;
lData |= 1 << 0; //Data Enable - Enable data transfer for current command
lData |= 1 << 1; //RWN: Set transfer direction 1 read; 0 write
lData |= 1 << 2; //QUAD mode: Use quad mode.
lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
psdio_regs->data_setup = lData;
psdio_regs->rx_cfg_b.en = 1;
}
uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf)
{
uint8_t lSts = 0;
uint32_t lData = 0;
uint32_t lLoopCounter = 0;
UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
lData |= (aRspType & REG_CMD_OP_CMD_RSP_TYPE_MASK ) << REG_CMD_OP_CMD_RSP_TYPE_LSB;
lData |= ( aCmdOpCode & REG_CMD_OP_CMD_OP_MASK ) << REG_CMD_OP_CMD_OP_LSB;
psdio_regs->cmd_op = lData;
//psdio_regs->cmd_op_b.cmd_op = ( aCmdOpCode & 0x3F );
//psdio_regs->cmd_op_b.cmd_rsp_type = ( aRspType & 0x07 );
psdio_regs->cmd_arg = aCmdArgument;
psdio_regs->start = 1;
while( ( ( psdio_regs->status & ( REG_STATUS_EOT_MASK << REG_STATUS_EOT_LSB ) ) >> REG_STATUS_EOT_LSB ) == 0 )
{
if( ( ( psdio_regs->status & ( REG_STATUS_ERROR_MASK << REG_STATUS_ERROR_LSB ) ) >> REG_STATUS_ERROR_LSB ) == 1 )
{
lSts = (psdio_regs->status & ( REG_STATUS_CMD_ERR_STATUS_MASK << REG_STATUS_CMD_ERR_STATUS_LSB ) ) >> REG_STATUS_CMD_ERR_STATUS_LSB;
break;
}
else
{
if(++lLoopCounter >= 0x00010000 )
{
lSts = 5;
break;
}
}
}
psdio_regs->status_b.eot = 1; //Write 1 to EOT bit to clear it.
if( aResponseBuf )
{
aResponseBuf[0] = psdio_regs->rsp0;
aResponseBuf[1] = psdio_regs->rsp1;
aResponseBuf[2] = psdio_regs->rsp2;
aResponseBuf[3] = psdio_regs->rsp3;
}
return lSts;
}
#if 0
static uint32_t auccmd[16];
void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
UdmaQspi_t* pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
uint32_t* pcmd = auccmd;
configASSERT(read_len < 256);
SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
pqspim_regs->rx_cfg_b.en = 0;
pqspim_regs->tx_cfg_b.en = 0;
pqspim_regs->cmd_cfg_b.en = 0;
*pcmd++ = kSPIm_Cfg | aucclkdiv;
*pcmd++ = kSPIm_SOT | cs; //cs 1
*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
*pcmd++ = kSPIm_EOT | 1; // generate event
pqspim_regs->rx_saddr = read_buffer;
pqspim_regs->rx_size = read_len;
pqspim_regs->rx_cfg_b.en = 1;
pqspim_regs->cmd_saddr = auccmd;
pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
pqspim_regs->cmd_cfg_b.en = 1;
// Block until UDMA operation is complete
shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
}
void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
UdmaQspi_t* pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
uint32_t* pcmd = auccmd;
uint32_t tmp_size;
configASSERT(write_len < 256);
SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
pqspim_regs->rx_cfg_b.clr = 1;
pqspim_regs->tx_cfg_b.clr = 1;
pqspim_regs->cmd_cfg_b.clr = 1;
*pcmd++ = kSPIm_Cfg | aucclkdiv;
*pcmd++ = kSPIm_SOT | cs;
*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
*pcmd++ = kSPIm_EOT | 1; // generate event
pqspim_regs->tx_saddr = write_data;
pqspim_regs->tx_size = write_len-1;
pqspim_regs->tx_cfg_b.datasize = 2;
pqspim_regs->tx_cfg_b.en = 1;
pqspim_regs->cmd_saddr = auccmd;
pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
pqspim_regs->cmd_cfg_b.en = 1;
// Block until UDMA operation is complete
shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
}
#endif

217
bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_uart_driver.c Normal file
View File

@@ -0,0 +1,217 @@
/*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "core-v-mcu-config.h"
#include <string.h>
#include "hal_fc_event.h"
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_uart_reg_defs.h"
#include <drv_usart.h>
#include <stdint.h>
//#include "FreeRTOS.h"
//#include "semphr.h"
#include "core-v-mcu-config.h"
#include "udma_uart_driver.h"
#include "rtthread.h"
//#include <ringbuffer.h>
//#include "ipc/ringbuffer.h"
#include "rtdevice.h"
#define unuse_freertos_in_uart
//SemaphoreHandle_t uart_semaphores_rx[N_UART];
//SemaphoreHandle_t uart_semaphores_tx[N_UART];
char u1buffer[128], u0buffer[128];
int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
UdmaUart_t *puart0 = (UdmaUart_t*)(UDMA_CH_ADDR_UART);
UdmaUart_t *puart1 = (UdmaUart_t*)(UDMA_CH_ADDR_UART + UDMA_CH_SIZE);
uint16_t outdata(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->status_b.tx_busy) { // ToDo: Why is this necessary? Thought the semaphore should have protected
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1; //enable the transfer
return 0;
}
// ringbuffer
#define UART_RX_BUFFER_LEN 16
rt_uint8_t uart_rxbuffer[UART_RX_BUFFER_LEN]={0};
struct rt_ringbuffer uart_rxTCB;
struct rt_semaphore shell_rx_semaphore;
// extern struct ch32_uart_config uart_config[];
// extern void uart_isr(struct rt_serial_device *serial);
// extern struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] ;
// extern UART1_INDEX;
char n_data[]="\r\n";
// void uart_rx_isr (void *id){
// rt_interrupt_enter();
// if (id == 6) {
// while (*(int*)0x1a102130) {
// u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
// u1wrptr &= 0x7f;
// }
// }
// if (id == 2) {
// while (puart0->valid) {
// //u0buffer[u0wrptr++] = puart0->data_b.rx_data & 0xff;
// //u0wrptr &= 0x7f;
// //outdata(0,sizeof(u0buffer),u0buffer);
// //outdata(0,sizeof(n_data),n_data);
// //rt_ringbuffer_putchar(&uart_rxTCB,puart0->data_b.rx_data & 0xff);
// //u0wrptr=0;
// uart_isr(&(uart_obj[UART1_INDEX].serial));
// }
// //rt_sem_release(&shell_rx_semaphore);
// }
// rt_interrupt_leave();
// }
uint8_t uart_getchar (uint8_t id) {
uint8_t retval;
if (id == 1) {
while (u1rdptr == u1wrptr) ;
retval = u1buffer[u1rdptr++];
u1rdptr &= 0x7f;
}
if (id == 0) {
while (u0rdptr == u0wrptr) ;
retval = u0buffer[u0rdptr++];
u0rdptr &= 0x7f;
}
return retval;
}
void uart_rx_isr (void *id);
uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate) {
UdmaUart_t* puart;
volatile UdmaCtrl_t* pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
/* See if already initialized */
pudma_ctrl->reg_rst |= (UDMA_CTRL_UART0_CLKEN << uart_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_UART0_CLKEN << uart_id);
pudma_ctrl->reg_cg |= (UDMA_CTRL_UART0_CLKEN << uart_id);
user_pi_fc_event_handler_set(SOC_EVENT_UART_RX(uart_id), uart_rx_isr);
/* Enable SOC events propagation to FC. */
hal_soc_eu_set_fc_mask(SOC_EVENT_UART_RX(uart_id));
hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_UART_TX(uart_id));
/* configure */
puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
puart->uart_setup_b.div = (uint16_t)(5000000/xbaudrate);
puart->uart_setup_b.bits = 3; // 8-bits
puart->irq_en_b.rx_irq_en = 1;
puart->uart_setup_b.en_tx = 1;
puart->uart_setup_b.en_rx = 1;
puart->uart_setup_b.rx_clean_fifo = 1;
if (uart_id == 1) {
u1rdptr = 0;
u1wrptr = 0;
}
if (uart_id == 0) {
u0rdptr = 0;
u0wrptr = 0;
}
return 0;
}
uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
// SemaphoreHandle_t shSemaphoreHandle = uart_semaphores_tx[uart_id];
// if( xSemaphoreTake( shSemaphoreHandle, 1000000 ) != pdTRUE ) {
// return 1;
// }
while (puart->status_b.tx_busy) { // ToDo: Why is this necessary? Thought the semaphore should have protected
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1; //enable the transfer
return 0;
}
uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
uint16_t ret = 0;
uint8_t last_char = 0;
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while ( (ret < (read_len - 2)) && (last_char != 0xd)) {
if (puart->valid_b.rx_data_valid == 1) {
last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
if (last_char == 0xd) // if cr add
read_buffer[ret++] = 0xa; // linefeed
read_buffer[ret++] = last_char;
}
}
read_buffer[ret] = '\0';
return ret--;
}
uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
uint16_t ret = 0;
uint8_t last_char = 0;
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while ( ret < read_len ) {
if (puart->valid_b.rx_data_valid == 1) {
last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
read_buffer[ret++] = last_char;
}
}
return ret--;
}
uint8_t udma_uart_getchar(uint8_t uart_id) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->valid_b.rx_data_valid == 0) {
}
return (puart->data_b.rx_data & 0xff);
}
uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
switch(control_type) {
case kUartDataValid:
if (uart_id == 0)
return !(u0rdptr == u0wrptr);
if (uart_id == 1)
return !(u1rdptr == u1wrptr);
return puart->valid_b.rx_data_valid;
default:
return 0xFFFF;
}
return 0;
}

31
bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript Normal file
View File

@@ -0,0 +1,31 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
src = Split("""
core_v_hal/source/hal_apb_i2cs.c
core_v_hal/source/hal_fc_event.c
core_v_hal/source/hal_fll.c
core_v_hal/source/hal_fll_pi.c
core_v_hal/source/hal_gpio.c
core_v_hal/source/hal_gpio_pulp.c
core_v_hal/source/hal_irq.c
core_v_hal/source/hal_pinmux.c
core_v_hal/source/hal_pinmux1.c
core_v_hal/source/hal_soc_eu.c
core_v_hal/source/hal_timer_irq.c
bmsis/core-v-mcu/source/core-v-mcu.c
bmsis/core-v-mcu/source/crt0.S
bmsis/core-v-mcu/source/vectors.S
""")
path = [
cwd + '/bmsis/core-v-mcu/include',
cwd + '/core_v_hal/include']
group = DefineGroup('core_v_hal_lib', src, depend = [''], CPPPATH = path)
Return('group')

58
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/bits.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __BITS_H
#define __BITS_H
#include <stdbool.h>
/* Helper to pass a int as a pointer or vice-versa. */
#define POINTER_TO_UINT(x) ((uintptr_t) (x))
#define UINT_TO_POINTER(x) ((void *) (uintptr_t) (x))
#define POINTER_TO_INT(x) ((intptr_t) (x))
#define INT_TO_POINTER(x) ((void *) (intptr_t) (x))
#if !(defined (__CHAR_BIT__) && defined (__SIZEOF_LONG__))
# error Missing required predefined macros for BITS_PER_LONG calculation
#endif
#define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__)
/* Create a contiguous bitmask starting at bit position @l and ending at
* position @h.
*/
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
/* KB, MB, GB */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)
#define GB(x) (MB(x) << 10)
/* KHZ, MHZ */
#define KHZ(x) ((x) * 1000)
#define MHZ(x) (KHZ(x) * 1000)
#ifndef BIT
#if defined(_ASMLANGUAGE)
#define BIT(n) (1 << (n))
#else
#define BIT(n) (1UL << (n))
#endif
#endif
/**
* @brief Macro sets or clears bit depending on boolean value
*
* @param var Variable to be altered
* @param bit Bit number
* @param set Value 0 clears bit, any other value sets bit
*/
#define WRITE_BIT(var, bit, set) \
((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
#define BIT_MASK(n) (BIT(n) - 1)
#endif

284
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-config.h Normal file
View File

@@ -0,0 +1,284 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __CORE_V_MCU_CONFIG_H_
#define __CORE_V_MCU_CONFIG_H_
#define NEW_BIT_FILE 1
#define OLD_BIT_FILE 0
#if (NEW_BIT_FILE == 1 )
#define BUILD_DATE 0x20220127
#define BUILD_TIME 0x00215431
#define FAKE_PLL 0
#define PERCEPTIA_PLL 1
// SOC options
#define N_IO 48
#define N_SYSIO 3
#define N_GPIO 32
#define N_APBIO 51
#define NBIT_PADCFG 6
#define NBIT_PADMUX 2
#define N_UART 2
#define N_QSPIM 2 // two QSPI master
#define N_I2CM 2 // two I2C master
#define N_I2SC 0
#define N_CSI2 0
#define N_HYPER 0
#define N_SDIO 1
#define N_CAM 1
#define N_JTAG 0
#define N_MRAM 0
#define N_FILTER 1
#define N_FPGA 0
#define N_EXT_PER 0
#define N_EFPGA_TCDM_PORTS 4
#define N_FPGAIO 43
#define N_EFPGA_EVENTS 16
// UDMA configuration information
#define UDMA_START_ADDR 0x1A102000
#define UDMA_CH_SIZE (0x80)
// peripheral channel definitions
#define UDMA_CH_ADDR_CTRL (0x1A102000)
#define UDMA_CH_ADDR_UART (0x1A102000 + 1 * 0x80)
#define UDMA_UART_ID(id) (0 + id)
#define UDMA_CH_ADDR_UART0 (0x1A102000 + 1 * 0x80)
#define UDMA_CH_ADDR_UART1 (0x1A102000 + 2 * 0x80)
#define UDMA_CH_ADDR_QSPIM (0x1A102000 + 3 * 0x80)
#define UDMA_QSPIM_ID(id) (2 + id)
#define UDMA_CH_ADDR_QSPIM0 (0x1A102000 + 3 * 0x80)
#define UDMA_CH_ADDR_QSPIM1 (0x1A102000 + 4 * 0x80)
#define UDMA_CH_ADDR_I2CM (0x1A102000 + 5 * 0x80)
#define UDMA_I2CM_ID(id) (4 + id)
#define UDMA_CH_ADDR_I2CM0 (0x1A102000 + 5 * 0x80)
#define UDMA_CH_ADDR_I2CM1 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_I2SC (0x1A102000 + 7 * 0x80)
#define UDMA_I2SC_ID(id) (6 + id)
#define UDMA_CH_ADDR_I2SC0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_CSI2 (0x1A102000 + 7 * 0x80)
#define UDMA_CSI2_ID(id) (6 + id)
#define UDMA_CH_ADDR_CSI20 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_HYPER (0x1A102000 + 7 * 0x80)
#define UDMA_HYPER_ID(id) (6 + id)
#define UDMA_CH_ADDR_HYPER0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_SDIO (0x1A102000 + 7 * 0x80)
#define UDMA_SDIO_ID(id) (6 + id)
#define UDMA_CH_ADDR_SDIO0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_CAM (0x1A102000 + 8 * 0x80)
#define UDMA_CAM_ID(id) (7 + id)
#define UDMA_CH_ADDR_CAM0 (0x1A102000 + 8 * 0x80)
#define UDMA_CH_ADDR_JTAG (0x1A102000 + 9 * 0x80)
#define UDMA_JTAG_ID(id) (8 + id)
#define UDMA_CH_ADDR_JTAG0 (0x1A102000 + 9 * 0x80)
#define UDMA_CH_ADDR_MRAM (0x1A102000 + 9 * 0x80)
#define UDMA_MRAM_ID(id) (8 + id)
#define UDMA_CH_ADDR_MRAM0 (0x1A102000 + 9 * 0x80)
#define UDMA_CH_ADDR_FILTER (0x1A102000 + 9 * 0x80)
#define UDMA_FILTER_ID(id) (8 + id)
#define UDMA_CH_ADDR_FILTER0 (0x1A102000 + 9 * 0x80)
#define UDMA_CH_ADDR_FPGA (0x1A102000 + 10 * 0x80)
#define UDMA_FPGA_ID(id) (9 + id)
#define UDMA_CH_ADDR_FPGA0 (0x1A102000 + 10 * 0x80)
#define UDMA_CH_ADDR_EXT_PER (0x1A102000 + 10 * 0x80)
#define UDMA_EXT_PER_ID(id) (9 + id)
#define UDMA_CH_ADDR_EXT_PER0 (0x1A102000 + 10 * 0x80)
// Peripheral clock enable masks
#define UDMA_CTRL_UART0_CLKEN (1 << 0)
#define UDMA_CTRL_UART1_CLKEN (1 << 1)
#define UDMA_CTRL_QSPIM0_CLKEN (1 << 2)
#define UDMA_CTRL_QSPIM1_CLKEN (1 << 3)
#define UDMA_CTRL_I2CM0_CLKEN (1 << 4)
#define UDMA_CTRL_I2CM1_CLKEN (1 << 5)
#define UDMA_CTRL_I2SC0_CLKEN (1 << 6)
#define UDMA_CTRL_CSI20_CLKEN (1 << 6)
#define UDMA_CTRL_HYPER0_CLKEN (1 << 6)
#define UDMA_CTRL_SDIO0_CLKEN (1 << 6)
#define UDMA_CTRL_CAM0_CLKEN (1 << 7)
#define UDMA_CTRL_JTAG0_CLKEN (1 << 8)
#define UDMA_CTRL_MRAM0_CLKEN (1 << 8)
#define UDMA_CTRL_FILTER0_CLKEN (1 << 8)
#define UDMA_CTRL_FPGA0_CLKEN (1 << 9)
#define UDMA_CTRL_EXT_PER0_CLKEN (1 << 9)
// FLL configuration information
#define FLL1_START_ADDR 0x1A100000
#define FLL2_START_ADDR 0x1A100020
#define FLL3_START_ADDR 0x1A100040
// GPIO configuration information
#define GPIO_START_ADDR 0x1A101000
#define SOC_EVENT_GEN_START_ADDR 0x1A106000
// I2C Slave configuration information
#define I2CS_START_ADDR 0x1A107000
// EFPGAIO configuration information
#define EFPGAIO_START_ADDR 0x1A300000
// SOC controller configuration information
#define SOC_CTRL_START_ADDR 0x1A104000
// Event Unit (Interrupts) configuration information
#define EU_START_ADDR 0x1A109000
// Timer configuration information
#define TIMER_START_ADDR 0x1A10B000
// AdvTimer configuration information
#define ADV_TIMER_START_ADDR 0x1A105000
// EFPGA configuration information (FCB)
#define EFPGA_CONFIG_START_ADDR 0x1A200000
#elif (OLD_BIT_FILE == 1)
#define BUILD_DATE 0x20210623
#define BUILD_TIME 0x00111431
#define FAKE_PLL 0
#define PERCEPTIA_PLL 1
// SOC options
#define N_IO 48
#define N_SYSIO 3
#define N_GPIO 32
#define N_APBIO 50
#define NBIT_PADCFG 6
#define NBIT_PADMUX 2
#define N_UART 2
#define N_QSPIM 1
#define N_I2CM 2
#define N_I2SC 0
#define N_CSI2 0
#define N_HYPER 0
#define N_SDIO 1
#define N_CAM 1
#define N_JTAG 0
#define N_MRAM 0
#define N_FILTER 1
#define N_FPGA 1
#define N_EXT_PER 0
#define N_EFPGA_TCDM_PORTS 4
#define N_FPGAIO 43
#define N_EFPGA_EVENTS 16
// UDMA configuration information
#define UDMA_START_ADDR 0x1A102000
#define UDMA_CH_SIZE (0x80)
// peripheral channel definitions
#define UDMA_CH_ADDR_CTRL (0x1A102000)
#define UDMA_CH_ADDR_UART (0x1A102000 + 1 * 0x80)
#define UDMA_UART_ID(id) (0 + id)
#define UDMA_CH_ADDR_UART0 (0x1A102000 + 1 * 0x80)
#define UDMA_CH_ADDR_UART1 (0x1A102000 + 2 * 0x80)
#define UDMA_CH_ADDR_QSPIM (0x1A102000 + 3 * 0x80)
#define UDMA_QSPIM_ID(id) (2 + id)
#define UDMA_CH_ADDR_QSPIM0 (0x1A102000 + 3 * 0x80)
#define UDMA_CH_ADDR_I2CM (0x1A102000 + 4 * 0x80)
#define UDMA_I2CM_ID(id) (3 + id)
#define UDMA_CH_ADDR_I2CM0 (0x1A102000 + 4 * 0x80)
#define UDMA_CH_ADDR_I2CM1 (0x1A102000 + 5 * 0x80)
#define UDMA_CH_ADDR_I2SC (0x1A102000 + 6 * 0x80)
#define UDMA_I2SC_ID(id) (5 + id)
#define UDMA_CH_ADDR_I2SC0 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_CSI2 (0x1A102000 + 6 * 0x80)
#define UDMA_CSI2_ID(id) (5 + id)
#define UDMA_CH_ADDR_CSI20 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_HYPER (0x1A102000 + 6 * 0x80)
#define UDMA_HYPER_ID(id) (5 + id)
#define UDMA_CH_ADDR_HYPER0 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_SDIO (0x1A102000 + 6 * 0x80)
#define UDMA_SDIO_ID(id) (5 + id)
#define UDMA_CH_ADDR_SDIO0 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_CAM (0x1A102000 + 7 * 0x80)
#define UDMA_CAM_ID(id) (6 + id)
#define UDMA_CH_ADDR_CAM0 (0x1A102000 + 6 * 0x80)
#define UDMA_CH_ADDR_JTAG (0x1A102000 + 7 * 0x80)
#define UDMA_JTAG_ID(id) (6 + id)
#define UDMA_CH_ADDR_JTAG0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_MRAM (0x1A102000 + 7 * 0x80)
#define UDMA_MRAM_ID(id) (6 + id)
#define UDMA_CH_ADDR_MRAM0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_FILTER (0x1A102000 + 7 * 0x80)
#define UDMA_FILTER_ID(id) (6 + id)
#define UDMA_CH_ADDR_FILTER0 (0x1A102000 + 7 * 0x80)
#define UDMA_CH_ADDR_FPGA (0x1A102000 + 8 * 0x80)
#define UDMA_FPGA_ID(id) (7 + id)
#define UDMA_CH_ADDR_FPGA0 (0x1A102000 + 8 * 0x80)
#define UDMA_CH_ADDR_EXT_PER (0x1A102000 + 9 * 0x80)
#define UDMA_EXT_PER_ID(id) (8 + id)
#define UDMA_CH_ADDR_EXT_PER0 (0x1A102000 + 9 * 0x80)
// Peripheral clock enable masks
#define UDMA_CTRL_UART0_CLKEN (1 << 0)
#define UDMA_CTRL_UART1_CLKEN (1 << 1)
#define UDMA_CTRL_QSPIM0_CLKEN (1 << 2)
#define UDMA_CTRL_I2CM0_CLKEN (1 << 3)
#define UDMA_CTRL_I2CM1_CLKEN (1 << 4)
#define UDMA_CTRL_I2SC0_CLKEN (1 << 5)
#define UDMA_CTRL_CSI20_CLKEN (1 << 5)
#define UDMA_CTRL_HYPER0_CLKEN (1 << 5)
#define UDMA_CTRL_SDIO0_CLKEN (1 << 5)
#define UDMA_CTRL_CAM0_CLKEN (1 << 6)
#define UDMA_CTRL_JTAG0_CLKEN (1 << 6)
#define UDMA_CTRL_MRAM0_CLKEN (1 << 6)
#define UDMA_CTRL_FILTER0_CLKEN (1 << 6)
#define UDMA_CTRL_FPGA0_CLKEN (1 << 7)
#define UDMA_CTRL_EXT_PER0_CLKEN (1 << 8)
// FLL configuration information
#define FLL1_START_ADDR 0x1A100000
#define FLL2_START_ADDR 0x1A100020
#define FLL3_START_ADDR 0x1A100040
// GPIO configuration information
#define GPIO_START_ADDR 0x1A101000
#define SOC_EVENT_GEN_START_ADDR 0x1A106000
// I2C Slave configuration information
#define I2CS_START_ADDR 0x1A107000
// EFPGAIO configuration information
#define EFPGAIO_START_ADDR 0x1A300000
// SOC controller configuration information
#define SOC_CTRL_START_ADDR 0x1A104000
// Event Unit (Interrupts) configuration information
#define EU_START_ADDR 0x1A109000
// Timer configuration information
#define TIMER_START_ADDR 0x1A10B000
// AdvTimer configuration information
#define ADV_TIMER_START_ADDR 0x1A105000
// EFPGA configuration information (FCB)
#define EFPGA_CONFIG_START_ADDR 0x1A200000
#endif
#endif //__CORE_V_MCU_CONFIG_H_

129
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-events.h Normal file
View File

@@ -0,0 +1,129 @@
/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
#include "core-v-mcu-properties.h"
/* Events offsets. */
#define UDMA_EVENT_OFFSET_RX (0U)
#define UDMA_EVENT_OFFSET_TX (1U)
#define EVENT_UART_RX (2U)
#define EVENT_UART_ERR (3U)
#define UDMA_EVENT_OFFSET_SPI_CMD (2)
#define UDMA_EVENT_OFFSET_SPI_EOT (3)
/* Number of events per peripheral. */
#define UDMA_CHANNEL_NB_EVENTS_LOG2 (2)
#define UDMA_CHANNEL_NB_EVENTS (1 << UDMA_CHANNEL_NB_EVENTS_LOG2)
/* Number of SW events. */
#define NB_SW_EVENTS (8)
/*! @brief FC events (aka IRQ lines)*/
#define FC_EVENT_SW(id) (id & (NB_SW_EVENTS - 1))
#define FC_EVENT_DMA_EVT (8)
#define FC_EVENT_DMA (9)
#define FC_EVENT_TIMER0 (10) /* Timer low. */
#define SYSTICK_IRQN FC_EVENT_TIMER0
#define FC_EVENT_TIMER1 (11) /* Timer high. */
/* #define FC_EVENT_EU_HWCE (12) */
/*
* SoC event unit events: Many events get implicitely muxed into this interrupt.
* A user that gets such an interrupt has to check the event unit's registers to
* see what happened
*/
#define FC_EVENT_SOC_EVENT (27)
/* #define FC_EVENT_MPU_ERROR (28) */
/*
* Event queue error: If we don't process event unit events quickly enough
* internal fifos can overflow and we get this error interrupt
*/
#define FC_EVENT_FC_QUEUE_ERROR (29)
#define FC_EVENT_HP0 runn (30)
#define FC_EVENT_HP1 (31)
/*! @name SoC events */
/*! @brief Number of FC_Events. */
#define SOC_EU_NB_FC_EVENTS (168)
/*! @brief UDMA events */
/* SPIM */
#define SOC_EVENT_UDMA_SPIM_RX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_SPIM_TX(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
#define SOC_EVENT_UDMA_SPIM_CMD(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_CMD)
#define SOC_EVENT_UDMA_SPIM_EOT(id) ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_EOT)
/* HYPER */
/* #define SOC_EVENT_UDMA_HYPER_RX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
/* #define SOC_EVENT_UDMA_HYPER_TX(id) ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
/* UART */
#define SOC_EVENT_UDMA_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_UART_TX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
#define SOC_EVENT_UART_RX(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_RX)
#define SOC_EVENT_UART_ERR(id) ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_ERR)
/* I2C */
#define SOC_EVENT_UDMA_I2C_RX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_I2C_TX(id) ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
/* DMACPY */
/* #define SOC_EVENT_UDMA_DMACPY_RX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
/* #define SOC_EVENT_UDMA_DMACPY_TX(id) ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
/* I2S */
#define SOC_EVENT_UDMA_I2S_RX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
#define SOC_EVENT_UDMA_I2S_TX(id) ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
/* CPI */
#define SOC_EVENT_UDMA_CAM_RX(id) ((UDMA_CAM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
/* UDMA EOT & error events. */
//#define SOC_EVENT_UDMA_I2C_ERROR(id) (26 + id)
/*! @brief PMU events, no pmu*/
/* #define SOC_EVENT_PMU_CLUSTER_POWER (31) */
/* #define SOC_EVENT_PMU_CLUSTER_CG (35) */
/* #define SOC_EVENT_PMU_DLC_BRIDGE_PICL (36) */
/* #define SOC_EVENT_PMU_DLC_BRIDGE_SCU (37) */
/* #define SOC_EVENT_PWM(id) (38 + id) */
#define SOC_EVENT_GPIO (139)
#define SOC_EVENT_HWPE0 (140)
#define SOC_EVENT_HWPE1 (141)
/* #define SOC_EVENT_RTC_APB (43) */
/* #define SOC_EVENT_RTC (44) */
#define SOC_EVENT_SW(id) (160 + (id & (NB_SW_EVENTS - 1)))
#define SOC_EVENT_REF32K_CLK_RISE (168)
/* @brief Cluster events */
#define CL_EVENT_SW(id) (id & (NB_SW_EVENTS - 1))
#define CL_EVENT_DMA0 (8)
#define CL_EVENT_DMA1 (9)
#define CL_EVENT_TIMER0_LO (10)
#define CL_EVENT_TIMER0_HI (11)
#define CL_EVENT_ACC0 (12)
#define CL_EVENT_ACC1 (13)
#define CL_EVENT_ACC2 (14)
#define CL_EVENT_ACC3 (15)
#define CL_EVENT_BAR (16)
#define CL_EVENT_MUTEX (17)
#define CL_EVENT_DISPATCH (18)
/* #define CL_EVENT_CLUSTER0 (22) */
/* #define CL_EVENT_CLUSTER1 (23) */
#define CL_EVENT_SOC_EVT (30) /* adapted */
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ */

127
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-memory-map.h Normal file
View File

@@ -0,0 +1,127 @@
/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
#include "core-v-mcu-properties.h"
/* Memories */
/* FC memory. */
#define FC_TCDM_ADDR (0x1B000000)
#if (ARCHI_HAS_FC_ALIAS)
#define FC_TCDM_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_FC_ALIAS */
/* L2 memory */
#define L2_SHARED_ADDR (0x1C000000)
#if (ARCHI_HAS_L2_ALIAS)
#define L2_SHARED_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_L2_ALIAS */
/* L1 cluster memory */
#define CL_L1_ADDR (0x10000000)
#if (ARCHI_HAS_CL_L1_ALIAS)
#define CL_L1_ADDR_ALIAS (0x00000000)
#endif /* ARCHI_HAS_CL_L1_ALIAS */
/* L1 cluster TS */
#if (ARCHI_HAS_CL_L1_TS)
#define L2_PRIV0_TS_ADDR (0x10100000)
#endif /* ARCHI_HAS_CL_L1_TS */
/* ROM memory (8 KiB)*/
#define ROM_ADDR (0x1A000000)
#define ROM_SIZE (0x00002000)
/* Cluster */
#define ARCHI_CLUSTER_ADDR (0x00000000)
#define ARCHI_CLUSTER_SIZE (0x00400000)
#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
#define ARCHI_CLUSTER_PERIPHERALS_OFFSET (0x00200000)
/* Cluster peripherals */
#define ARCHI_TIMER_SIZE (0x00000800)
#define ARCHI_CLUSTER_CTRL_OFFSET (0x00000000)
#define ARCHI_TIMER_OFFSET (0x00000400)
#define ARCHI_EU_OFFSET (0x00000800)
#define ARCHI_HWCE_OFFSET (0x00001000)
#define ARCHI_ICACHE_CTRL_OFFSET (0x00001400)
#define ARCHI_MCHAN_EXT_OFFSET (0x00001800)
#define ARCHI_CLUSTER_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
#define ARCHI_CLUSTER_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_CLUSTER_CTRL_OFFSET)
#define ARCHI_CLUSTER_TIMER_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET)
#define ARCHI_ICACHE_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_ICACHE_CTRL_OFFSET)
#define ARCHI_EU_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET)
#define ARCHI_HWCE_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_HWCE_OFFSET)
#define ARCHI_MCHAN_EXT_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_MCHAN_EXT_OFFSET)
#define ARCHI_DEMUX_PERIPHERALS_OFFSET (0x204000)
#define ARCHI_EU_DEMUX_OFFSET (0x00000)
#define ARCHI_MCHAN_DEMUX_OFFSET (0x00400)
#define ARCHI_DEMUX_PERIPHERALS_ADDR (ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_DEMUX_PERIPHERALS_OFFSET)
#define ARCHI_EU_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET)
#define ARCHI_MCHAN_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET)
/* SoC peripherals */
#define SOC_PERIPHERALS_ADDR (0x1A100000)
#define SOC_FLL_OFFSET (0x00000000)
#define CL_FLL_OFFSET (0x00000800)
#define GPIO_OFFSET (0x00001000)
#define UDMA_OFFSET (0x00002000)
#define APB_SOC_CTRL_OFFSET (0x00004000)
#define ADV_TIMER_OFFSET (0x00005000) /* PWM. */
#define SOC_EU_OFFSET (0x00006000)
#define FC_IRQ_OFFSET (0x00009800)
/* #define FC_IRQ_OFFSET (0x00009000) */ /* valid mirror address */
#define FC_TIMER_OFFSET (0x0000B000)
#define FC_HWPE_OFFSET (0x0000C000)
#define STDOUT_OFFSET (0x0000F000)
#define DEBUG_OFFSET (0x00010000)
#define SOC_FLL_ADDR (SOC_PERIPHERALS_ADDR + SOC_FLL_OFFSET)
#define CL_FLL_ADDR (SOC_PERIPHERALS_ADDR + CL_FLL_OFFSET)
#define GPIO_ADDR (SOC_PERIPHERALS_ADDR + GPIO_OFFSET)
#define UDMA_CTRL_ADDR (SOC_PERIPHERALS_ADDR + UDMA_OFFSET)
#define APB_SOC_CTRL_ADDR (SOC_PERIPHERALS_ADDR + APB_SOC_CTRL_OFFSET)
#define ADV_TIMER_ADDR (SOC_PERIPHERALS_ADDR + ADV_TIMER_OFFSET)
#define SOC_EU_ADDR (SOC_PERIPHERALS_ADDR + SOC_EU_OFFSET)
#define FC_IRQ_ADDR (SOC_PERIPHERALS_ADDR + FC_IRQ_OFFSET)
#define FC_TIMER_ADDR (SOC_PERIPHERALS_ADDR + FC_TIMER_OFFSET)
#define FC_HWPE_ADDR (SOC_PERIPHERALS_ADDR + FC_HWPE_OFFSET)
#define STDOUT_ADDR (SOC_PERIPHERALS_ADDR + STDOUT_OFFSET)
#define DEBUG_ADDR (SOC_PERIPHERALS_ADDR + DEBUG_OFFSET)
/* UDMA peripherals */
/* #define UDMA_GC_ADDR (UDMA_CTRL_ADDR + 0x780) */
/* UDMA base peripheral addr = UDMA base address + UDMA ctrl. */
#define UDMA_PERIPH_BASE_ADDR (UDMA_CTRL_ADDR + 0x80)
#define UDMA_SPIM(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_SPIM_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_HYPER(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_HYPER_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_UART(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_UART_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_I2C(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2C_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_DMACPY(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_DMACPY_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_I2S(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#define UDMA_CPI(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2))
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */

1414
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-periph.h Normal file
View File

File diff suppressed because it is too large Load Diff

188
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h Normal file
View File

@@ -0,0 +1,188 @@
/*
* Copyright 2020 GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
//#include "pmsis/rtos/os_frontend_api/os.h"
//#include "pmsis/backend/implementation_specific_defines.h"
//#include "pmsis/backend/pmsis_backend_native_task_api.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Function declaration
******************************************************************************/
/*******************************************************************************
* API implementation
******************************************************************************/
//static inline int pmsis_kickoff(void *arg)
//{
// return __os_native_kickoff(arg);
//}
//static inline void pmsis_exit(int err)
//{
// __os_native_exit(err);
//}
//static inline void *pmsis_task_create(void (*entry)(void*),
// void *arg,
// char *name,
// int priority)
//{
// return __os_native_api_create_task(entry, arg, name, priority);
//}
//static inline void pmsis_task_suspend(void *task_handler)
//{
// __os_native_task_t *task = (__os_native_task_t *) task_handler;
// __os_native_task_suspend(task);
//}
//static inline void pi_yield()
//{
// __os_native_yield();
//}
//static inline int disable_irq(void)
//{
// hal_compiler_barrier();
// return __os_native_api_disable_irq();
//}
//static inline void restore_irq(int irq_enable)
//{
// hal_compiler_barrier();
// __os_native_api_restore_irq(irq_enable);
//}
//
//static inline int pi_sem_init(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// return __os_native_api_sem_init(sem);
//}
//
//static inline int pi_sem_deinit(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// return __os_native_api_sem_deinit(sem);
//}
//
//static inline void pi_sem_take(pi_sem_t *sem)
//{
// hal_compiler_barrier();
// sem->take(sem->sem_object);
//}
//
//static inline void pi_sem_give(pi_sem_t *sem)
//{
// sem->give(sem->sem_object);
// hal_compiler_barrier();
//}
//static inline void pmsis_mutex_take(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// int irq_enabled;
// volatile int mutex_free=0;
// while (!mutex_free)
// {
// irq_enabled = disable_irq();
// hal_compiler_barrier();
// mutex_free = !((volatile uint32_t)mutex->mutex_object);
// hal_compiler_barrier();
// restore_irq(irq_enabled);
// }
// irq_enabled = disable_irq();
// mutex->mutex_object = (void*)1;
// restore_irq(irq_enabled);
//#else
// mutex->take(mutex->mutex_object);
//#endif
//}
//
//static inline void pmsis_mutex_release(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// mutex->mutex_object = (void*)0;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//#else
// mutex->release(mutex->mutex_object);
// hal_compiler_barrier();
//#endif
//}
//
//static inline int pmsis_mutex_init(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// mutex->mutex_object = (void*)0;
// return 0;
//#else
// return __os_native_api_mutex_init(mutex);
//#endif
//}
//
//static inline int pmsis_mutex_deinit(pmsis_mutex_t *mutex)
//{
// hal_compiler_barrier();
//#ifdef __NO_NATIVE_MUTEX__
// mutex->mutex_object = (void*)0;
// return 0;
//#else
// return __os_native_api_mutex_deinit(mutex);
//#endif
//}
//
//static inline void pmsis_spinlock_init(pmsis_spinlock_t *spinlock)
//{
// hal_compiler_barrier();
// spinlock->lock = 0;
//}
//
//static inline void pmsis_spinlock_take(pmsis_spinlock_t *spinlock)
//{
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// spinlock->lock = 1;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//}
//
//static inline void pmsis_spinlock_release(pmsis_spinlock_t *spinlock)
//{
// int irq_enabled = disable_irq();
// hal_compiler_barrier();
// spinlock->lock = 0;
// hal_compiler_barrier();
// restore_irq(irq_enabled);
//}
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_ */

68
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis.h Normal file
View File

@@ -0,0 +1,68 @@
/*
* Copyright 2019 GreenWaves Technologies
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
#include <stddef.h>
#include <inttypes.h>
/* Debug helper. */
#ifdef DEBUG
#define DEBUG_PRINTF printf
#else
#define DEBUG_PRINTF(...) ((void) 0)
#endif /* DEBUG */
#if (!defined(HW_VERIF_ONLY))
/* Backend includes. */
//#include "pmsis/backend/implementation_specific_defines.h"
//#include "hal/include/hal_target.h"
/* pmsis_api includes. */
//#include "pmsis/device.h"
//#include "pmsis/task.h"
//#include "pmsis_types.h"
//#include "../../../pmsis_api/include/pmsis/rtos/rtos-orig.h"
//#include "pmsis/rtos/assert.h"
//#include "pmsis/mem_slab.h"
/* PMSIS includes. */
//#include "pmsis/implem/debug.h"
//#include "pmsis/implem/drivers/drivers_data.h"
//#include "hal/include/hal_pmsis_drivers.h"
#include "hal_fc_event.h"
#include "hal_fll_pi.h"
#include "hal_i2c_internal.h"
#include "hal_uart_internal.h"
//#include "pmsis/rtos/os/pmsis_task.h"
//#include "pmsis/rtos/os/pmsis_freq.h"
//#include "target/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h"
//#include "hal/include/hal_native_task_api.h"
#if defined(FEATURE_CLUSTER)
//#include "pmsis/implem/cluster/cluster.h"
#endif /* FEATURE_CLUSTER */
#endif /* HW_VERIF_ONLY */
/* Hal includes. */
//#include "pmsis/implem/hal/hal.h"
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_ */

124
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-properties.h Normal file
View File

@@ -0,0 +1,124 @@
/*
* Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
/* PULP defs */
#define PULP
#define ARCHI_FPGA_FREQUENCY 5000000
/* hardware modules */
#define ARCHI_NUM_TIMER 1
#define ARCHI_NUM_FLL 2
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
#define ARCHI_NB_FLL 3
#define __RT_FLL_CL 2
#define __RT_FLL_PERIPH 1
#define __RT_FLL_FC 0
#define __RT_FREQ_DOMAIN_FC 0
#define __RT_FREQ_DOMAIN_CL 2
#define __RT_FREQ_DOMAIN_PERIPH 1
#define RT_FREQ_NB_DOMAIN 3
/* Cores & cluster */
/* FC */
#define ARCHI_FC_CID (32)
/* Cluster */
#define ARCHI_HAS_CLUSTER (1)
#define ARCHI_CL_CID(id) (id)
#define ARCHI_CLUSTER_NB_PE (8) /* Processing elements. */
/* Memories */
/* FC memory */
#define ARCHI_HAS_FC_TCDM (1)
#define ARCHI_HAS_FC_ALIAS (1)
#define FC_TCDM_SIZE (0x00004000) /* 16kB. */
/* L2 memory */
#define ARCHI_HAS_L2_ALIAS (0)
#define L2_SHARED_SIZE (0x00080000) /* 512kB. */
/* L1 cluster memory */
#define ARCHI_HAS_CL_L1_ALIAS (1)
#define CL_L1_SIZE (0x00010000) /* 64kB. */
/* L1 cluster TS */
#define ARCHI_HAS_CL_L1_TS (1)
/* TODO: fix this table */
/* UDMA peripherals */
// #define UDMA_HAS_SPIM (1)
// #define UDMA_HAS_HYPER (0)
// #define UDMA_HAS_UART (1)
// #define UDMA_HAS_I2C (1)
// #define UDMA_HAS_DMACPY (0)
// #define UDMA_HAS_I2S (1)
// #define UDMA_HAS_CPI (1)
/* TODO: fix this table */
/* Number of UDMA peripherals */
// #define UDMA_NB_SPIM (2)
// #define UDMA_NB_HYPER (0)
// #define UDMA_NB_UART (1)
// #define UDMA_NB_I2C (2)
// #define UDMA_NB_DMACPY (0)
// #define UDMA_NB_I2S (1)
// #define UDMA_NB_CPI (1)
/* TODO: fix this table */
/* #define UDMA_NB_PERIPH ((UDMA_HAS_SPIM ? UDMA_NB_SPIM) + \ */
/* (UDMA_HAS_HYPER ? UDMA_NB_HYPER) + \ */
/* (UDMA_HAS_UART ? UDMA_NB_UART) + \ */
/* (UDMA_HAS_I2C ? UDMA_NB_I2C) + \ */
/* (UDMA_HAS_DMACPY ? UDMA_NB_DMACPY) + \ */
/* (UDMA_HAS_I2S ? UDMA_NB_I2S) + \ */
/* (UDMA_HAS_CPI ? UDMA_NB_CPI)) */
#define UDMA_NB_PERIPH (10)
/* Size of each UDMA peripheral */
#define UDMA_PERIPH_SIZE_LOG2 (7)
#define UDMA_PERIPH_SIZE (1 << UDMA_PERIPH_SIZE_LOG2)
/* UDMA peripherals ID, this maps to PER_ID_* in udma_subsystem.sv */
//#define UDMA_SPIM_ID(id) (1 + (id))
/* #define UDMA_HYPER_ID(id) (3 + (id)) */
//#define UDMA_UART_ID(id) (0 + (id))
//#define UDMA_I2C_ID(id) (2 + (id))
/* #define UDMA_DMACPY_ID(id) (7 + (id)) */
//#define ARCHI_UDMA_FILTER_ID(id) (7 + (id))
////#define UDMA_I2S_ID(id) (5 + (id))
//#define UDMA_CPI_ID(id) (6 + (id))
//#define UDMA_SDIO_ID(id) (4 + (id))
/* Pads & GPIO. */
// #define ARCHI_NB_PAD (48)
// #define ARCHI_NB_GPIO (32)
/* PWM. */
/* #define ARCHI_NB_PWM (4) */
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */

82
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pulp-mem-map.h Normal file
View File

@@ -0,0 +1,82 @@
/*
* Copyright (C) 2019 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
/*
* SOC PERIPHERALS
*/
#define PULP_SOC_PERIPHERALS_ADDR 0x1A100000
#define PULP_FC_TIMER_SIZE 0x00000800
#define PULP_FLL_OFFSET 0x00000000
#define PULP_GPIO_OFFSET 0x00001000
#define PULP_UDMA_OFFSET 0x00002000
#define PULP_APB_SOC_CTRL_OFFSET 0x00004000
#define PULP_ADV_TIMER_OFFSET 0x00005000
#define PULP_SOC_EU_OFFSET 0x00006000
#define PULP_FC_IRQ_OFFSET 0x00009800
/* #define PULP_FC_IRQ_OFFSET 0x00009000 */ /* this is a mirror of above */
#define PULP_FC_TIMER_OFFSET 0x0000B000
#define PULP_FC_HWPE_OFFSET 0x0000C000
#define PULP_STDOUT_OFFSET 0x0000F000
#define PULP_DEBUG_OFFSET 0x00010000
#define PULP_FLL_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET)
#define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET)
#define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET)
#define PULP_APB_SOC_CTRL_ADDR \
(PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET)
#define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET)
#define PULP_SOC_EU_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET)
#define PULP_FC_IRQ_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET)
/* #define PULP_FC_ITC_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_ITC_OFFSET) */
#define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET)
#define PULP_FC_HWPE_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET)
#define PULP_STDOUT_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET)
#define PULP_FLL_AREA_SIZE 0x00000010
/*
* CLUSTER
*/
#define PULP_CLUSTER_ADDR 0x00000000
#define PULP_CLUSTER_SIZE 0x00400000
#define PULP_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*PULP_CLUSTER_SIZE)
/*
* CLUSTER PERIPHERALS
*/
#define PULP_CLUSTER_PERIPHERALS_OFFSET 0x00200000
#define PULP_TIMER_OFFSET 0x00000400
#define PULP_CLUSTER_PERIPHERALS_ADDR \
(PULP_CLUSTER_ADDR + PULP_CLUSTER_PERIPHERALS_OFFSET)
#define PULP_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) \
(PULP_CLUSTER_GLOBAL_ADDR(cid) + PULP_CLUSTER_PERIPHERALS_OFFSET)
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ */

36
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-system.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: Platform system level functions */
#ifndef _CORE_V_MCU_SYSTEM_H
#define _CORE_V_MCU_SYSTEM_H
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOSConfig.h"
extern volatile uint32_t system_core_clock;
void system_init (void);
void system_core_clock_update (void);
#endif /* _CORE_V_MCU_SYSTEM_H */

104
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-target.h Normal file
View File

@@ -0,0 +1,104 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Author: Robert Balas */
#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
#include "core_pulp.h"
#include "core_utils.h"
#include "core-v-mcu-periph.h"
//#include "pmsis/targets/periph.h"
static inline void hal_compiler_barrier()
{
asm volatile ("" : : : "memory");
}
static inline void hal_write32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) = value;
asm volatile ("" : : : "memory");
}
static inline void hal_write8(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint8_t *)addr) = value;
asm volatile ("" : : : "memory");
}
static inline void hal_or32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) |= value;
asm volatile ("" : : : "memory");
}
static inline void hal_and32(volatile void *addr, uint32_t value)
{
asm volatile ("" : : : "memory");
*((volatile uint32_t *)addr) &= value;
asm volatile ("" : : : "memory");
}
static inline uint32_t hal_read32(volatile void *addr)
{
asm volatile ("" : : : "memory");
uint32_t ret = *((volatile uint32_t *)addr);
asm volatile ("" : : : "memory");
return ret;
}
static inline uint8_t hal_read8(volatile void *addr)
{
asm volatile ("" : : : "memory");
uint8_t ret = *((volatile uint8_t *)addr);
asm volatile ("" : : : "memory");
return ret;
}
static inline uint32_t pi_core_id()
{
return __native_core_id();
}
static inline uint32_t pi_cluster_id()
{
return __native_cluster_id();
}
static inline uint32_t pi_is_fc()
{
return __native_is_fc();
}
static inline uint32_t pi_nb_cluster_cores()
{
return ARCHI_CLUSTER_NB_PE;
}
static inline int pi_cl_cluster_nb_cores()
{
return ARCHI_CLUSTER_NB_PE;
}
#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_ */

1483
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp.h Normal file
View File

File diff suppressed because it is too large Load Diff

457
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp_cluster.h Normal file
View File

@@ -0,0 +1,457 @@
/******************************************************************************
* @file core_pulp_cluster.h
* @brief CMSIS PULP Core Cluster Peripheral Access Layer Header File
* @version V0.0.1
* @date 04. April 2020
******************************************************************************/
/*
* Copyright (c) 2017 GreenWaves Technologies SAS. All rights reserved.
* Copyright (c) 2020 ETH Zurich
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CLUSTER_PULP_H_GENERIC__
#define __CLUSTER_PULP_H_GENERIC__
#ifdef FEATURE_CLUSTER
//#include "cores/TARGET_RISCV_32/core_pulp.h"
#include "core_pulp.h"
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
#define CLUSTER_ID 0 /**< CLuster ID */
#define CLUSTER_CORES_NUM 8 /**< CLuster cores number */
#define CLUSTER_HW_MUTEX_NUM 1
/** SoC events statically reserved by the runtime*/
#define FC_CLUSTER_SW_NOTIF_EVENT 0 /**< Used to notify FC*/
#define CLUSTER_CLUSTER_SW_NOTIF_EVENT 1 /**< Used to notify CLUSTER*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__OM uint32_t EOC; /*!< Offset: 0x000 (R/W ) CPUID Base Register */
__IOM uint32_t _reserved0; /*!< Offset: 0x004 (R/W) reserved Register */
__IOM uint32_t FETCH_EN; /*!< Offset: 0x008 (R/W) Interrupt Control and State Register */
__IOM uint32_t _reserved1; /*!< Offset: 0x00C (R/W) reserved Register */
__OM uint32_t EVENT; /*!< Offset: 0x010 (W) Event out Register */
__IOM uint32_t _reserved2[3]; /*!< Offset: 0x014 (R/W) reserved Register */
__OM uint32_t CLUSTER_CG; /*!< Offset: 0x020 (R/W) Event out Register */
__IOM uint32_t _reserved3[7]; /*!< Offset: 0x024 (R/W) reserved Registers */
__IOM uint32_t BOOT_ADDR[8]; /*!< Offset: 0x040 (R/W) Vector Table Offset Register */
} SCB_Type;
/* SCB Registers Definitions */
#define SCB_EOC_Pos 0U /*!< SCB EOC Position */
#define SCB_EOC_Msk (1UL /* << SCB_EOC_Pos*/) /*!< SCB EOC Mask */
#define SCB_FETCH_EN_Pos 0U /*!< SCB FETCH_EN Position */
#define SCB_FETCH_EN_Msk (1UL /* << SCB_FETCH_EN_Pos*/) /*!< SCB FETCH_EN Mask */
/*@} end of group CMSIS_FC_CTRL */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCBC System Control Block for Icache (SCBC)
\brief Type definitions for the System Control Block Registers
@{
*/
typedef struct
{
__IOM uint32_t ICACHE_ENABLE; /*!< Offset: 0x00 (R/W ) Cluster Icache Enable Register */
__IOM uint32_t ICACHE_FLUSH; /*!< Offset: 0x04 (R/W) Cluster Icache Flush Register */
__IOM uint32_t ICACHE_LX_SEL_FLUSH; /*!< Offset: 0x08 (R/W) Cluster Icache Level-X Flush Register or FC Flush Selected Address Register*/
__IOM uint32_t ICACHE_SEL_FLUSH_STATUS; /*!< Offset: 0x0C (R/W) Cluster Icache Flush Selected Address Register or FC ICACHE status */
__IOM uint32_t ICACHE_CNTS_CLEAR; /*!< Offset: 0x10 (R/W) Cluster Icache is private Icache */
__IOM uint32_t ICACHE_CNTS_ENABLE; /*!< Offset: 0x10 (R/W) Cluster Icache is private Icache */
} SCBC_Type;
/* SCBC Registers Definitions */
#define SCBC_ENABLE_Pos 0U /*!< SCBC_ENABLE Position */
#define SCBC_ENABLE_Msk (1UL /* << SCBC_ENABLE_Pos*/) /*!< SCBC_ENABLE Mask */
#define SCBC_STATUS_Pos 0U /*!< SCBC_STATUS Position */
#define SCBC_STATUS_Msk (1UL /* << SCBC_STATUS_Pos*/) /*!< SCBC_STATUS Mask */
/*@} end of group CMSIS_SCBC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_CORE_DEMUX Event Unit Core
\brief Type definitions for the event unit core Registers
@{
*/
/**
\brief Structure type to access the EU_CORE_DEMUX.
*/
typedef struct {
__IOM uint32_t MASK; /**< EU_DEMUX mask register, offset: 0x00 */
__IOM uint32_t MASK_AND; /**< EU_DEMUX mask and register, offset: 0x04 */
__IOM uint32_t MASK_OR; /**< EU_DEMUX mask or register, offset: 0x08 */
__IOM uint32_t MASK_IRQ; /**< EU_DEMUX mask irq register, offset: 0x0C */
__IOM uint32_t MASK_IRQ_AND; /**< EU_DEMUX mask irq and register, offset: 0x10 */
__IOM uint32_t MASK_IRQ_OR; /**< EU_DEMUX mask irq or register, offset: 0x14 */
__IOM uint32_t STATUS; /**< EU_DEMUX Status register, offset: 0x18 */
__IOM uint32_t BUFFER; /**< EU_DEMUX buffer register, offset: 0x1C */
__IOM uint32_t BUFFER_MASKED; /**< EU_DEMUX buffer masked register, offset: 0x20 */
__IOM uint32_t BUFFER_IRQ_MASKED; /**< EU_DEMUX buffer irq masked register, offset: 0x24 */
__IOM uint32_t BUFFER_CLEAR; /**< EU_DEMUX buffer clear register, offset: 0x28 */
__IOM uint32_t SW_EVENTS_MASK; /**< EU_DEMUX software event mask register, offset: 0x2C */
__IOM uint32_t SW_EVENTS_MASK_AND; /**< EU_DEMUX software event mask and register, offset: 0x30 */
__IOM uint32_t SW_EVENTS_MASK_OR; /**< EU_DEMUX software event mask or register, offset: 0x34 */
__IOM uint32_t EVENT_WAIT; /**< EU_DEMUX event wait register, offset: 0x38 */
__IOM uint32_t EVENT_WAIT_CLEAR; /**< EU_DEMUX event wait clear register, offset: 0x3C */
__IOM uint32_t MASK_SEC_IRQ; /**< EU_DEMUX mask sec irq register, offset: 0x40 */
} EU_CORE_DEMUX_Type;
/*@} end of group CMSIS_EU_CORE_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_SEC_DEMUX Event Unit Security
\brief Type definitions for the event unit security Registers
@{
*/
/**
\brief Structure type to access the EU_SEC_DEMUX.
*/
typedef struct {
__IOM uint32_t MASK; /**< EU_SEC_DEMUX mask register, offset: 0x00 */
__IOM uint32_t MASK_AND; /**< EU_SEC_DEMUX mask and register, offset: 0x04 */
__IOM uint32_t MASK_OR; /**< EU_SEC_DEMUX mask or register, offset: 0x08 */
} EU_SEC_DEMUX_Type;
#define EU_SEC_ELEM_NUM 8
/*@} end of group CMSIS_EU_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_LOOP_DEMUX Event Unit Loop
\brief Type definitions for the event unit Loop Registers
@{
*/
/**
\brief Structure type to access the EU_LOOP_DEMUX.
*/
typedef struct {
__IOM uint32_t STATE; /**< EU_LOOP_DEMUX state register, offset: 0x00 */
__IOM uint32_t START; /**< EU_LOOP_DEMUX start register, offset: 0x04 */
__IOM uint32_t END; /**< EU_LOOP_DEMUX end register, offset: 0x08 */
__IOM uint32_t INCR; /**< EU_LOOP_DEMUX increment register, offset: 0x0C */
__IOM uint32_t CHUNK; /**< EU_LOOP_DEMUX chunk register, offset: 0x10 */
__IOM uint32_t EPOCH; /**< EU_LOOP_DEMUX epoch register, offset: 0x14 */
__IOM uint32_t SINGLE; /**< EU_LOOP_DEMUX single register, offset: 0x18 */
} EU_LOOP_DEMUX_Type;
#define EU_LOOP_DEMUX_DONE_ 0x0
#define EU_LOOP_DEMUX_LOCKED_ 0x1
#define EU_LOOP_DEMUX_SKIP_ 0x2
/*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_SW_EVENTS_DEMUX Event Unit Loop
\brief Type definitions for the event unit Loop Registers
@{
*/
/**
\brief Structure type to access the EU_SW_EVENTS_DEMUX.
*/
typedef struct {
__IOM uint32_t TRIGGER_SET[8]; /**< EU_SW_EVENTS_DEMUX trigger set register, offset: 0x00 */
__IOM uint32_t _reserved0[8]; /*!< Offset: 0x20 (R/W) Empty Registers */
__IOM uint32_t TRIGGER_WAIT[8]; /**< EU_SW_EVENTS_DEMUX trigger wait register, offset: 0x40 */
__IOM uint32_t _reserved1[8]; /*!< Offset: 0x60 (R/W) Empty Registers */
__IOM uint32_t TRIGGER_CLR[8]; /**< EU_SW_EVENTS_DEMUX trigger clear register, offset: 0x80 */
} EU_SW_EVENTS_DEMUX_Type;
/*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_DISPATCH_DEMUX Event Unit Dispatch
\brief Type definitions for the event unit Dispatch Registers
@{
*/
typedef struct {
__IOM uint32_t FIFO_ACCESS; /**< EU_DISPATCH_DEMUX fifo access register, offset: 0x00 */
__IOM uint32_t TEAM_CONFIG; /**< EU_DISPATCH_DEMUX team config register, offset: 0x04 */
} EU_DISPATCH_DEMUX_Type;
#define EU_DISPATCH_DEMUX_ELEM_NUM 8
/*@} end of group CMSIS_EU_DISPATCH_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_MUTEX_DEMUX Event Unit Hardware Mutex
\brief Type definitions for the event unit Dispatch Registers
@{
*/
typedef struct {
__IOM uint32_t MUTEX[1]; /**< EU_MUTEX_DEMUX mutex register, offset: 0x00 */
} EU_MUTEX_DEMUX_Type;
#define EU_MUTEX_DEMUX_ELEM_NUM 1
/*@} end of group CMSIS_EU_MUTEX_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_BARRIER_DEMUX Event Unit Barrier
\brief Type definitions for the event unit Barrier Registers
@{
*/
typedef struct {
__IOM uint32_t TRIGGER_MASK; /**< EU_BARRIER_DEMUX triger mask register, offset: 0x00 */
__IOM uint32_t STATUS; /**< EU_BARRIER_DEMUX status register, offset: 0x04 */
__IOM uint32_t STATUS_SUMMRY; /**< EU_BARRIER_DEMUX status summary register, offset: 0x08 */
__IOM uint32_t TARGET_MASK; /**< EU_BARRIER_DEMUX target mask register, offset: 0x0C */
__IOM uint32_t TRIGGER; /**< EU_BARRIER_DEMUX trigger register, offset: 0x10 */
__IOM uint32_t TRIGGER_SET; /**< EU_BARRIER_DEMUX trigger set register, offset: 0x14 */
__IOM uint32_t TRIGGER_WAIT; /**< EU_BARRIER_DEMUX trigger wait register, offset: 0x18 */
__IOM uint32_t TRIGGER_WAIT_CLEAR; /**< EU_BARRIER_DEMUX trigger clear register, offset: 0x1C */
} EU_BARRIER_DEMUX_Type;
/* We have only one HW Barrier */
/*@} end of group CMSIS_EU_BARRIER_DEMUX */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_EU_SOC_EVENTS Event Unit Barrier
\brief Type definitions for the event unit Barrier Registers
@{
*/
typedef struct {
__IM uint32_t CURRENT_EVENT; /**< EU_SOC_EVENTS current event register, offset: 0x00 */
} EU_SOC_EVENTS_Type;
/* We have only one HW Barrier */
#define EU_CURRENT_VALID_BIT_MASK (0x80000000U)
#define EU_CURRENT_VALID_BIT_SHIFT (31U)
#define EU_CURRENT_VALID_BIT(x) (((uint32_t)(((uint32_t)(x)) << EU_CURRENT_VALID_BIT_SHIFT)) & EU_CURRENT_VALID_BIT_MASK)
#define EU_CURRENT_SOC_EVENT_MASK 0xFF
/*@} end of group CMSIS_EU_SOC_EVENTS */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/**
\brief Structure type to access the direct memory access (DMAMCHAN).
*/
typedef struct
{
__IOM uint32_t CMD; /*!< Offset: 0x00 (R/W ) DMAMCHAN Command Base Register */
__IOM uint32_t STATUS; /*!< Offset: 0x04 (R/W) DMAMCHAN Channle Status Register */
} DMAMCHAN_Type;
/* DMAMCHAN Registers Definitions */
#define DMAMCHAN_CMD_TID_Pos 0U /*!< DMAMCHAN TID Position */
#define DMAMCHAN_CMD_TID_Msk (0xFUL /* << DMAMCHAN_CMD_TID_Pos*/) /*!< DMAMCHAN TID Mask */
#define DMAMCHAN_CMD_BLE_Pos 21U /*!< DMAMCHAN Broadcast Lines Enable Position */
#define DMAMCHAN_CMD_BLE_Msk (1UL << DMAMCHAN_CMD_BLE_Pos) /*!< DMAMCHAN CMD Broadcast Lines Enable Mask */
#define DMAMCHAN_CMD_ILE_Pos 20U /*!< DMAMCHAN Intrrupt Line EnableID Position */
#define DMAMCHAN_CMD_ILE_Msk (1UL << DMAMCHAN_CMD_ILE_Pos) /*!< DMAMCHAN Intrrupt Line Enable Mask */
#define DMAMCHAN_CMD_ELE_Pos 19U /*!< DMAMCHAN CMD Event Line Enable Position */
#define DMAMCHAN_CMD_ELE_Msk (1UL << DMAMCHAN_CMD_ELE_Pos) /*!< DMAMCHAN CMD Event Line Enable Mask */
#define DMAMCHAN_CMD_2D_Pos 18U /*!< DMAMCHAN CMD 2D transfer Position */
#define DMAMCHAN_CMD_2D_Msk (1UL << DMAMCHAN_CMD_2D_Pos) /*!< DMAMCHAN CMD 2D transfer Mask */
#define DMAMCHAN_CMD_INC_Pos 17U /*!< DMAMCHAN CMD Increment Position */
#define DMAMCHAN_CMD_INC_Msk (1UL << DMAMCHAN_CMD_INC_Pos) /*!< DMAMCHAN CMD Increment Mask */
#define DMAMCHAN_CMD_TYP_Pos 16U /*!< DMAMCHAN CMD Type Position */
#define DMAMCHAN_CMD_TYP_Msk (1UL << DMAMCHAN_CMD_TYP_Pos) /*!< DMAMCHAN CMD Type Mask */
#define DMAMCHAN_CMD_LEN_Pos 0U /*!< DMAMCHAN CMD Length Position */
#define DMAMCHAN_CMD_LEN_Msk (0xFFUL /*<< DMAMCHAN_EOC_Pos*/) /*!< DMAMCHAN CMD Length Mask */
#define DMAMCHAN_CMD_2D_STRIDE_Pos 16U /*!< DMAMCHAN CMD 2D STRIDE Position */
#define DMAMCHAN_CMD_2D_STRIDE_Msk (0xFFUL << DMAMCHAN_CMD_2D_STRIDE_Pos) /*!< DMAMCHAN CMD 2D STRIDE Mask */
#define DMAMCHAN_CMD_2D_COUNT_Pos 0U /*!< DMAMCHAN CMD 2D COUNT Position */
#define DMAMCHAN_CMD_2D_COUNT_Msk (0xFFUL /* << DMAMCHAN_CMD_2D_COUNT_Pos*/) /*!< DMAMCHAN CMD 2D COUNT Mask */
/*@} end of group CMSIS_DMAMCHAN */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/**
\brief Structure type to access the direct memory access compressor (DMAMCHAN).
*/
typedef struct
{
/*!< Offset: 0x00 (W ) Compressor TCDM Address Register */
__O uint32_t TCDM_ADDRESS;
/*!< Offset: 0x04 (W ) Compressor L2 Address Register */
__O uint32_t L2_ADDRESS;
/*!< Offset: 0x08 (W ) Compressor configuration Register */
__O uint32_t CONFIG;
// 0xC
__IOM uint32_t PAD0;
/*!< Offset: 0x10 (W ) Compressor LUT patterns Register */
__O uint32_t LUT;
/*!< Offset: 0x14 (W ) Compressor compression special value Register */
__O uint32_t SPECIAL;
/*!< Offset: 0x18 (R ) Compressor readen bits Register */
__I uint32_t BIT_READ;
/*!< Offset: 0x1C (W ) Compressor transfer direction Register */
__O uint32_t DIRECTION;
} DMAMCHAN_COMPRESSOR_Type;
typedef struct {
__O uint32_t TCDM_ADDR;
__O uint32_t L2_ADDR;
__O uint32_t CONF_REG;
__I uint32_t STAT_REG;
__O uint32_t LUT_REG;
__O uint32_t SYMBOL_REG;
__O uint32_t BIT_READ_REG;
__O uint32_t MODE_REG;
__O uint32_t SW_RST_REG;
__O uint32_t CLKEN_REG;
__O uint32_t TRIGGER_REG;
__IOM uint32_t PAD0;
__O uint32_t L2_COUNT_REG;
__O uint32_t L2_STRIDE_REG;
__O uint32_t TCDM_COUNT_REG;
__O uint32_t TCDM_STRIDE_REG;
} decompressor_t;
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CLUSTER_EU_CORES Cluster Event Unit Cores
\brief Type definitions for the event unit core Registers
@{
*/
/**
\brief Structure type to access the CLUSTER_EU_CORES.
*/
typedef struct {
EU_CORE_DEMUX_Type CORES[CLUSTER_CORES_NUM]; /*!< Offset: 0x000 (R/W) Cluster Event Unit cores */
} CLUSTER_EU_CORES_Type;
/*@} end of group CMSIS_CLUSTER_EU_CORE */
#define CLUSTER_DISPATCH_IS_ENTRY_MASK (0x1U)
#define CLUSTER_DISPATCH_IS_ENTRY_SHIFT (0U)
#define CLUSTER_DISPATCH_IS_ENTRY(x) (((uint32_t)(((uint32_t)(x)) /* << CLUSTER_DISPATCH_IS_ENTRY_SHIFT */)) & CLUSTER_DISPATCH_IS_ENTRY_MASK)
#define CLUSTER_DISPATCH_ENTRY_ADDR_MASK (0x7FFFFFFEU)
#define CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT (1U)
#define CLUSTER_DISPATCH_ADDR_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT)) & CLUSTER_DISPATCH_ENTRY_ADDR_MASK)
#define CLUSTER_DISPATCH_ENTRY_MASK (0x7FFFFFFFU)
#define CLUSTER_DISPATCH_ENTRY_SHIFT (0U)
#define CLUSTER_DISPATCH_ENTRY(x) (((uint32_t)(((uint32_t)(x)) /*<< CLUSTER_DISPATCH_ENTRY_SHIFT*/)) & CLUSTER_DISPATCH_ENTRY_MASK)
#define READ_CLUSTER_DISPATCH_ENTRY(x) (((uint32_t)(((uint32_t)(x)) & CLUSTER_DISPATCH_ENTRY_MASK)) /*>> CLUSTER_DISPATCH_ENTRY_SHIFT*/)
#define CLUSTER_DISPATCH_IS_JOB_MASK (0x80000000U)
#define CLUSTER_DISPATCH_IS_JOB_SHIFT (31U)
#define CLUSTER_DISPATCH_IS_JOB(x) (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_IS_JOB_SHIFT)) & CLUSTER_DISPATCH_IS_JOB_MASK)
/* Memory map */
#define CLUSTER_BASE (ARCHI_CLUSTER_GLOBAL_ADDR(0)) /*!< CLUSTER Base Address */
#define CLUSTER_SCB_BASE (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0)) /*!< CLUSTER System Control Block Base Address */
#define CLUSTER_SCBC_BASE (ARCHI_ICACHE_CTRL_ADDR) /*!< CLUSTER System Control Block Cache Base Address */
#define CLUSTER_SysTick_BASE (ARCHI_CLUSTER_TIMER_ADDR) /*!< CLUSTER SysTick Base Address */
#define CLUSTER_EU_BARRIER_BASE (ARCHI_EU_ADDR + 0x400UL) /*!< CLUSTER Event Unit HW Barrier Base Address */
#define CLUSTER_EU_SW_EVENTS_BASE (ARCHI_EU_ADDR + 0x600UL) /*!< CLUSTER Event Unit SW Events Base Address */
#define CLUSTER_EU_SOC_EVENTS_BASE (ARCHI_EU_ADDR + 0x700UL) /*!< CLUSTER Event Unit SOC Events Base Address */
#define CLUSTER_EU_EXT_EVENTS_BASE (ARCHI_EU_ADDR + 0x780UL) /*!< CLUSTER Event Unit EXT Events Base Address */
#define CLUSTER_EU_CORE_DEMUX_BASE (ARCHI_DEMUX_PERIPHERALS_ADDR) /*!< CLUSTER Event Unit Core Demux Base Address */
#define CLUSTER_EU_SEC_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x040UL) /*!< CLUSTER Event Unit Security Demux Base Address */
#define CLUSTER_EU_LOOP_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x060UL) /*!< CLUSTER Event Unit Loop Demux Base Address */
#define CLUSTER_EU_DISPATCH_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x080UL) /*!< CLUSTER Event Unit Dispatch Demux Base Address */
#define CLUSTER_EU_MUTEX_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x0C0UL) /*!< CLUSTER Event Unit Mutex Demux Base Address */
#define CLUSTER_EU_SW_EVENTS_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x100UL) /*!< CLUSTER Event Unit SW Events Demux Base Address */
#define CLUSTER_EU_BARRIER_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x200UL) /*!< CLUSTER Event Unit Barrier Demux Base Address */
/* Cluster Core Structrue definitions */
#define CLUSTER_EU_SW_EVENTS ((EU_SW_EVENTS_DEMUX_Type *) CLUSTER_EU_SW_EVENTS_BASE) /*!< EU_SW_EVENTS_DEMUX configuration struct */
#define EU_CORES ((CLUSTER_EU_CORES_Type *) ARCHI_EU_ADDR) /*!< CLUSTER_EU_CORES configuration struct */
#define SCB ((SCB_Type *) CLUSTER_SCB_BASE ) /*!< CLUSTER SCB configuration struct */
#define CLUSTER_SCBC ((SCBC_Type *) CLUSTER_SCBC_BASE ) /*!< CLUSTER SCBC configuration struct */
#define CLUSTER_SysTick ((SysTick_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */
#define CLUSTER_TIMERL ((TimerL_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */
#define CLUSTER_TIMERH ((TimerH_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */
#ifdef __cplusplus
}
#endif
#endif
#endif /* __CLUSTER_PULP_H_GENERIC */

51
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_utils.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright 2020 Greenwaves Technologies
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PMSIS_CORE_UTILS__
#define __PMSIS_CORE_UTILS__
#include "csr.h"
/** FC_CLUSTER_ID Definitions */
#define FC_CLUSTER_ID 32 /**< FC CLuster ID */
/**
\ingroup CMSIS_Core_IDFunctionInterface
\defgroup CMSIS_Core_IDFunctions ID Functions
\brief Functions that manage Cluster and Core ID.
@{
*/
static inline uint32_t __native_core_id() {
/* encoding of mhartid: {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
uint32_t mhartid = csr_read(MHARTID_ADDR);
return mhartid & 0x01f;
}
static inline uint32_t __native_cluster_id() {
/* encoding of mhartid {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
uint32_t mhartid = csr_read(MHARTID_ADDR);
return 0 ;//(mhartid >> 5) & 0x3f;
}
static inline uint32_t __native_is_fc() {
return ( __native_cluster_id() == FC_CLUSTER_ID);
}
#endif

86
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/csr.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: CSR access macros */
#ifndef __CSR_H
#define __CSR_H
#include "bits.h"
/* TODO: complete this */
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
/* TODO: complete this */
#define MSTATUS_IE BIT(3)
#define __CSR_EXPAND(x) #x
#define csr_read(csr) \
({ \
register unsigned long __val; \
asm volatile("csrr %0, " __CSR_EXPAND(csr) \
: "=r"(__val) \
: \
: "memory"); \
__val; \
})
#define csr_write(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrw " __CSR_EXPAND(csr) ", %0" \
: \
: "rK"(__val) \
: "memory"); \
})
/* TODO: I hope this properly does a memory barrier with the "memory" hint */
#define csr_read_clear(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})
#define csr_read_set(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})
#endif

452
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pmsis_gcc.h Normal file
View File

@@ -0,0 +1,452 @@
/**************************************************************************//**
* @file pmsis_gcc.h
* @brief CMSIS compiler GCC header file
* @version V5.0.2
* @date 4. April 2020
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2020 ETH Zurich
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
Modifications copyright (C) 2018 GreenWaves Technologies
- Add __RISCV_ARCH_GAP__ macro define
- Delete and Change some Cortex-M registers access functions, and replace them by
RISC-V 32-bit GAP8 registers access functions
- Add some GAP8 builtin functions
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
#include <stdint.h>
#define __RISCV_ARCH_PULP__ 1
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#define __get_BASEPRI() 0
#define __get_PRIMASK() 1
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_RW_REG(r) "+l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_RW_REG(r) "+r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
//{
// __ASM volatile ("nop");
//}
#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
//{
// __ASM volatile ("wfi");
//}
#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
//{
// __ASM volatile ("wfe");
//}
#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
//{
// __ASM volatile ("sev");
//}
#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
// __ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
// __ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
// __ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\ingroup PULP_BUILTIN_MARCO
@{
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ExtInsMaskFast(uint32_t size, uint32_t offset) { return ((((size - 1))<<5) | (offset)); }
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ExtInsMaskSafe(uint32_t size, uint32_t offset) { return ((((size - 1) & 0x1F)<<5) | (offset & 0x1F)); }
/*! @brief Packing of scalars into vectors */
#define __VEC_PACK2(x, y) __builtin_pulp_pack2((int16_t) x, (int16_t) y)
#define __VEC_PACKU2(x, y) __builtin_pulp_pack2((uint16_t) x, (uint16_t) y)
#define __VEC_PACK4(x, y, z, t) __builtin_pulp_pack4((int8_t) x, (int8_t) y, (int8_t) z, (int8_t) t)
#define __VEC_PACKU4(x, y, z, t) __builtin_pulp_pack4((uint8_t) x, (uint8_t) y, (uint8_t) z, (uint8_t) t)
/*! @brief Max */
#define __MAX(x, y) __builtin_pulp_maxsi((x), (y))
#define __MAX2(x, y) __builtin_pulp_max2(x, y)
#define __MAX4(x, y) __builtin_pulp_max4(x, y)
#define __MAXU2(x, y) __builtin_pulp_maxu2(x, y)
#define __MAXU4(x, y) __builtin_pulp_maxu4(x, y)
/*! @brief Min */
#define __MIN2(x, y) __builtin_pulp_min2(x, y)
#define __MIN4(x, y) __builtin_pulp_min4(x, y)
#define __MINU2(x, y) __builtin_pulp_minu2(x, y)
#define __MINU4(x, y) __builtin_pulp_minu4(x, y)
/*! @brief Clip */
#define __CLIP(x, precision) __builtin_pulp_clip(x, -(1<<(precision)), (1<<precision)-1)
#define __CLIPU(x, precision) __builtin_pulp_clipu(x, 0, (1<<precision)-1)
/*! @brief Abs */
#define __ABS2(x) __builtin_pulp_abs2(x)
#define __ABS4(x) __builtin_pulp_abs4(x)
/* Unary minus */
#define __NEG2(x) __builtin_pulp_neg2(x)
#define __NEG4(x) __builtin_pulp_neg4(x)
/* Addition */
#define __ADD2(x, y) __builtin_pulp_add2(x, y)
#define __ADD4(x, y) __builtin_pulp_add4(x, y)
/* Substraction */
#define __SUB2(x, y) __builtin_pulp_sub2(x, y)
#define __SUB4(x, y) __builtin_pulp_sub4(x, y)
/* Average */
#define __AVG2(x, y) __builtin_pulp_avg2(x, y)
#define __AVG4(x, y) __builtin_pulp_avg4(x, y)
/* Average unsigned */
#define __AVGU2(x, y) __builtin_pulp_avgu2(x, y)
#define __AVGU4(x, y) __builtin_pulp_avgu4(x, y)
/* Bitwise and */
#define __AND2(x, y) __builtin_pulp_and2(x, y)
#define __AND4(x, y) __builtin_pulp_and4(x, y)
/* Bitwise or */
#define __OR2(x, y) __builtin_pulp_or2(x, y)
#define __OR4(x, y) __builtin_pulp_or4(x, y)
/* Bitwise exor */
#define __EXOR2(x, y) __builtin_pulp_exor2(x, y)
#define __EXOR4(x, y) __builtin_pulp_exor4(x, y)
/* Logical shift right */
#define __SRL2(x, y) __builtin_pulp_srl2(x, y)
#define __SRL4(x, y) __builtin_pulp_srl4(x, y)
/* Arithmetic shift right */
#define __SRA2(x, y) __builtin_pulp_sra2(x, y)
#define __SRA4(x, y) __builtin_pulp_sra4(x, y)
/* Logical shift left */
#define __SLL2(x, y) __builtin_pulp_sll2(x, y)
#define __SLL4(x, y) __builtin_pulp_sll4(x, y)
/*! @brief Mac */
#define __MAC(acc, x, y) __builtin_pulp_mac(x, y, acc)
#define __MSU(acc, x, y) __builtin_pulp_msu(x, y, acc)
#define __MACS(acc, x, y) __builtin_pulp_macs(x, y, acc)
#define __MACHHS(acc, x, y) __builtin_pulp_machhs(x, y, acc)
#define __MACU(acc, x, y) __builtin_pulp_macu(x, y, acc)
#define __MACHHU(acc, x, y) __builtin_pulp_machhu(x, y, acc)
#define __MACSN(acc, x, y, n) __builtin_pulp_macsN(x, y, acc, n)
#define __MACUN(acc, x, y, n) __builtin_pulp_macuN(x, y, acc, n)
#define __MACSRN(acc, x, y, n) __builtin_pulp_macsRN(x, y, acc, n, (1<<(n-1)))
#define __MACURN(acc, x, y, n) __builtin_pulp_macuRN(x, y, acc, n, (1<<(n-1)))
#define __MACHHSN(acc, x, y, n) __builtin_pulp_machhsN(x, y, acc, n)
#define __MACHHUN(acc, x, y, n) __builtin_pulp_machhuN(x, y, acc, n)
#define __MACHHSRN(acc, x, y, n) __builtin_pulp_machhsN(x, y, acc, n, (1<<(n-1)))
#define __MACHHURN(acc, x, y, n) __builtin_pulp_machhuN(x, y, acc, n, (1<<(n-1)))
/*! @brief Multiplications */
#define __MULS(x, y) __builtin_pulp_muls(x, y)
#define __MULU(x, y) __builtin_pulp_mulu(x, y)
#define __MULHHS(x, y) __builtin_pulp_mulhhs(x, y)
#define __MULHHU(x, y) __builtin_pulp_mulhhu(x, y)
#define __MULSN(x, y, n) __builtin_pulp_mulsN(x, y, n)
#define __MULSRN(x, y, n) __builtin_pulp_mulsRN(x, y, n, (1<<(n-1)))
#define __MULUN(x, y, n) __builtin_pulp_muluN(x, y, n)
#define __MULURN(x, y, n) __builtin_pulp_muluRN(x, y, n, (1<<(n-1)))
#define __MULHHSN(x, y, n) __builtin_pulp_mulhhsN(x, y, n)
#define __MULHHSRN(x, y, n) __builtin_pulp_mulhhsRN(x, y, n, (1<<(n-1)))
#define __MULHHUN(x, y, n) __builtin_pulp_mulhhuN(x, y, n)
#define __MULHHURN(x, y, n) __builtin_pulp_mulhhuRN(x, y, n, (1<<(n-1)))
/*! @brief Vectorial product and sum of products */
#define __DOTP2(x, y) __builtin_pulp_dotsp2(x, y)
#define __DOTPU2(x, y) __builtin_pulp_dotup2(x, y)
#define __DOTPUS2(x, y) __builtin_pulp_dotusp2(x, y)
#define __SUM_DOTP2(x, y, z) __builtin_pulp_sdotsp2(x, y, z)
#define __SUM_DOTPU2(x, y, z) __builtin_pulp_sdotup2(x, y, z)
#define __SUM_DOTPUS2(x, y, z) __builtin_pulp_sdotusp2(x, y, z)
#define __DOTP4(x, y) __builtin_pulp_dotsp4(x, y)
#define __DOTPU4(x, y) __builtin_pulp_dotup4(x, y)
#define __DOTPUS4(x, y) __builtin_pulp_dotusp4(x, y)
#define __SUM_DOTP4(x, y, z) __builtin_pulp_sdotsp4(x, y, z)
#define __SUM_DOTPU4(x, y, z) __builtin_pulp_sdotup4(x, y, z)
#define __SUM_DOTPUS4(x, y, z) __builtin_pulp_sdotusp4(x, y, z)
/*! @brief Complex Multiplication, Q15x15 into Q15, with optional post scaling by 1 or 2 */
#define __CPLX_MULS(x, y) __builtin_pulp_cplxmuls(x, y)
#define __CPLX_MULS_DIV2(x, y) __builtin_pulp_cplxmulsdiv2(x, y)
#define __CPLX_MULS_DIV4(x, y) __builtin_pulp_cplxmulsdiv4(x, y)
/*! @brief Complex conjugate */
#define __CPLX_CONJ(x) __builtin_pulp_cplx_conj(x)
/*! @brief Complex rotation by -pi/2 */
#define __CPLX_MJ(x) __builtin_pulp_cplxmjrot2(x)
/*! @brief Complex substration, result rotated by -pi/2 */
#define __SUB2_ROTMJ(x, y) __builtin_pulp_sub2rotmj(x, y)
/*! @brief Complex addition with post scaling by 1 or 2 */
#define __ADD2_DIV2(x, y) __builtin_pulp_add2div2(x, y)
#define __ADD2_DIV4(x, y) __builtin_pulp_add2div4(x, y)
/*! @brief Complex subtraction with post scaling by 1 or 2 */
#define __SUB2_DIV2(x, y) __builtin_pulp_sub2div2(x, y)
#define __SUB2_DIV4(x, y) __builtin_pulp_sub2div4(x, y)
/*! @brief Viterbi Max and Viterbi Select, pair of Q15 */
#define __VIT_MAX(x, y) __builtin_pulp_vitmax2(x, y)
#define __VIT_SEL(x, y) __builtin_pulp_vitsel2(x, y)
/*! @brief Position of the most significant bit of x */
#define __FL1(x) __builtin_pulp_fl1(x)
/*! @brief Number of sign bits */
#define __CLB(x) __builtin_pulp_clb(x)
/*! @brief Bit Extraction */
#define __BIT_EXTRACT(src, size, off) __builtin_pulp_bextract(src, size, off)
#define __BIT_EXTRACTU(src, size, off) __builtin_pulp_bextractu(src, size, off)
#define __BIT_EXTRACT_R(src, size, off) __builtin_pulp_bextract_r(src, __ExtInsMaskFast(size, off))
#define __BIT_EXTRACTU_R(src, size, off) __builtin_pulp_bextractu_r(src, __ExtInsMaskFast(size, off))
#define __BIT_EXTRACT_R_SAFE(src, size, off) __builtin_pulp_bextract_r(src, __ExtInsMaskSafe(size, off))
#define __BIT_EXTRACTU_R_SAFE(src, size, off) __builtin_pulp_bextractu_r(src, __ExtInsMaskSafe(size, off))
/*! @brief Bit insertion */
#define __BIT_INSERT(dst, src, size, off) __builtin_pulp_binsert(dst, ~(((1<<size)-1)<<off), src, (((1<<size)-1)<<off), off)
#define __BIT_INSERT_R(dst, src, size, off) __builtin_pulp_binsert_r(dst, src, __ExtInsMaskFast(size, off))
#define __BIT_INSERT_R_SAFE(dst, src, size, off) __builtin_pulp_binsert_r(dst, src, __ExtInsMaskSafe(size, off))
/*! @brief 1 bit rotation to the right, 32 bits input */
#define __ROTR(x) __builtin_pulp_rotr(x)
/*! @brief Add with normalization and rounding */
#define __ADD_ROUND_NORM(x, y, scale) __builtin_pulp_addRN(x, y, scale, (1<<(scale-1)))
#define __ADD_ROUND_NORM_REG(x, y, scale) __builtin_pulp_addRN_r(x, y, scale)
#define __ADD_ROUND_NORMU(x, y, scale) __builtin_pulp_adduRN(x, y, scale, (1<<(scale-1)))
#define __ADD_ROUND_NORMU_REG(x, y, scale) __builtin_pulp_adduRN_r(x, y, scale)
/*! @brief Normalization and rounding */
#define __ROUND_NORM(x, scale) __builtin_pulp_addRN(x, 0, scale, (1<<(scale-1)))
#define __ROUND_NORM_REG(x, scale) __builtin_pulp_addRN_r(x, 0, scale)
#define __ROUND_NORMU(x, scale) __builtin_pulp_adduRN(x, 0, scale, (1<<(scale-1)))
#define __ROUND_NORMU_REG(x, scale) __builtin_pulp_adduRN_r(x, 0, scale)
/*@} end of group PULP_BUILTIN_MARCO */
/**
\ingroup PULP_VECTOR_TYPE
@{
*/
typedef signed short v2s __attribute__((vector_size (4)));
typedef unsigned short v2u __attribute__((vector_size (4)));
typedef signed char v4s __attribute__((vector_size (4)));
typedef unsigned char v4u __attribute__((vector_size (4)));
typedef signed char v4qi __attribute__((vector_size (4)));
typedef unsigned char v4qu __attribute__((vector_size (4)));
typedef signed short v2hi __attribute__((vector_size (4)));
typedef unsigned short v2hu __attribute__((vector_size (4)));
/*@} end of group PULP_VECTOR_TYPE */
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */

97
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pulp_io.h Normal file
View File

@@ -0,0 +1,97 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
/* Description: Register I/O access
*/
#ifndef __PULP_IO_H
#define __PULP_IO_H
#include <stdint.h>
/* generic I/O write */
static inline void writeb(uint8_t val, uintptr_t addr)
{
asm volatile("sb %0, 0(%1)"
:
: "r"(val), "r"((volatile uint8_t *)addr));
}
static inline void writeh(uint16_t val, uintptr_t addr)
{
asm volatile("sh %0, 0(%1)"
:
: "r"(val), "r"((volatile uint16_t *)addr));
}
static inline void writew(uint32_t val, uintptr_t addr)
{
asm volatile("sw %0, 0(%1)"
:
: "r"(val), "r"((volatile uint32_t *)addr));
}
static inline void writed(uint64_t val, uintptr_t addr)
{
asm volatile("sd %0, 0(%1)"
:
: "r"(val), "r"((volatile uint64_t *)addr));
}
/* generic I/O read */
static inline uint8_t readb(const uintptr_t addr)
{
uint8_t val;
asm volatile("lb %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint8_t *)addr));
return val;
}
static inline uint16_t readh(const uintptr_t addr)
{
uint16_t val;
asm volatile("lh %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint16_t *)addr));
return val;
}
static inline uint32_t readw(const uintptr_t addr)
{
uint32_t val;
asm volatile("lw %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint32_t *)addr));
return val;
}
static inline uint64_t readd(const uintptr_t addr)
{
uint64_t val;
asm volatile("ld %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint64_t *)addr));
return val;
}
#endif

63
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_core-v-mcu_metal.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef __SYSTEM_PULPISSIMO_RI5CY_METAL_H
#define __SYSTEM_PULPISSIMO_RI5CY_METAL_H
#include <stdint.h>
#include <stdbool.h>
//#include "FreeRTOSConfig.h"
/* PULPissimo defs */
#define PULPISSIMO
#define ARCHI_FPGA_FREQUENCY 5000000
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
/* hardware modules */
#define ARCHI_NUM_TIMER 1
#define ARCHI_NUM_FLL 2
/* TODO: clean up those macros */
#define ARCHI_FPGA_FREQUENCY 5000000
#define ARCHI_REF_CLOCK_LOG2 15
#define ARCHI_REF_CLOCK (1 << ARCHI_REF_CLOCK_LOG2)
#define ARCHI_NB_FLL 2
#define RT_FREQ_NB_DOMAIN 2
#define __RT_FLL_CL 2
#define __RT_FLL_PERIPH 1
#define __RT_FLL_FC 0
#define __RT_FREQ_DOMAIN_FC 0
#define __RT_FREQ_DOMAIN_CL 2
#define __RT_FREQ_DOMAIN_PERIPH 1
#define RT_FREQ_NB_DOMAIN 2
extern volatile uint32_t system_core_clock;
void pulp_sys_init (void);
void system_core_clock_update (void);
#endif /* __SYSTEM_PULPISSIMO_RI5CY_H */

20
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_metal.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include "system_core-v-mcu_metal.h"

20
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_pmsis.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
*/
#include "system_pulpissimo_ri5cy.h"

462
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c Normal file
View File

@@ -0,0 +1,462 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun Remove FreeRTOS related code and add RT-Thread code
*/
#include <stdint.h>
#include <assert.h>
#include <core_pulp_cluster.h>
#include <core-v-mcu-config.h>
//#include "pmsis/implem/drivers/fc_event/fc_event.h"
#include "hal_fc_event.h"
/* TODO: weird include */
#include "core-v-mcu-properties.h"
#include "hal_irq.h"
#include "hal_soc_eu.h"
#include "hal_apb_soc_ctrl_reg_defs.h"
#include "udma_uart_driver.h"
#include "udma_i2cm_driver.h"
#include "udma_qspi_driver.h"
#include "hal_apb_i2cs.h"
#include "hal_udma_ctrl_reg_defs.h"
#include "hal_udma_uart_reg_defs.h"
#include <rthw.h>
#include <rtthread.h>
#include "rtconfig.h"
#define FOR_SIMULATION_TESTING 0
#if (FOR_SIMULATION_TESTING == 1)
typedef struct
{
volatile uint32_t *rx_saddr; // 0x00
volatile uint32_t rx_size; // 0x04
volatile uint32_t rx_cfg; // 0x08
volatile uint32_t rx_initcfg; // 0x0C
volatile uint32_t *tx_saddr; // 0x10
volatile uint32_t tx_size; // 0x14
volatile uint32_t tx_cfg; // 0x18
volatile uint32_t tx_initcfg; // 0x1C
volatile uint32_t cfg_glob; // 0x20
volatile uint32_t cfg_ll; // 0x24
volatile uint32_t cfg_ur; // 0x28
volatile uint32_t cfg_size; // 0x2C
volatile uint32_t cfg_filter; // 0x30
volatile uint32_t vsync_pol; // 0x34
} camera_struct_t;
void forSimulationTesting(void);
#endif
//FLASH_DEVICE_OBJECT gFlashDeviceObject[N_QSPIM];
uint8_t gQSPIFlashPresentFlg[N_QSPIM] = {0};
uint8_t gMicronFlashDetectedFlg[N_QSPIM] = {0};
/* test some assumptions we make about compiler settings */
static_assert(sizeof(uintptr_t) == 4,
"uintptr_t is not 4 bytes. Make sure you are using -mabi=ilp32*");
/* Allocate heap to special section. Note that we have no references in the
* whole program to this variable (since its just here to allocate space in the
* section for our heap), so when using LTO it will be removed. We force it to
* stay with the "used" attribute
*/
__attribute__((section(".heap"), used)) uint8_t ucHeap[configTOTAL_HEAP_SIZE];
/* Inform linker script about .heap section size. Note: GNU ld seems to
* internally represent integers with the bfd_vma type, that is a type that can
* contain memory addresses (typdefd to some int type depending on the
* architecture). uint32_t seems to me the most fitting candidate for rv32.
*/
uint32_t __heap_size = configTOTAL_HEAP_SIZE;
volatile uint32_t system_core_clock = 5000000u;
/* interrupt handling */
void timer_irq_handler(uint32_t mcause);
void undefined_handler(uint32_t mcause);
extern void fc_soc_event_handler1(uint32_t mcause);
void (*isr_table[32])(uint32_t);
void flash_readid(const struct cli_cmd_entry *pEntry);
/**
* Board init code. Always call this before anything else.
*/
uint8_t setFLLFrequencyInIntegerMode(uint8_t aFLLNum, uint8_t aRefFreqInMHz, uint16_t aMultiplier, uint8_t aDivideRatio_R_Prescale, uint8_t aPS0_L1, uint8_t aPS0_L2)
{
uint8_t lSts = 0;
volatile uint32_t *lPLLStartAddress = (uint32_t *)NULL;
uint32_t lCounter = 0;
uint32_t lCfgVal = 0;
uint8_t lPS0_L1 = aPS0_L1 & 0x03;
uint8_t lPS0_L2 = aPS0_L2 & 0xFF;
if (aFLLNum == 0)
lPLLStartAddress = (uint32_t *)FLL1_START_ADDR;
else if (aFLLNum == 1)
lPLLStartAddress = (uint32_t *)FLL2_START_ADDR;
else if (aFLLNum == 2)
lPLLStartAddress = (uint32_t *)FLL3_START_ADDR;
else
lPLLStartAddress = (uint32_t *)NULL;
if (lPLLStartAddress != NULL)
{
if ((aRefFreqInMHz >= 5) && (aRefFreqInMHz <= 500))
{
if ((aMultiplier > 0) && (aMultiplier < 2048))
{
if (aDivideRatio_R_Prescale < 16)
{
*lPLLStartAddress |= (1 << 19); // Bypass on;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress &= ~(1 << 2); // Reset low;
*lPLLStartAddress &= ~(1 << 18); // PS0_EN is set to low
*lPLLStartAddress |= (lPS0_L1 << 0); // PS0_L1 0 which gives L01 = 1
*lPLLStartAddress |= (lPS0_L2 << 4); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
*lPLLStartAddress |= (0 << 12); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
// FLL1 Config 1 register not configuring PS1
*(lPLLStartAddress + 1) = 0;
// FLL1 Config 2 register
lCfgVal = 0;
lCfgVal |= (aMultiplier << 4); // MULT_INT 0x28 = 40 (40*10 = 400MHz) Multiplier cannot hold 0
lCfgVal |= (1 << 27); // INTEGER_MODE is enabled
lCfgVal |= (aDivideRatio_R_Prescale << 28); // PRESCALE value (Divide Ratio R = 1)
*(lPLLStartAddress + 2) = lCfgVal;
// FLL1 Config 3 register not configuring SSC
*(lPLLStartAddress + 3) = 0;
// FLL1 Config 4 register
*(lPLLStartAddress + 4) = 0x64;
// FLL1 Config 5 register
*(lPLLStartAddress + 5) = 0x269;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress |= (1 << 18); // PS0_EN;
// lCounter = 0;
while ((*(lPLLStartAddress + 4) & 0x80000000) == 0) // Wait for lock detect to go high
{
lCounter++;
if (lCounter >= 0x00010000)
{
lSts = 5; // Unable to achieve lock
lCounter = 0;
break;
}
}
if (lSts == 0)
*(lPLLStartAddress) &= ~(1 << 19); // Bypass off;
}
else
{
lSts = 1; // aDivideRatio_R_Prescale
}
}
else
{
lSts = 2; // Invalid aMultiplier
}
}
else
{
lSts = 3; // Invalid reference freq
}
}
else
{
lSts = 4; // Invalid PLL number
}
return lSts;
}
int handler_count[32];
uint32_t gSpecialHandlingIRQCnt = 0;
uint8_t gQSPIIdNum = 0;
void system_init(void)
{
uint32_t lFlashID = 0;
SocCtrl_t *soc = APB_SOC_CTRL_ADDR;
soc->soft_reset = 1;
uint32_t val = 0;
uint8_t i = 0;
timer_irq_disable();
uint32_t *lFFL1StartAddress = (uint32_t *)FLL1_START_ADDR;
uint32_t *lFFL2StartAddress = (uint32_t *)FLL2_START_ADDR;
uint32_t *lFFL3StartAddress = (uint32_t *)FLL3_START_ADDR;
setFLLFrequencyInIntegerMode(0, 10, 40, 1, 0, 1); // 400
setFLLFrequencyInIntegerMode(1, 10, 40, 1, 0, 2); // 200
setFLLFrequencyInIntegerMode(2, 10, 40, 1, 0, 4); // 100
/* Hook up isr table. This table is temporary until we figure out how to do proper vectored interrupts. */
for (int i = 0; i < 32; i++)
{
isr_table[i] = undefined_handler;
handler_count[i] = 0;
}
isr_table[0x7] = timer_irq_handler;
isr_table[0xb] = (void (*)(uint32_t))fc_soc_event_handler1; // 11 for cv32
/* mtvec is set in crt0.S */
/* deactivate all soc events as they are enabled by default */
pulp_soc_eu_event_init();
/* Setup soc events handler. */
// pi_fc_event_handler_init(FC_SOC_EVENT);
pi_fc_event_handler_init(11);
/* TODO: I$ enable*/
/* enable core level interrupt (mie) */
//irq_clint_enable();
val = csr_read(CSR_MIE);
/* TODO: enable uart */
for (uint8_t id = 0; id != N_UART; id++)
{
udma_uart_open(id, 115200);
}
#if 0
for (uint8_t id = 0; id != N_I2CM; id++)
{
udma_i2cm_open(id, 400000); // 200000
}
for (i = 0; i < N_QSPIM; i++)
{
setQspimPinMux(i);
udma_qspim_open(i, 2500000);
udma_qspim_control((uint8_t)i, (udma_qspim_control_type_t)kQSPImReset, (void *)0);
lFlashID = udma_flash_readid(i, 0);
if ((lFlashID == 0xFFFFFFFF) || (lFlashID == 0))
{
gQSPIFlashPresentFlg[i] = 0;
}
else
{
gQSPIFlashPresentFlg[i] = 1;
if ((lFlashID & 0xFF) == 0x20)
{
gMicronFlashDetectedFlg[i] = 1;
gQSPIIdNum = 0;
}
else
gMicronFlashDetectedFlg[i] = 0;
}
restoreQspimPinMux(i);
}
#endif
#if (FOR_SIMULATION_TESTING == 1)
forSimulationTesting();
#endif
// hal_set_apb_i2cs_slave_on_off(1);
// if (hal_get_apb_i2cs_slave_address() != MY_I2C_SLAVE_ADDRESS)
// hal_set_apb_i2cs_slave_address(MY_I2C_SLAVE_ADDRESS);
}
void system_core_clock_update(void)
{
system_core_clock = pi_fll_get_frequency(FLL_SOC, 0);
}
void system_core_clock_get(void)
{
system_core_clock_update();
return;
}
uint16_t Writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->status_b.tx_busy) { // ToDo: Why is this necessary? Thought the semaphore should have protected
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1; //enable the transfer
return 0;
}
void timer_irq_handler(uint32_t mcause)
{
#warning requires critical section if interrupt nesting is used.
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
void vSystemIrqHandler(uint32_t mcause)
{
isr_table[mcause & 0x1f](mcause & 0x1f);
}
void undefined_handler(uint32_t mcause)
{
uint32_t RegReadVal = 0;
#ifdef __PULP_USE_LIBC
abort();
#else
if ((mcause == 18) || (mcause == 19) || (mcause == 31))
{
gSpecialHandlingIRQCnt++;
if (gSpecialHandlingIRQCnt >= 20)
{
RegReadVal = csr_read(CSR_MIE);
if ((RegReadVal & BIT(mcause)) != 0) // Check if the event interrupt mask is open.
{
// close the event interrupt mask.
csr_read_clear(CSR_MIE, BIT(mcause));
}
}
}
else
{
handler_count[mcause]++;
}
#endif
}
void rt_systick_config(void)
{
extern int timer_irq_init(uint32_t ticks);
timer_irq_init(ARCHI_FPGA_FREQUENCY / RT_TICK_PER_SECOND);
}
#if (FOR_SIMULATION_TESTING == 1)
uint8_t gCamDataBuf[1024];
void udma_cam_open(uint8_t cam_id)
{
int i = 0;
volatile UdmaCtrl_t *pudma_ctrl = (UdmaCtrl_t *)UDMA_CH_ADDR_CTRL;
/* Enable reset and enable uart clock */
pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
// psdio_regs->clk_div_b.clk_div = 5;
// psdio_regs->clk_div_b.valid = 1;
hal_setpinmux(21, 0); // cam0_vsync
hal_setpinmux(22, 0); // cam0_hsync
hal_setpinmux(25, 0); // cam0_clk
for (i = 0; i < 8; i++)
{
// set pin muxes to cam functionality
hal_setpinmux(29 + i, 0);
}
return;
}
void cam_interface_init(uint16_t x, uint16_t y, uint8_t aBitMode)
{
camera_struct_t *camera;
uint16_t lXCoordOfUpperRightCorner = 0; // X coordinate of upper right corner of slice
uint16_t lYCoordOfUpperRightCorner = 0; // Y coordinate of upper right corner of slice
lXCoordOfUpperRightCorner = x + 3;
lYCoordOfUpperRightCorner = y + 3;
// camera = (camera_struct_t *)0x1A102300; // Peripheral 5?
camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
camera->cfg_ll = 0 << 16 | 0;
camera->cfg_ur = ((lYCoordOfUpperRightCorner << 16) | lXCoordOfUpperRightCorner);
// camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
// camera->cfg_size = 324;
camera->cfg_size = y + 4;
camera->vsync_pol = 1;
if (aBitMode == 1)
{
camera->cfg_glob |= (1 << 17);
}
else if (aBitMode == 4)
{
camera->cfg_glob |= (1 << 16);
}
else if (aBitMode == 8)
{
camera->cfg_glob |= (0 << 0);
}
camera->cfg_glob |= (0 << 0) | // framedrop disabled
(000000 << 1) | // number of frames to drop
(0 << 7) | // Frame slice disabled
(004 << 8) | // Format binary 100 = ByPass little endian
(0000 << 11); // Shift value ignored in bypass
}
uint8_t cam_grab_frame(int x, int y, uint8_t *pparam)
{
uint32_t lCounter = 0;
uint8_t lStatus = 0;
uint16_t lX = x + 4;
uint16_t lY = y + 4;
camera_struct_t *camera;
// camera = (camera_struct_t *)0x1A102300; // Peripheral 5?
camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
camera->rx_saddr = pparam;
camera->rx_size = (lX * lY);
camera->rx_cfg = 0x12; // start 16-bit transfers
camera->cfg_glob |= camera->cfg_glob | (1 << 31); // enable 1 == go
lCounter = 0;
while (camera->rx_size != 0)
{
lCounter++;
if (lCounter >= 0x00100000)
{
lStatus = 3; // Time out
break;
}
}
// configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
camera->cfg_glob = camera->cfg_glob & (0x7fffffff); // enable 1 == go
// configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
return lStatus;
}
void forSimulationTesting(void)
{
udma_cam_open(0);
cam_interface_init(240, 320, 8);
cam_grab_frame(240, 320, gCamDataBuf);
}
#endif

93
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/crt0.S Normal file
View File

@@ -0,0 +1,93 @@
/*
* Copyright 2020 ETH Zurich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause
*/
/* Copyright (c) 2017 SiFive Inc. All rights reserved.
* Copyright (c) 2019 ETH Zürich and University of Bologna
* This copyrighted material is made available to anyone wishing to use,
* modify, copy, or redistribute it subject to the terms and conditions
* of the FreeBSD License. This program is distributed in the hope that
* it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
* including the implied warranties of MERCHANTABILITY or FITNESS FOR
* A PARTICULAR PURPOSE. A copy of this license is available at
* http://www.opensource.org/licenses.
*/
/* entry point */
.section .text.start
.global _start
.type _start, @function
_start:
/* initialize global pointer */
.option push
.option norelax
1: auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
#if defined(ARCHI_HAS_CLUSTER)
/* TODO */
#endif
/* initialize stack pointer */
la sp, __stack_top
/*or a0, a0, 0*/
and a0, a0, 0
csrw mie, a0 // disable interrupts
csrr a0, mie
/* set vector table address */
la a0, __vector_start
or a0, a0, 1 /* enable vectored mode (hardcoded anyway for CV32E40P) */
csrw mtvec, a0
/* clear the bss segment */
la t0, __bss_start
la t1, __bss_end
/* TODO: optionally compile this out to speed simulation */
1:
sw zero,0(t0)
addi t0, t0, 4
bltu t0, t1, 1b
/* new-style constructors and destructors */
#if defined(__PULP_USE_LIBC)
la a0, __libc_fini_array
call atexit
call __libc_init_array
#endif
/* call main */
lw a0, 0(sp) /* a0 = argc */
addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
li a2, 0 /* a2 = envp = NULL */
call entry
tail exit
.size _start, .-_start
.global _init
.type _init, @function
.global _fini
.type _fini, @function
_init:
_fini:
/* These don't have to do anything since we use init_array/fini_array. Prevent
missing symbol error */
ret
.size _init, .-_init
.size _fini, .-_fini

129
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/vectors.S Normal file
View File

@@ -0,0 +1,129 @@
/*
* Copyright 2019 ETH Zürich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
* Author: Robert Balas (balasr@iis.ee.ethz.ch)
* Change Logs:
* Date Author Notes
* 2022-12-08 WangShun Remove FreeRTOS related code and add RT-Thread code
*/
.extern IRQ_Handler
#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
.extern freertos_risc_v_ctxt_handler
#endif
#ifdef __HACK_FIRMWARE_OPT1 /* TODO: properly do this with weak symbols */
.extern TIMER1_IRQ_handler
#endif
.extern fc_soc_event_handler
.section .vectors, "ax"
.option norvc
vector_table:
j IRQ_Handler // irq0
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // irq3
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler //ctxt_handler // irq 7 mtime or timer
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ_Handler
j IRQ_Handler // irq 11 Machine (event Fifo)
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ16
j IRQ_Handler // IRQ17
j IRQ_Handler // IRQ18
j IRQ_Handler // IRQ19
j IRQ_Handler // IRQ20
j IRQ_Handler // IRQ21
j IRQ_Handler // IRQ22
j IRQ_Handler // IRQ23
j IRQ_Handler // IRQ24
j IRQ_Handler // IRQ25
j IRQ_Handler // IRQ26
j IRQ_Handler // IRQ27
j IRQ_Handler // IRQ28
j IRQ_Handler // IRQ29
j IRQ_Handler // IRQ30
j IRQ_Handler // IRQ30
/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
new vector table (which is at mtvec) */
/* .section .legacy_irq, "ax" */
/* j vector_table */
/* j __no_irq_handler */
/* j __no_irq_handler */
/* j __no_irq_handler */
.section .text.vecs
/* exception handling */
__no_irq_handler:
la a0, no_exception_handler_msg
jal ra, puts
j __no_irq_handler
sw_irq_handler:
csrr t0, mcause
slli t0, t0, 1 /* shift off the high bit */
srli t0, t0, 1
li t1, 2
beq t0, t1, handle_illegal_insn
li t1, 11
beq t0, t1, handle_ecall
li t1, 3
beq t0, t1, handle_ebreak
j handle_unknown
handle_ecall:
la a0, ecall_msg
jal ra, puts
j end_handler
handle_ebreak:
la a0, ebreak_msg
jal ra, puts
j end_handler
handle_illegal_insn:
la a0, illegal_insn_msg
jal ra, puts
j end_handler
handle_unknown:
la a0, unknown_msg
jal ra, puts
j end_handler
end_handler:
csrr a0, mepc
addi a0, a0, 4
csrw mepc, a0
mret
.section .rodata
illegal_insn_msg:
.string "illegal instruction exception handler entered\n"
ecall_msg:
.string "ecall exception handler entered\n"
ebreak_msg:
.string "ebreak exception handler entered\n"
unknown_msg:
.string "unknown exception handler entered\n"
no_exception_handler_msg:
.string "no exception handler installed\n"

805
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/adv_timer_unit_reg_defs.h Normal file
View File

File diff suppressed because it is too large Load Diff

1454
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/efpga_template_reg_defs.h Normal file
View File

File diff suppressed because it is too large Load Diff

299
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_event_cntrl_reg_defs.h Normal file
View File

@@ -0,0 +1,299 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __APB_EVENT_CNTRL_H_
#define __APB_EVENT_CNTRL_H_
//---------------------------------//
//
// Module: APB_EVENT_CNTRL
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t apb_events;
struct {
__IO uint32_t apb_event : 16;
} apb_events_b;
};
// Offset = 0x0004
union {
__IO uint32_t event_mask0;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask0_b;
};
// Offset = 0x0008
union {
__IO uint32_t event_mask1;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask1_b;
};
// Offset = 0x000c
union {
__IO uint32_t event_mask2;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask2_b;
};
// Offset = 0x0010
union {
__IO uint32_t event_mask3;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask3_b;
};
// Offset = 0x0014
union {
__IO uint32_t event_mask4;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask4_b;
};
// Offset = 0x0018
union {
__IO uint32_t event_mask5;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask5_b;
};
// Offset = 0x001c
union {
__IO uint32_t event_mask6;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask6_b;
};
// Offset = 0x0020
union {
__IO uint32_t event_mask7;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_mask7_b;
};
__I uint32_t unused0[16];
// Offset = 0x0064
union {
__IO uint32_t event_err0;
struct {
__IO uint32_t : 30;
__IO uint32_t event_err : 2;
} event_err0_b;
};
// Offset = 0x0068
union {
__IO uint32_t event_err1;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err1_b;
};
// Offset = 0x006c
union {
__IO uint32_t event_err2;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err2_b;
};
// Offset = 0x0070
union {
__IO uint32_t event_err3;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err3_b;
};
// Offset = 0x0074
union {
__IO uint32_t event_err4;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err4_b;
};
// Offset = 0x0078
union {
__IO uint32_t event_err5;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err5_b;
};
// Offset = 0x007c
union {
__IO uint32_t event_err6;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err6_b;
};
// Offset = 0x0080
union {
__IO uint32_t event_err7;
struct {
__IO uint32_t : 30;
__IO uint32_t event_enable : 2;
} event_err7_b;
};
// Offset = 0x0084
union {
__IO uint32_t timer_lo_event;
struct {
__IO uint32_t event : 8;
} timer_lo_event_b;
};
// Offset = 0x0088
union {
__IO uint32_t timer_hi_event;
struct {
__IO uint32_t event : 8;
} timer_hi_event_b;
};
__I uint32_t unused1[1];
// Offset = 0x0090
union {
__IO uint32_t event_fifo;
struct {
__IO uint32_t event_id : 8;
} event_fifo_b;
};
} ApbEventCntrl_t;
#define REG_APB_EVENTS 0x000
#define REG_APB_EVENTS_apb_event_LSB 0
#define REG_APB_EVENTS_apb_event_MASK 0xffff
#define REG_EVENT_MASK0 0x004
#define REG_EVENT_MASK0_event_enable_LSB 30
#define REG_EVENT_MASK0_event_enable_MASK 0x3
#define REG_EVENT_MASK1 0x008
#define REG_EVENT_MASK1_event_enable_LSB 30
#define REG_EVENT_MASK1_event_enable_MASK 0x3
#define REG_EVENT_MASK2 0x00C
#define REG_EVENT_MASK2_event_enable_LSB 30
#define REG_EVENT_MASK2_event_enable_MASK 0x3
#define REG_EVENT_MASK3 0x010
#define REG_EVENT_MASK3_event_enable_LSB 30
#define REG_EVENT_MASK3_event_enable_MASK 0x3
#define REG_EVENT_MASK4 0x014
#define REG_EVENT_MASK4_event_enable_LSB 30
#define REG_EVENT_MASK4_event_enable_MASK 0x3
#define REG_EVENT_MASK5 0x018
#define REG_EVENT_MASK5_event_enable_LSB 30
#define REG_EVENT_MASK5_event_enable_MASK 0x3
#define REG_EVENT_MASK6 0x01C
#define REG_EVENT_MASK6_event_enable_LSB 30
#define REG_EVENT_MASK6_event_enable_MASK 0x3
#define REG_EVENT_MASK7 0x020
#define REG_EVENT_MASK7_event_enable_LSB 30
#define REG_EVENT_MASK7_event_enable_MASK 0x3
#define REG_EVENT_ERR0 0x064
#define REG_EVENT_ERR0_event_err_LSB 30
#define REG_EVENT_ERR0_event_err_MASK 0x3
#define REG_EVENT_ERR1 0x068
#define REG_EVENT_ERR1_event_enable_LSB 30
#define REG_EVENT_ERR1_event_enable_MASK 0x3
#define REG_EVENT_ERR2 0x06C
#define REG_EVENT_ERR2_event_enable_LSB 30
#define REG_EVENT_ERR2_event_enable_MASK 0x3
#define REG_EVENT_ERR3 0x070
#define REG_EVENT_ERR3_event_enable_LSB 30
#define REG_EVENT_ERR3_event_enable_MASK 0x3
#define REG_EVENT_ERR4 0x074
#define REG_EVENT_ERR4_event_enable_LSB 30
#define REG_EVENT_ERR4_event_enable_MASK 0x3
#define REG_EVENT_ERR5 0x078
#define REG_EVENT_ERR5_event_enable_LSB 30
#define REG_EVENT_ERR5_event_enable_MASK 0x3
#define REG_EVENT_ERR6 0x07C
#define REG_EVENT_ERR6_event_enable_LSB 30
#define REG_EVENT_ERR6_event_enable_MASK 0x3
#define REG_EVENT_ERR7 0x080
#define REG_EVENT_ERR7_event_enable_LSB 30
#define REG_EVENT_ERR7_event_enable_MASK 0x3
#define REG_TIMER_LO_EVENT 0x0084
#define REG_TIMER_LO_EVENT_event_LSB 0
#define REG_TIMER_LO_EVENT_event_MASK 0xff
#define REG_TIMER_HI_EVENT 0x0088
#define REG_TIMER_HI_EVENT_event_LSB 0
#define REG_TIMER_HI_EVENT_event_MASK 0xff
#define REG_EVENT_FIFO 0x090
#define REG_EVENT_FIFO_EVENT_ID_LSB 0
#define REG_EVENT_FIFO_EVENT_ID_MASK 0xff
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __APB_EVENT_CNTRL_H_

259
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_gpio_reg_defs.h Normal file
View File

@@ -0,0 +1,259 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __APB_GPIO_H_
#define __APB_GPIO_H_
//---------------------------------//
//
// Module: APB_GPIO
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t setgpio;
struct {
__IO uint32_t gpio_num : 8;
} setgpio_b;
};
// Offset = 0x0004
union {
__IO uint32_t clrgpio;
struct {
__IO uint32_t gpio_num : 8;
} clrgpio_b;
};
// Offset = 0x0008
union {
__IO uint32_t toggpio;
struct {
__IO uint32_t gpio_num : 8;
} toggpio_b;
};
__I uint32_t unused0[1];
// Offset = 0x0010
union {
__IO uint32_t pin0;
struct {
__IO uint32_t gpio_value : 32;
} pin0_b;
};
// Offset = 0x0014
union {
__IO uint32_t pin1;
struct {
__IO uint32_t gpio_value : 32;
} pin1_b;
};
// Offset = 0x0018
union {
__IO uint32_t pin2;
struct {
__IO uint32_t gpio_value : 32;
} pin2_b;
};
// Offset = 0x001c
union {
__IO uint32_t pin3;
struct {
__IO uint32_t gpio_value : 32;
} pin3_b;
};
// Offset = 0x0020
union {
__IO uint32_t out0;
struct {
__IO uint32_t value : 32;
} out0_b;
};
// Offset = 0x0024
union {
__IO uint32_t out1;
struct {
__IO uint32_t value : 32;
} out1_b;
};
// Offset = 0x0028
union {
__IO uint32_t out2;
struct {
__IO uint32_t value : 32;
} out2_b;
};
// Offset = 0x002c
union {
__IO uint32_t out3;
struct {
__IO uint32_t value : 32;
} out3_b;
};
// Offset = 0x0030
union {
__IO uint32_t setsel;
struct {
__IO uint32_t gpio_num : 8;
} setsel_b;
};
// Offset = 0x0034
union {
__IO uint32_t rdstat;
struct {
__IO uint32_t gpio_sel : 8;
__IO uint32_t output : 1;
__IO uint32_t : 3;
__IO uint32_t input : 1;
__IO uint32_t : 3;
__IO uint32_t inten : 1;
__IO uint32_t inttype : 3;
__IO uint32_t : 4;
__IO uint32_t mode : 2;
} rdstat_b;
};
// Offset = 0x0038
union {
__IO uint32_t setmode;
struct {
__IO uint32_t gpio_num : 8;
__IO uint32_t : 16;
__IO uint32_t mode : 2;
} setmode_b;
};
// Offset = 0x003c
union {
__IO uint32_t setint;
struct {
__IO uint32_t gpio_num : 8;
__IO uint32_t : 8;
__IO uint32_t intenable : 1;
__IO uint32_t inttype : 3;
} setint_b;
};
union {
__IO uint32_t intack;
struct {
__IO uint32_t gpio_num : 8;
__IO uint32_t : 24;
} intack_b;
};
} ApbGpio_t;
#define REG_SETGPIO 0x00
#define REG_SETGPIO_gpio_num_LSB 0
#define REG_SETGPIO_gpio_num_MASK 0xff
#define REG_CLRGPIO 0x04
#define REG_CLRGPIO_gpio_num_LSB 0
#define REG_CLRGPIO_gpio_num_MASK 0xff
#define REG_TOGGPIO 0x08
#define REG_TOGGPIO_gpio_num_LSB 0
#define REG_TOGGPIO_gpio_num_MASK 0xff
#define REG_PIN0 0x10
#define REG_PIN0_gpio_value_LSB 0
#define REG_PIN0_gpio_value_MASK 0xffffffff
#define REG_PIN1 0x14
#define REG_PIN1_gpio_value_LSB 0
#define REG_PIN1_gpio_value_MASK 0xffffffff
#define REG_PIN2 0x18
#define REG_PIN2_gpio_value_LSB 0
#define REG_PIN2_gpio_value_MASK 0xffffffff
#define REG_PIN3 0x1C
#define REG_PIN3_gpio_value_LSB 0
#define REG_PIN3_gpio_value_MASK 0xffffffff
#define REG_OUT0 0x20
#define REG_OUT0_value_LSB 0
#define REG_OUT0_value_MASK 0xffffffff
#define REG_OUT1 0x24
#define REG_OUT1_value_LSB 0
#define REG_OUT1_value_MASK 0xffffffff
#define REG_OUT2 0x28
#define REG_OUT2_value_LSB 0
#define REG_OUT2_value_MASK 0xffffffff
#define REG_OUT3 0x2C
#define REG_OUT3_value_LSB 0
#define REG_OUT3_value_MASK 0xffffffff
#define REG_SETSEL 0x30
#define REG_SETSEL_gpio_num_LSB 0
#define REG_SETSEL_gpio_num_MASK 0xff
#define REG_RDSTAT 0x34
#define REG_RDSTAT_mode_LSB 24
#define REG_RDSTAT_mode_MASK 0x3
#define REG_RDSTAT_INTTYPE_LSB 16
#define REG_RDSTAT_INTTYPE_MASK 0x7
#define REG_RDSTAT_INPUT_LSB 12
#define REG_RDSTAT_INPUT_MASK 0x1
#define REG_RDSTAT_OUTPUT_LSB 8
#define REG_RDSTAT_OUTPUT_MASK 0x1
#define REG_SETMODE 0x38
#define REG_SETMODE_mode_LSB 24
#define REG_SETMODE_mode_MASK 0x3
#define REG_SETMODE_gpio_num_LSB 0
#define REG_SETMODE_gpio_num_MASK 0xff
#define REG_SETINT 0x3C
#define REG_SETINT_INTTYPE_LSB 17
#define REG_SETINT_INTTYPE_MASK 0x7
#define REG_SETINT_INTENABLE_LSB 16
#define REG_SETINT_INTENABLE_MASK 0x1
#define REG_SETINT_gpio_num_LSB 0
#define REG_SETINT_gpio_num_MASK 0xff
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __APB_GPIO_H_

74
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __HAL_APB_I2CS_H__
#define __HAL_APB_I2CS_H__
#include "stdint.h"
#define MY_I2C_SLAVE_ADDRESS 0x62
#define MY_I2C_SLAVE_ADDRESS_7BIT (0x62 << 1)
#define I2C_MASTER_REG_DEV_ADDRESS 0x00
#define I2C_MASTER_REG_ENABLE 0x01
#define I2C_MASTER_REG_DEBOUNCE_LENGTH 0x02
#define I2C_MASTER_REG_SCL_DELAY_LENGTH 0x03
#define I2C_MASTER_REG_SDA_DELAY_LENGTH 0x04
#define I2C_MASTER_REG_MSG_I2C_APB 0x10
#define I2C_MASTER_REG_MSG_I2C_APB_STATUS 0x11
#define I2C_MASTER_REG_MSG_APB_I2C 0x12
#define I2C_MASTER_REG_MSG_APB_I2C_STATUS 0x13
#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_DATA_PORT 0x20
#define I2C_MASTER_REG_FIFO_I2C_APB_READ_DATA_PORT 0x21
#define I2C_MASTER_REG_FIFO_I2C_APB_FLUSH 0x22
#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_FLAGS 0x23
#define I2C_MASTER_REG_FIFO_I2C_APB_READ_FLAGS 0x24
#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_DATA_PORT 0x30
#define I2C_MASTER_REG_FIFO_APB_I2C_READ_DATA_PORT 0x31
#define I2C_MASTER_REG_FIFO_APB_I2C_FLUSH 0x32
#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_FLAGS 0x33
#define I2C_MASTER_REG_FIFO_APB_I2C_READ_FLAGS 0x34
#define I2C_MASTER_REG_INTERRUPT_STATUS 0x40
#define I2C_MASTER_REG_INTERRUPT_ENABLE 0x41
#define I2C_MASTER_REG_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT 0x42
#define I2C_MASTER_REG_INTERRUPT_APB_I2C_READ_FLAGS_SELECT 0x43
#define I2C_MASTER_REG_INTERRUPT_TO_APB_STATUS 0x50
#define I2C_MASTER_REG_INTERRUPT_TO_APB_ENABLE 0x51
#define I2C_MASTER_REG_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 0x52
#define I2C_MASTER_REG_INTERRUPT_I2C_APB_READ_FLAGS_SELECT 0x53
uint8_t hal_get_apb_i2cs_slave_address(void);
void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress);
uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus);
uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void);
void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData);
uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void);
uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void);
uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void);
uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void);
uint8_t hal_get_i2cs_msg_i2c_apb(void);
uint8_t hal_get_i2cs_msg_i2c_apb_status(void);
void hal_set_i2cs_msg_apb_i2c(uint8_t aData);
uint8_t hal_get_i2cs_msg_apb_i2c_status(void);
void hal_i2cs_fifo_i2c_apb_FIFO_flush(void);
void hal_i2cs_fifo_apb_i2c_FIFO_flush(void);
#endif // __HAL_APB_I2CS_H__

513
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs_reg_defs.h Normal file
View File

File diff suppressed because it is too large Load Diff

441
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_interrupt_cntrl_reg_defs.h Normal file
View File

@@ -0,0 +1,441 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __APB_INTERRUPT_CNTRL_H_
#define __APB_INTERRUPT_CNTRL_H_
//---------------------------------//
//
// Module: APB_INTERRUPT_CNTRL
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t reg_mask;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_mask_b;
};
// Offset = 0x0004
union {
__IO uint32_t reg_mask_set;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_mask_set_b;
};
// Offset = 0x0008
union {
__IO uint32_t reg_mask_clear;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_mask_clear_b;
};
// Offset = 0x000c
union {
__IO uint32_t reg_int;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_int_b;
};
// Offset = 0x0010
union {
__IO uint32_t reg_int_set;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_int_set_b;
};
// Offset = 0x0014
union {
__IO uint32_t reg_int_clear;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_int_clear_b;
};
// Offset = 0x0018
union {
__IO uint32_t reg_ack;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_ack_b;
};
// Offset = 0x001c
union {
__IO uint32_t reg_ack_set;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_ack_set_b;
};
// Offset = 0x0020
union {
__IO uint32_t reg_ack_clear;
struct {
__IO uint32_t reserved : 7;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t unused2 : 8;
__IO uint32_t timer_lo_event : 1;
__IO uint32_t timer_hi_event : 1;
__IO uint32_t gpio_event : 1;
__IO uint32_t adv_timer_evens : 4;
__IO uint32_t ref_change_event : 1;
__IO uint32_t unused1 : 5;
__IO uint32_t fc_err_events : 1;
__IO uint32_t fc_hp_events : 2;
} reg_ack_clear_b;
};
// Offset = 0x0024
union {
__IO uint32_t reg_fifo;
struct {
__IO uint32_t event_id : 8;
} reg_fifo_b;
};
} ApbInterruptCntrl_t;
#define REG_REG_MASK 0x000
#define REG_REG_MASK_fc_hp_events_LSB 30
#define REG_REG_MASK_fc_hp_events_MASK 0x3
#define REG_REG_MASK_fc_err_events_LSB 29
#define REG_REG_MASK_fc_err_events_MASK 0x1
#define REG_REG_MASK_unused1_LSB 24
#define REG_REG_MASK_unused1_MASK 0x1f
#define REG_REG_MASK_ref_change_event_LSB 23
#define REG_REG_MASK_ref_change_event_MASK 0x1
#define REG_REG_MASK_adv_timer_evens_LSB 19
#define REG_REG_MASK_adv_timer_evens_MASK 0xf
#define REG_REG_MASK_gpio_event_LSB 18
#define REG_REG_MASK_gpio_event_MASK 0x1
#define REG_REG_MASK_timer_hi_event_LSB 17
#define REG_REG_MASK_timer_hi_event_MASK 0x1
#define REG_REG_MASK_timer_lo_event_LSB 16
#define REG_REG_MASK_timer_lo_event_MASK 0x1
#define REG_REG_MASK_unused2_LSB 8
#define REG_REG_MASK_unused2_MASK 0xff
#define REG_REG_MASK_timer_lo_event_LSB 7
#define REG_REG_MASK_timer_lo_event_MASK 0x1
#define REG_REG_MASK_reserved_LSB 0
#define REG_REG_MASK_reserved_MASK 0x7f
#define REG_REG_MASK_SET 0x004
#define REG_REG_MASK_SET_fc_hp_events_LSB 30
#define REG_REG_MASK_SET_fc_hp_events_MASK 0x3
#define REG_REG_MASK_SET_fc_err_events_LSB 29
#define REG_REG_MASK_SET_fc_err_events_MASK 0x1
#define REG_REG_MASK_SET_unused1_LSB 24
#define REG_REG_MASK_SET_unused1_MASK 0x1f
#define REG_REG_MASK_SET_ref_change_event_LSB 23
#define REG_REG_MASK_SET_ref_change_event_MASK 0x1
#define REG_REG_MASK_SET_adv_timer_evens_LSB 19
#define REG_REG_MASK_SET_adv_timer_evens_MASK 0xf
#define REG_REG_MASK_SET_gpio_event_LSB 18
#define REG_REG_MASK_SET_gpio_event_MASK 0x1
#define REG_REG_MASK_SET_timer_hi_event_LSB 17
#define REG_REG_MASK_SET_timer_hi_event_MASK 0x1
#define REG_REG_MASK_SET_timer_lo_event_LSB 16
#define REG_REG_MASK_SET_timer_lo_event_MASK 0x1
#define REG_REG_MASK_SET_unused2_LSB 8
#define REG_REG_MASK_SET_unused2_MASK 0xff
#define REG_REG_MASK_SET_timer_lo_event_LSB 7
#define REG_REG_MASK_SET_timer_lo_event_MASK 0x1
#define REG_REG_MASK_SET_reserved_LSB 0
#define REG_REG_MASK_SET_reserved_MASK 0x7f
#define REG_REG_MASK_CLEAR 0x008
#define REG_REG_MASK_CLEAR_fc_hp_events_LSB 30
#define REG_REG_MASK_CLEAR_fc_hp_events_MASK 0x3
#define REG_REG_MASK_CLEAR_fc_err_events_LSB 29
#define REG_REG_MASK_CLEAR_fc_err_events_MASK 0x1
#define REG_REG_MASK_CLEAR_unused1_LSB 24
#define REG_REG_MASK_CLEAR_unused1_MASK 0x1f
#define REG_REG_MASK_CLEAR_ref_change_event_LSB 23
#define REG_REG_MASK_CLEAR_ref_change_event_MASK 0x1
#define REG_REG_MASK_CLEAR_adv_timer_evens_LSB 19
#define REG_REG_MASK_CLEAR_adv_timer_evens_MASK 0xf
#define REG_REG_MASK_CLEAR_gpio_event_LSB 18
#define REG_REG_MASK_CLEAR_gpio_event_MASK 0x1
#define REG_REG_MASK_CLEAR_timer_hi_event_LSB 17
#define REG_REG_MASK_CLEAR_timer_hi_event_MASK 0x1
#define REG_REG_MASK_CLEAR_timer_lo_event_LSB 16
#define REG_REG_MASK_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_MASK_CLEAR_unused2_LSB 8
#define REG_REG_MASK_CLEAR_unused2_MASK 0xff
#define REG_REG_MASK_CLEAR_timer_lo_event_LSB 7
#define REG_REG_MASK_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_MASK_CLEAR_reserved_LSB 0
#define REG_REG_MASK_CLEAR_reserved_MASK 0x7f
#define REG_REG_INT 0x00C
#define REG_REG_INT_fc_hp_events_LSB 30
#define REG_REG_INT_fc_hp_events_MASK 0x3
#define REG_REG_INT_fc_err_events_LSB 29
#define REG_REG_INT_fc_err_events_MASK 0x1
#define REG_REG_INT_unused1_LSB 24
#define REG_REG_INT_unused1_MASK 0x1f
#define REG_REG_INT_ref_change_event_LSB 23
#define REG_REG_INT_ref_change_event_MASK 0x1
#define REG_REG_INT_adv_timer_evens_LSB 19
#define REG_REG_INT_adv_timer_evens_MASK 0xf
#define REG_REG_INT_gpio_event_LSB 18
#define REG_REG_INT_gpio_event_MASK 0x1
#define REG_REG_INT_timer_hi_event_LSB 17
#define REG_REG_INT_timer_hi_event_MASK 0x1
#define REG_REG_INT_timer_lo_event_LSB 16
#define REG_REG_INT_timer_lo_event_MASK 0x1
#define REG_REG_INT_unused2_LSB 8
#define REG_REG_INT_unused2_MASK 0xff
#define REG_REG_INT_timer_lo_event_LSB 7
#define REG_REG_INT_timer_lo_event_MASK 0x1
#define REG_REG_INT_reserved_LSB 0
#define REG_REG_INT_reserved_MASK 0x7f
#define REG_REG_INT_SET 0x010
#define REG_REG_INT_SET_fc_hp_events_LSB 30
#define REG_REG_INT_SET_fc_hp_events_MASK 0x3
#define REG_REG_INT_SET_fc_err_events_LSB 29
#define REG_REG_INT_SET_fc_err_events_MASK 0x1
#define REG_REG_INT_SET_unused1_LSB 24
#define REG_REG_INT_SET_unused1_MASK 0x1f
#define REG_REG_INT_SET_ref_change_event_LSB 23
#define REG_REG_INT_SET_ref_change_event_MASK 0x1
#define REG_REG_INT_SET_adv_timer_evens_LSB 19
#define REG_REG_INT_SET_adv_timer_evens_MASK 0xf
#define REG_REG_INT_SET_gpio_event_LSB 18
#define REG_REG_INT_SET_gpio_event_MASK 0x1
#define REG_REG_INT_SET_timer_hi_event_LSB 17
#define REG_REG_INT_SET_timer_hi_event_MASK 0x1
#define REG_REG_INT_SET_timer_lo_event_LSB 16
#define REG_REG_INT_SET_timer_lo_event_MASK 0x1
#define REG_REG_INT_SET_unused2_LSB 8
#define REG_REG_INT_SET_unused2_MASK 0xff
#define REG_REG_INT_SET_timer_lo_event_LSB 7
#define REG_REG_INT_SET_timer_lo_event_MASK 0x1
#define REG_REG_INT_SET_reserved_LSB 0
#define REG_REG_INT_SET_reserved_MASK 0x7f
#define REG_REG_INT_CLEAR 0x014
#define REG_REG_INT_CLEAR_fc_hp_events_LSB 30
#define REG_REG_INT_CLEAR_fc_hp_events_MASK 0x3
#define REG_REG_INT_CLEAR_fc_err_events_LSB 29
#define REG_REG_INT_CLEAR_fc_err_events_MASK 0x1
#define REG_REG_INT_CLEAR_unused1_LSB 24
#define REG_REG_INT_CLEAR_unused1_MASK 0x1f
#define REG_REG_INT_CLEAR_ref_change_event_LSB 23
#define REG_REG_INT_CLEAR_ref_change_event_MASK 0x1
#define REG_REG_INT_CLEAR_adv_timer_evens_LSB 19
#define REG_REG_INT_CLEAR_adv_timer_evens_MASK 0xf
#define REG_REG_INT_CLEAR_gpio_event_LSB 18
#define REG_REG_INT_CLEAR_gpio_event_MASK 0x1
#define REG_REG_INT_CLEAR_timer_hi_event_LSB 17
#define REG_REG_INT_CLEAR_timer_hi_event_MASK 0x1
#define REG_REG_INT_CLEAR_timer_lo_event_LSB 16
#define REG_REG_INT_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_INT_CLEAR_unused2_LSB 8
#define REG_REG_INT_CLEAR_unused2_MASK 0xff
#define REG_REG_INT_CLEAR_timer_lo_event_LSB 7
#define REG_REG_INT_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_INT_CLEAR_reserved_LSB 0
#define REG_REG_INT_CLEAR_reserved_MASK 0x7f
#define REG_REG_ACK 0x018
#define REG_REG_ACK_fc_hp_events_LSB 30
#define REG_REG_ACK_fc_hp_events_MASK 0x3
#define REG_REG_ACK_fc_err_events_LSB 29
#define REG_REG_ACK_fc_err_events_MASK 0x1
#define REG_REG_ACK_unused1_LSB 24
#define REG_REG_ACK_unused1_MASK 0x1f
#define REG_REG_ACK_ref_change_event_LSB 23
#define REG_REG_ACK_ref_change_event_MASK 0x1
#define REG_REG_ACK_adv_timer_evens_LSB 19
#define REG_REG_ACK_adv_timer_evens_MASK 0xf
#define REG_REG_ACK_gpio_event_LSB 18
#define REG_REG_ACK_gpio_event_MASK 0x1
#define REG_REG_ACK_timer_hi_event_LSB 17
#define REG_REG_ACK_timer_hi_event_MASK 0x1
#define REG_REG_ACK_timer_lo_event_LSB 16
#define REG_REG_ACK_timer_lo_event_MASK 0x1
#define REG_REG_ACK_unused2_LSB 8
#define REG_REG_ACK_unused2_MASK 0xff
#define REG_REG_ACK_timer_lo_event_LSB 7
#define REG_REG_ACK_timer_lo_event_MASK 0x1
#define REG_REG_ACK_reserved_LSB 0
#define REG_REG_ACK_reserved_MASK 0x7f
#define REG_REG_ACK_SET 0x01C
#define REG_REG_ACK_SET_fc_hp_events_LSB 30
#define REG_REG_ACK_SET_fc_hp_events_MASK 0x3
#define REG_REG_ACK_SET_fc_err_events_LSB 29
#define REG_REG_ACK_SET_fc_err_events_MASK 0x1
#define REG_REG_ACK_SET_unused1_LSB 24
#define REG_REG_ACK_SET_unused1_MASK 0x1f
#define REG_REG_ACK_SET_ref_change_event_LSB 23
#define REG_REG_ACK_SET_ref_change_event_MASK 0x1
#define REG_REG_ACK_SET_adv_timer_evens_LSB 19
#define REG_REG_ACK_SET_adv_timer_evens_MASK 0xf
#define REG_REG_ACK_SET_gpio_event_LSB 18
#define REG_REG_ACK_SET_gpio_event_MASK 0x1
#define REG_REG_ACK_SET_timer_hi_event_LSB 17
#define REG_REG_ACK_SET_timer_hi_event_MASK 0x1
#define REG_REG_ACK_SET_timer_lo_event_LSB 16
#define REG_REG_ACK_SET_timer_lo_event_MASK 0x1
#define REG_REG_ACK_SET_unused2_LSB 8
#define REG_REG_ACK_SET_unused2_MASK 0xff
#define REG_REG_ACK_SET_timer_lo_event_LSB 7
#define REG_REG_ACK_SET_timer_lo_event_MASK 0x1
#define REG_REG_ACK_SET_reserved_LSB 0
#define REG_REG_ACK_SET_reserved_MASK 0x7f
#define REG_REG_ACK_CLEAR 0x020
#define REG_REG_ACK_CLEAR_fc_hp_events_LSB 30
#define REG_REG_ACK_CLEAR_fc_hp_events_MASK 0x3
#define REG_REG_ACK_CLEAR_fc_err_events_LSB 29
#define REG_REG_ACK_CLEAR_fc_err_events_MASK 0x1
#define REG_REG_ACK_CLEAR_unused1_LSB 24
#define REG_REG_ACK_CLEAR_unused1_MASK 0x1f
#define REG_REG_ACK_CLEAR_ref_change_event_LSB 23
#define REG_REG_ACK_CLEAR_ref_change_event_MASK 0x1
#define REG_REG_ACK_CLEAR_adv_timer_evens_LSB 19
#define REG_REG_ACK_CLEAR_adv_timer_evens_MASK 0xf
#define REG_REG_ACK_CLEAR_gpio_event_LSB 18
#define REG_REG_ACK_CLEAR_gpio_event_MASK 0x1
#define REG_REG_ACK_CLEAR_timer_hi_event_LSB 17
#define REG_REG_ACK_CLEAR_timer_hi_event_MASK 0x1
#define REG_REG_ACK_CLEAR_timer_lo_event_LSB 16
#define REG_REG_ACK_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_ACK_CLEAR_unused2_LSB 8
#define REG_REG_ACK_CLEAR_unused2_MASK 0xff
#define REG_REG_ACK_CLEAR_timer_lo_event_LSB 7
#define REG_REG_ACK_CLEAR_timer_lo_event_MASK 0x1
#define REG_REG_ACK_CLEAR_reserved_LSB 0
#define REG_REG_ACK_CLEAR_reserved_MASK 0x7f
#define REG_REG_FIFO 0x024
#define REG_REG_FIFO_EVENT_ID_LSB 0
#define REG_REG_FIFO_EVENT_ID_MASK 0xff
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __APB_INTERRUPT_CNTRL_H_

131
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc.h Normal file
View File

@@ -0,0 +1,131 @@
/*
* Copyright (C) 2020 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Description: SoC configuration registers (apb_soc_ctrl)
* Authors: Germain Haugou (germain.haugou@iis.ee.ethz.ch)
* Robert Balas (balasr@iis.ee.ethz.ch)
*/
#ifndef HAL_INCLUDE_HAL_APB_SOC_H_
#define HAL_INCLUDE_HAL_APB_SOC_H_
#define APB_SOC_BOOT_OTHER 0
#define APB_SOC_BOOT_JTAG 1
#define APB_SOC_BOOT_SPI 2
#define APB_SOC_BOOT_ROM 3
#define APB_SOC_BOOT_PRELOAD 4
#define APB_SOC_BOOT_HYPER 5
#define APB_SOC_BOOT_SPIM 6
#define APB_SOC_BOOT_SPIM_QPI 7
#define APB_SOC_PLT_OTHER 0
#define APB_SOC_PLT_FPGA 1
#define APB_SOC_PLT_RTL 2
#define APB_SOC_PLT_VP 3
#define APB_SOC_PLT_CHIP 4
//PADs configuration is made of 8bits out of which only the first 6 are used
//bit0 enable pull UP
//bit1 enable pull DOWN
//bit2 enable ST
//bit3 enable SlewRate Limit
//bit4..5 Driving Strength
//bit6..7 not used
#define APB_SOC_BOOTADDR_OFFSET 0x04
#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0]
#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment
#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment
#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment
#define APB_SOC_PADFUN0_OFFSET 0x10
#define APB_SOC_PADCFG0_OFFSET 0x20
#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4)
#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
#define APB_SOC_PADFUN_SIZE 2
#define ARCHI_APB_SOC_PADFUN_NB 4
#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1)
#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24])
#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2)
#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
#define APB_SOC_PADCFG_SIZE 8
#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3)
#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet)
#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet)
#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment
#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment)
#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment
#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment)
#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment
#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed)
#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed)
#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment
#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment
#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment
#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment
#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment
#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment
#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
#define APB_SOC_PADS_CONFIG 0xC4
#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
#define APB_SOC_JTAG_REG_EXT_BIT 8
#define APB_SOC_JTAG_REG_EXT_WIDTH 4
#define APB_SOC_JTAG_REG_LOC_BIT 0
#define APB_SOC_JTAG_REG_LOC_WIDTH 4
#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2)
#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
#define APB_SOC_STATUS_EOC_BIT 31
#define APB_SOC_NB_CORE_BIT 16
#define APB_SOC_BYPASS_OFFSET 0x70
#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
#define APB_SOC_BYPASS_USER0_BIT 14
#define APB_SOC_BYPASS_USER1_BIT 15
#define APB_SOC_FLL_CTRL_OFFSET 0xD0
#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4
#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8
#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC
#define APB_SOC_FLL_CTRL_SOC_BIT 0
#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1
#define APB_SOC_FLL_CTRL_PERIPH_BIT 2
#define APB_SOC_RTC_OFFSET 0x1D0
#endif /* HAL_INCLUDE_HAL_APB_SOC_H_ */

365
bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc_ctrl_reg_defs.h Normal file
View File

@@ -0,0 +1,365 @@
/*
* This is a generated file
*
* Copyright 2021 QuickLogic
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_CTRL_H_
#define __SOC_CTRL_H_
//---------------------------------//
//
// Module: SOC_CTRL
//
//---------------------------------//
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile
#endif
#ifndef __O
#define __O volatile
#endif
#include "stdint.h"
typedef struct {
// Offset = 0x0000
union {
__IO uint32_t info;
struct {
__IO uint32_t n_clusters : 16;
__IO uint32_t n_cores : 16;
} info_b;
};
__I uint32_t unused0[2];
// Offset = 0x000c
union {
__IO uint32_t build_date;
struct {
__IO uint32_t day : 8;
__IO uint32_t month : 8;
__IO uint32_t year : 16;
} build_date_b;
};
// Offset = 0x0010
union {
__IO uint32_t build_time;
struct {
__IO uint32_t seconds : 8;
__IO uint32_t minutes : 8;
__IO uint32_t hour : 8;
} build_time_b;
};
// Offset = 0x0014
union {
__IO uint32_t io_cfg0;
struct {
__IO uint32_t n_io : 8;
__IO uint32_t n_sysio : 8;
__IO uint32_t n_gpio : 8;
} io_cfg0_b;
};
// Offset = 0x0018
union {
__IO uint32_t io_cfg1;
struct {
__IO uint32_t nbit_padcfg : 8;
__IO uint32_t nbit_padmux : 8;
} io_cfg1_b;
};
__I uint32_t unused1[1];
// Offset = 0x0020
union {
__IO uint32_t per_cfg0;
struct {
__IO uint32_t n_uart : 8;
__IO uint32_t n_qspim : 8;
__IO uint32_t n_i2cm : 8;
__IO uint32_t n_i2sc : 8;
} per_cfg0_b;
};
// Offset = 0x0024
union {
__IO uint32_t per_cfg1;
struct {
__IO uint32_t n_sdio : 8;
__IO uint32_t n_cam : 8;
} per_cfg1_b;
};
__I uint32_t unused2[19];
// Offset = 0x0074
union {
__IO uint32_t jtagreg;
};
__I uint32_t unused3[10];
// Offset = 0x00a0
union {
__IO uint32_t corestatus;
struct {
__IO uint32_t status : 31;
__IO uint32_t eoc : 1;
} corestatus_b;
};
__I uint32_t unused4[7];
// Offset = 0x00c0
union {
__IO uint32_t cs_ro;
struct {
__IO uint32_t status : 31;
__IO uint32_t eoc : 1;
} cs_ro_b;
};
// Offset = 0x00c4
union {
__IO uint32_t bootsel;
};
// Offset = 0x00c8
union {
__IO uint32_t clksel;
};
__I uint32_t unused5[3];
// Offset = 0x00d8
union {
__IO uint32_t clk_div_clu;
};
__I uint32_t unused6[1];
// Offset = 0x00e0
union {
__IO uint32_t rto_peripheral_error;
struct {
__IO uint32_t fll_rto : 1;
__IO uint32_t gpio_rto : 1;
__IO uint32_t udma_rto : 1;
__IO uint32_t soc_control_rto : 1;
__IO uint32_t adv_timer_rto : 1;
__IO uint32_t event_gen_rto : 1;
__IO uint32_t i2cs_rto : 1;
__IO uint32_t timer_rto : 1;
__IO uint32_t fcb_rto : 1;
} rto_peripheral_error_b;
};
// Offset = 0x00e4
union {
__IO uint32_t ready_timeout_count;
struct {
__IO uint32_t count : 20;
} ready_timeout_count_b;
};
// Offset = 0x00e8
union {
__IO uint32_t reset_type1_efpga;
struct {
__IO uint32_t reset_lt : 1;
__IO uint32_t reset_rt : 1;
__IO uint32_t reset_rb : 1;
__IO uint32_t reset_lb : 1;
} reset_type1_efpga_b;
};
// Offset = 0x00ec
union {
__IO uint32_t enable_in_out_efpga;
struct {
__IO uint32_t enable_tcdm_p0 : 1;
__IO uint32_t enable_tcdm_p1 : 1;
__IO uint32_t enable_tcdm_p2 : 1;
__IO uint32_t enable_tcdm_p3 : 1;
__IO uint32_t enable_soc_access : 1;
__IO uint32_t enable_events : 1;
} enable_in_out_efpga_b;
};
// Offset = 0x00f0
union {
__IO uint32_t efpga_control_in;
};
// Offset = 0x00f4
union {
__IO uint32_t efpga_status_out;
};
// Offset = 0x00f8
union {
__IO uint32_t efpga_version;
};
// Offset = 0x00fc
union {
__IO uint32_t soft_reset;
};
__I uint32_t unused7[192];
// Offset = 0x0400
union {
__IO uint32_t io_ctrl[48];
struct {
__IO uint32_t mux : 2;
__IO uint32_t : 6;
__IO uint32_t cfg : 6;
} io_ctrl_b[48];
};
} SocCtrl_t;
#define REG_INFO 0x0000
#define REG_INFO_N_CORES_LSB 16
#define REG_INFO_N_CORES_MASK 0xffff
#define REG_INFO_N_CLUSTERS_LSB 0
#define REG_INFO_N_CLUSTERS_MASK 0xffff
#define REG_BUILD_DATE 0x000C
#define REG_BUILD_DATE_YEAR_LSB 16
#define REG_BUILD_DATE_YEAR_MASK 0xffff
#define REG_BUILD_DATE_MONTH_LSB 8
#define REG_BUILD_DATE_MONTH_MASK 0xff
#define REG_BUILD_DATE_DAY_LSB 0
#define REG_BUILD_DATE_DAY_MASK 0xff
#define REG_BUILD_TIME 0x0010
#define REG_BUILD_TIME_HOUR_LSB 16
#define REG_BUILD_TIME_HOUR_MASK 0xff
#define REG_BUILD_TIME_MINUTES_LSB 8
#define REG_BUILD_TIME_MINUTES_MASK 0xff
#define REG_BUILD_TIME_SECONDS_LSB 0
#define REG_BUILD_TIME_SECONDS_MASK 0xff
#define REG_IO_CFG0 0x0014
#define REG_IO_CFG0_N_GPIO_LSB 16
#define REG_IO_CFG0_N_GPIO_MASK 0xff
#define REG_IO_CFG0_N_SYSIO_LSB 8
#define REG_IO_CFG0_N_SYSIO_MASK 0xff
#define REG_IO_CFG0_N_IO_LSB 0
#define REG_IO_CFG0_N_IO_MASK 0xff
#define REG_IO_CFG1 0x0018
#define REG_IO_CFG1_NBIT_PADMUX_LSB 8
#define REG_IO_CFG1_NBIT_PADMUX_MASK 0xff
#define REG_IO_CFG1_NBIT_PADCFG_LSB 0
#define REG_IO_CFG1_NBIT_PADCFG_MASK 0xff
#define REG_PER_CFG0 0x0020
#define REG_PER_CFG0_N_I2SC_LSB 24
#define REG_PER_CFG0_N_I2SC_MASK 0xff
#define REG_PER_CFG0_N_I2CM_LSB 16
#define REG_PER_CFG0_N_I2CM_MASK 0xff
#define REG_PER_CFG0_N_QSPIM_LSB 8
#define REG_PER_CFG0_N_QSPIM_MASK 0xff
#define REG_PER_CFG0_N_UART_LSB 0
#define REG_PER_CFG0_N_UART_MASK 0xff
#define REG_PER_CFG1 0x0024
#define REG_PER_CFG1_N_CAM_LSB 8
#define REG_PER_CFG1_N_CAM_MASK 0xff
#define REG_PER_CFG1_N_SDIO_LSB 0
#define REG_PER_CFG1_N_SDIO_MASK 0xff
#define REG_JTAGREG 0x0074
#define REG_CORESTATUS 0x00A0
#define REG_CORESTATUS_EOC_LSB 31
#define REG_CORESTATUS_EOC_MASK 0x1
#define REG_CORESTATUS_STATUS_LSB 0
#define REG_CORESTATUS_STATUS_MASK 0x7fffffff
#define REG_CS_RO 0x00C0
#define REG_CS_RO_EOC_LSB 31
#define REG_CS_RO_EOC_MASK 0x1
#define REG_CS_RO_STATUS_LSB 0
#define REG_CS_RO_STATUS_MASK 0x7fffffff
#define REG_BOOTSEL 0x00C4
#define REG_CLKSEL 0x00C8
#define REG_CLK_DIV_CLU 0x00D8
#define REG_RTO_PERIPHERAL_ERROR 0x00E0
#define REG_RTO_PERIPHERAL_ERROR_FCB_RTO_LSB 8
#define REG_RTO_PERIPHERAL_ERROR_FCB_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_LSB 7
#define REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_LSB 6
#define REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_LSB 5
#define REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_LSB 4
#define REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_LSB 3
#define REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_LSB 2
#define REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_LSB 1
#define REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_MASK 0x1
#define REG_RTO_PERIPHERAL_ERROR_FLL_RTO_LSB 0
#define REG_RTO_PERIPHERAL_ERROR_FLL_RTO_MASK 0x1
#define REG_READY_TIMEOUT_COUNT 0x00E4
#define REG_READY_TIMEOUT_COUNT_COUNT_LSB 0
#define REG_READY_TIMEOUT_COUNT_COUNT_MASK 0xfffff
#define REG_RESET_TYPE1_EFPGA 0x00E8
#define REG_RESET_TYPE1_EFPGA_RESET_LB_LSB 3
#define REG_RESET_TYPE1_EFPGA_RESET_LB_MASK 0x1
#define REG_RESET_TYPE1_EFPGA_RESET_RB_LSB 2
#define REG_RESET_TYPE1_EFPGA_RESET_RB_MASK 0x1
#define REG_RESET_TYPE1_EFPGA_RESET_RT_LSB 1
#define REG_RESET_TYPE1_EFPGA_RESET_RT_MASK 0x1
#define REG_RESET_TYPE1_EFPGA_RESET_LT_LSB 0
#define REG_RESET_TYPE1_EFPGA_RESET_LT_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA 0x00EC
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_LSB 5
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_LSB 4
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_LSB 3
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_LSB 2
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_LSB 1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_MASK 0x1
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_LSB 0
#define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_MASK 0x1
#define REG_EFPGA_CONTROL_IN 0x00F0
#define REG_EFPGA_STATUS_OUT 0x00F4
#define REG_EFPGA_VERSION 0x00F8
#define REG_SOFT_RESET 0x00FC
#define REG_IO_CTRL 0x0400
#define REG_IO_CTRL_CFG_LSB 8
#define REG_IO_CTRL_CFG_MASK 0x3f
#define REG_IO_CTRL_MUX_LSB 0
#define REG_IO_CTRL_MUX_MASK 0x3
#ifndef __REGFIELD_OPS_
#define __REGFIELD_OPS_
static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
return (reg >> lsb) & mask;
}
static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
reg &= ~(mask << lsb);
reg |= (value & mask) << lsb;
return reg;
}
#endif // __REGFIELD_OPS_
#endif // __SOC_CTRL_H_

Some files were not shown because too many files have changed in this diff Show More