Add psoc6-cy8cproto-062S3-4343W BSP and update doc

2026-10-07 00:59:00 +08:00 · 2023-01-16 23:37:22 -05:00
parent c9f7f0e771
commit 9a6dab644a
232 changed files with 33597 additions and 727 deletions
@@ -73,7 +73,7 @@ BSP 的制作过程分为如下四个步骤：

 ### 3.2 修改芯片基本配置

-在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，这个文件中需要修改的是 `IFX_FLASH_START_ADRESS` 、`IFX_EFLASH_START_ADRESS` 和 `IFX_SRAM_SIZE` 这两个宏控制的参数。本次制作的 BSP 所用的 CY8CKIT-062S2-43012 芯片的 flash 大小为 2M，ram 的大小为 1M，因此对该文件作出如下的修改：
+在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，`IFX_SRAM_SIZE` 这个宏控制的参数。本次制作的 BSP 所用的 CY8CKIT-062S2-43012 芯片 RAM 的大小为 1M，因此对该文件作出如下的修改：

 ![](./figures/board_h.png)

@@ -107,44 +107,26 @@ BSP 的制作过程分为如下四个步骤：

 #### 3.4.1 添加底层外设库

-接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。
+接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**

 ![](./figures/hal_config2.png)

-Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下：
+Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下：**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**

 ![](./figures/hal_config3.png)

-将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。
+将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**

 ![](./figures/hal_config1.png)

-同时复制 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下。
+同时下载 [TARGET_CY8CKIT-062S2-43012](https://github.com/Infineon/TARGET_CY8CKIT-062S2-43012/releases)  **V3.0.0** 发行版本（需根据不同芯片型号下载），至具体 BSP 的 libs 文件夹下。

 ![](./figures/hal_config4.png)

-拷贝至具体 BSP 的 libs 文件夹下，例如下图：
+下载至具体 BSP 的 libs 文件夹下，例如下图：

 ![](./figures/hal_config4-1.png)

-#### 3.4.1 修改外设配置脚本
-
-根据具体的路径添加通用外设配置（只有移植新的系列才需要做此步骤）
-
-![](./figures/hal_config5.png)
-
-添加专有芯片相关文件，如下图：
-
-![](./figures/hal_config5-1.png)
-
-首次移植，需要使用串口外设（只有移植新的系列才需要做此步骤）:
-
-![](./figures/hal_config6.png)
-
-添加库所使用到的头文件路径，如下图：
-
-![](./figures/hal_config7.png)
-
 ### 3.5 修改工程构建相关文件

 接下来需要修改用于构建工程相关的文件。
@@ -155,46 +137,74 @@ Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_s

 ![](./figures/linker_scripts.png)

-**linker_scripts** 链接文件是从 Modus 生成的示例工程中拷贝而来，需要修改其名称为 link.ld/.icf/.sct ，源文件路径如下：
-
-ARMCC/ARMClang 使用:
-
-![](./figures/linker_scripts2.png)
-
-GCC 使用：
-
-![](./figures/linker_scripts1.png)
-
-下面以 MDK 使用的链接脚本 link.sct 为例，演示如何修改链接脚本：
-
-![](./figures/linkscripts_change.png)
-
-本次制作 BSP 使用的芯片为  `CY8CKIT-062S2-43012` ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
-
-其他两个链接脚本的文件为 iar 使用的 link.icf 和 gcc 编译器使用的 link.lds，修改的方式也是类似的，如下图所示：
-
-* link.ld 修改内容
+以 **GCC** 工具链使用的链接脚本 link.ld 为例，演示如何修改链接脚本：

 ![](./figures/link_lds.png)

+**方式一（推荐）：**
+
+**FLASH** 和 **RAM** 大小信息可以参考上述拷贝的 **TARGET_CY8CKIT-062S2-43012** 文件夹下的链接脚本，进行修改，其路径在 TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM（TOOLCHAIN_GCC_ARM）/cy8c6xxa_cm4_dual.sct（.ld）：
+
+![](./figures/link_ifx1.png)
+
+![](./figures/link_ifx2.png)
+
+**方式二：**
+
+本次制作 BSP 使用的芯片为  `CY8CKIT-062S2-43012` ，FLASH 为 **2M**，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 **1M**， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
+
+---
+
+MDK 编译器使用的 link.sct，修改的方式也是类似的，如下图所示：
+
+* link.sct 修改内容
+
+![](./figures/linkscripts_change.png)
+
 ####  3.5.2 修改构建脚本

-**SConscript** 脚本决定 MDK/IAR/RT-Thread Studio 工程的生成以及编译过程中要添加文件。
+**SConscript** 脚本决定 **MDK/IAR/RT-Thread Studio** 工程的生成以及编译过程中要添加文件。

-在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES**  的参数要根据芯片的 low level（hal)  库中定义的芯片型号去填写。
+根据具体的路径添加通用外设配置**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**

-![](./figures/SConscript1.png)
+![](./figures/hal_config5.png)
+
+添加专有芯片相关文件，如下图：
+
+![](./figures/hal_config5-1.png)
+
+首次移植，需要使用串口外设**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
+
+![](./figures/hal_config6.png)
+
+添加库所使用到的头文件路径，如下图：
+
+![](./figures/hal_config7.png)
+
+在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES**  的参数要根据芯片底层库中定义的芯片型号去填写。

 ![](./figures/SConscript2.png)

+BSP 下的 lib/SConscript 中需要根据不同编译器选择不同的启动文件。
+
+![](./figures/SConscript1.png)
+
+**注意：**
+
+需要特别注意的是，假如使用的是 GCC 工具链，那么需要对启动文件做如下修改：将原有的 **main** 改成 **entry**
+
+![](./figures/entry.png)
+
 #### 3.5.3 修改编译选项

-rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。
+rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 GCC 和 ArmClang 两种工具链。

 ![](./figures/rt_configpy.png)

 #### 3.5.4 修改工程模板

+MDK 为例：
+
 **template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示：

 ![](./figures/template_1.png)
@@ -209,7 +219,7 @@ rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面

 ---

-以 RT-Thread Studio 为例，介绍如何导入，修改模板配置：
+**RT-Thread Studio** 为例，介绍如何导入，修改模板配置：

 1、打开 ENV 工具，在工程目录使用 `scons --dist` 命令将工程打包。（整个过程需要保证没有错误）

@@ -267,7 +277,7 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移

 **RT-Thread Studio：**

-使用上述方法/点击同步 scons 配置至项目
+使用上述方法/点击同步 scons 配置至项目。

 #### 3.6.2 重新生成 MDK 工程

@@ -287,6 +297,20 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移

 感谢每一位贡献代码的开发者，RT-Thread 将与你一同成长。

+### 3.7 RT-Thread Studio 下载配置
+
+1、点击 Studio 顶部导航栏中的配置按钮：
+
+![](./figures/studio_cfg1.png)
+
+2、确保可执行文件选择配置如下图：
+
+![](./figures/studio_cfg2.png)
+
+3、Debugger 配置项，需按照不同的芯片选择目标文件，OpenOCD 会根据此文件进行烧录：
+
+![](./figures/studio_cfg3.png)
+
 ## 4. 规范

 本章节介绍 RT-Thread PSOC6 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。
@@ -22,10 +22,14 @@
 static const struct pin_irq_map pin_irq_map[] =
 {
    {CYHAL_PORT_0,  ioss_interrupts_gpio_0_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
    {CYHAL_PORT_1,  ioss_interrupts_gpio_1_IRQn},
+#endif
    {CYHAL_PORT_2,  ioss_interrupts_gpio_2_IRQn},
    {CYHAL_PORT_3,  ioss_interrupts_gpio_3_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
    {CYHAL_PORT_4,  ioss_interrupts_gpio_4_IRQn},
+#endif
    {CYHAL_PORT_5,  ioss_interrupts_gpio_5_IRQn},
    {CYHAL_PORT_6,  ioss_interrupts_gpio_6_IRQn},
    {CYHAL_PORT_7,  ioss_interrupts_gpio_7_IRQn},
@@ -34,7 +38,9 @@ static const struct pin_irq_map pin_irq_map[] =
    {CYHAL_PORT_10,  ioss_interrupts_gpio_10_IRQn},
    {CYHAL_PORT_11,  ioss_interrupts_gpio_11_IRQn},
    {CYHAL_PORT_12,  ioss_interrupts_gpio_12_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
    {CYHAL_PORT_13,  ioss_interrupts_gpio_13_IRQn},
+#endif
    {CYHAL_PORT_14,  ioss_interrupts_gpio_14_IRQn},
 };

@@ -42,6 +42,12 @@ if GetDepend(['SOC_CY8C624ABZI_S2D44']):
    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c']
    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')

+if GetDepend(['SOC_CY8C6245LQI_S3D72']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_03.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_68_qfn.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
 if GetDepend(['RT_USING_SERIAL']):
    src += ['retarget-io/cy_retarget_io.c']
    src += ['mtb-hal-cat1/source/cyhal_uart.c']
@@ -125,6 +131,12 @@ if GetDepend(['SOC_CY8C624ABZI_S2D44']):
    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']

+if GetDepend(['SOC_CY8C6245LQI_S3D72']):
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
+
 group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)

 Return('group')
@@ -27,18 +27,6 @@
    #include "cycfg_usbdev.h"
 #endif

-/*FLASH CONFIG*/
-#define IFX_FLASH_START_ADRESS          ((uint32_t)0x10000000)
-#define IFX_FLASH_PAGE_SIZE             (256 * 1024)
-#define IFX_FLASH_SIZE                  (2 * 1024 * 1024)
-#define IFX_FLASH_END_ADDRESS           ((uint32_t)(IFX_FLASH_START_ADRESS + IFX_FLASH_SIZE))
-
-/*EFLASH CONFIG*/
-#define IFX_EFLASH_START_ADRESS         ((uint32_t)0x14000000)
-#define IFX_EFLASH_PAGE_SIZE            (32 * 1024)
-#define IFX_EFLASH_SIZE                 (32 * 1024)
-#define IFX_EFLASH_END_ADDRESS          ((uint32_t)(IFX_EFLASH_START_ADRESS + IFX_EFLASH_SIZE))
-
 /*SRAM CONFIG*/
 #define IFX_SRAM_SIZE                   (1014)
 #define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
@@ -11,8 +11,8 @@ if rtconfig.PLATFORM in ['iccarm']:
    print("\nThe current project does not support IAR build\n")
    Return('group')
 elif rtconfig.PLATFORM in ['gcc', 'armclang']:
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/*.c')
    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')

    CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',
@@ -141,7 +141,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_NULL is not set
 # CONFIG_RT_USING_ZERO is not set
 # CONFIG_RT_USING_RANDOM is not set
-CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -729,11 +729,7 @@ CONFIG_BSP_USING_UART=y
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_USING_UART4 is not set
 CONFIG_BSP_USING_UART5=y
-CONFIG_BSP_USING_PWM=y
-CONFIG_BSP_USING_PWM0=y
-CONFIG_BSP_USING_PWM0_CH3=y
-CONFIG_BSP_USING_PWM0_PORT13=y
-# CONFIG_BSP_USING_PWM0_CH7 is not set
+# CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_SDMMC is not set
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-</listAttribute>
-<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+temp.toolchain.exec.path=D\:\\IDE\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin
@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
@@ -11,8 +11,8 @@ if rtconfig.PLATFORM in ['iccarm']:
    print("\nThe current project does not support IAR build\n")
    Return('group')
 elif rtconfig.PLATFORM in ['gcc', 'armclang']:
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/*.c')
    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')

    CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',
@@ -0,0 +1,18 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define COMPONENT_BSP_DESIGN_MODUS
+#define COMPONENT_CAT1
+#define COMPONENT_CAT1A
+#define CY8C624ABZI_S2D44
+#define CY_USING_HAL
+#define RT_USING_LIBC
+#define RT_USING_NEWLIBC
+#define _POSIX_C_SOURCE 1
+#define __RTTHREAD__
+
+#endif /*RTCONFIG_PREINC_H__*/
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>com.cypress.studio.app.cymodusnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1522148012290462689" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+#Thu Jan 12 11:11:44 CST 2023
+project_type=rt-thread
+chip_name=CY8C624ABZI
+os_branch=full
+example_name=
+os_version=latest
+selected_rtt_version=latest
+cfg_version=v3.0
+board_base_nano_proj=False
+is_use_scons_build=True
+output_project_path=E\:/software/RT-ThreadStudio/workspace
+project_base_bsp=true
+hardware_adapter=KitProg3
+project_name=1111
+is_base_example_project=False
+board_name=psoc6-cy8ckit-062S2-43012
+device_vendor=Infineon 
+bsp_version=1.0.0
+bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
@@ -12,7 +12,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd_debugger_relative_path}openocd/bin/openocd.exe"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6_2m.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
@@ -21,7 +21,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.hex}"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
@@ -34,20 +34,20 @@
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="E:\software\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\ARM\GNU_Tools_for_ARM_Embedded_Processors\10.2.1\bin\arm-none-eabi-gdb.exe"/>
 <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="1111"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/1111"/>
+<listEntry value="/dist_ide_project"/>
 </listAttribute>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
 <listEntry value="4"/>
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="12000000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="cy8c64xA_cm4"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="E:\software\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\openocd\bin\openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="HEX"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/dist_ide_project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+IFX_library = 'IFX_PSOC6_HAL'
+rtconfig.BSP_LIBRARY_TYPE = IFX_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, IFX_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,16 @@
+import rtconfig
+from building import *
+import os
+
+cwd  = GetCurrentDir()
+path = [cwd]
+src  = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-01-16     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "drv_gpio.h"
+
+#define LED_PIN     GET_PIN(11, 1)
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    for (;;)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
@@ -0,0 +1,40 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+objs = []
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+if GetDepend(['BSP_USING_SPI3_SAMPLE']):
+    src += Glob('ports/spi_sample.c')
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('ports/drv_rw007.c')
+
+if GetDepend(['BSP_USING_SLIDER']):
+    src += Glob('ports/slider_sample.c')
+
+path = [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
+elif rtconfig.PLATFORM in ['armclang']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
+
+CPPDEFINES = ['CY8C6245LQI_S3D72', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
+
+Return('group')
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include "board.h"
+
+void cy_bsp_all_init(void)
+{
+    cy_rslt_t result;
+
+    /* Initialize the device and board peripherals */
+    result = cybsp_init();
+
+    /* Board init failed. Stop program execution */
+    if (result != CY_RSLT_SUCCESS)
+    {
+        CY_ASSERT(0);
+    }
+}
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-01-16     Rbb666       first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef BSP_USING_USBD
+    #include "cy_usb_dev.h"
+    #include "cy_usb_dev_hid.h"
+    #include "cycfg_usbdev.h"
+#endif
+
+/*SRAM CONFIG*/
+#define IFX_SRAM_SIZE                   (246)
+#define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+    #define HEAP_END        IFX_SRAM_END
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+    extern unsigned int __end__;
+    extern unsigned int __HeapLimit;
+    #define HEAP_BEGIN    (void*)&__end__
+    #define HEAP_END      (void*)&__HeapLimit
+#endif
+
+void cy_bsp_all_init(void);
+
+#endif
+
@@ -0,0 +1,67 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static struct rt_spi_device rw007_dev;
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = IFX_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     Rbb666       first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev ifx_onchip_flash_32k;
+extern const struct fal_flash_dev ifx_onchip_flash_256k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE         \
+    {                               \
+        &ifx_onchip_flash_32k,      \
+        &ifx_onchip_flash_256k,     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                  \
+    {                                                                                   \
+        {FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0},      \
+        {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0},        \
+    }
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-19     Rbbb666      first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_SPI3_SAMPLE)
+#include <drv_spi.h>
+
+#define SPI_NAME     "spi30"
+static struct rt_spi_device *spi_dev = RT_NULL;
+
+/* attach spi5 device */
+static int rt_spi_device_init(void)
+{
+    struct rt_spi_configuration cfg;
+
+    rt_hw_spi_device_attach("spi3", "spi30", NULL);
+
+    cfg.data_width = 8;
+    cfg.mode   = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
+    cfg.max_hz = 1 *1000 *1000;
+
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
+
+    if (RT_NULL == spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
+        return RT_ERROR;
+    }
+
+    rt_spi_configure(spi_dev, &cfg);
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_spi_device_init);
+
+/* spi5 loopback mode test case */
+static int spi_sample(int argc, char **argv)
+{
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
+    static struct rt_spi_message msg1;
+
+    if (argc != 9)
+    {
+        rt_kprintf("Please Usage:\n");
+        rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        t_buf[i] = atoi(argv[i+1]);
+    }
+
+    msg1.send_buf   = &t_buf;
+    msg1.recv_buf   = &r_buf;
+    msg1.length     = sizeof(t_buf);
+    msg1.cs_take    = 1;
+    msg1.cs_release = 0;
+    msg1.next       = RT_NULL;
+
+    rt_spi_transfer_message(spi_dev, &msg1);
+
+    rt_kprintf("spi rbuf : ");
+    for (i = 0; i < sizeof(t_buf); i++)
+    {
+        rt_kprintf("%x ", r_buf[i]);
+    }
+
+    rt_kprintf("\nspi loopback mode test over!\n");
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(spi_sample, spi loopback test);
+
+#endif /* BSP_USING_SPI3 */
@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/*.c')
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/*.c')
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
+
+    CPPPATH = [ cwd + '/TARGET_CY8CPROTO-062S3-4343W',
+                cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    if rtconfig.PLATFORM in ['gcc']:
+        src += [cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S']
+    elif rtconfig.PLATFORM in ['armclang']:
+        src += [cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S']
+
+group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
@@ -0,0 +1,9 @@
+docs
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2)
+$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/
+$(SEARCH_bluetooth-freertos)/firmware_deprecated/
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1)
+../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/
+../bluetooth-freertos/firmware_deprecated/
@@ -0,0 +1,39 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_peripherals();
+    init_cycfg_pins();
+}
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_connectivity_bt.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */
@@ -0,0 +1,29 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_defines.h
+*
+* Description:
+* CapSense configuration defines.
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.5943
+*
+********************************************************************************
+* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_DEFINES_H)
+#define CYCFG_CAPSENSE_DEFINES_H
+
+#include <stddef.h>
+
+/* General */
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (7u)
+#define CY_CAPSENSE_PIN_COUNT                                                    (7u)
+#define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
+#define CY_CAPSENSE_POSITION_SIZE                                                (1u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (7u)
+#define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
+#define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
+#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE                                         (0u)
+#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE                                 (0u)
+#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE                                    (0u)
+#define CY_CAPSENSE_DIPLEX_SIZE                                                  (0u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE                                (0u)
+#define CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE                                      (0u)
+#define CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE                                       (0u)
+#define CY_CAPSENSE_BALLISTIC_WIDGET_COUNT                                       (0u)
+#define CY_CAPSENSE_GESTURE_WIDGET_COUNT                                         (0u)
+
+/* Sensing Methods */
+#define CY_CAPSENSE_CSD_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (0u)
+#define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (0u)
+#define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
+#define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
+#define CY_CAPSENSE_CSD_SHIELD_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SHIELD_CAP_EN                                            (0u)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER                                          (CY_CAPSENSE_IDAC_SOURCING)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN                                             (1u)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN                                        (1u)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN                                    (1u)
+#define CY_CAPSENSE_LFSR_EN                                                      (1u)
+#define CY_CAPSENSE_LFSR_AUTO_EN                                                 (1u)
+#define CY_CAPSENSE_CLOCK_SOURCE_AUTO_EN                                         (1u)
+
+/* Filtering */
+#define CY_CAPSENSE_ADAPTIVE_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN                                      (0u)
+#define CY_CAPSENSE_RAWCOUNT_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN                                  (0u)
+#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN                                 (0u)
+#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN                                    (0u)
+#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_POSITION_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_CSD_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_CSX_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_POS_IIR_FILTER_EN                                            (0u)
+#define CY_CAPSENSE_POS_MEDIAN_FILTER_EN                                         (0u)
+#define CY_CAPSENSE_POS_AVERAGE_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_POS_JITTER_FILTER_EN                                         (0u)
+
+/* Widgets */
+#define CY_CAPSENSE_CSD_BUTTON_EN                                                (1u)
+#define CY_CAPSENSE_CSD_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SLIDER_EN                                                (1u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_CSD_PROXIMITY_EN                                             (0u)
+#define CY_CAPSENSE_CSX_BUTTON_EN                                                (0u)
+#define CY_CAPSENSE_CSX_SLIDER_EN                                                (0u)
+#define CY_CAPSENSE_CSX_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSX_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN                                     (0u)
+#define CY_CAPSENSE_CSD_LINEAR_SLIDER_EN                                         (1u)
+#define CY_CAPSENSE_CSD_RADIAL_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSD_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_LINEAR_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_GANGED_SNS_EN                                                (0u)
+#define CY_CAPSENSE_CSD_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_CSX_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_BUTTON_EN                                                    (1u)
+#define CY_CAPSENSE_MATRIX_EN                                                    (0u)
+#define CY_CAPSENSE_SLIDER_EN                                                    (1u)
+#define CY_CAPSENSE_TOUCHPAD_EN                                                  (0u)
+
+/* Features */
+#define CY_CAPSENSE_GESTURE_EN                                                   (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_SCAN_EN                                      (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_WIDGET_EN                                    (0u)
+#define CY_CAPSENSE_SNS_AUTO_RESET_EN                                            (0u)
+
+/* Self-test */
+#define CY_CAPSENSE_BIST_EN                                                      (0u)
+#define CY_CAPSENSE_TST_WDGT_CRC_EN                                              (0u)
+#define CY_CAPSENSE_TST_BSLN_INTEGRITY_EN                                        (0u)
+#define CY_CAPSENSE_TST_RAW_INTEGRITY_EN                                         (0u)
+#define CY_CAPSENSE_TST_SNS_SHORT_EN                                             (0u)
+#define CY_CAPSENSE_TST_SNS_CAP_EN                                               (0u)
+#define CY_CAPSENSE_TST_SH_CAP_EN                                                (0u)
+#define CY_CAPSENSE_TST_EXTERNAL_CAP_EN                                          (0u)
+#define CY_CAPSENSE_TST_VDDA_EN                                                  (0u)
+
+
+#endif /* CYCFG_CAPSENSE_DEFINES_H */
+
+/* [] END OF FILE */
@@ -0,0 +1,50 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = CYBSP_CSD_CLK_DIV_HW,
+        .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+    Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
+    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}
@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+    #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */
@@ -0,0 +1,31 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.c
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_connectivity_bt.h"
+
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.h
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CONNECTIVITY_BT_H)
+#define CYCFG_CONNECTIVITY_BT_H
+
+#include "cycfg_notices.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define bt_0_power_0_ENABLED 1U
+#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
+#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CONNECTIVITY_BT_H */
@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef CY8C6245LQI_S3D72
+    #error "Unexpected target MCU; expected CY8C6245LQI-S3D72. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+
+#endif /* CYCFG_NOTICES_H */
@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context =
+{
+    .lockKey = CY_CSD_NONE_KEY,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+    Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+}
@@ -0,0 +1,77 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_ENABLED 1U
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 100000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 0u
+#define Cmod_PORT GPIO_PRT7
+#define Button0_Sns0_PORT GPIO_PRT8
+#define Button1_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns0_PORT GPIO_PRT7
+#define LinearSlider0_Sns1_PORT GPIO_PRT7
+#define LinearSlider0_Sns2_PORT GPIO_PRT7
+#define LinearSlider0_Sns3_PORT GPIO_PRT7
+#define LinearSlider0_Sns4_PORT GPIO_PRT9
+#define Cmod_PIN 7u
+#define Button0_Sns0_PIN 0u
+#define Button1_Sns0_PIN 1u
+#define LinearSlider0_Sns0_PIN 0u
+#define LinearSlider0_Sns1_PIN 1u
+#define LinearSlider0_Sns2_PIN 2u
+#define LinearSlider0_Sns3_PIN 3u
+#define LinearSlider0_Sns4_PIN 0u
+#define Cmod_PORT_NUM 7u
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */
@@ -0,0 +1,65 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION           (220)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED       (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+    #define CY_SMIF_DRV_VERSION            (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+   #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
+
@@ -0,0 +1,44 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[3] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}
@@ -0,0 +1,58 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXA
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */
@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 2.20.0.2857
+#
+################################################################################
+# Copyright 2020 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
@@ -0,0 +1,20 @@
+[Device=CY8C6245LQI-S3D72]
+ 
+[Blocks]
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
+<Configuration app="QSPI" major="2" minor="20">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <MemoryId>S25FL512S-4byteaddr</MemoryId>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
--- a/Show More
+++ b/Show More