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[bsp/ch32v103r-evt] add ch32v103r-evt bsp

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feat: move MRS demo source to bsp and libraries folder

feat: update Sconscript

feat: modify SConstruct in the bsp

feat: use the rtconfig.py of gd32vf103v-eval bsp to modify

feat: use the MRS's rtconfig.h temoporarily

feat: update Kconfig files

feat: use the MRS's .ld and rename as link.lds

feat: add ch32v1 porting folder

perf: remove board/system_ch32v10x.c

fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h

fix: add some neccessary macros in rtconfig.h

perf: use the menuconfig to generate rtconfig.h

feat: add readme.md

fix: correct the bad encode in main.c

fix: include board.h in main.c

perf: check and update README.md

perf: remove ch32f10x_port_cn.md

feat: ignore the standard libraries's CI checking

feat: add sdk_dist.py

fix: correct some style errors again

perf: simply the board/kconfig

fix: format ch32v103r-evt

fix: format drvs and libcpu
This commit is contained in:
blta
2022-04-06 11:06:55 +08:00
committed by guo
parent cceefd5ef9
commit 99526cc047
83 changed files with 26450 additions and 0 deletions
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bsp/wch/risc-v/.ignore_format.yml
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# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- Libraries/CH32V10x_StdPeriph_Driver
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/ch32v10x.h
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/system_ch32v10x.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v10x.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : CH32V10x Device Peripheral Access Layer System Header File.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __SYSTEM_CH32V10x_H
#define __SYSTEM_CH32V10x_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V10x_SYSTEM_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Source/GCC/startup_ch32v10x.S
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;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v10x.s
;* Author : WCH
;* Version : V1.0.0
;* Date : 2020/04/30
;* Description : CH32V10x vector table for eclipse toolchain.
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* SPDX-License-Identifier: Apache-2.0
;*******************************************************************************/
.section .init,"ax",@progbits
.global _start
.align 1
_start:
j handle_reset
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00100073
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
j _start
.word 0
j NMI_Handler /* NMI Handler */
j HardFault_Handler /* Hard Fault Handler */
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
j SysTick_Handler /* SysTick Handler */
.word 0
j SW_handler /* SW Handler */
.word 0
/* External Interrupts */
j WWDG_IRQHandler /* Window Watchdog */
j PVD_IRQHandler /* PVD through EXTI Line detect */
j TAMPER_IRQHandler /* TAMPER */
j RTC_IRQHandler /* RTC */
j FLASH_IRQHandler /* Flash */
j RCC_IRQHandler /* RCC */
j EXTI0_IRQHandler /* EXTI Line 0 */
j EXTI1_IRQHandler /* EXTI Line 1 */
j EXTI2_IRQHandler /* EXTI Line 2 */
j EXTI3_IRQHandler /* EXTI Line 3 */
j EXTI4_IRQHandler /* EXTI Line 4 */
j DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
j DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
j DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
j DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
j DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
j DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
j DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
j ADC1_2_IRQHandler /* ADC1_2 */
.word 0
.word 0
.word 0
.word 0
j EXTI9_5_IRQHandler /* EXTI Line 9..5 */
j TIM1_BRK_IRQHandler /* TIM1 Break */
j TIM1_UP_IRQHandler /* TIM1 Update */
j TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
j TIM1_CC_IRQHandler /* TIM1 Capture Compare */
j TIM2_IRQHandler /* TIM2 */
j TIM3_IRQHandler /* TIM3 */
j TIM4_IRQHandler /* TIM4 */
j I2C1_EV_IRQHandler /* I2C1 Event */
j I2C1_ER_IRQHandler /* I2C1 Error */
j I2C2_EV_IRQHandler /* I2C2 Event */
j I2C2_ER_IRQHandler /* I2C2 Error */
j SPI1_IRQHandler /* SPI1 */
j SPI2_IRQHandler /* SPI2 */
j USART1_IRQHandler /* USART1 */
j USART2_IRQHandler /* USART2 */
j USART3_IRQHandler /* USART3 */
j EXTI15_10_IRQHandler /* EXTI Line 15..10 */
j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
j USBWakeUp_IRQHandler /* USB Wakeup from suspend */
j USBHD_IRQHandler /* USBHD */
.option rvc;
.section .text.vector_handler, "ax", @progbits
.weak NMI_Handler
.weak HardFault_Handler
.weak SysTick_Handler
.weak SW_handler
.weak WWDG_IRQHandler
.weak PVD_IRQHandler
.weak TAMPER_IRQHandler
.weak RTC_IRQHandler
.weak FLASH_IRQHandler
.weak RCC_IRQHandler
.weak EXTI0_IRQHandler
.weak EXTI1_IRQHandler
.weak EXTI2_IRQHandler
.weak EXTI3_IRQHandler
.weak EXTI4_IRQHandler
.weak DMA1_Channel1_IRQHandler
.weak DMA1_Channel2_IRQHandler
.weak DMA1_Channel3_IRQHandler
.weak DMA1_Channel4_IRQHandler
.weak DMA1_Channel5_IRQHandler
.weak DMA1_Channel6_IRQHandler
.weak DMA1_Channel7_IRQHandler
.weak ADC1_2_IRQHandler
.weak EXTI9_5_IRQHandler
.weak TIM1_BRK_IRQHandler
.weak TIM1_UP_IRQHandler
.weak TIM1_TRG_COM_IRQHandler
.weak TIM1_CC_IRQHandler
.weak TIM2_IRQHandler
.weak TIM3_IRQHandler
.weak TIM4_IRQHandler
.weak I2C1_EV_IRQHandler
.weak I2C1_ER_IRQHandler
.weak I2C2_EV_IRQHandler
.weak I2C2_ER_IRQHandler
.weak SPI1_IRQHandler
.weak SPI2_IRQHandler
.weak USART1_IRQHandler
.weak USART2_IRQHandler
.weak USART3_IRQHandler
.weak EXTI15_10_IRQHandler
.weak RTCAlarm_IRQHandler
.weak USBWakeUp_IRQHandler
.weak USBHD_IRQHandler
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.option push
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* disable interrupt */
li t0, 0x1800
csrs mstatus, t0
la t0, _vector_base
ori t0, t0, 1
csrw mtvec, t0
jal SystemInit /* ϵͳʱÖÓ³õʼ»¯ */
la t0,entry /* rttµÄÈë¿Ú */
csrw mepc, t0
mret
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Source/system_ch32v10x.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/core_riscv.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/core_riscv.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : RISC-V Core Peripheral Access Layer Header File
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CORE_RISCV_H__
#define __CORE_RISCV_H__
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#define RV_STATIC_INLINE static inline
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct{
__I uint32_t ISR[8];
__I uint32_t IPR[8];
__IO uint32_t ITHRESDR;
__IO uint32_t FIBADDRR;
__IO uint32_t CFGR;
__I uint32_t GISR;
uint8_t RESERVED0[0x10];
__IO uint32_t FIOFADDRR[4];
uint8_t RESERVED1[0x90];
__O uint32_t IENR[8];
uint8_t RESERVED2[0x60];
__O uint32_t IRER[8];
uint8_t RESERVED3[0x60];
__O uint32_t IPSR[8];
uint8_t RESERVED4[0x60];
__O uint32_t IPRR[8];
uint8_t RESERVED5[0x60];
__IO uint32_t IACTR[8];
uint8_t RESERVED6[0xE0];
__IO uint8_t IPRIOR[256];
uint8_t RESERVED7[0x810];
__IO uint32_t SCTLR;
}PFIC_Type;
/* memory mapped structure for SysTick */
typedef struct
{
__IO uint32_t CTLR;
__IO uint8_t CNTL0;
__IO uint8_t CNTL1;
__IO uint8_t CNTL2;
__IO uint8_t CNTL3;
__IO uint8_t CNTH0;
__IO uint8_t CNTH1;
__IO uint8_t CNTH2;
__IO uint8_t CNTH3;
__IO uint8_t CMPLR0;
__IO uint8_t CMPLR1;
__IO uint8_t CMPLR2;
__IO uint8_t CMPLR3;
__IO uint8_t CMPHR0;
__IO uint8_t CMPHR1;
__IO uint8_t CMPHR2;
__IO uint8_t CMPHR3;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
/*********************************************************************
* @fn __NOP
*
* @brief nop
*
* @return none
*/
RV_STATIC_INLINE void __NOP()
{
__asm volatile ("nop");
}
/*********************************************************************
* @fn NVIC_EnableIRQ
*
* @brief Enable Interrupt
*
* @param IRQn: Interrupt Numbers
*
* @return none
*/
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_DisableIRQ
*
* @brief Disable Interrupt
*
* @param IRQn: Interrupt Numbers
*
* @return none
*/
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
uint32_t t;
t = NVIC->ITHRESDR;
NVIC->ITHRESDR = 0x10;
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
NVIC->ITHRESDR = t;
}
/*********************************************************************
* @fn NVIC_GetStatusIRQ
*
* @brief Get Interrupt Enable State
*
* @param IRQn: Interrupt Numbers
*
* @return 1 - Interrupt Enable
* 0 - Interrupt Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_GetPendingIRQ
*
* @brief Get Interrupt Pending State
*
* @param IRQn: Interrupt Numbers
*
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPendingIRQ
*
* @brief Set Interrupt Pending
*
* @param IRQn: Interrupt Numbers
*
* @return None
*/
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_ClearPendingIRQ
*
* @brief Clear Interrupt Pending
*
* @param IRQn: Interrupt Numbers
*
* @return None
*/
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetActive
*
* @brief Get Interrupt Active State
*
* @param IRQn: Interrupt Numbers
*
* @return 1 - Interrupt Active
* 0 - Interrupt No Active
*/
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPriority
*
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* priority -
* bit7 - pre-emption priority
* bit6~bit4 - subpriority
* @return None
*/
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
/*********************************************************************
* @fn __WFI
*
* @brief Wait for Interrupt
*
* @return None
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
{
NVIC->SCTLR &= ~(1<<3); // wfi
asm volatile ("wfi");
}
/*********************************************************************
* @fn __WFE
*
* @brief Wait for Events
*
* @return None
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
asm volatile ("wfi");
NVIC->SCTLR |= (1<<3);
asm volatile ("wfi");
}
/*********************************************************************
* @fn NVIC_SetFastIRQ
*
* @brief Set VTF Interrupt
*
* @param add - VTF interrupt service function base address.
* IRQn -Interrupt Numbers
* num - VTF Interrupt Numbers
* @return None
*/
RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num)
{
if(num > 3) return ;
NVIC->FIBADDRR = addr;
NVIC->FIOFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff);
}
/*********************************************************************
* @fn NVIC_SystemReset
*
* @brief Initiate a system reset request
*
* @return None
*/
RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/*********************************************************************
* @fn NVIC_HaltPushCfg
*
* @brief Enable Hardware Stack
*
* @param NewState - DISABLE or ENABLE
* @return None
*/
RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState)
{
if (NewState != DISABLE)
{
NVIC->CFGR = NVIC_KEY1;
}
else{
NVIC->CFGR = NVIC_KEY1|(1<<0);
}
}
/*********************************************************************
* @fn NVIC_INTNestCfg
*
* @brief Enable Interrupt Nesting
*
* @param NewState - DISABLE or ENABLE
* @return None
*/
RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState)
{
if (NewState != DISABLE)
{
NVIC->CFGR = NVIC_KEY1;
}
else
{
NVIC->CFGR = NVIC_KEY1|(1<<1);
}
}
/* Core_Exported_Functions */
extern uint32_t __get_FFLAGS(void);
extern void __set_FFLAGS(uint32_t value);
extern uint32_t __get_FRM(void);
extern void __set_FRM(uint32_t value);
extern uint32_t __get_FCSR(void);
extern void __set_FCSR(uint32_t value);
extern uint32_t __get_MSTATUS(void);
extern void __set_MSTATUS(uint32_t value);
extern uint32_t __get_MISA(void);
extern void __set_MISA(uint32_t value);
extern uint32_t __get_MIE(void);
extern void __set_MIE(uint32_t value);
extern uint32_t __get_MTVEC(void);
extern void __set_MTVEC(uint32_t value);
extern uint32_t __get_MSCRATCH(void);
extern void __set_MSCRATCH(uint32_t value);
extern uint32_t __get_MEPC(void);
extern void __set_MEPC(uint32_t value);
extern uint32_t __get_MCAUSE(void);
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MTVAL(void);
extern void __set_MTVAL(uint32_t value);
extern uint32_t __get_MIP(void);
extern void __set_MIP(uint32_t value);
extern uint32_t __get_MCYCLE(void);
extern void __set_MCYCLE(uint32_t value);
extern uint32_t __get_MCYCLEH(void);
extern void __set_MCYCLEH(uint32_t value);
extern uint32_t __get_MINSTRET(void);
extern void __set_MINSTRET(uint32_t value);
extern uint32_t __get_MINSTRETH(void);
extern void __set_MINSTRETH(uint32_t value);
extern uint32_t __get_MVENDORID(void);
extern uint32_t __get_MARCHID(void);
extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#endif/* __CORE_RISCV_H__ */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/SConscript
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
src = Split("""
StdPeriph_Driver/src/ch32v10x_adc.c
StdPeriph_Driver/src/ch32v10x_bkp.c
StdPeriph_Driver/src/ch32v10x_crc.c
StdPeriph_Driver/src/ch32v10x_dbgmcu.c
StdPeriph_Driver/src/ch32v10x_dma.c
StdPeriph_Driver/src/ch32v10x_exti.c
StdPeriph_Driver/src/ch32v10x_flash.c
StdPeriph_Driver/src/ch32v10x_gpio.c
StdPeriph_Driver/src/ch32v10x_i2c.c
StdPeriph_Driver/src/ch32v10x_iwdg.c
StdPeriph_Driver/src/ch32v10x_misc.c
StdPeriph_Driver/src/ch32v10x_pwr.c
StdPeriph_Driver/src/ch32v10x_rcc.c
StdPeriph_Driver/src/ch32v10x_rtc.c
StdPeriph_Driver/src/ch32v10x_spi.c
StdPeriph_Driver/src/ch32v10x_tim.c
StdPeriph_Driver/src/ch32v10x_usart.c
StdPeriph_Driver/src/ch32v10x_wwdg.c
CMSIS/core_riscv.c
CMSIS/WCH/CH32V10x/Source/system_ch32v10x.c
CMSIS/WCH/CH32V10x/Source/GCC/startup_ch32v10x.S
""")
path = [
cwd + '/CMSIS',
cwd + '/CMSIS/WCH/CH32V10x/Include',
cwd + '/StdPeriph_Driver/inc']
group = DefineGroup('ch32v10x_lib', src, depend = [''], CPPPATH = path)
Return('group')
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x.h
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_adc.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_ADC_H
#define __CH32V10x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* ADC Init structure definition */
typedef struct
{
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
} ADC_InitTypeDef;
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
/* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
/* ADC_sampling_time */
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
/* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_StartCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
s32 TempSensor_Volt_To_Temper(s32 Value);
int16_t Get_CalibrationValue(ADC_TypeDef *ADCx);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V10x_ADC_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_bkp.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_bkp.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_BKP_H
#define __CH32V10x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* Tamper_Pin_active_level */
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
/* RTC_output_source_to_output_on_the_Tamper_pin */
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
/* Data_Backup_Register */
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_BKP_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_crc.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_crc.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_CRC_H
#define __CH32V10x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_CRC_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_dbgmcu.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_dbgmcu.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_DBGMCU_H
#define __CH32V10x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* CFGR0 Register */
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000004)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000008)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000040)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000080)
/* CFGR1 Register */
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_DBGMCU_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_dma.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_DMA_H
#define __CH32V10x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* DMA Init structure definition */
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitTypeDef;
/* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
/* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V10x_DMA_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_exti.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_exti.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_EXTI_H
#define __CH32V10x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* EXTI mode enumeration */
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTIMode_TypeDef;
/* EXTI Trigger enumeration */
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTITrigger_TypeDef;
/* EXTI Init Structure definition */
typedef struct
{
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitTypeDef;
/* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000)
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBHD Wakeup event */
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_EXTI_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_flash.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_FLASH_H
#define __CH32V10x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
} FLASH_Status;
/* Flash_Latency */
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
/* Half_Cycle_Enable_Disable */
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
/* Prefetch_Buffer_Enable_Disable */
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
/* Values to be used with CH32V10x Low and Medium density devices */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */
/* Values to be used with CH32V10x Medium-density devices */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
/* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/*Functions used for all CH32V10x devices*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void);
void FLASH_BufReset(void);
void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
/* New function used for all CH32V10x devices */
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_FLASH_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_gpio.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_GPIO_H
#define __CH32V10x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* Output Maximum frequency selection */
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
} GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */
typedef enum
{
GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
} GPIOMode_TypeDef;
/* GPIO Init structure definition */
typedef struct
{
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
} GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{
Bit_RESET = 0,
Bit_SET
} BitAction;
/* GPIO_pins_define */
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
/* GPIO_Remap_define */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
to TIM2 Internal Trigger 1 for calibration \
(only for Connectivity line devices) */
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \
only for High density Value line devices) */
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_GPIO_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_i2c.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_i2c.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_I2C_H
#define __CH32V10x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* I2C Init structure definition */
typedef struct
{
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /* Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
} I2C_InitTypeDef;
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
/* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_SMBus_alert_pin_level */
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
/* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
/* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
/****************I2C Master Events (Events grouped in order of communication)********************/
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
/****************************************************************************************
* I2C State Monitoring Functions
****************************************************************************************/
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V10x_I2C_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_iwdg.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_iwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_IWDG_H
#define __CH32V10x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_IWDG_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_misc.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_misc.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10X_MISC_H
#define __CH32V10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* NVIC Init Structure definition */
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_MISC_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_pwr.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_PWR_H
#define __CH32V10x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* PVD_detection_level */
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
/* Regulator_state_is_STOP_mode */
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_PWR_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_rcc.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the RCC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_RCC_H
#define __CH32V10x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* RCC_Exported_Types */
typedef struct
{
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
} RCC_ClocksTypeDef;
/* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
/* PLL_multiplication_factor */
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
/* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
/* APB1_APB2_clock_source */
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
/* USB_Device_clock_source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
/* LSE_configuration */
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHD ((uint32_t)0x00001000)
/* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
/* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
/* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_RCC_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_rtc.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_rtc.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the RTC
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_RTC_H
#define __CH32V10x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* RTC_interrupts_define */
#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */
/* RTC_interrupts_flags */
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_RTC_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_spi.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_SPI_H
#define __CH32V10x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* SPI Init structure definition */
typedef struct
{
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /* Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
} SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitTypeDef;
/* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
/* I2S_Standard */
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
/* I2S_Data_Format */
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
/* I2S_MCLK_Output */
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
/* I2S_Audio_Frequency */
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
/* I2S_Clock_Polarity */
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
/* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef *SPIx);
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V10x_SPI_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_tim.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the
* USART firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_USART_H
#define __CH32V10x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* USART Init Structure definition */
typedef struct
{
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /* Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define USART_IT_ORE USART_IT_ORE_ER
/* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef *USARTx);
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
void USART_SendBreak(USART_TypeDef *USARTx);
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_USART_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_usb.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_usb_host.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the USB
* Host firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_USBHOST_H
#define __CH32V10x_USBHOST_H
#include "ch32v10x_usb.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ERR_SUCCESS 0x00
#define ERR_USB_CONNECT 0x15
#define ERR_USB_DISCON 0x16
#define ERR_USB_BUF_OVER 0x17
#define ERR_USB_DISK_ERR 0x1F
#define ERR_USB_TRANSFER 0x20
#define ERR_USB_UNSUPPORT 0xFB
#define ERR_USB_UNKNOWN 0xFE
#define ERR_AOA_PROTOCOL 0x41
#define ROOT_DEV_DISCONNECT 0
#define ROOT_DEV_CONNECTED 1
#define ROOT_DEV_FAILED 2
#define ROOT_DEV_SUCCESS 3
#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20)
#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30)
#define DEF_AOA_DEVICE 0xF0
#define DEV_TYPE_UNKNOW 0xFF
#define HUB_MAX_PORTS 4
#define WAIT_USB_TOUT_200US 3000
typedef struct
{
UINT8 DeviceStatus;
UINT8 DeviceAddress;
UINT8 DeviceSpeed;
UINT8 DeviceType;
UINT16 DeviceVID;
UINT16 DevicePID;
UINT8 GpVar[4];
UINT8 GpHUBPortNum;
} _RootHubDev;
extern _RootHubDev ThisUsbDev;
extern UINT8 UsbDevEndp0Size;
extern UINT8 FoundNewDev;
extern PUINT8 pHOST_RX_RAM_Addr;
extern PUINT8 pHOST_TX_RAM_Addr;
#define pSetupReq ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr)
extern const UINT8 SetupGetDevDescr[];
extern const UINT8 SetupGetCfgDescr[];
extern const UINT8 SetupSetUsbAddr[];
extern const UINT8 SetupSetUsbConfig[];
extern const UINT8 SetupSetUsbInterface[];
extern const UINT8 SetupClrEndpStall[];
void DisableRootHubPort(void);
UINT8 AnalyzeRootHub(void);
void SetHostUsbAddr(UINT8 addr);
void SetUsbSpeed(UINT8 FullSpeed);
void ResetRootHubPort(void);
UINT8 EnableRootHubPort(void);
void SelectHubPort(UINT8 HubPortIndex);
UINT8 WaitUSB_Interrupt(void);
UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout);
UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen);
void CopySetupReqPkg(const UINT8 *pReqPkt);
UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf);
UINT8 CtrlGetConfigDescr(PUINT8 DataBuf);
UINT8 CtrlSetUsbAddress(UINT8 addr);
UINT8 CtrlSetUsbConfig(UINT8 cfg);
UINT8 CtrlClearEndpStall(UINT8 endp);
UINT8 CtrlSetUsbIntercace(UINT8 cfg);
void USB_HostInit(void);
UINT8 InitRootDevice(PUINT8 DataBuf);
UINT8 HubGetPortStatus(UINT8 HubPortIndex); // 查询HUB端口状态,返回在TxBuffer中
UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); // 设置HUB端口特性
UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); // 清除HUB端口特性
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_USBHOST_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_wwdg.h
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_wwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file contains all the functions prototypes for the WWDG
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V10x_WWDG_H
#define __CH32V10x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v10x.h"
/* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V10x_WWDG_H */
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_adc.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_bkp.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_bkp.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the BKP firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v10x_bkp.h"
#include "ch32v10x_rcc.h"
/* BKP registers bit mask */
/* OCTLR register bit mask */
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
#define OCTLR_MASK ((uint16_t)0xFC7F)
/*********************************************************************
* @fn BKP_DeInit
*
* @brief Deinitializes the BKP peripheral registers to their default reset values.
*
* @return none
*/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*********************************************************************
* @fn BKP_TamperPinLevelConfig
*
* @brief Configures the Tamper Pin active level.
*
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* BKP_TamperPinLevel_High - Tamper pin active on high level.
* BKP_TamperPinLevel_Low - Tamper pin active on low level.
*
* @return none
*/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
if(BKP_TamperPinLevel)
{
BKP->TPCTLR |= (1 << 1);
}
else
{
BKP->TPCTLR &= ~(1 << 1);
}
}
/*********************************************************************
* @fn BKP_TamperPinCmd
*
* @brief Enables or disables the Tamper Pin activation.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCTLR |= (1 << 0);
}
else
{
BKP->TPCTLR &= ~(1 << 0);
}
}
/*********************************************************************
* @fn BKP_ITConfig
*
* @brief Enables or disables the Tamper Pin Interrupt.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_ITConfig(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCSR |= (1 << 2);
}
else
{
BKP->TPCSR &= ~(1 << 2);
}
}
/*********************************************************************
* @fn BKP_RTCOutputConfig
*
* @brief Select the RTC output source to output on the Tamper pin.
*
* @param BKP_RTCOutputSource - specifies the RTC output source.
* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
* BKP_RTCOutputSource_CalibClock - output the RTC clock with
* frequency divided by 64 on the Tamper pin.
* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
* on the Tamper pin.
* BKP_RTCOutputSource_Second - output the RTC Second pulse
* signal on the Tamper pin.
*
* @return none
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_MASK;
tmpreg |= BKP_RTCOutputSource;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_SetRTCCalibrationValue
*
* @brief Sets RTC Clock Calibration value.
*
* @param CalibrationValue - specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x1F.
*
* @return none
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_CAL_MASK;
tmpreg |= CalibrationValue;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_WriteBackupRegister
*
* @brief Writes user data to the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* Data - data to write.
*
* @return none
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *)tmp = Data;
}
/*********************************************************************
* @fn BKP_ReadBackupRegister
*
* @brief Reads data from the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* This parameter can be BKP_DRx where x=[1, 42].
*
* @return none
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *)tmp);
}
/*********************************************************************
* @fn BKP_GetFlagStatus
*
* @brief Checks whether the Tamper Pin Event flag is set or not.
*
* @return FlagStatus - SET or RESET.
*/
FlagStatus BKP_GetFlagStatus(void)
{
if(BKP->TPCSR & (1 << 8))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearFlag
*
* @brief Clears Tamper Pin Event pending flag.
*
* @return none
*/
void BKP_ClearFlag(void)
{
BKP->TPCSR |= BKP_CTE;
}
/*********************************************************************
* @fn BKP_GetITStatus
*
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
*
* @return ITStatus - SET or RESET.
*/
ITStatus BKP_GetITStatus(void)
{
if(BKP->TPCSR & (1 << 9))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearITPendingBit
*
* @brief Clears Tamper Pin Interrupt pending bit.
*
* @return none
*/
void BKP_ClearITPendingBit(void)
{
BKP->TPCSR |= BKP_CTI;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_crc.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_crc.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the CRC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v10x_crc.h"
/*********************************************************************
* @fn CRC_ResetDR
*
* @brief Resets the CRC Data register (DR).
*
* @return none
*/
void CRC_ResetDR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/*********************************************************************
* @fn CRC_CalcCRC
*
* @brief Computes the 32-bit CRC of a given data word(32-bit).
*
* @param Data - data word(32-bit) to compute its CRC.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DATAR = Data;
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_CalcBlockCRC
*
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
*
* @param pBuffer - pointer to the buffer containing the data to be computed.
* BufferLength - length of the buffer to be computed.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DATAR = pBuffer[index];
}
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_GetCRC
*
* @brief Returns the current CRC value.
*
* @return 32-bit CRC.
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->IDATAR);
}
/*********************************************************************
* @fn CRC_SetIDRegister
*
* @brief Stores a 8-bit data in the Independent Data(ID) register.
*
* @param IDValue - 8-bit value to be stored in the ID register.
*
* @return none
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDATAR = IDValue;
}
/*********************************************************************
* @fn CRC_GetIDRegister
*
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
*
* @return 8-bit value of the ID register.
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDATAR);
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_dbgmcu.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_dbgmcu.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the DBGMCU firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
****************************************************************************************/
#include "ch32v10x_dbgmcu.h"
/*********************************************************************
* @fn DBGMCU_Config
*
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
*
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
* DBGMCU_I2C1_SMBUS_TIMEOUT - I2C1 SMBUS timeout mode stopped when Core is halted
* DBGMCU_I2C2_SMBUS_TIMEOUT - I2C2 SMBUS timeout mode stopped when Core is halted
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
* DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted
* DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted
* DBGMCU_SLEEP - Keep debugger connection during SLEEP mode
* DBGMCU_STOP - Keep debugger connection during STOP mode
* DBGMCU_STANDBY - Keep debugger connection during STANDBY mode
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
if((DBGMCU_Periph == DBGMCU_SLEEP) || (DBGMCU_Periph == DBGMCU_STOP) || (DBGMCU_Periph == DBGMCU_STANDBY))
{
if(NewState != DISABLE)
{
DBGMCU->CFGR1 |= DBGMCU_Periph;
}
else
{
DBGMCU->CFGR1 &= ~DBGMCU_Periph;
}
}
else
{
if(NewState != DISABLE)
{
DBGMCU->CFGR0 |= DBGMCU_Periph;
}
else
{
DBGMCU->CFGR0 &= ~DBGMCU_Periph;
}
}
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_dma.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_exti.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the EXTI firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
#include "ch32v10x_exti.h"
/* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000)
/*********************************************************************
* @fn EXTI_DeInit
*
* @brief Deinitializes the EXTI peripheral registers to their default
* reset values.
*
* @return none.
*/
void EXTI_DeInit(void)
{
EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
}
/*********************************************************************
* @fn EXTI_Init
*
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
*
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{
uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/*********************************************************************
* @fn EXTI_StructInit
*
* @brief Fills each EXTI_InitStruct member with its reset value.
*
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*********************************************************************
* @fn EXTI_GenerateSWInterrupt
*
* @brief Generates a Software interrupt.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none.
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
EXTI->SWIEVR |= EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetFlagStatus
*
* @brief Checks whether the specified EXTI line flag is set or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearFlag
*
* @brief Clears the EXTI's line pending flags.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetITStatus
*
* @brief Checks whether the specified EXTI line is asserted or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearITPendingBit
*
* @brief Clears the EXTI's line pending bits.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_flash.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_gpio.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_i2c.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_iwdg.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the IWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v10x_iwdg.h"
/* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/*********************************************************************
* @fn IWDG_WriteAccessCmd
*
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
*
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* and IWDG_RLDR registers.
*
* @return none
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/*********************************************************************
* @fn IWDG_SetPrescaler
*
* @brief Sets IWDG Prescaler value.
*
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
*
* @return none
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
IWDG->PSCR = IWDG_Prescaler;
}
/*********************************************************************
* @fn IWDG_SetReload
*
* @brief Sets IWDG Reload value.
*
* @param Reload - specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
*
* @return none
*/
void IWDG_SetReload(uint16_t Reload)
{
IWDG->RLDR = Reload;
}
/*********************************************************************
* @fn IWDG_ReloadCounter
*
* @brief Reloads IWDG counter with value defined in the reload register.
*
* @return none
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_Reload;
}
/*********************************************************************
* @fn IWDG_Enable
*
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
*
* @return none
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
}
/*********************************************************************
* @fn IWDG_GetFlagStatus
*
* @brief Checks whether the specified IWDG flag is set or not.
*
* @param IWDG_FLAG - specifies the flag to check.
* IWDG_FLAG_PVU - Prescaler Value Update on going.
* IWDG_FLAG_RVU - Reload Value Update on going.
*
* @return none
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_misc.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_misc.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the miscellaneous firmware functions .
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
#include "ch32v10x_misc.h"
__IO uint32_t NVIC_Priority_Group = 0;
/*********************************************************************
* @fn NVIC_PriorityGroupConfig
*
* @brief Configures the priority grouping - pre-emption priority and subpriority.
*
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 4 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
* 2 bits for subpriority
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
* 1 bits for subpriority
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
* 0 bits for subpriority
*
* @return none
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
NVIC_Priority_Group = NVIC_PriorityGroup;
}
/*********************************************************************
* @fn NVIC_Init
*
* @brief Initializes the NVIC peripheral according to the specified parameters in
* the NVIC_InitStruct.
*
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
*
* @return none
*/
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{
uint8_t tmppre = 0;
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
}
else
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
}
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
else
{
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_pwr.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_pwr.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the PWR firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
#include "ch32v10x_pwr.h"
#include "ch32v10x_rcc.h"
/* PWR registers bit mask */
/* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/*********************************************************************
* @fn PWR_DeInit
*
* @brief Deinitializes the PWR peripheral registers to their default
* reset values.
*
* @return none
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*********************************************************************
* @fn PWR_BackupAccessCmd
*
* @brief Enables or disables access to the RTC and backup registers.
*
* @param NewState - new state of the access to the RTC and backup registers,
* This parameter can be: ENABLE or DISABLE.
*
* @return none
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 8);
}
else
{
PWR->CTLR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_PVDCmd
*
* @brief Enables or disables the Power Voltage Detector(PVD).
*
* @param NewState - new state of the PVD(ENABLE or DISABLE).
*
* @return none
*/
void PWR_PVDCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 4);
}
else
{
PWR->CTLR &= ~(1 << 4);
}
}
/*********************************************************************
* @fn PWR_PVDLevelConfig
*
* @brief Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
*
* @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
* PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
* PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
* PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
* PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
* PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
* PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
*
* @return none
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_PLS_MASK;
tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg;
}
/*********************************************************************
* @fn PWR_WakeUpPinCmd
*
* @brief Enables or disables the WakeUp Pin functionality.
*
* @param NewState - new state of the WakeUp Pin functionality
* (ENABLE or DISABLE).
*
* @return none
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CSR |= (1 << 8);
}
else
{
PWR->CSR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_EnterSTOPMode
*
* @brief Enters STOP mode.
*
* @param PWR_Regulator - specifies the regulator state in STOP mode.
* PWR_Regulator_ON - STOP mode with regulator ON
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
*
* @return none
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK;
tmpreg |= PWR_Regulator;
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
__WFI();
}
else
{
__WFE();
}
NVIC->SCTLR &= ~(1 << 2);
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode
*
* @brief Enters STANDBY mode.
*
* @return none
*/
void PWR_EnterSTANDBYMode(void)
{
PWR->CTLR |= PWR_CTLR_CWUF;
PWR->CTLR |= PWR_CTLR_PDDS;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_GetFlagStatus
*
* @brief Checks whether the specified PWR flag is set or not.
*
* @param PWR_FLAG - specifies the flag to check.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
* PWR_FLAG_PVDO - PVD Output
*
* @return The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn PWR_ClearFlag
*
* @brief Clears the PWR's pending flags.
*
* @param PWR_FLAG - specifies the flag to clear.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
*
* @return none
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
PWR->CTLR |= PWR_FLAG << 2;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_rcc.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_rtc.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_rtc.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the RTC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
#include "ch32v10x_rtc.h"
/* RTC_Private_Defines */
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
/*********************************************************************
* @fn RTC_ITConfig
*
* @brief Enables or disables the specified RTC interrupts.
*
* @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
* RTC_IT_OW - Overflow interrupt
* RTC_IT_ALR - Alarm interrupt
* RTC_IT_SEC - Second interrupt
*
* @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
*/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
RTC->CTLRH |= RTC_IT;
}
else
{
RTC->CTLRH &= (uint16_t)~RTC_IT;
}
}
/*********************************************************************
* @fn RTC_EnterConfigMode
*
* @brief Enters the RTC configuration mode.
*
* @return none
*/
void RTC_EnterConfigMode(void)
{
RTC->CTLRL |= RTC_CTLRL_CNF;
}
/*********************************************************************
* @fn RTC_ExitConfigMode
*
* @brief Exits from the RTC configuration mode.
*
* @return none
*/
void RTC_ExitConfigMode(void)
{
RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
}
/*********************************************************************
* @fn RTC_GetCounter
*
* @brief Gets the RTC counter value
*
* @return RTC counter value
*/
uint32_t RTC_GetCounter(void)
{
uint16_t high1 = 0, high2 = 0, low = 0;
high1 = RTC->CNTH;
low = RTC->CNTL;
high2 = RTC->CNTH;
if(high1 != high2)
{
return (((uint32_t)high2 << 16) | RTC->CNTL);
}
else
{
return (((uint32_t)high1 << 16) | low);
}
}
/*********************************************************************
* @fn RTC_SetCounter
*
* @brief Sets the RTC counter value.
*
* @param CounterValue - RTC counter new value.
*
* @return RTC counter value
*/
void RTC_SetCounter(uint32_t CounterValue)
{
RTC_EnterConfigMode();
RTC->CNTH = CounterValue >> 16;
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_SetPrescaler
*
* @brief Sets the RTC prescaler value
*
* @param PrescalerValue - RTC prescaler new value
*
* @return none
*/
void RTC_SetPrescaler(uint32_t PrescalerValue)
{
RTC_EnterConfigMode();
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_SetAlarm
*
* @brief Sets the RTC alarm value
*
* @param AlarmValue - RTC alarm new value
*
* @return none
*/
void RTC_SetAlarm(uint32_t AlarmValue)
{
RTC_EnterConfigMode();
RTC->ALRMH = AlarmValue >> 16;
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_GetDivider
*
* @brief Gets the RTC divider value
*
* @return RTC Divider value
*/
uint32_t RTC_GetDivider(void)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/*********************************************************************
* @fn RTC_WaitForLastTask
*
* @brief Waits until last write operation on RTC registers has finished
*
* @return none
*/
void RTC_WaitForLastTask(void)
{
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
{
}
}
/*********************************************************************
* @fn RTC_WaitForSynchro
*
* @brief Waits until the RTC registers are synchronized with RTC APB clock
*
* @return none
*/
void RTC_WaitForSynchro(void)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
{
}
}
/*********************************************************************
* @fn RTC_GetFlagStatus
*
* @brief Checks whether the specified RTC flag is set or not
*
* @param RTC_FLAG- specifies the flag to check
* RTC_FLAG_RTOFF - RTC Operation OFF flag
* RTC_FLAG_RSF - Registers Synchronized flag
* RTC_FLAG_OW - Overflow flag
* RTC_FLAG_ALR - Alarm flag
* RTC_FLAG_SEC - Second flag
*
* @return The new state of RTC_FLAG (SET or RESET)
*/
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
{
FlagStatus bitstatus = RESET;
if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RTC_ClearFlag
*
* @brief Clears the RTC's pending flags
*
* @param RTC_FLAG - specifies the flag to clear
* RTC_FLAG_RSF - Registers Synchronized flag
* RTC_FLAG_OW - Overflow flag
* RTC_FLAG_ALR - Alarm flag
* RTC_FLAG_SEC - Second flag
*
* @return none
*/
void RTC_ClearFlag(uint16_t RTC_FLAG)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
}
/*********************************************************************
* @fn RTC_GetITStatus
*
* @brief Checks whether the specified RTC interrupt has occurred or not
*
* @param RTC_IT - specifies the RTC interrupts sources to check
* RTC_FLAG_OW - Overflow interrupt
* RTC_FLAG_ALR - Alarm interrupt
* RTC_FLAG_SEC - Second interrupt
*
* @return The new state of the RTC_IT (SET or RESET)
*/
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
{
ITStatus bitstatus = RESET;
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RTC_ClearITPendingBit
*
* @brief Clears the RTC's interrupt pending bits
*
* @param RTC_IT - specifies the interrupt pending bit to clear
* RTC_FLAG_OW - Overflow interrupt
* RTC_FLAG_ALR - Alarm interrupt
* RTC_FLAG_SEC - Second interrupt
*
* @return none
*/
void RTC_ClearITPendingBit(uint16_t RTC_IT)
{
RTC->CTLRL &= (uint16_t)~RTC_IT;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_spi.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_usart.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_usb.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the USB firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v10x_usb.h"
#include "ch32v10x_rcc.h"
#include "debug.h"
/******************************** USB DEVICE **********************************/
/* Endpoint address */
PUINT8 pEP0_RAM_Addr;
PUINT8 pEP1_RAM_Addr;
PUINT8 pEP2_RAM_Addr;
PUINT8 pEP3_RAM_Addr;
PUINT8 pEP4_RAM_Addr;
PUINT8 pEP5_RAM_Addr;
PUINT8 pEP6_RAM_Addr;
PUINT8 pEP7_RAM_Addr;
/*********************************************************************
* @fn USB_DeviceInit
*
* @brief Initializes USB device.
*
* @return none
*/
void USB_DeviceInit(void)
{
R8_USB_CTRL = 0x00;
R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN;
R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN;
R8_UEP5_6_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN;
R8_UEP7_MOD = RB_UEP7_RX_EN | RB_UEP7_TX_EN;
R16_UEP0_DMA = (UINT16)(UINT32)pEP0_RAM_Addr;
R16_UEP1_DMA = (UINT16)(UINT32)pEP1_RAM_Addr;
R16_UEP2_DMA = (UINT16)(UINT32)pEP2_RAM_Addr;
R16_UEP3_DMA = (UINT16)(UINT32)pEP3_RAM_Addr;
R16_UEP4_DMA = (UINT16)(UINT32)pEP4_RAM_Addr;
R16_UEP5_DMA = (UINT16)(UINT32)pEP5_RAM_Addr;
R16_UEP6_DMA = (UINT16)(UINT32)pEP6_RAM_Addr;
R16_UEP7_DMA = (UINT16)(UINT32)pEP7_RAM_Addr;
R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP5_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP6_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP7_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_USB_INT_FG = 0xFF;
R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
R8_USB_DEV_AD = 0x00;
R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN;
}
/*********************************************************************
* @fn DevEP1_IN_Deal
*
* @brief Device endpoint1 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP1_IN_Deal(UINT8 l)
{
R8_UEP1_T_LEN = l;
R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP2_IN_Deal
*
* @brief Device endpoint2 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP2_IN_Deal(UINT8 l)
{
R8_UEP2_T_LEN = l;
R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP3_IN_Deal
*
* @brief Device endpoint3 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP3_IN_Deal(UINT8 l)
{
R8_UEP3_T_LEN = l;
R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP4_IN_Deal
*
* @brief Device endpoint4 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP4_IN_Deal(UINT8 l)
{
R8_UEP4_T_LEN = l;
R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP5_IN_Deal
*
* @brief Device endpoint5 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP5_IN_Deal(UINT8 l)
{
R8_UEP5_T_LEN = l;
R8_UEP5_CTRL = (R8_UEP5_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP6_IN_Deal
*
* @brief Device endpoint6 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP6_IN_Deal(UINT8 l)
{
R8_UEP6_T_LEN = l;
R8_UEP6_CTRL = (R8_UEP6_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
/*********************************************************************
* @fn DevEP7_IN_Deal
*
* @brief Device endpoint7 IN
*
* @param l: IN length(<64B)
*
* @return none
*/
void DevEP7_IN_Deal(UINT8 l)
{
R8_UEP7_T_LEN = l;
R8_UEP7_CTRL = (R8_UEP7_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
}
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_usb_host.c
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bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_wwdg.c
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v10x_wwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2020/04/30
* Description : This file provides all the WWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
**********************************************************************************/
#include "ch32v10x_wwdg.h"
#include "ch32v10x_rcc.h"
/* CTLR register bit mask */
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
/* CFGR register bit mask */
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F)
/*********************************************************************
* @fn WWDG_DeInit
*
* @brief Deinitializes the WWDG peripheral registers to their default reset values
*
* @return none
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*********************************************************************
* @fn WWDG_SetPrescaler
*
* @brief Sets the WWDG Prescaler
*
* @param WWDG_Prescaler - specifies the WWDG Prescaler
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
*
* @return none
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
tmpreg |= WWDG_Prescaler;
WWDG->CFGR = tmpreg;
}
/*********************************************************************
* @fn WWDG_SetWindowValue
*
* @brief Sets the WWDG window value
*
* @param WindowValue - specifies the window value to be compared to the
* downcounter,which must be lower than 0x80
*
* @return none
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_W_Mask;
tmpreg |= WindowValue & (uint32_t)BIT_Mask;
WWDG->CFGR = tmpreg;
}
/*********************************************************************
* @fn WWDG_EnableIT
*
* @brief Enables the WWDG Early Wakeup interrupt(EWI)
*
* @return none
*/
void WWDG_EnableIT(void)
{
WWDG->CFGR |= (1 << 9);
}
/*********************************************************************
* @fn WWDG_SetCounter
*
* @brief Sets the WWDG counter value
*
* @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
*
* @return none
*/
void WWDG_SetCounter(uint8_t Counter)
{
WWDG->CTLR = Counter & BIT_Mask;
}
/*********************************************************************
* @fn WWDG_Enable
*
* @brief Enables WWDG and load the counter value
*
* @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
* @return none
*/
void WWDG_Enable(uint8_t Counter)
{
WWDG->CTLR = CTLR_WDGA_Set | Counter;
}
/*********************************************************************
* @fn WWDG_GetFlagStatus
*
* @brief Checks whether the Early Wakeup interrupt flag is set or not
*
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
*/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->STATR);
}
/*********************************************************************
* @fn WWDG_ClearFlag
*
* @brief Clears Early Wakeup interrupt flag
*
* @return none
*/
void WWDG_ClearFlag(void)
{
WWDG->STATR = (uint32_t)RESET;
}
bsp/wch/risc-v/Libraries/Kconfig
+8
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config SOC_RISCV_FAMILY_CH32
bool
config SOC_RISCV_SERIES_CH32V103
bool
select ARCH_RISCV
select SOC_RISCV_FAMILY_CH32

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