mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-06-12 20:24:15 +08:00
[bsp/nxp/mcx/mcxe]: Add MCX E247 and FRDM-MCXE247 support. #10654
This commit is contained in:
Yilin Sun
GitHub
@@ -247,6 +247,7 @@
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"nxp/mcx/mcxa/frdm-mcxa153",
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"nxp/mcx/mcxa/frdm-mcxa156",
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"nxp/mcx/mcxa/frdm-mcxa346",
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"nxp/mcx/mcxe/frdm-mcxe247",
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||||
"renesas/ebf_qi_min_6m5",
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"renesas/ra6m4-cpk",
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"renesas/ra6m4-iot",
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@@ -0,0 +1,242 @@
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# Available style options are described in https://clang.llvm.org/docs/ClangFormatStyleOptions.html
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#
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# An easy way to create the .clang-format file is:
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#
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# clang-format -style=llvm -dump-config > .clang-format
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#
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Language: Cpp
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---
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@@ -0,0 +1,6 @@
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config SOC_MCX
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bool
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select ARCH_ARM_CORTEX_M4
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select ARCH_ARM_CORTEX_FPU
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select PKG_USING_NXP_MCX_CMSIS_DRIVER
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select PKG_USING_NXP_MCX_SERIES_DRIVER
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@@ -0,0 +1,41 @@
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from building import *
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cwd = GetCurrentDir()
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src = []
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if GetDepend('BSP_USING_PIN'):
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src += ['drv_pin.c']
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if GetDepend('BSP_USING_UART'):
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src += ['drv_uart.c']
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if GetDepend('BSP_USING_RTC'):
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src += ['drv_rtc.c']
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if GetDepend('BSP_USING_SPI'):
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src += ['drv_spi.c']
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if GetDepend('BSP_USING_I2C'):
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src += ['drv_i2c.c']
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if GetDepend('BSP_USING_ADC'):
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src += ['drv_adc.c']
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if GetDepend('BSP_USING_HWTIMER'):
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src += ['drv_hwtimer.c']
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if GetDepend('BSP_USING_WDT'):
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src += ['drv_wdt.c']
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if GetDepend('BSP_USING_PWM'):
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src += ['drv_pwm.c']
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if GetDepend('BSP_USING_FLASH'):
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src += ['drv_chipflash.c']
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path = [cwd,cwd + '/config']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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Return('group')
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@@ -0,0 +1,167 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2024-07-21 liujianhua added mcxa153
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*
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*/
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#include <rtconfig.h>
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#include <rtdevice.h>
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#include "fsl_adc12.h"
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#include "fsl_pmc.h"
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#define DBG_TAG "drv.adc"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifdef RT_USING_ADC
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#define ADC_VBG_CH 27
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#define ADC_VBG_VOLT 1000
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struct mcx_adc
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{
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struct rt_adc_device adc_device;
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ADC_Type *adc_base;
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clock_ip_name_t clock_ip_name;
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clock_ip_src_t clock_ip_src;
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uint8_t resolution_bits;
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uint8_t max_channels;
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uint32_t vref;
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char *name;
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};
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static struct mcx_adc mcx_adc_obj[] =
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{
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#ifdef BSP_USING_ADC0
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{
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.adc_base = ADC0,
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.clock_ip_name = kCLOCK_Adc0,
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.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
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.resolution_bits = 12,
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.max_channels = 32,
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.name = "adc0",
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},
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#endif
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#ifdef BSP_USING_ADC1
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{
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.adc_base = ADC1,
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.clock_ip_name = kCLOCK_Adc1,
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.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
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.resolution_bits = 12,
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.max_channels = 32,
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.name = "adc1",
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},
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#endif
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};
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static uint16_t mcx_adc_get_raw(struct mcx_adc *adc, uint32_t channel)
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{
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adc12_channel_config_t chnl_cfg = {0};
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chnl_cfg.channelNumber = channel;
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chnl_cfg.enableInterruptOnConversionCompleted = false;
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ADC12_SetChannelConfig(adc->adc_base, 0, &chnl_cfg);
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while ((ADC12_GetChannelStatusFlags(adc->adc_base, 0) & kADC12_ChannelConversionCompletedFlag) == 0U)
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{
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}
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return ADC12_GetChannelConversionValue(adc->adc_base, 0);
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}
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static rt_err_t mcx_adc_set_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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/* ADC is enabled by global probe. */
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RT_UNUSED(adc);
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return RT_EOK;
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}
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static rt_int16_t mcx_get_vref(struct rt_adc_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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return (int16_t)adc->vref;
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}
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static rt_err_t mcx_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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*value = mcx_adc_get_raw(adc, channel);
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return RT_EOK;
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}
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static rt_uint8_t mcx_adc_get_resolution(struct rt_adc_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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return adc->resolution_bits;
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}
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static const struct rt_adc_ops mcx_adc_ops =
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{
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.get_resolution = mcx_adc_get_resolution,
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.enabled = mcx_adc_set_enabled,
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.convert = mcx_adc_get_value,
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.get_vref = mcx_get_vref,
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};
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static int rt_hw_adc_init(void)
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{
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int result = RT_EOK;
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int i = 0;
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for (i = 0; i < sizeof(mcx_adc_obj) / sizeof(mcx_adc_obj[0]); i++)
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{
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struct mcx_adc *adc = &mcx_adc_obj[i];
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CLOCK_SetIpSrc(adc->clock_ip_name, adc->clock_ip_src);
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adc12_config_t cfg;
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ADC12_GetDefaultConfig(&cfg);
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cfg.clockSource = kADC12_ClockSourceAlt0; /* Only available selection. */
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cfg.resolution = kADC12_Resolution12Bit;
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cfg.sampleClockCount = 64;
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ADC12_Init(adc->adc_base, &cfg);
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ADC12_EnableHardwareTrigger(adc->adc_base, false);
|
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if (ADC12_DoAutoCalibration(adc->adc_base) != kStatus_Success)
|
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{
|
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return -RT_ERROR;
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}
|
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uint32_t vref_raw = mcx_adc_get_raw(adc, ADC_VBG_CH);
|
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adc->vref = (1U << adc->resolution_bits) * ADC_VBG_VOLT / vref_raw;
|
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if (rt_hw_adc_register(&mcx_adc_obj[i].adc_device, mcx_adc_obj[i].name, &mcx_adc_ops, &mcx_adc_obj[i]) != RT_EOK)
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{
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||||
return -RT_ERROR;
|
||||
}
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}
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return result;
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||||
}
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||||
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif /* BSP_USING_ADC */
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@@ -0,0 +1,170 @@
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/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-08-21 hywing The first version
|
||||
*/
|
||||
|
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#include <rtdevice.h>
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#include "fsl_lpi2c.h"
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#ifdef RT_USING_I2C
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#define DBG_TAG "drv.i2c"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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enum
|
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{
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#ifdef BSP_USING_I2C0
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I2C0_INDEX,
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#endif
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#ifdef BSP_USING_I2C1
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I2C1_INDEX,
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#endif
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};
|
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struct mcx_i2c_bus
|
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{
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struct rt_i2c_bus_device i2c_bus;
|
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LPI2C_Type *i2c_base;
|
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uint32_t baud;
|
||||
clock_ip_name_t clock_ip_name;
|
||||
clock_ip_src_t clock_ip_src;
|
||||
char *name;
|
||||
};
|
||||
|
||||
|
||||
static struct mcx_i2c_bus i2c_buses[] =
|
||||
{
|
||||
#ifdef BSP_USING_I2C0
|
||||
{
|
||||
.i2c_base = LPI2C0,
|
||||
.baud = 100000U,
|
||||
.clock_ip_name = kCLOCK_Lpi2c0,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.name = "i2c0",
|
||||
},
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C1
|
||||
{
|
||||
.i2c_base = LPI2C1,
|
||||
.baud = 100000U,
|
||||
.clock_ip_name = kCLOCK_Lpi2c1,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.name = "i2c1",
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static rt_ssize_t lpc_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
|
||||
{
|
||||
struct rt_i2c_msg *msg;
|
||||
lpi2c_master_transfer_t xfer = {0};
|
||||
rt_uint32_t i;
|
||||
rt_ssize_t ret = 0;
|
||||
|
||||
struct mcx_i2c_bus *priv = (struct mcx_i2c_bus *)bus;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
msg = &msgs[i];
|
||||
|
||||
if (msg->flags & RT_I2C_RD)
|
||||
{
|
||||
xfer.slaveAddress = msg->addr;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = 0;
|
||||
xfer.subaddressSize = 0;
|
||||
xfer.data = msg->buf;
|
||||
xfer.dataSize = msg->len;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
xfer.flags |= kLPI2C_TransferRepeatedStartFlag;
|
||||
}
|
||||
|
||||
if (i != num - 1)
|
||||
{
|
||||
xfer.flags |= kLPI2C_TransferNoStopFlag;
|
||||
}
|
||||
|
||||
if (LPI2C_MasterTransferBlocking(priv->i2c_base, &xfer) != kStatus_Success)
|
||||
{
|
||||
LOG_D("i2c bus read failed!\n");
|
||||
return i;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xfer.slaveAddress = msg->addr;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = 0;
|
||||
xfer.subaddressSize = 0;
|
||||
xfer.data = msg->buf;
|
||||
xfer.dataSize = msg->len;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
xfer.flags |= kLPI2C_TransferRepeatedStartFlag;
|
||||
}
|
||||
|
||||
if (i != num - 1)
|
||||
{
|
||||
xfer.flags |= kLPI2C_TransferNoStopFlag;
|
||||
}
|
||||
|
||||
if (LPI2C_MasterTransferBlocking(priv->i2c_base, &xfer) != kStatus_Success)
|
||||
{
|
||||
LOG_D("i2c bus write failed!\n");
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
ret = i;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rt_i2c_bus_device_ops i2c_ops = {
|
||||
.master_xfer = lpc_i2c_xfer,
|
||||
.slave_xfer = RT_NULL,
|
||||
.i2c_bus_control = RT_NULL,
|
||||
};
|
||||
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
int i;
|
||||
lpi2c_master_config_t masterConfig;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(i2c_buses); i++)
|
||||
{
|
||||
struct mcx_i2c_bus *priv = &i2c_buses[i];
|
||||
|
||||
CLOCK_SetIpSrc(priv->clock_ip_name, priv->clock_ip_src);
|
||||
|
||||
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
||||
masterConfig.baudRate_Hz = priv->baud;
|
||||
|
||||
LPI2C_MasterInit(priv->i2c_base, &masterConfig, CLOCK_GetIpFreq(priv->clock_ip_name));
|
||||
|
||||
priv->i2c_bus.ops = &i2c_ops;
|
||||
|
||||
rt_i2c_bus_device_register(&priv->i2c_bus, priv->name);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
||||
|
||||
#endif /* RT_USING_I2C */
|
||||
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-03-24 YangXi the first version.
|
||||
*/
|
||||
|
||||
#include "drv_pin.h"
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_port.h"
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
|
||||
#define DBG_TAG "drv.pin"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#define GET_GPIO_PORT(x) ((x) / 32)
|
||||
#define GET_GPIO_PIN(x) ((x) % 32)
|
||||
|
||||
static struct rt_pin_ops mcx_pin_ops;
|
||||
|
||||
static GPIO_Type *GPIO_TYPE_TBL[] = GPIO_BASE_PTRS;
|
||||
static PORT_Type *PORT_TYPE_TBL[] = PORT_BASE_PTRS;
|
||||
static IRQn_Type IRQ_TYPE_TBL[] = PORT_IRQS;
|
||||
|
||||
|
||||
#define PIN2GPIO(x) GPIO_TYPE_TBL[GET_GPIO_PORT(x)]
|
||||
#define PIN2PORT(x) PORT_TYPE_TBL[GET_GPIO_PORT(x)]
|
||||
#define PIN2IRQ(x) IRQ_TYPE_TBL[GET_GPIO_PORT(x)]
|
||||
|
||||
struct rt_pin_irq_hdr pin_irq_hdr_tab[32*5] = {0};
|
||||
|
||||
static void mcx_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
||||
{
|
||||
port_pin_config_t port_pin_config = {0};
|
||||
gpio_pin_config_t gpio_pin_config = {0};
|
||||
|
||||
port_pin_config.mux = kPORT_MuxAsGpio;
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case PIN_MODE_OUTPUT:
|
||||
case PIN_MODE_OUTPUT_OD: /* MCX E2 does not support OD. */
|
||||
{
|
||||
gpio_pin_config.pinDirection = kGPIO_DigitalOutput;
|
||||
port_pin_config.pullSelect = kPORT_PullDisable;
|
||||
}
|
||||
break;
|
||||
|
||||
case PIN_MODE_INPUT:
|
||||
{
|
||||
gpio_pin_config.pinDirection = kGPIO_DigitalInput;
|
||||
port_pin_config.pullSelect = kPORT_PullDisable;
|
||||
}
|
||||
break;
|
||||
|
||||
case PIN_MODE_INPUT_PULLDOWN:
|
||||
{
|
||||
gpio_pin_config.pinDirection = kGPIO_DigitalInput;
|
||||
port_pin_config.pullSelect = kPORT_PullDown;
|
||||
}
|
||||
break;
|
||||
|
||||
case PIN_MODE_INPUT_PULLUP:
|
||||
{
|
||||
gpio_pin_config.pinDirection = kGPIO_DigitalInput;
|
||||
port_pin_config.pullSelect = kPORT_PullUp;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
PORT_SetPinConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), &port_pin_config);
|
||||
GPIO_PinInit(PIN2GPIO(pin), GET_GPIO_PIN(pin) , &gpio_pin_config);
|
||||
}
|
||||
|
||||
|
||||
static void mcx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
|
||||
{
|
||||
GPIO_PinWrite(PIN2GPIO(pin), GET_GPIO_PIN(pin), value);
|
||||
}
|
||||
|
||||
static rt_ssize_t mcx_pin_read(rt_device_t dev, rt_base_t pin)
|
||||
{
|
||||
return GPIO_PinRead(PIN2GPIO(pin), GET_GPIO_PIN(pin)) ? 1 : 0;
|
||||
}
|
||||
|
||||
|
||||
rt_inline void pin_irq_handler(uint8_t gpio_idx)
|
||||
{
|
||||
int i;
|
||||
|
||||
rt_interrupt_enter();
|
||||
|
||||
uint32_t INTFLAG = PORT_GetPinsInterruptFlags(PORT_TYPE_TBL[gpio_idx]);
|
||||
PORT_ClearPinsInterruptFlags(PORT_TYPE_TBL[gpio_idx], INTFLAG);
|
||||
|
||||
|
||||
for(i=0; i<ARRAY_SIZE(pin_irq_hdr_tab); i++)
|
||||
{
|
||||
if((INTFLAG & (1<<GET_GPIO_PIN(pin_irq_hdr_tab[i].pin))) && pin_irq_hdr_tab[i].hdr && (GET_GPIO_PORT(pin_irq_hdr_tab[i].pin)) == gpio_idx)
|
||||
{
|
||||
pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args);
|
||||
}
|
||||
}
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void PORTA_IRQHandler(void)
|
||||
{
|
||||
pin_irq_handler(0);
|
||||
}
|
||||
|
||||
void PORTB_IRQHandler(void)
|
||||
{
|
||||
pin_irq_handler(1);
|
||||
}
|
||||
|
||||
void PORTC_IRQHandler(void)
|
||||
{
|
||||
pin_irq_handler(2);
|
||||
}
|
||||
|
||||
void PORTD_IRQHandler(void)
|
||||
{
|
||||
pin_irq_handler(3);
|
||||
}
|
||||
|
||||
void PORTE_IRQHandler(void)
|
||||
{
|
||||
pin_irq_handler(4);
|
||||
}
|
||||
|
||||
|
||||
static rt_err_t mcx_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case PIN_IRQ_MODE_RISING:
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptRisingEdge);
|
||||
break;
|
||||
case PIN_IRQ_MODE_FALLING:
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptFallingEdge);
|
||||
break;
|
||||
case PIN_IRQ_MODE_RISING_FALLING:
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptEitherEdge);
|
||||
break;
|
||||
case PIN_IRQ_MODE_HIGH_LEVEL:
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptLogicOne);
|
||||
break;
|
||||
case PIN_IRQ_MODE_LOW_LEVEL:
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptLogicZero);
|
||||
break;
|
||||
}
|
||||
|
||||
pin_irq_hdr_tab[pin].pin = pin;
|
||||
pin_irq_hdr_tab[pin].mode = mode;
|
||||
pin_irq_hdr_tab[pin].hdr = hdr;
|
||||
pin_irq_hdr_tab[pin].args = args;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t mcx_pin_detach_irq(struct rt_device *device, rt_base_t pin)
|
||||
{
|
||||
PORT_SetPinInterruptConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_InterruptOrDMADisabled);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t mcx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
|
||||
{
|
||||
if(enabled)
|
||||
{
|
||||
EnableIRQ(PIN2IRQ(pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
DisableIRQ(PIN2IRQ(pin));
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
int ret = RT_EOK;
|
||||
|
||||
mcx_pin_ops.pin_mode = mcx_pin_mode;
|
||||
mcx_pin_ops.pin_read = mcx_pin_read;
|
||||
mcx_pin_ops.pin_write = mcx_pin_write;
|
||||
mcx_pin_ops.pin_attach_irq = mcx_pin_attach_irq;
|
||||
mcx_pin_ops.pin_detach_irq = mcx_pin_detach_irq;
|
||||
mcx_pin_ops.pin_irq_enable = mcx_pin_irq_enable;
|
||||
mcx_pin_ops.pin_get = RT_NULL,
|
||||
|
||||
ret = rt_device_pin_register("pin", &mcx_pin_ops, RT_NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
||||
|
||||
#endif /*RT_USING_PIN */
|
||||
|
||||
// end file
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-03-13 Liuguang the first version.
|
||||
* 2018-03-19 Liuguang add GPIO interrupt mode support.
|
||||
* 2024-02-06 yandld The first version for MCX
|
||||
*/
|
||||
|
||||
#ifndef __DRV_PIN_H__
|
||||
#define __DRV_PIN_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
|
||||
extern int rt_hw_pin_init(void);
|
||||
|
||||
#endif /* __DRV_PIN_H__ */
|
||||
@@ -0,0 +1,278 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-08-19 Alex Yang Add MCXA346 RTC driver for RT-Thread
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <sys/time.h>
|
||||
|
||||
#ifdef BSP_USING_RTC
|
||||
|
||||
#define DBG_TAG "drv.rtc"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#include "fsl_rtc.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
|
||||
/* Get RTC timestamp */
|
||||
static time_t get_rtc_timestamp(void)
|
||||
{
|
||||
rtc_datetime_t datetime;
|
||||
struct tm tm_new;
|
||||
|
||||
/* Get current time from RTC */
|
||||
RTC_GetDatetime(RTC, &datetime);
|
||||
|
||||
tm_new.tm_sec = datetime.second;
|
||||
tm_new.tm_min = datetime.minute;
|
||||
tm_new.tm_hour = datetime.hour;
|
||||
tm_new.tm_mday = datetime.day;
|
||||
tm_new.tm_mon = datetime.month - 1;
|
||||
tm_new.tm_year = datetime.year - 1900;
|
||||
tm_new.tm_isdst = 0;
|
||||
|
||||
LOG_D("get rtc time: %04d-%02d-%02d %02d:%02d:%02d",
|
||||
datetime.year, datetime.month, datetime.day,
|
||||
datetime.hour, datetime.minute, datetime.second);
|
||||
|
||||
return mktime(&tm_new);
|
||||
}
|
||||
|
||||
/* Set RTC timestamp */
|
||||
static rt_err_t set_rtc_time_stamp(time_t time_stamp)
|
||||
{
|
||||
rtc_datetime_t datetime;
|
||||
struct tm *time_tm;
|
||||
|
||||
time_tm = gmtime(&time_stamp);
|
||||
if (time_tm->tm_year < 70) /* Year should be >= 1970 */
|
||||
{
|
||||
LOG_E("Invalid year: %d", time_tm->tm_year + 1900);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
/* Convert to RTC datetime format */
|
||||
datetime.year = time_tm->tm_year + 1900;
|
||||
datetime.month = time_tm->tm_mon + 1;
|
||||
datetime.day = time_tm->tm_mday;
|
||||
datetime.hour = time_tm->tm_hour;
|
||||
datetime.minute = time_tm->tm_min;
|
||||
datetime.second = time_tm->tm_sec;
|
||||
|
||||
/* Set RTC time */
|
||||
RTC_StopTimer(RTC);
|
||||
|
||||
RTC_SetDatetime(RTC, &datetime);
|
||||
|
||||
RTC_StartTimer(RTC);
|
||||
|
||||
LOG_D("set rtc time: %04d-%02d-%02d %02d:%02d:%02d",
|
||||
datetime.year, datetime.month, datetime.day,
|
||||
datetime.hour, datetime.minute, datetime.second);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* RTC configuration */
|
||||
static rt_err_t rt_rtc_config(void)
|
||||
{
|
||||
rtc_config_t rtc_config;
|
||||
|
||||
/* Get default RTC configuration */
|
||||
RTC_GetDefaultConfig(&rtc_config);
|
||||
|
||||
/* Initialize RTC - Note: RTC_Init returns void, not status */
|
||||
RTC_Init(RTC, &rtc_config);
|
||||
|
||||
/* Start RTC timer */
|
||||
RTC_StartTimer(RTC);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* RTC initialization */
|
||||
static rt_err_t rtc_init(void)
|
||||
{
|
||||
|
||||
/* Configure RTC */
|
||||
if (rt_rtc_config() != RT_EOK)
|
||||
{
|
||||
LOG_E("RTC config failed.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
LOG_D("RTC initialized successfully");
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* Get RTC seconds */
|
||||
static rt_err_t rtc_get_secs(time_t *args)
|
||||
{
|
||||
RT_ASSERT(args != RT_NULL);
|
||||
|
||||
*args = get_rtc_timestamp();
|
||||
LOG_D("RTC: get rtc_time %x", *args);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* Set RTC seconds */
|
||||
static rt_err_t rtc_set_secs(time_t *args)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
RT_ASSERT(args != RT_NULL);
|
||||
|
||||
if (set_rtc_time_stamp(*args) != RT_EOK)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
LOG_D("RTC: set rtc_time %x", *args);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Get RTC alarm */
|
||||
static rt_err_t rtc_get_alarm(struct rt_rtc_wkalarm *wkalarm)
|
||||
{
|
||||
rtc_datetime_t datetime;
|
||||
|
||||
RT_ASSERT(wkalarm != RT_NULL);
|
||||
|
||||
/* Get alarm time from RTC */
|
||||
RTC_GetAlarm(RTC, &datetime);
|
||||
|
||||
/* Convert to wkalarm format */
|
||||
wkalarm->tm_sec = datetime.second;
|
||||
wkalarm->tm_min = datetime.minute;
|
||||
wkalarm->tm_hour = datetime.hour;
|
||||
wkalarm->tm_mday = datetime.day;
|
||||
wkalarm->tm_mon = datetime.month - 1;
|
||||
wkalarm->tm_year = datetime.year - 1900;
|
||||
|
||||
/* Check if alarm is enabled */
|
||||
wkalarm->enable = (RTC_GetEnabledInterrupts(RTC) & kRTC_AlarmInterruptEnable) ? 1 : 0;
|
||||
|
||||
LOG_D("RTC: get alarm %04d-%02d-%02d %02d:%02d:%02d (%s)",
|
||||
datetime.year, datetime.month, datetime.day,
|
||||
datetime.hour, datetime.minute, datetime.second,
|
||||
wkalarm->enable ? "ENABLED" : "DISABLED");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* Set RTC alarm */
|
||||
static rt_err_t rtc_set_alarm(struct rt_rtc_wkalarm *wkalarm)
|
||||
{
|
||||
rtc_datetime_t datetime;
|
||||
|
||||
RT_ASSERT(wkalarm != RT_NULL);
|
||||
|
||||
/* Convert from wkalarm format */
|
||||
datetime.year = wkalarm->tm_year + 1900;
|
||||
datetime.month = wkalarm->tm_mon + 1;
|
||||
datetime.day = wkalarm->tm_mday;
|
||||
datetime.hour = wkalarm->tm_hour;
|
||||
datetime.minute = wkalarm->tm_min;
|
||||
datetime.second = wkalarm->tm_sec;
|
||||
|
||||
/* Set alarm time */
|
||||
RTC_SetAlarm(RTC, &datetime);
|
||||
|
||||
/* Enable/disable alarm interrupt */
|
||||
if (wkalarm->enable)
|
||||
{
|
||||
RTC_EnableInterrupts(RTC, kRTC_AlarmInterruptEnable);
|
||||
EnableIRQ(RTC_IRQn); /* Use RTC_IRQn instead of RTC0_IRQn */
|
||||
LOG_D("RTC alarm enabled");
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable);
|
||||
LOG_D("RTC alarm disabled");
|
||||
}
|
||||
|
||||
LOG_D("RTC: set alarm %04d-%02d-%02d %02d:%02d:%02d",
|
||||
datetime.year, datetime.month, datetime.day,
|
||||
datetime.hour, datetime.minute, datetime.second);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* RTC operations structure */
|
||||
static const struct rt_rtc_ops rtc_ops =
|
||||
{
|
||||
rtc_init,
|
||||
rtc_get_secs,
|
||||
rtc_set_secs,
|
||||
rtc_get_alarm,
|
||||
rtc_set_alarm,
|
||||
RT_NULL, /* get_timeval */
|
||||
RT_NULL, /* set_timeval */
|
||||
};
|
||||
|
||||
static rt_rtc_dev_t mcxa_rtc_dev;
|
||||
|
||||
/* RTC interrupt handler */
|
||||
void RTC_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
/* Get interrupt status */
|
||||
uint32_t status = RTC_GetStatusFlags(RTC);
|
||||
|
||||
/* Handle alarm interrupt */
|
||||
if (status & kRTC_AlarmFlag)
|
||||
{
|
||||
/* Clear alarm flag */
|
||||
RTC_ClearStatusFlags(RTC, kRTC_AlarmFlag);
|
||||
|
||||
LOG_D("RTC alarm triggered");
|
||||
|
||||
/* If alarm framework is available, notify it */
|
||||
#ifdef RT_USING_ALARM
|
||||
/* Send alarm event to alarm thread */
|
||||
rt_event_send(&_container.event, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Handle seconds interrupt if needed */
|
||||
if (status & kRTC_SecondsInterruptEnable)
|
||||
{
|
||||
LOG_D("RTC seconds interrupt");
|
||||
}
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/* Hardware RTC initialization */
|
||||
int rt_hw_rtc_init(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
/* Set RTC operations */
|
||||
mcxa_rtc_dev.ops = &rtc_ops;
|
||||
|
||||
/* Register RTC device */
|
||||
result = rt_hw_rtc_register(&mcxa_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
LOG_E("RTC register failed, err code: %d", result);
|
||||
return result;
|
||||
}
|
||||
|
||||
LOG_D("RTC init success");
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
|
||||
|
||||
#endif /* BSP_USING_RTC */
|
||||
@@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-1 hywing The first version for MCXA
|
||||
*/
|
||||
#include "rtdevice.h"
|
||||
#include "drv_spi.h"
|
||||
#include "fsl_lpspi.h"
|
||||
|
||||
|
||||
#ifdef RT_USING_SPI
|
||||
|
||||
#define DBG_TAG "drv.spi"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_SPI0
|
||||
SPI0_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
SPI1_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mcx_spi_bus
|
||||
{
|
||||
struct rt_spi_bus spi_bus;
|
||||
LPSPI_Type *spi_base;
|
||||
clock_ip_name_t clock_ip_name;
|
||||
clock_ip_src_t clock_ip_src;
|
||||
rt_sem_t sem;
|
||||
char *name;
|
||||
};
|
||||
|
||||
static struct mcx_spi_bus mcx_spi_buses[] =
|
||||
{
|
||||
#ifdef BSP_USING_SPI0
|
||||
{
|
||||
.spi_base = LPSPI0,
|
||||
.clock_ip_name = kCLOCK_Lpspi0,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.name = "spi0",
|
||||
},
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI1
|
||||
{
|
||||
.spi_base = LPSPI1,
|
||||
.clock_ip_name = kCLOCK_Lpspi1,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.name = "spi1",
|
||||
},
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI2
|
||||
{
|
||||
.spi_base = LPSPI2,
|
||||
.clock_ip_name = kCLOCK_Lpspi2,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.name = "spi2",
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
|
||||
{
|
||||
struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device));
|
||||
if (!spi_device)
|
||||
{
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
return rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL);
|
||||
}
|
||||
|
||||
static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
{
|
||||
lpspi_transfer_t transfer = {0};
|
||||
status_t status;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(device->bus != RT_NULL);
|
||||
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
|
||||
|
||||
struct mcx_spi_bus *spi = device->bus->parent.user_data;
|
||||
|
||||
if (message->cs_take)
|
||||
{
|
||||
rt_pin_write(device->cs_pin, PIN_LOW);
|
||||
}
|
||||
|
||||
transfer.dataSize = message->length;
|
||||
transfer.rxData = (uint8_t *)(message->recv_buf);
|
||||
transfer.txData = (uint8_t *)(message->send_buf);
|
||||
transfer.configFlags = kLPSPI_MasterPcs0;
|
||||
|
||||
// Use blocking transfer instead of DMA
|
||||
status = LPSPI_MasterTransferBlocking(spi->spi_base, &transfer);
|
||||
|
||||
if (message->cs_release)
|
||||
{
|
||||
rt_pin_write(device->cs_pin, PIN_HIGH);
|
||||
}
|
||||
|
||||
if (status != kStatus_Success)
|
||||
{
|
||||
return 0; // Transfer failed
|
||||
}
|
||||
|
||||
return message->length;
|
||||
}
|
||||
|
||||
|
||||
static struct rt_spi_ops lpc_spi_ops =
|
||||
{
|
||||
.configure = spi_configure,
|
||||
.xfer = spixfer};
|
||||
|
||||
int rt_hw_spi_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mcx_spi_buses); i++)
|
||||
{
|
||||
struct mcx_spi_bus *priv = &mcx_spi_buses[i];
|
||||
|
||||
|
||||
CLOCK_SetIpSrc(priv->clock_ip_name, priv->clock_ip_src);
|
||||
|
||||
priv->spi_bus.parent.user_data = &mcx_spi_buses[i];
|
||||
priv->sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
lpspi_master_config_t masterConfig;
|
||||
LPSPI_MasterGetDefaultConfig(&masterConfig);
|
||||
masterConfig.baudRate = 10 * 1000 * 1000;
|
||||
masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
|
||||
masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
|
||||
masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
|
||||
|
||||
LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetIpFreq(priv->clock_ip_name));
|
||||
|
||||
rt_spi_bus_register(&priv->spi_bus, priv->name, &lpc_spi_ops);
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_spi_init);
|
||||
|
||||
#endif /* RT_USING_SPI */
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-03-22 Jisheng Zhang The first version for mcxn
|
||||
*/
|
||||
|
||||
#ifndef DRV_SPI_H
|
||||
#define DRV_SPI_H
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin);
|
||||
|
||||
int rt_hw_spi_init(void);
|
||||
|
||||
#endif //DRV_SPI_H
|
||||
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-06 yandld The first version for MCX
|
||||
* 2024-11-11 hywing add more UART channels
|
||||
*/
|
||||
#include <rtdevice.h>
|
||||
#include "drv_uart.h"
|
||||
#include "fsl_lpuart.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
|
||||
#define DBG_TAG "drv.uart"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
struct mcx_uart
|
||||
{
|
||||
struct rt_serial_device *serial;
|
||||
LPUART_Type *uart_base;
|
||||
IRQn_Type irqn;
|
||||
clock_ip_name_t clock_ip_name;
|
||||
clock_ip_src_t clock_ip_src;
|
||||
char *device_name;
|
||||
};
|
||||
|
||||
static void uart_isr(struct rt_serial_device *serial);
|
||||
|
||||
#if defined(BSP_USING_UART0)
|
||||
struct rt_serial_device serial0;
|
||||
|
||||
void LPUART0_IRQHandler(void)
|
||||
{
|
||||
uart_isr(&serial0);
|
||||
}
|
||||
#endif
|
||||
#if defined(BSP_USING_UART1)
|
||||
struct rt_serial_device serial1;
|
||||
|
||||
void LPUART1_IRQHandler(void)
|
||||
{
|
||||
uart_isr(&serial1);
|
||||
}
|
||||
#endif
|
||||
#if defined(BSP_USING_UART2)
|
||||
struct rt_serial_device serial2;
|
||||
|
||||
void LPUART2_IRQHandler(void)
|
||||
{
|
||||
uart_isr(&serial2);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct mcx_uart uarts[] =
|
||||
{
|
||||
#ifdef BSP_USING_UART0
|
||||
{
|
||||
.serial = &serial0,
|
||||
.uart_base = LPUART0,
|
||||
.irqn = LPUART0_IRQn,
|
||||
.clock_ip_name = kCLOCK_Lpuart0,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.device_name = "uart0",
|
||||
},
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
{
|
||||
.serial = &serial1,
|
||||
.uart_base = LPUART1,
|
||||
.irqn = LPUART1_IRQn,
|
||||
.clock_ip_name = kCLOCK_Lpuart1,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.device_name = "uart1",
|
||||
},
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
{
|
||||
.serial = &serial2,
|
||||
.uart_base = LPUART2,
|
||||
.irqn = LPUART2_IRQn,
|
||||
.clock_ip_name = kCLOCK_Lpuart2,
|
||||
.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
|
||||
.device_name = "uart2",
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct mcx_uart *uart;
|
||||
lpuart_config_t config;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
uart = (struct mcx_uart *)serial->parent.user_data;
|
||||
|
||||
CLOCK_SetIpSrc(uart->clock_ip_name, uart->clock_ip_src);
|
||||
|
||||
LPUART_GetDefaultConfig(&config);
|
||||
config.baudRate_Bps = cfg->baud_rate;
|
||||
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_7:
|
||||
config.dataBitsCount = kLPUART_SevenDataBits;
|
||||
break;
|
||||
|
||||
default:
|
||||
config.dataBitsCount = kLPUART_EightDataBits;
|
||||
break;
|
||||
}
|
||||
|
||||
config.enableTx = true;
|
||||
config.enableRx = true;
|
||||
|
||||
LPUART_Init(uart->uart_base, &config, CLOCK_GetIpFreq(uart->clock_ip_name));
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t mcx_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||
DisableIRQ(uart->irqn);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||
EnableIRQ(uart->irqn);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int mcx_putc(struct rt_serial_device *serial, char ch)
|
||||
{
|
||||
struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data;
|
||||
|
||||
while (!(kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(uart->uart_base)));
|
||||
LPUART_WriteByte(uart->uart_base, ch);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int mcx_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data;
|
||||
|
||||
if (kLPUART_RxDataRegFullInterruptEnable & LPUART_GetStatusFlags(uart->uart_base))
|
||||
{
|
||||
return LPUART_ReadByte(uart->uart_base);
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Uart common interrupt process. This need add to uart ISR.
|
||||
*
|
||||
* @param serial serial device
|
||||
*/
|
||||
static void uart_isr(struct rt_serial_device *serial)
|
||||
{
|
||||
struct mcx_uart *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
uart = (struct mcx_uart *)serial->parent.user_data;
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
/* UART in mode Receiver -------------------------------------------------*/
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops mcx_uart_ops =
|
||||
{
|
||||
mcx_configure,
|
||||
mcx_control,
|
||||
mcx_putc,
|
||||
mcx_getc,
|
||||
};
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
|
||||
{
|
||||
uarts[i].serial->ops = &mcx_uart_ops;
|
||||
uarts[i].serial->config = config;
|
||||
|
||||
/* register UART device */
|
||||
rt_hw_serial_register(uarts[i].serial, uarts[i].device_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, (void *)&uarts[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_uart_init);
|
||||
#endif /*BSP_USING_SERIAL */
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-06 yandld The first version for MCX
|
||||
*/
|
||||
|
||||
#ifndef __DRV_UART_H__
|
||||
#define __DRV_UART_H__
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
|
||||
|
||||
#endif /* __DRV_UART_H__ */
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-11-25 hywing The first version for NXP MCXA153 Board
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "drv_wdt.h"
|
||||
|
||||
#include "fsl_wdog32.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
#ifdef RT_USING_WDT
|
||||
|
||||
#define WDT WDOG
|
||||
#define WDT_CLOCK_SOURCE kWDOG32_ClockSource1 /* 0: Bus, 1: LPO, 2: SOSC, 3: SIRC */
|
||||
#define WDT_CLOCK_SOURCE_FREQ (128 * 1000 / 256) /* 128kHz LPO divided by 256 */
|
||||
|
||||
#define APP_WDT_IRQn WDOG_EWM_IRQn
|
||||
#define APP_WDT_IRQ_HANDLER WDOG_EWM_IRQHandler
|
||||
|
||||
struct mcx_wdt
|
||||
{
|
||||
rt_watchdog_t watchdog;
|
||||
WDOG_Type *wdt_base;
|
||||
};
|
||||
|
||||
static struct mcx_wdt wdt_dev;
|
||||
|
||||
void APP_WDT_IRQ_HANDLER(void)
|
||||
{
|
||||
/* ---- There's no WARN feature for WDOG32, will reset. ---- */
|
||||
for (;;)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t wdt_init(rt_watchdog_t *wdt)
|
||||
{
|
||||
wdog32_config_t config;
|
||||
|
||||
WDOG32_GetDefaultConfig(&config);
|
||||
|
||||
config.enableWdog32 = false;
|
||||
config.clockSource = WDT_CLOCK_SOURCE;
|
||||
config.prescaler = kWDOG32_ClockPrescalerDivide256;
|
||||
config.timeoutValue = WDT_CLOCK_SOURCE_FREQ * 5;
|
||||
config.enableInterrupt = true;
|
||||
|
||||
WDOG32_Init(WDT, &config);
|
||||
NVIC_EnableIRQ(APP_WDT_IRQn);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
|
||||
{
|
||||
/* Feed fast path */
|
||||
if (cmd == RT_DEVICE_CTRL_WDT_KEEPALIVE)
|
||||
{
|
||||
WDOG32_Refresh(wdt_dev.wdt_base);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
__disable_irq();
|
||||
WDOG32_Unlock(wdt_dev.wdt_base);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_WDT_START:
|
||||
WDOG32_Enable(wdt_dev.wdt_base);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_WDT_STOP:
|
||||
WDOG32_Disable(wdt_dev.wdt_base);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
|
||||
if (arg != RT_NULL)
|
||||
{
|
||||
uint32_t timeout = *((uint32_t *)arg);
|
||||
timeout = timeout * WDT_CLOCK_SOURCE_FREQ;
|
||||
WDOG32_SetTimeoutValue(wdt_dev.wdt_base, timeout);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
__enable_irq();
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static struct rt_watchdog_ops wdt_ops =
|
||||
{
|
||||
wdt_init,
|
||||
wdt_control,
|
||||
};
|
||||
|
||||
int rt_hw_wdt_init(void)
|
||||
{
|
||||
wdt_dev.wdt_base = WDT;
|
||||
wdt_dev.watchdog.ops = &wdt_ops;
|
||||
|
||||
if (rt_hw_watchdog_register(&wdt_dev.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
|
||||
{
|
||||
rt_kprintf("wdt register failed\n");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
INIT_BOARD_EXPORT(rt_hw_wdt_init);
|
||||
|
||||
#endif /* RT_USING_WDT */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-11-25 hywing The first version for NXP MCXA153 Board
|
||||
*/
|
||||
|
||||
#ifndef __DRV_WDT_H__
|
||||
#define __DRV_WDT_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
int rt_hw_wdt_init(void);
|
||||
|
||||
#endif /* __DRV_WDT_H__ */
|
||||
@@ -0,0 +1,426 @@
|
||||
CONFIG_SOC_MCX=y
|
||||
|
||||
#
|
||||
# RT-Thread Kernel
|
||||
#
|
||||
|
||||
#
|
||||
# klibc options
|
||||
#
|
||||
|
||||
#
|
||||
# rt_vsnprintf options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
|
||||
# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
|
||||
# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
|
||||
# end of rt_vsnprintf options
|
||||
|
||||
#
|
||||
# rt_vsscanf options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
|
||||
# end of rt_vsscanf options
|
||||
|
||||
#
|
||||
# rt_memset options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
|
||||
# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
|
||||
# end of rt_memset options
|
||||
|
||||
#
|
||||
# rt_memcpy options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
|
||||
# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
|
||||
# end of rt_memcpy options
|
||||
|
||||
#
|
||||
# rt_memmove options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
|
||||
# end of rt_memmove options
|
||||
|
||||
#
|
||||
# rt_memcmp options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
|
||||
# end of rt_memcmp options
|
||||
|
||||
#
|
||||
# rt_strstr options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
|
||||
# end of rt_strstr options
|
||||
|
||||
#
|
||||
# rt_strcasecmp options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
|
||||
# end of rt_strcasecmp options
|
||||
|
||||
#
|
||||
# rt_strncpy options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
|
||||
# end of rt_strncpy options
|
||||
|
||||
#
|
||||
# rt_strcpy options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
|
||||
# end of rt_strcpy options
|
||||
|
||||
#
|
||||
# rt_strncmp options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
|
||||
# end of rt_strncmp options
|
||||
|
||||
#
|
||||
# rt_strcmp options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
|
||||
# end of rt_strcmp options
|
||||
|
||||
#
|
||||
# rt_strlen options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
|
||||
# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
|
||||
# end of rt_strlen options
|
||||
|
||||
#
|
||||
# rt_strnlen options
|
||||
#
|
||||
# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
|
||||
# end of rt_strnlen options
|
||||
|
||||
# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
|
||||
# end of klibc options
|
||||
|
||||
CONFIG_RT_NAME_MAX=16
|
||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||
# CONFIG_RT_USING_NANO is not set
|
||||
# CONFIG_RT_USING_SMART is not set
|
||||
# CONFIG_RT_USING_AMP is not set
|
||||
# CONFIG_RT_USING_SMP is not set
|
||||
CONFIG_RT_CPUS_NR=1
|
||||
CONFIG_RT_ALIGN_SIZE=8
|
||||
# CONFIG_RT_THREAD_PRIORITY_8 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_32=y
|
||||
# CONFIG_RT_THREAD_PRIORITY_256 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_MAX=32
|
||||
CONFIG_RT_TICK_PER_SECOND=1000
|
||||
CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||
CONFIG_RT_USING_HOOK=y
|
||||
CONFIG_RT_HOOK_USING_FUNC_PTR=y
|
||||
# CONFIG_RT_USING_HOOKLIST is not set
|
||||
CONFIG_RT_USING_IDLE_HOOK=y
|
||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||
CONFIG_RT_USING_TIMER_SOFT=y
|
||||
CONFIG_RT_TIMER_THREAD_PRIO=4
|
||||
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
|
||||
# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
|
||||
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
|
||||
|
||||
#
|
||||
# kservice options
|
||||
#
|
||||
# CONFIG_RT_USING_TINY_FFS is not set
|
||||
# end of kservice options
|
||||
|
||||
CONFIG_RT_USING_DEBUG=y
|
||||
CONFIG_RT_DEBUGING_ASSERT=y
|
||||
CONFIG_RT_DEBUGING_COLOR=y
|
||||
CONFIG_RT_DEBUGING_CONTEXT=y
|
||||
# CONFIG_RT_DEBUGING_AUTO_INIT is not set
|
||||
# CONFIG_RT_USING_CI_ACTION is not set
|
||||
|
||||
#
|
||||
# Inter-Thread communication
|
||||
#
|
||||
CONFIG_RT_USING_SEMAPHORE=y
|
||||
CONFIG_RT_USING_MUTEX=y
|
||||
CONFIG_RT_USING_EVENT=y
|
||||
CONFIG_RT_USING_MAILBOX=y
|
||||
CONFIG_RT_USING_MESSAGEQUEUE=y
|
||||
# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
|
||||
# CONFIG_RT_USING_SIGNALS is not set
|
||||
# end of Inter-Thread communication
|
||||
|
||||
#
|
||||
# Memory Management
|
||||
#
|
||||
CONFIG_RT_USING_MEMPOOL=y
|
||||
CONFIG_RT_USING_SMALL_MEM=y
|
||||
# CONFIG_RT_USING_SLAB is not set
|
||||
# CONFIG_RT_USING_MEMHEAP is not set
|
||||
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
|
||||
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
|
||||
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
|
||||
# CONFIG_RT_USING_USERHEAP is not set
|
||||
# CONFIG_RT_USING_NOHEAP is not set
|
||||
# CONFIG_RT_USING_MEMTRACE is not set
|
||||
# CONFIG_RT_USING_HEAP_ISR is not set
|
||||
CONFIG_RT_USING_HEAP=y
|
||||
# end of Memory Management
|
||||
|
||||
CONFIG_RT_USING_DEVICE=y
|
||||
# CONFIG_RT_USING_DEVICE_OPS is not set
|
||||
# CONFIG_RT_USING_INTERRUPT_INFO is not set
|
||||
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
|
||||
CONFIG_RT_USING_CONSOLE=y
|
||||
CONFIG_RT_CONSOLEBUF_SIZE=128
|
||||
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
|
||||
CONFIG_RT_VER_NUM=0x50201
|
||||
# CONFIG_RT_USING_STDC_ATOMIC is not set
|
||||
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
|
||||
# end of RT-Thread Kernel
|
||||
|
||||
CONFIG_RT_USING_HW_ATOMIC=y
|
||||
CONFIG_RT_USING_CPU_FFS=y
|
||||
CONFIG_ARCH_ARM=y
|
||||
CONFIG_ARCH_ARM_CORTEX_M=y
|
||||
CONFIG_ARCH_ARM_CORTEX_FPU=y
|
||||
CONFIG_ARCH_ARM_CORTEX_M4=y
|
||||
|
||||
#
|
||||
# RT-Thread Components
|
||||
#
|
||||
CONFIG_RT_USING_COMPONENTS_INIT=y
|
||||
CONFIG_RT_USING_USER_MAIN=y
|
||||
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
# CONFIG_RT_USING_LEGACY is not set
|
||||
CONFIG_RT_USING_MSH=y
|
||||
CONFIG_RT_USING_FINSH=y
|
||||
CONFIG_FINSH_USING_MSH=y
|
||||
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||
CONFIG_FINSH_USING_HISTORY=y
|
||||
CONFIG_FINSH_HISTORY_LINES=5
|
||||
# CONFIG_FINSH_USING_WORD_OPERATION is not set
|
||||
CONFIG_FINSH_USING_SYMTAB=y
|
||||
CONFIG_FINSH_CMD_SIZE=80
|
||||
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
|
||||
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||
# CONFIG_FINSH_USING_AUTH is not set
|
||||
CONFIG_FINSH_ARG_MAX=10
|
||||
CONFIG_FINSH_USING_OPTION_COMPLETION=y
|
||||
|
||||
#
|
||||
# DFS: device virtual file system
|
||||
#
|
||||
CONFIG_RT_USING_DFS=y
|
||||
CONFIG_DFS_USING_POSIX=y
|
||||
CONFIG_DFS_USING_WORKDIR=y
|
||||
# CONFIG_RT_USING_DFS_MNTTABLE is not set
|
||||
CONFIG_DFS_FD_MAX=16
|
||||
CONFIG_RT_USING_DFS_V1=y
|
||||
# CONFIG_RT_USING_DFS_V2 is not set
|
||||
CONFIG_DFS_FILESYSTEMS_MAX=4
|
||||
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
|
||||
# CONFIG_RT_USING_DFS_ELMFAT is not set
|
||||
CONFIG_RT_USING_DFS_DEVFS=y
|
||||
# CONFIG_RT_USING_DFS_ROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_CROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_RAMFS is not set
|
||||
# CONFIG_RT_USING_DFS_TMPFS is not set
|
||||
# CONFIG_RT_USING_DFS_MQUEUE is not set
|
||||
# end of DFS: device virtual file system
|
||||
|
||||
# CONFIG_RT_USING_FAL is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
# CONFIG_RT_USING_DM is not set
|
||||
# CONFIG_RT_USING_DEV_BUS is not set
|
||||
CONFIG_RT_USING_DEVICE_IPC=y
|
||||
CONFIG_RT_UNAMED_PIPE_NUMBER=64
|
||||
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
|
||||
CONFIG_RT_USING_SERIAL=y
|
||||
CONFIG_RT_USING_SERIAL_V1=y
|
||||
# CONFIG_RT_USING_SERIAL_V2 is not set
|
||||
CONFIG_RT_SERIAL_USING_DMA=y
|
||||
CONFIG_RT_SERIAL_RB_BUFSZ=64
|
||||
# CONFIG_RT_USING_SERIAL_BYPASS is not set
|
||||
# CONFIG_RT_USING_CAN is not set
|
||||
# CONFIG_RT_USING_CPUTIME is not set
|
||||
CONFIG_RT_USING_I2C=y
|
||||
# CONFIG_RT_I2C_DEBUG is not set
|
||||
CONFIG_RT_USING_I2C_BITOPS=y
|
||||
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
|
||||
# CONFIG_RT_USING_SOFT_I2C is not set
|
||||
# CONFIG_RT_USING_PHY is not set
|
||||
# CONFIG_RT_USING_PHY_V2 is not set
|
||||
CONFIG_RT_USING_ADC=y
|
||||
# CONFIG_RT_USING_DAC is not set
|
||||
# CONFIG_RT_USING_NULL is not set
|
||||
# CONFIG_RT_USING_ZERO is not set
|
||||
# CONFIG_RT_USING_RANDOM is not set
|
||||
# CONFIG_RT_USING_PWM is not set
|
||||
# CONFIG_RT_USING_PULSE_ENCODER is not set
|
||||
# CONFIG_RT_USING_INPUT_CAPTURE is not set
|
||||
# CONFIG_RT_USING_MTD_NOR is not set
|
||||
# CONFIG_RT_USING_MTD_NAND is not set
|
||||
# CONFIG_RT_USING_PM is not set
|
||||
CONFIG_RT_USING_RTC=y
|
||||
# CONFIG_RT_USING_ALARM is not set
|
||||
# CONFIG_RT_USING_SOFT_RTC is not set
|
||||
# CONFIG_RT_USING_SDIO is not set
|
||||
CONFIG_RT_USING_SPI=y
|
||||
# CONFIG_RT_USING_SOFT_SPI is not set
|
||||
# CONFIG_RT_USING_QSPI is not set
|
||||
# CONFIG_RT_USING_SPI_MSD is not set
|
||||
# CONFIG_RT_USING_SFUD is not set
|
||||
# CONFIG_RT_USING_ENC28J60 is not set
|
||||
# CONFIG_RT_USING_SPI_WIFI is not set
|
||||
# CONFIG_RT_USING_WDT is not set
|
||||
# CONFIG_RT_USING_AUDIO is not set
|
||||
# CONFIG_RT_USING_SENSOR is not set
|
||||
# CONFIG_RT_USING_TOUCH is not set
|
||||
# CONFIG_RT_USING_LCD is not set
|
||||
# CONFIG_RT_USING_HWCRYPTO is not set
|
||||
# CONFIG_RT_USING_WIFI is not set
|
||||
# CONFIG_RT_USING_BLK is not set
|
||||
# CONFIG_RT_USING_VIRTIO is not set
|
||||
CONFIG_RT_USING_PIN=y
|
||||
# CONFIG_RT_USING_KTIME is not set
|
||||
CONFIG_RT_USING_HWTIMER=y
|
||||
# CONFIG_RT_USING_CHERRYUSB is not set
|
||||
# end of Device Drivers
|
||||
|
||||
#
|
||||
# C/C++ and POSIX layer
|
||||
#
|
||||
|
||||
#
|
||||
# ISO-ANSI C layer
|
||||
#
|
||||
|
||||
#
|
||||
# Timezone and Daylight Saving Time
|
||||
#
|
||||
# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
|
||||
CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
|
||||
CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
|
||||
CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
|
||||
CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
|
||||
# end of Timezone and Daylight Saving Time
|
||||
# end of ISO-ANSI C layer
|
||||
|
||||
#
|
||||
# POSIX (Portable Operating System Interface) layer
|
||||
#
|
||||
# CONFIG_RT_USING_POSIX_FS is not set
|
||||
# CONFIG_RT_USING_POSIX_DELAY is not set
|
||||
# CONFIG_RT_USING_POSIX_CLOCK is not set
|
||||
# CONFIG_RT_USING_POSIX_TIMER is not set
|
||||
# CONFIG_RT_USING_PTHREADS is not set
|
||||
# CONFIG_RT_USING_MODULE is not set
|
||||
|
||||
#
|
||||
# Interprocess Communication (IPC)
|
||||
#
|
||||
# CONFIG_RT_USING_POSIX_PIPE is not set
|
||||
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
|
||||
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
|
||||
|
||||
#
|
||||
# Socket is in the 'Network' category
|
||||
#
|
||||
# end of Interprocess Communication (IPC)
|
||||
# end of POSIX (Portable Operating System Interface) layer
|
||||
|
||||
# CONFIG_RT_USING_CPLUSPLUS is not set
|
||||
# end of C/C++ and POSIX layer
|
||||
|
||||
#
|
||||
# Network
|
||||
#
|
||||
# CONFIG_RT_USING_SAL is not set
|
||||
# CONFIG_RT_USING_NETDEV is not set
|
||||
# CONFIG_RT_USING_LWIP is not set
|
||||
# CONFIG_RT_USING_AT is not set
|
||||
# end of Network
|
||||
|
||||
#
|
||||
# Memory protection
|
||||
#
|
||||
# CONFIG_RT_USING_MEM_PROTECTION is not set
|
||||
# CONFIG_RT_USING_HW_STACK_GUARD is not set
|
||||
# end of Memory protection
|
||||
|
||||
#
|
||||
# Utilities
|
||||
#
|
||||
# CONFIG_RT_USING_RYM is not set
|
||||
# CONFIG_RT_USING_ULOG is not set
|
||||
# CONFIG_RT_USING_UTEST is not set
|
||||
# CONFIG_RT_USING_VAR_EXPORT is not set
|
||||
# CONFIG_RT_USING_RESOURCE_ID is not set
|
||||
# CONFIG_RT_USING_ADT is not set
|
||||
# CONFIG_RT_USING_RT_LINK is not set
|
||||
# end of Utilities
|
||||
|
||||
# CONFIG_RT_USING_VBUS is not set
|
||||
|
||||
#
|
||||
# Using USB legacy version
|
||||
#
|
||||
# CONFIG_RT_USING_USB_HOST is not set
|
||||
# CONFIG_RT_USING_USB_DEVICE is not set
|
||||
# end of Using USB legacy version
|
||||
|
||||
# CONFIG_RT_USING_FDT is not set
|
||||
# end of RT-Thread Components
|
||||
|
||||
#
|
||||
# RT-Thread Utestcases
|
||||
#
|
||||
# CONFIG_RT_USING_UTESTCASES is not set
|
||||
# end of RT-Thread Utestcases
|
||||
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
CONFIG_SOC_MCXE247=y
|
||||
|
||||
#
|
||||
# On-chip Peripheral Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_PIN=y
|
||||
CONFIG_BSP_USING_UART=y
|
||||
# CONFIG_BSP_USING_UART0 is not set
|
||||
# CONFIG_BSP_USING_UART1 is not set
|
||||
CONFIG_BSP_USING_UART2=y
|
||||
# CONFIG_BSP_USING_I2C is not set
|
||||
# CONFIG_BSP_USING_SPI is not set
|
||||
# CONFIG_BSP_USING_ADC is not set
|
||||
# CONFIG_BSP_USING_RTC is not set
|
||||
# CONFIG_BSP_USING_WDT is not set
|
||||
# CONFIG_BSP_USING_HWTIMER is not set
|
||||
# CONFIG_BSP_USING_PWM is not set
|
||||
# end of On-chip Peripheral Drivers
|
||||
|
||||
#
|
||||
# Board extended module Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_RW007 is not set
|
||||
# end of Board extended module Drivers
|
||||
# end of Hardware Drivers Config
|
||||
@@ -0,0 +1,17 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
config SOC_MCX
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M4
|
||||
default y
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../Libraries/Kconfig"
|
||||
rsource "board/Kconfig"
|
||||
@@ -0,0 +1,14 @@
|
||||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,83 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "nxp-mcx-cmsis-latest"),
|
||||
os.path.join("packages", "nxp-mcx-series-latest"),
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
if rtconfig.PLATFORM == 'armcc':
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
# overwrite cflags, because cflags has '--C99'
|
||||
CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
else:
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/Libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/Libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
src = Glob('*.c')
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,73 @@
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_RW007
|
||||
#include <rtdbg.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
#include <spi_wifi_rw007.h>
|
||||
|
||||
#define BOARD_RW007_DEVICE_NAME "rw007"
|
||||
|
||||
extern void spi_wifi_isr(int vector);
|
||||
|
||||
static void rw007_gpio_init(void)
|
||||
{
|
||||
/* Configure IO */
|
||||
rt_pin_mode(BOARD_RW007_RST_PIN, PIN_MODE_OUTPUT);
|
||||
rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
|
||||
|
||||
/* Reset rw007 and config mode */
|
||||
rt_pin_write(BOARD_RW007_RST_PIN, PIN_LOW);
|
||||
|
||||
rt_thread_delay(rt_tick_from_millisecond(100));
|
||||
rt_pin_write(BOARD_RW007_RST_PIN, PIN_HIGH);
|
||||
|
||||
/* Wait rw007 ready(exit busy stat) */
|
||||
while (!rt_pin_read(BOARD_RW007_INT_BUSY_PIN))
|
||||
{
|
||||
rt_thread_delay(5);
|
||||
}
|
||||
|
||||
rt_thread_delay(rt_tick_from_millisecond(200));
|
||||
rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
int wifi_spi_device_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
char sn_version[32];
|
||||
|
||||
struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device));
|
||||
if (!spi_device) return -1;
|
||||
|
||||
rw007_gpio_init();
|
||||
ret = rt_spi_bus_attach_device_cspin(spi_device, BOARD_RW007_DEVICE_NAME, BOARD_RW007_SPI_BUS_NAME, BOARD_RW007_CS_PIN, RT_NULL);
|
||||
if (ret != RT_EOK) return -2;
|
||||
|
||||
rt_hw_wifi_init("rw007");
|
||||
|
||||
rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
|
||||
rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
|
||||
|
||||
rw007_sn_get(sn_version);
|
||||
rt_kprintf("\nrw007 sn: [%s]\n", sn_version);
|
||||
rw007_version_get(sn_version);
|
||||
rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_APP_EXPORT(wifi_spi_device_init);
|
||||
|
||||
static void int_wifi_irq(void *p)
|
||||
{
|
||||
((void)p);
|
||||
spi_wifi_isr(0);
|
||||
}
|
||||
|
||||
void spi_wifi_hw_init(void)
|
||||
{
|
||||
rt_pin_attach_irq(BOARD_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
|
||||
rt_pin_irq_enable(BOARD_RW007_INT_BUSY_PIN, RT_TRUE);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-24 Magicoe first version
|
||||
* 2020-01-10 Kevin/Karl Add PS demo
|
||||
* 2020-09-21 supperthomas fix the main.c
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "drv_pin.h"
|
||||
|
||||
#define LED_PIN ((2 * 32) + 13) /* PTC13, RGB LED RED */
|
||||
#define BTN_PIN ((2 * 32) + 10) /* PTC10, SW3 (User) */
|
||||
|
||||
static rt_bool_t s_led_state = RT_FALSE; /* Current LED state */
|
||||
|
||||
static void app_btn_irq_callback(void *args)
|
||||
{
|
||||
RT_UNUSED(args);
|
||||
|
||||
rt_kprintf("SW3 pressed\n");
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
|
||||
rt_pin_write(LED_PIN, PIN_LOW);
|
||||
|
||||
rt_pin_mode(BTN_PIN, PIN_MODE_INPUT_PULLUP);
|
||||
rt_pin_attach_irq(BTN_PIN, PIN_IRQ_MODE_FALLING, app_btn_irq_callback, RT_NULL);
|
||||
rt_pin_irq_enable(BTN_PIN, PIN_IRQ_ENABLE);
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION);
|
||||
#elif defined(__clang__)
|
||||
rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION);
|
||||
#elif defined(__ICCARM__)
|
||||
rt_kprintf("using iccarm, version: %d\n", __VER__);
|
||||
#elif defined(__GNUC__)
|
||||
rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
|
||||
#endif
|
||||
|
||||
rt_kprintf("NXP MCXE247\r\n");
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* Toggle LED state */
|
||||
s_led_state = !s_led_state;
|
||||
rt_pin_write(LED_PIN, s_led_state ? PIN_HIGH : PIN_LOW);
|
||||
|
||||
rt_thread_mdelay(500); /* Delay 500mS */
|
||||
}
|
||||
}
|
||||
|
||||
// end file
|
||||
@@ -0,0 +1,175 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_MCXE247
|
||||
bool
|
||||
select SOC_MCXE247_SERIES
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
config BSP_USING_PIN
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
config BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
select RT_USING_UART
|
||||
default y
|
||||
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART0
|
||||
bool "Enable LPUART0"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART1
|
||||
bool "Enable LPUART1"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable LPUART2"
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
config BSP_USING_I2C
|
||||
bool "Enable I2C"
|
||||
select RT_USING_I2C
|
||||
default y
|
||||
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C0
|
||||
bool "Enable LPI2C0"
|
||||
default n
|
||||
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable LPI2C1"
|
||||
default y
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
config BSP_USING_SPI
|
||||
bool "Enable SPI"
|
||||
select RT_USING_SPI
|
||||
default y
|
||||
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI0
|
||||
bool "Enable LPSPI0"
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable LPSPI1"
|
||||
default y
|
||||
|
||||
config BSP_USING_SPI2
|
||||
bool "Enable LPSPI2"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
config BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
select RT_USING_ADC
|
||||
default y
|
||||
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
|
||||
config BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
config BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default y
|
||||
|
||||
config BSP_USING_WDT
|
||||
bool "Enable WatchDog"
|
||||
select RT_USING_WDT
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_HWTIMER
|
||||
config BSP_USING_HWTIMER
|
||||
bool "Enable Timer"
|
||||
select RT_USING_HWTIMER
|
||||
default y
|
||||
|
||||
if BSP_USING_HWTIMER
|
||||
config BSP_USING_CTIMER0
|
||||
bool "Enable CIMER0"
|
||||
default y
|
||||
|
||||
config BSP_USING_CTIMER1
|
||||
bool "Enable CIMER1"
|
||||
default n
|
||||
|
||||
config BSP_USING_CTIMER3
|
||||
bool "Enable CIMER3"
|
||||
default n
|
||||
|
||||
config BSP_USING_CTIMER4
|
||||
bool "Enable CIMER4"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_PWM
|
||||
config BSP_USING_PWM
|
||||
bool "Enable PWM"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
|
||||
if BSP_USING_PWM
|
||||
config BSP_USING_PWM0
|
||||
bool "Enable eFlex PWM0"
|
||||
default n
|
||||
config BSP_USING_PWM1
|
||||
bool "Enable eFlex PWM1"
|
||||
default n
|
||||
config BSP_USING_PWM2
|
||||
bool "Enable eFlex PWM2"
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
menuconfig BSP_USING_RW007
|
||||
bool "Enable RW007"
|
||||
default n
|
||||
select BSP_USING_SPI
|
||||
select BSP_USING_SPI1
|
||||
select PKG_USING_RW007
|
||||
select RT_USING_MEMPOOL
|
||||
select RW007_NOT_USE_EXAMPLE_DRIVERS
|
||||
|
||||
if BSP_USING_RW007
|
||||
config BOARD_RW007_SPI_BUS_NAME
|
||||
string "RW007 BUS NAME"
|
||||
default "spi1"
|
||||
|
||||
config BOARD_RW007_CS_PIN
|
||||
int "CS pin index"
|
||||
default 16
|
||||
|
||||
config BOARD_RW007_INT_BUSY_PIN
|
||||
int "INT/BUSY pin index"
|
||||
default 143
|
||||
|
||||
config BOARD_RW007_RST_PIN
|
||||
hex "RESET pin index"
|
||||
default 42
|
||||
endif
|
||||
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,326 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
kClockModule_SOSC,
|
||||
kClockModule_FIRC,
|
||||
kClockModule_SIRC,
|
||||
kClockModule_PowerMode,
|
||||
kClockModule_SPLL,
|
||||
kClockModule_SystemClkSrc,
|
||||
kClockModule_SCG_CLKOUTSEL,
|
||||
kClockModule_SIM_CLKOUTSEL,
|
||||
kClockModule_LPOClkOut,
|
||||
kClockModule_RTCClkOut,
|
||||
kClockModule_TRACEClkOut,
|
||||
kClockModule_RMIIClkOut,
|
||||
kClockModule_PCC_FTM3,
|
||||
kClockModule_PCC_ADC1,
|
||||
kClockModule_PCC_LPSPI0,
|
||||
kClockModule_PCC_LPSPI1,
|
||||
kClockModule_PCC_LPSPI2,
|
||||
kClockModule_PCC_LPIT,
|
||||
kClockModule_PCC_FTM0,
|
||||
kClockModule_PCC_FTM1,
|
||||
kClockModule_PCC_FTM2,
|
||||
kClockModule_PCC_ADC0,
|
||||
kClockModule_PCC_LPTMR0,
|
||||
kClockModule_PCC_FlexIO,
|
||||
kClockModule_PCC_LPI2C0,
|
||||
kClockModule_PCC_LPI2C1,
|
||||
kClockModule_PCC_LPUART0,
|
||||
kClockModule_PCC_LPUART1,
|
||||
kClockModule_PCC_LPUART2,
|
||||
kClockModule_PCC_FTM4,
|
||||
kClockModule_PCC_FTM5,
|
||||
kClockModule_PCC_FTM6,
|
||||
kClockModule_PCC_FTM7,
|
||||
kClockModule_PCC_ENET,
|
||||
kClockModule_LPO,
|
||||
kClockModule_QSPIClkSrc,
|
||||
} clock_module_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_CLOCK 48000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */
|
||||
#define BOARD_BOOTCLOCKRUN_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000UL /* Clock consumers of Core_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FIRCDIV1_CLK 48000000UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_FIRCDIV2_CLK 48000000UL /* Clock consumers of FIRCDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLASH_CLOCK 24000000UL /* Clock consumers of Flash_clock output : FTFC */
|
||||
#define BOARD_BOOTCLOCKRUN_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKRUN_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKRUN_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKRUN_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKRUN_PLLDIV1_CLK 0UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_PLLDIV2_CLK 0UL /* Clock consumers of PLLDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PREDIV_SYSTEM_CLOCK 48000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKRUN_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKRUN_SIRCDIV1_CLK 8000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SIRCDIV2_CLK 4000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKRUN_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKRUN_SOSCDIV1_CLK 8000000UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SOSCDIV2_CLK 8000000UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SOSC_CLK 8000000UL /* Clock consumers of SOSC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKRUN_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKVLPR_BUS_CLOCK 4000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */
|
||||
#define BOARD_BOOTCLOCKVLPR_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000UL /* Clock consumers of Core_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKVLPR_FIRCDIV1_CLK 0UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKVLPR_FIRCDIV2_CLK 0UL /* Clock consumers of FIRCDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKVLPR_FLASH_CLOCK 1000000UL /* Clock consumers of Flash_clock output : FTFC */
|
||||
#define BOARD_BOOTCLOCKVLPR_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKVLPR_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKVLPR_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKVLPR_PLLDIV1_CLK 0UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKVLPR_PLLDIV2_CLK 0UL /* Clock consumers of PLLDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKVLPR_PREDIV_SYSTEM_CLOCK 8000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKVLPR_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKVLPR_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKVLPR_SIRCDIV1_CLK 4000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKVLPR_SIRCDIV2_CLK 4000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKVLPR_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKVLPR_SOSCDIV1_CLK 0UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */
|
||||
#define BOARD_BOOTCLOCKVLPR_SOSCDIV2_CLK 0UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKVLPR_SOSC_CLK 0UL /* Clock consumers of SOSC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKVLPR_SYSTEM_CLOCK 4000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */
|
||||
#define BOARD_BOOTCLOCKVLPR_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKHSRUN_BUS_CLOCK 56000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */
|
||||
#define BOARD_BOOTCLOCKHSRUN_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 112000000UL /* Clock consumers of Core_clock output : N/A */
|
||||
#define BOARD_BOOTCLOCKHSRUN_FIRCDIV1_CLK 48000000UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKHSRUN_FIRCDIV2_CLK 48000000UL /* Clock consumers of FIRCDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKHSRUN_FLASH_CLOCK 28000000UL /* Clock consumers of Flash_clock output : FTFC */
|
||||
#define BOARD_BOOTCLOCKHSRUN_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKHSRUN_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKHSRUN_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PLLDIV1_CLK 112000000UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PLLDIV2_CLK 56000000UL /* Clock consumers of PLLDIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKHSRUN_PREDIV_SYSTEM_CLOCK 112000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */
|
||||
#define BOARD_BOOTCLOCKHSRUN_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */
|
||||
#define BOARD_BOOTCLOCKHSRUN_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SIRCDIV1_CLK 8000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SIRCDIV2_CLK 8000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SOSCDIV1_CLK 8000000UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SOSCDIV2_CLK 8000000UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SOSC_CLK 8000000UL /* Clock consumers of SOSC_CLK output : WDOG */
|
||||
#define BOARD_BOOTCLOCKHSRUN_SYSTEM_CLOCK 112000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */
|
||||
#define BOARD_BOOTCLOCKHSRUN_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockHSRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* RT-Thread Configuration */
|
||||
#include "rtconfig.h"
|
||||
|
||||
/* SDK drivers */
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
static void BOARD_InitUARTPins(void);
|
||||
static void BOARD_InitI2CPins(void);
|
||||
static void BOARD_InitSPIPins(void);
|
||||
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
BOARD_InitUARTPins();
|
||||
BOARD_InitI2CPins();
|
||||
BOARD_InitSPIPins();
|
||||
}
|
||||
|
||||
static void BOARD_InitUARTPins(void)
|
||||
{
|
||||
#if defined(BSP_USING_UART0)
|
||||
BOARD_InitUART0Pins();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
BOARD_InitUART1Pins();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
BOARD_InitUART2Pins();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void BOARD_InitI2CPins(void)
|
||||
{
|
||||
#if defined(BSP_USING_I2C0)
|
||||
BOARD_InitI2C0Pins();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
BOARD_InitI2C1Pins();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void BOARD_InitSPIPins(void)
|
||||
{
|
||||
#if defined(BSP_USING_SPI0)
|
||||
BOARD_InitSPI0Pins();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI1)
|
||||
BOARD_InitSPI1Pins();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2)
|
||||
BOARD_InitSPI2Pins();
|
||||
#endif
|
||||
}
|
||||
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_PortA);
|
||||
CLOCK_EnableClock(kCLOCK_PortB);
|
||||
CLOCK_EnableClock(kCLOCK_PortC);
|
||||
CLOCK_EnableClock(kCLOCK_PortD);
|
||||
CLOCK_EnableClock(kCLOCK_PortE);
|
||||
}
|
||||
|
||||
void BOARD_InitUART0Pins(void)
|
||||
{
|
||||
/* UART 0 pins are not used on this board. */
|
||||
}
|
||||
|
||||
void BOARD_InitUART1Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTC, 8U, kPORT_MuxAlt2); /* Default route to UART TX/RX pins on MikroBUS */
|
||||
PORT_SetPinMux(PORTC, 9U, kPORT_MuxAlt2); /* Default route to UART TX/RX pins on MikroBUS */
|
||||
}
|
||||
|
||||
void BOARD_InitUART2Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTD, 17U, kPORT_MuxAlt3); /* Default route to Arduino D0/D1 and MCU-Link Virtual COM Port */
|
||||
PORT_SetPinMux(PORTE, 12U, kPORT_MuxAlt3); /* Default route to Arduino D0/D1 and MCU-Link Virtual COM Port */
|
||||
}
|
||||
|
||||
void BOARD_InitI2C0Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt3); /* Default route to I2C SCL/SDA pins on MikroBUS */
|
||||
PORT_SetPinMux(PORTA, 3U, kPORT_MuxAlt3); /* Default route to I2C SCL/SDA pins on MikroBUS */
|
||||
}
|
||||
|
||||
void BOARD_InitI2C1Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTD, 8U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */
|
||||
PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */
|
||||
}
|
||||
|
||||
void BOARD_InitSPI0Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTB, 3U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */
|
||||
PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt2); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */
|
||||
PORT_SetPinMux(PORTE, 2U, kPORT_MuxAlt2); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */
|
||||
}
|
||||
|
||||
void BOARD_InitSPI1Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTB, 14U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */
|
||||
PORT_SetPinMux(PORTB, 15U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */
|
||||
PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */
|
||||
}
|
||||
|
||||
void BOARD_InitSPI2Pins(void)
|
||||
{
|
||||
PORT_SetPinMux(PORTA, 8U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */
|
||||
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */
|
||||
PORT_SetPinMux(PORTE, 16U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
|
||||
#ifndef PIN_MUX_H
|
||||
#define PIN_MUX_H
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void BOARD_InitBootPins(void);
|
||||
void BOARD_InitPins(void);
|
||||
void BOARD_InitUART0Pins(void);
|
||||
void BOARD_InitUART1Pins(void);
|
||||
void BOARD_InitUART2Pins(void);
|
||||
void BOARD_InitI2C0Pins(void);
|
||||
void BOARD_InitI2C1Pins(void);
|
||||
void BOARD_InitSPI0Pins(void);
|
||||
void BOARD_InitSPI1Pins(void);
|
||||
void BOARD_InitSPI2Pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PIN_MUX_H */
|
||||
@@ -0,0 +1,25 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/board/clock_config.c
|
||||
MCUX_Config/board/pin_mux.c
|
||||
""")
|
||||
|
||||
if GetDepend(['BSP_USING_RW007']):
|
||||
src += Glob('ports/drv_spi_sample_rw007.c')
|
||||
|
||||
CPPPATH = [cwd, cwd + '/MCUX_Config/board']
|
||||
CPPDEFINES = ['DEBUG', 'CPU_MCXE247VLQ']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-06 yandld first implementation
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock_config.h"
|
||||
#include "drv_uart.h"
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootClocks();
|
||||
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
/* set pend exception priority */
|
||||
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
|
||||
|
||||
/*init uart device*/
|
||||
rt_hw_uart_init();
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
/* initialization board with RT-Thread Components */
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
rt_uint32_t ticks;
|
||||
rt_uint32_t told, tnow, tcnt = 0;
|
||||
rt_uint32_t reload = SysTick->LOAD;
|
||||
|
||||
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
|
||||
told = SysTick->VAL;
|
||||
while (1)
|
||||
{
|
||||
tnow = SysTick->VAL;
|
||||
if (tnow != told)
|
||||
{
|
||||
if (tnow < told)
|
||||
{
|
||||
tcnt += told - tnow;
|
||||
}
|
||||
else
|
||||
{
|
||||
tcnt += reload - tnow + told;
|
||||
}
|
||||
told = tnow;
|
||||
if (tcnt >= ticks)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will called when memory fault.
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
extern void HardFault_Handler(void);
|
||||
|
||||
rt_kprintf("Memory Fault!\n");
|
||||
HardFault_Handler();
|
||||
}
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-09-22 Bernard add board.h to this bsp
|
||||
* 2010-02-04 Magicoe add board.h to LPC176x bsp
|
||||
* 2013-12-18 Bernard porting to LPC4088 bsp
|
||||
* 2017-08-02 XiaoYang porting to LPC54608 bsp
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
#include "fsl_edma.h"
|
||||
|
||||
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
|
||||
|
||||
// </RDTConfigurator>
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
|
||||
extern int Image$$ARM_LIB_STACK$$ZI$$Base;
|
||||
#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
|
||||
#define HEAP_END ((void *)&Image$$ARM_LIB_STACK$$ZI$$Base)
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma section = "HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
extern void __RTT_HEAP_END;
|
||||
#define HEAP_END (&__RTT_HEAP_END)
|
||||
#elif defined(__GNUC__)
|
||||
extern int __HeapBase;
|
||||
extern int __HeapLimit;
|
||||
#define HEAP_BEGIN ((void *)&__HeapBase)
|
||||
#define HEAP_END ((void *)&__HeapLimit)
|
||||
#endif
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,229 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MCXE247VLL
|
||||
** MCXE247VLQ
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: MCXE24x RM Rev.1
|
||||
** Version: rev. 1.0, 2025-02-21
|
||||
** Build: b250311
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2025 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
|
||||
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0017FBF0
|
||||
m_data (RW) : ORIGIN = 0x1FFE0000, LENGTH = 0x00020000
|
||||
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001F000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
|
||||
. = ALIGN(4);
|
||||
} > m_flash_config
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.rtt_const_tables :
|
||||
{
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(NonCacheable.init) /* NonCacheable init section */
|
||||
*(NonCacheable) /* NonCacheable section */
|
||||
*(CodeQuickAccess) /* quick access code section */
|
||||
*(DataQuickAccess) /* quick access data section */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data_2
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data_2
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
|
||||
}
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MCXE247VLL
|
||||
** MCXE247VLQ
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: MCXE24x RM Rev.1
|
||||
** Version: rev. 1.0, 2025-02-21
|
||||
** Build: b250311
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2025 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_flash_config_start 0x00000400
|
||||
#define m_flash_config_size 0x00000010
|
||||
|
||||
#define m_text_start 0x00000410
|
||||
#define m_text_size 0x0017FBF0
|
||||
|
||||
#define m_data_start 0x1FFE0000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_data_2_start 0x20000000
|
||||
#define m_data_2_size 0x0001F000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.FlashConfig,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_m_data m_data_start m_data_size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (RamFunction)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (CodeQuickAccess)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
ARM_LIB_HEAP ((ImageLimit(RW_m_data_2) == m_data_2_start) ? m_data_2_start : +0) EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,440 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
#define SOC_MCX
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 16
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart2"
|
||||
#define RT_VER_NUM 0x50201
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_FPU
|
||||
#define ARCH_ARM_CORTEX_M4
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define RT_USING_DFS_DEVFS
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_ADC
|
||||
#define RT_USING_RTC
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_HWTIMER
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* WCH HAL & SDK Drivers */
|
||||
|
||||
/* end of WCH HAL & SDK Drivers */
|
||||
|
||||
/* AT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of AT32 HAL & SDK Drivers */
|
||||
|
||||
/* HC32 DDL Drivers */
|
||||
|
||||
/* end of HC32 DDL Drivers */
|
||||
|
||||
/* NXP HAL & SDK Drivers */
|
||||
|
||||
#define PKG_USING_NXP_MCX_CMSIS_DRIVER
|
||||
#define PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION
|
||||
#define PKG_USING_NXP_MCX_SERIES_DRIVER
|
||||
#define PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION
|
||||
/* end of NXP HAL & SDK Drivers */
|
||||
|
||||
/* NUVOTON Drivers */
|
||||
|
||||
/* end of NUVOTON Drivers */
|
||||
|
||||
/* GD32 Drivers */
|
||||
|
||||
/* end of GD32 Drivers */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_MCXE247
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_PIN
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART2
|
||||
#define BSP_USING_ADC
|
||||
#define BSP_USING_ADC0
|
||||
#define BSP_USING_ADC1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Board extended module Drivers */
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,198 @@
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
BOARD_NAME = 'frdm-mcxe247'
|
||||
BSP_LIBRARY_TYPE = 'MCXE247'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armclang'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 9.1'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
#BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS'
|
||||
LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--defsym=__heap_size__=0x10000,--gc-sections,-Map=rtthread.map,--print-memory-usage -Tboard/linker_scripts/MCXE247_flash.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
|
||||
CXXFLAGS += CFLAGS
|
||||
|
||||
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
|
||||
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
|
||||
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' + \
|
||||
' -shared -fPIC -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU + '.fp.sp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./MCXE247_flash.scf" '
|
||||
|
||||
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
|
||||
|
||||
CFLAGS += ' --diag_suppress=66,1296,186,6134'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' --c99'
|
||||
|
||||
POST_ACTION = 'fromelf -z $TARGET'
|
||||
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'armclang':
|
||||
# toolchains
|
||||
CC = 'armclang'
|
||||
CXX = 'armclang'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4 '
|
||||
CFLAGS = ' --target=arm-arm-none-eabi'
|
||||
CFLAGS += ' -mcpu=' + CPU
|
||||
CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
|
||||
CFLAGS += ' -gdwarf-3 -ffunction-sections '
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
|
||||
LFLAGS += ' --list rt-thread.map '
|
||||
LFLAGS += r' --strict --scatter "board\linker_scripts\MCXE247_flash.sct" '
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
|
||||
|
||||
EXEC_PATH += '/ARM/ARMCLANG/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O1' # armclang recommend
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' -D__FPU_PRESENT'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' -Ol'
|
||||
CFLAGS += ' --use_c++_inline'
|
||||
|
||||
AFLAGS = ''
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu None'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/MCXE247_flash.icf"'
|
||||
LFLAGS += ' --redirect _Printf=_PrintfTiny'
|
||||
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
@@ -0,0 +1,172 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rtthread-frdm-mcxe247</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>0</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC -FS00 -FL0180000 -FP0($$Device:MCXE247VLQ$devices\MCXE247\arm\MCXE247_P1536_4KB_SEC.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,401 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rtthread-frdm-mcxe247</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6230000::V6.23::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MCXE247VLQ</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>NXP.MCXE247_DFP.25.06.00</PackID>
|
||||
<PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
|
||||
<Cpu>IRAM(0x14000000,0x1000) IRAM2(0x1ffe0000,0x020000) IROM(0x10000000,0x080000) IROM2(0x00000000,0x180000) XRAM(0x20000000,0x01f000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC -FS00 -FL0180000 -FP0($$Device:MCXE247VLQ$devices\MCXE247\arm\MCXE247_P1536_4KB_SEC.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MCXE247VLQ$devices\MCXE247\fsl_device_registers.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:MCXE247VLQ$devices\MCXE247\MCXE247.xml</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4102</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>0</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>1</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>16</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>4</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>1</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>1</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x14000000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x1f000</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x180000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x1f000</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x14000000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1ffe0000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>--target=arm-arm-none-eabi</MiscControls>
|
||||
<Define>CPU_MCXE247VLQ, ARM_MATH_CM4, RT_USING_ARM_LIBC</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>1</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls>-x assembler-with-cpp</MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x02000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\MCXE247_flash.scf</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName>template</LayName>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
Reference in New Issue
Block a user