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[bsp][n32] n32hxxx: extend H47x_48x/H49x/H7xx driver support

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- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the
  h47x_48x, h49x and h7xx series, and extend the shared drivers
  (adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt).
- n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing,
  phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and
  the IAR/Keil project files.
- n32h760zil7-stb: update Kconfig and rtconfig.
- CI: register the three n32hxxx boards.
This commit is contained in:
OnlyoutzZ
2026-09-16 09:06:34 +08:00
committed by Rbb666
parent 1d2152ceee
commit 97634bffe8
69 changed files with 7571 additions and 2764 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/workflows/manual_trigger_scons_except_STM32_all.yml
+15 -12
View File
@@ -190,18 +190,21 @@ jobs:
#- {RTT_BSP_NAME: "mm32f327x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f327x"} #编译问题
- {RTT_BSP_NAME: "mm32l07x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l07x"}
- {RTT_BSP_NAME: "mm32l3xx", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l3xx"}
- {RTT_BSP_NAME: "n32_n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g43xcl-stb"}
- {RTT_BSP_NAME: "n32_n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g457qel-stb"}
- {RTT_BSP_NAME: "n32_n32g45xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g45xcl-stb"}
- {RTT_BSP_NAME: "n32_n32g45xml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g45xml-stb"}
- {RTT_BSP_NAME: "n32_n32g45xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g45xrl-stb"}
- {RTT_BSP_NAME: "n32_n32g45xvl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g45xvl-stb"}
- {RTT_BSP_NAME: "n32_n32g4frml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g4frml-stb"}
- {RTT_BSP_NAME: "n32_n32l40xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32l40xcl-stb"}
- {RTT_BSP_NAME: "n32_n32l436-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32l436-evb"}
- {RTT_BSP_NAME: "n32_n32l43xml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32l43xml-stb"}
- {RTT_BSP_NAME: "n32_n32l43xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32l43xrl-stb"}
- {RTT_BSP_NAME: "n32_n32wb45xl-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32wb45xl-evb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g43xcl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g457qel-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g45xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g45xcl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g45xml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g45xml-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g45xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g45xrl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g45xvl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g45xvl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32g4frml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32g4frml-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32l40xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32l40xcl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32l436-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32l436-evb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32l43xml-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32l43xml-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32l43xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32l43xrl-stb"}
- {RTT_BSP_NAME: "n32_n32gxx_lxx_n32wb45xl-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32gxx_lxx/n32wb45xl-evb"}
- {RTT_BSP_NAME: "n32_n32hxxx_n32h487zgl7-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32hxxx/n32h487zgl7-evb"}
- {RTT_BSP_NAME: "n32_n32hxxx_n32h497zgl7-evb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32hxxx/n32h497zgl7-evb"}
- {RTT_BSP_NAME: "n32_n32hxxx_n32h760zil7-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32hxxx/n32h760zil7-stb"}
- {RTT_BSP_NAME: "n32g452xx_n32g452xx-mini-system", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32g452xx/n32g452xx-mini-system"}
#- {RTT_BSP_NAME: "nios_ii", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nios_ii"} #编译问题
- {RTT_BSP_NAME: "nrf5x_nrf51822", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nrf5x/nrf51822"}
bsp/README.md
+2 -2
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@@ -334,8 +334,8 @@ This document is based on the RT-Thread mainline repository and categorizes the
| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - |
| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - |
| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | - | - | - | ✅ | - | - | - |
| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | - | - | - | ✅ | - | - | - |
| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ |
| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - | - | ✅ |
#### 🟡 NRF5x
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/adc_config.h
+68
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@@ -0,0 +1,68 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 FUNMSAN first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define N32H47X_48X_ADC_CONFIG(ADC_INSTANCE, ADC_PERIPH) \
{ \
.ADCx = ADC_INSTANCE, \
.AHB_periph = ADC_PERIPH, \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.RCC_ADCPrescaler = RCC_ADCHCLK_DIV16, \
.ADC1M_ClkSource = RCC_ADC1MCLK_SRC_HSI, \
.ADC1M_ClkPrescaler = RCC_ADC1MCLK_DIV8, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_239_5, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
}
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG N32H47X_48X_ADC_CONFIG(ADC1, RCC_AHB_PERIPHEN_ADC1)
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG N32H47X_48X_ADC_CONFIG(ADC2, RCC_AHB_PERIPHEN_ADC2)
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG N32H47X_48X_ADC_CONFIG(ADC3, RCC_AHB_PERIPHEN_ADC3)
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef BSP_USING_ADC4
#ifndef ADC4_CONFIG
#define ADC4_CONFIG N32H47X_48X_ADC_CONFIG(ADC4, RCC_AHB_PERIPHEN_ADC4)
#endif /* ADC4_CONFIG */
#endif /* BSP_USING_ADC4 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/dac_config.h
+107
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@@ -0,0 +1,107 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 FUNMSAN first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(N32H473) || defined(N32H474)
#define N32H47X_48X_DAC1234_CLK_PRESCALER 100U
#else
#define N32H47X_48X_DAC1234_CLK_PRESCALER 120U
#endif
#define N32H47X_48X_DAC5678_CLK_PRESCALER 16U
#define N32H47X_48X_DAC_CONFIG(DAC_INSTANCE, DAC_MODULE, DAC_PERIPH, CLK_ENABLE, CLK_PRESCALER) \
{ \
.DACx = DAC_INSTANCE, \
.DAC_Module = DAC_MODULE, \
.periph_clk = DAC_PERIPH, \
.EnablePeriphClk = CLK_ENABLE, \
.DAC_clk_pres = CLK_PRESCALER, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#ifdef BSP_USING_DAC1
#ifndef DAC1_CONFIG
#define DAC1_CONFIG N32H47X_48X_DAC_CONFIG(DAC1, DAC12, RCC_APB1_PERIPH_DAC12, \
RCC_EnableAPB1PeriphClk, N32H47X_48X_DAC1234_CLK_PRESCALER)
#endif /* DAC1_CONFIG */
#endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2
#ifndef DAC2_CONFIG
#define DAC2_CONFIG N32H47X_48X_DAC_CONFIG(DAC2, DAC12, RCC_APB1_PERIPH_DAC12, \
RCC_EnableAPB1PeriphClk, N32H47X_48X_DAC1234_CLK_PRESCALER)
#endif /* DAC2_CONFIG */
#endif /* BSP_USING_DAC2 */
#ifdef BSP_USING_DAC3
#ifndef DAC3_CONFIG
#define DAC3_CONFIG N32H47X_48X_DAC_CONFIG(DAC3, DAC34, RCC_APB1_PERIPH_DAC34, \
RCC_EnableAPB1PeriphClk, N32H47X_48X_DAC1234_CLK_PRESCALER)
#endif /* DAC3_CONFIG */
#endif /* BSP_USING_DAC3 */
#ifdef BSP_USING_DAC4
#ifndef DAC4_CONFIG
#define DAC4_CONFIG N32H47X_48X_DAC_CONFIG(DAC4, DAC34, RCC_APB1_PERIPH_DAC34, \
RCC_EnableAPB1PeriphClk, N32H47X_48X_DAC1234_CLK_PRESCALER)
#endif /* DAC4_CONFIG */
#endif /* BSP_USING_DAC4 */
#ifdef BSP_USING_DAC5
#ifndef DAC5_CONFIG
#define DAC5_CONFIG N32H47X_48X_DAC_CONFIG(DAC5, DAC56, RCC_AHB_PERIPHEN_DAC56, \
RCC_EnableAHBPeriphClk, N32H47X_48X_DAC5678_CLK_PRESCALER)
#endif /* DAC5_CONFIG */
#endif /* BSP_USING_DAC5 */
#ifdef BSP_USING_DAC6
#ifndef DAC6_CONFIG
#define DAC6_CONFIG N32H47X_48X_DAC_CONFIG(DAC6, DAC56, RCC_AHB_PERIPHEN_DAC56, \
RCC_EnableAHBPeriphClk, N32H47X_48X_DAC5678_CLK_PRESCALER)
#endif /* DAC6_CONFIG */
#endif /* BSP_USING_DAC6 */
#ifdef BSP_USING_DAC7
#ifndef DAC7_CONFIG
#define DAC7_CONFIG N32H47X_48X_DAC_CONFIG(DAC7, DAC78, RCC_AHB_PERIPHEN_DAC78, \
RCC_EnableAHBPeriphClk, N32H47X_48X_DAC5678_CLK_PRESCALER)
#endif /* DAC7_CONFIG */
#endif /* BSP_USING_DAC7 */
#ifdef BSP_USING_DAC8
#ifndef DAC8_CONFIG
#define DAC8_CONFIG N32H47X_48X_DAC_CONFIG(DAC8, DAC78, RCC_AHB_PERIPHEN_DAC78, \
RCC_EnableAHBPeriphClk, N32H47X_48X_DAC5678_CLK_PRESCALER)
#endif /* DAC8_CONFIG */
#endif /* BSP_USING_DAC8 */
#ifdef __cplusplus
}
#endif
#endif /* __DAC_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/dma_config.h
+179 -1
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/i2c_hard_config.h
+204
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/spi_config.h
+254
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/adc_config.h
+62
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@@ -0,0 +1,62 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 FUNMSAN first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define N32H49X_ADC_CONFIG(ADC_INSTANCE, ADC_PERIPH) \
{ \
.ADCx = ADC_INSTANCE, \
.AHB_periph = ADC_PERIPH, \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.RCC_ADCPrescaler = RCC_ADCHCLK_DIV16, \
.ADC1M_ClkSource = RCC_ADC1MCLK_SRC_HSI, \
.ADC1M_ClkPrescaler = RCC_ADC1MCLK_DIV8, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_239_5, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
}
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG N32H49X_ADC_CONFIG(ADC1, RCC_AHB_PERIPHEN_ADC1)
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG N32H49X_ADC_CONFIG(ADC2, RCC_AHB_PERIPHEN_ADC2)
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG N32H49X_ADC_CONFIG(ADC3, RCC_AHB_PERIPHEN_ADC3)
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/dac_config.h
+55
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@@ -0,0 +1,55 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 FUNMSAN first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define N32H49X_DAC_CONFIG(DAC_INSTANCE) \
{ \
.DACx = DAC_INSTANCE, \
.DAC_Module = DAC12, \
.periph_clk = RCC_APB1_PERIPHEN_DAC12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
.DAC_clk_pres = 120U, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#ifdef BSP_USING_DAC1
#ifndef DAC1_CONFIG
#define DAC1_CONFIG N32H49X_DAC_CONFIG(DAC1)
#endif /* DAC1_CONFIG */
#endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2
#ifndef DAC2_CONFIG
#define DAC2_CONFIG N32H49X_DAC_CONFIG(DAC2)
#endif /* DAC2_CONFIG */
#endif /* BSP_USING_DAC2 */
#ifdef __cplusplus
}
#endif
#endif /* __DAC_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/dma_config.h
+1 -1
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@@ -239,7 +239,7 @@ extern "C" {
#define UART10_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART10_RX_DMA_REQUEST DMA_REMAP_UART10_RX
#define UART10_RX_DMA_CHANNEL 2U
#elif defined(BSP_USING_SDIO) && !defined(UART10_RX_DMA)
#elif defined(BSP_USING_SDIO)
#define SDIO_RX_DMA DMA2
#define SDIO_TX_DMA DMA2
#define SDIO_RX_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/i2c_hard_config.h
+204
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/spi_config.h
+254
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dma_config.h
+4 -1
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@@ -492,7 +492,10 @@ extern "C" {
#define SPI3_RX_DMA_IRQ DMA2_Channel7_IRQn
#define SPI3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define SPI3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
/* DMAMUX1 output 15 feeds DMA2 channel 7 (output N -> DMA(N/8+1) ch(N%8)),
* so the channel must match the IRQ/handshake below; DMA_CHANNEL_5 was a
* copy-paste defect that armed ch5 while the request lands on ch7. */
#define SPI3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define SPI3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define SPI3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_RX
#endif
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c
+209 -1
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h
+9
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@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-08-28 FUNMSAN add N32H47_48x and N32H49x support
*/
#ifndef __DRV_CONFIG_H_
@@ -34,11 +35,19 @@ extern "C" {
#elif defined(SOC_SERIES_N32H49x)
#include "h49x/dma_config.h"
#include "h49x/uart_config.h"
#include "h49x/adc_config.h"
#include "h49x/dac_config.h"
#include "h49x/can_config.h"
#include "h49x/spi_config.h"
#include "h49x/i2c_hard_config.h"
#elif defined(SOC_SERIES_N32H47x_48x)
#include "h47x_48x/dma_config.h"
#include "h47x_48x/uart_config.h"
#include "h47x_48x/adc_config.h"
#include "h47x_48x/dac_config.h"
#include "h47x_48x/can_config.h"
#include "h47x_48x/spi_config.h"
#include "h47x_48x/i2c_hard_config.h"
#endif /* defined(SOC_SERIES_N32H7xx) */
#ifdef __cplusplus
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c
+77 -4
View File
@@ -7,15 +7,28 @@
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-09 li.mengmeng port for N32H7xx
* 2026-08-28 FUNMSAN add N32H47_48x and N32H49x support
*/
#include <board.h>
#include <rtthread.h>
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2) || \
(defined(SOC_SERIES_N32H47x_48x) && (defined(BSP_USING_DAC3) || defined(BSP_USING_DAC4) || \
defined(BSP_USING_DAC5) || defined(BSP_USING_DAC6) || defined(BSP_USING_DAC7) || \
defined(BSP_USING_DAC8)))
#if defined(SOC_SERIES_N32H7xx)
#include "n32h7xx_rcc.h"
#include "n32h7xx_dac.h"
#elif defined(SOC_SERIES_N32H47x_48x)
#include "n32h47x_48x_rcc.h"
#include "n32h47x_48x_dac.h"
#elif defined(SOC_SERIES_N32H49x)
#include "n32h49x_rcc.h"
#include "n32h49x_dac.h"
#endif
#include "drv_config.h"
//#define DRV_DEBUG
@@ -46,9 +59,32 @@ static DAC_InitInfo_t dac_config[] = {
DAC2_CONFIG,
#endif
};
#if defined(SOC_SERIES_N32H47x_48x)
#ifdef BSP_USING_DAC3
DAC3_CONFIG,
#endif
static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
#ifdef BSP_USING_DAC4
DAC4_CONFIG,
#endif
#ifdef BSP_USING_DAC5
DAC5_CONFIG,
#endif
#ifdef BSP_USING_DAC6
DAC6_CONFIG,
#endif
#ifdef BSP_USING_DAC7
DAC7_CONFIG,
#endif
#ifdef BSP_USING_DAC8
DAC8_CONFIG,
#endif
#endif /* SOC_SERIES_N32H47x_48x */
};
struct n32_dac
{
@@ -56,6 +92,8 @@ struct n32_dac
struct rt_dac_device n32_dac_device;
};
static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
{
DAC_InitInfo_t *n32_dac_info;
@@ -86,7 +124,7 @@ static rt_uint8_t n32_dac_get_resolution(struct rt_dac_device *device)
{
RT_ASSERT(device != RT_NULL);
/* N32H7xx DAC supports 12-bit resolution */
/* N32H7xx and N32H47x/48x DACs support 12-bit resolution */
return 12;
}
@@ -142,13 +180,48 @@ static int n32_dac_init(void)
{
name_buf[3] = '2';
}
#if defined(SOC_SERIES_N32H47x_48x)
else if (n32_dac_obj[i].DAC_Info.DACx == DAC3)
{
name_buf[3] = '3';
}
else if (n32_dac_obj[i].DAC_Info.DACx == DAC4)
{
name_buf[3] = '4';
}
else if (n32_dac_obj[i].DAC_Info.DACx == DAC5)
{
name_buf[3] = '5';
}
else if (n32_dac_obj[i].DAC_Info.DACx == DAC6)
{
name_buf[3] = '6';
}
else if (n32_dac_obj[i].DAC_Info.DACx == DAC7)
{
name_buf[3] = '7';
}
else if (n32_dac_obj[i].DAC_Info.DACx == DAC8)
{
name_buf[3] = '8';
}
#endif /* SOC_SERIES_N32H47x_48x */
/* Enable DAC peripheral clock */
n32_dac_obj[i].DAC_Info.EnablePeriphClk(n32_dac_obj[i].DAC_Info.periph_clk, ENABLE);
/* Config DAC12 prescaler factor,DAC_CLK = 1M*/
DAC_ConfigClkPrescaler(n32_dac_obj[i].DAC_Info.DAC_Module, n32_dac_obj[i].DAC_Info.DAC_clk_pres);
#if defined(SOC_SERIES_N32H7xx) || defined(SOC_SERIES_N32H49x)
DAC_SetHighFrequencyMode(n32_dac_obj[i].DAC_Info.DAC_Module, DAC_HIGH_FREQ_MODE_BELOW_160M);
#elif defined(SOC_SERIES_N32H47x_48x)
/* The high-frequency mode field is only available for DAC1~DAC4. */
if ((n32_dac_obj[i].DAC_Info.DAC_Module == DAC12) ||
(n32_dac_obj[i].DAC_Info.DAC_Module == DAC34))
{
DAC_SetHighFrequencyMode(n32_dac_obj[i].DAC_Info.DAC_Module, DAC_HIGH_FREQ_MODE_BELOW_160M);
}
#endif
/* Initialize DAC */
DAC_Init(n32_dac_obj[i].DAC_Info.DACx, &n32_dac_obj[i].DAC_Info.Init);
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c
+52 -4
View File
@@ -9,6 +9,7 @@
*/
#include "drv_config.h"
#include <string.h>
#include "drv_eth.h"
#include <netif/ethernetif.h>
#include <lwipopts.h>
@@ -99,10 +100,12 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev)
struct rt_n32_eth *eth = (struct rt_n32_eth *)dev;
EthFuncStatusType status;
#if defined(SOC_SERIES_N32H7xx)
/* Enable or disable PWR Clock */
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_PWR, ENABLE);
/* Enable or disable the power domain of the ETH */
PWR_MoudlePowerEnable(ETH_PWR_CTRL, ENABLE);
#endif
/* Enable or disable ETH Clock */
ETH_RCC_ENABLE_AHB_PERIPHEN_CLK(ETH_RCC_AHB_PERIPHEN, ENABLE);
@@ -132,7 +135,7 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev)
ETH_DeInit(ETH);
/* Set ETH initialization parameters by default */
ETH_StructInit(ETH, &sETH_InitParam);
ETH_STRUCT_INIT(&sETH_InitParam);
/* Modify ETH initialization parameters (only override StructInit defaults) */
/* MAC Configuration */
@@ -687,6 +690,44 @@ static void phy_linkchange(void)
phy_speed_new |= PHY_FULL_DUPLEX;
}
#elif defined(PHY_USING_DM9162EP)
/* DM9162EP: read PHY specific status register (0x11) for speed/duplex */
ETH_ReadPHYRegister(ETH, phy_addr, PHY_SDSR, &SR);
LOG_D("DM9162EP status reg is 0x%X", (unsigned int)SR);
if (PHY_Status_SPEED_100M(SR))
{
phy_speed_new |= PHY_100M;
}
else
{
phy_speed_new |= PHY_10M;
}
if (PHY_Status_FULL_DUPLEX(SR))
{
phy_speed_new |= PHY_FULL_DUPLEX;
}
#elif defined(PHY_USING_LAN8720A)
/* LAN8720A: read PHY specific status register (0x1F) for speed/duplex */
ETH_ReadPHYRegister(ETH, phy_addr, PHY_SDSR, &SR);
LOG_D("LAN8720A status reg is 0x%X", (unsigned int)SR);
if (PHY_Status_SPEED_100M(SR))
{
phy_speed_new |= PHY_100M;
}
else
{
phy_speed_new |= PHY_10M;
}
if (PHY_Status_FULL_DUPLEX(SR))
{
phy_speed_new |= PHY_FULL_DUPLEX;
}
#else
/* Generic PHY: read from status register only, no extended info */
phy_speed_new |= PHY_100M;
@@ -703,12 +744,15 @@ static void phy_linkchange(void)
{
LOG_I("link up");
#if defined(SOC_SERIES_N32H7xx)
if (phy_speed & PHY_1000M)
{
LOG_D("1000Mbps");
n32_eth_device.ETH_Speed = ETH_SPEED_1000M;
}
else if (phy_speed & PHY_100M)
else
#endif
if (phy_speed & PHY_100M)
{
LOG_D("100Mbps");
n32_eth_device.ETH_Speed = ETH_SPEED_100M;
@@ -734,7 +778,7 @@ static void phy_linkchange(void)
* in MACCFG (PS[15], FES[14], DM[13]), then restart everything. */
ETH_StopIT(ETH, &sEthInfo);
MODIFY_REG(ETH->MACCFG,
(ETH_MACCFG_PS | ETH_MACCFG_FES | ETH_MACCFG_DM),
ETH_MACCFG_SPEED_DUPLEX_MASK,
(n32_eth_device.ETH_Speed | n32_eth_device.ETH_Mode));
ETH_StartIT(ETH, &sEthInfo);
@@ -894,7 +938,7 @@ static int rt_hw_n32_eth_init(void)
/* Set default speed based on media interface:
* GMII → 1000M, MII/RMII → 100M. Actual speed is updated after PHY auto-negotiation. */
#if (ETH_MEDIA_INTERFACE == ETH_GMII_MODE)
#if defined(SOC_SERIES_N32H7xx) && (ETH_MEDIA_INTERFACE == ETH_GMII_MODE)
n32_eth_device.ETH_Speed = ETH_SPEED_1000M;
#else
n32_eth_device.ETH_Speed = ETH_SPEED_100M;
@@ -1026,6 +1070,10 @@ const char *n32_eth_get_phy_name(void)
return "RTL8211EG";
#elif defined(PHY_USING_YT8522H)
return "YT8522H";
#elif defined(PHY_USING_DM9162EP)
return "DM9162EP";
#elif defined(PHY_USING_LAN8720A)
return "LAN8720A";
#else
return "Unknown";
#endif
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.h
+82 -2
View File
@@ -15,9 +15,15 @@
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#if defined(SOC_SERIES_N32H47x_48x)
#include "n32h47x_48x_eth.h"
#elif defined(SOC_SERIES_N32H49x)
#include "n32h49x_eth.h"
#elif defined(SOC_SERIES_N32H7xx)
#include "n32h7xx_eth.h"
#include "n32h7xx_rcc.h"
#include "n32h7xx_pwr.h"
#endif
#ifdef __cplusplus
extern "C" {
@@ -25,6 +31,14 @@ extern "C" {
/* ======================= ETH Instance Selection ======================= */
#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
/* n32h47x_48x / n32h49x have a single ETH instance; ETH pointer & ETH_IRQn come from the device header. */
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHBPeriphClk
#define ETH_RCC_AHB_PERIPHEN RCC_AHB_PERIPHEN_ETH
#define ETH_GLOBAL_IRQ ETH_IRQn
#define ETH_GLOBAL_IRQHANDLER ETH_IRQHandler
#elif defined(SOC_SERIES_N32H7xx)
#if defined(BSP_USING_ETH1)
#define ETH ETH1
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHB2PeriphClk2
@@ -49,6 +63,8 @@ extern "C" {
#endif /* BSP_USING_ETH1 / BSP_USING_ETH2 */
#endif /* SOC_SERIES_N32H47x_48x / SOC_SERIES_N32H7xx */
/* ======================= Media Interface Selection ======================= */
#if defined(ETH_INTERFACE_USING_GMII)
@@ -58,7 +74,21 @@ extern "C" {
#elif defined(ETH_INTERFACE_USING_RMII)
#define ETH_MEDIA_INTERFACE ETH_RMII_MODE
#else
#define ETH_MEDIA_INTERFACE ETH_GMII_MODE
#error "No ETH media interface selected (define ETH_INTERFACE_USING_GMII/MII/RMII)"
#endif
/* ======================= MACCFG Speed/Duplex Bit Mask ======================= */
#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
#define ETH_MACCFG_SPEED_DUPLEX_MASK (ETH_SPEED_100M | ETH_FULL_DUPLEX_MODE)
#else
#define ETH_MACCFG_SPEED_DUPLEX_MASK (ETH_MACCFG_PS | ETH_MACCFG_FES | ETH_MACCFG_DM)
#endif
/* ======================= ETH_Init Param Helper ======================= */
#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
#define ETH_STRUCT_INIT(p) ETH_StructInit(p)
#else
#define ETH_STRUCT_INIT(p) ETH_StructInit(ETH, p)
#endif
/* ======================= Standard IEEE 802.3 PHY Registers ======================= */
@@ -141,6 +171,29 @@ extern "C" {
#define PHY_INT_MASK ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_YT8522H */
/* ======================= DM9162EP PHY Specific Registers ======================= */
#ifdef PHY_USING_DM9162EP
/* DM9162EP is a Fast Ethernet PHY supporting MII/RMII, up to 100M */
#define PHY_DM9162EP_ID1 0x0181U
#define PHY_DM9162EP_ID2 0xB8A0U
/* DM9162EP PHY Specific Status Register (0x11)
* bit15 = 100M Full-Duplex, bit14 = 100M Half-Duplex,
* bit13 = 10M Full-Duplex, bit12 = 10M Half-Duplex */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_100M(sr) (((sr) & ((1 << 15) | (1 << 14))) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & ((1 << 15) | (1 << 13))) != 0)
/* DM9162EP PHY Specific Interrupt Registers
* 0x15 Interrupt Source Flag / Interrupt Mask */
#define PHY_INTERRUPT_FLAG_REG 0x15U
#define PHY_INTERRUPT_MASK_REG 0x15U
#define PHY_INT_MASK 0U
#endif /* PHY_USING_DM9162EP */
/* ======================= RTL8211EG PHY Specific Registers ======================= */
#ifdef PHY_USING_RTL8211EG
@@ -166,6 +219,28 @@ extern "C" {
#define PHY_INT_MASK ((1 << 15) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_RTL8211EG */
/* ======================= LAN8720A PHY Specific Registers ======================= */
#ifdef PHY_USING_LAN8720A
/* LAN8720A is a Fast Ethernet PHY supporting MII/RMII, up to 100M */
#define PHY_LAN8720A_ID1 0x0007U
#define PHY_LAN8720A_ID2 0xC0F1U
/* LAN8720A PHY Specific Status Register (0x1F)
* bit4 = Full-Duplex, bit3 = 100M, bit2 = 10M */
#define PHY_SDSR 0x1FU
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 3)) != 0)
#define PHY_Status_SPEED_10M(sr) (((sr) & (1 << 2)) != 0)
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 4)) != 0)
/* LAN8720A PHY Specific Interrupt Registers
* 0x1D Interrupt Source Flag, 0x1E Interrupt Mask */
#define PHY_INTERRUPT_FLAG_REG 0x1DU
#define PHY_INTERRUPT_MASK_REG 0x1EU
#define PHY_INT_MASK (1 << 4)
#endif /* PHY_USING_LAN8720A */
/* ======================= Buffer & Descriptor Configuration ======================= */
#ifndef ETH_TX_DESC_NUMBER
@@ -175,7 +250,12 @@ extern "C" {
#define ETH_RX_DESC_NUMBER ((uint32_t)4U)
#endif
/* ETH_MAX_PACKET_SIZE is defined in n32h7xx_eth.h (1528U) */
/* ETH_MAX_PACKET_SIZE is defined in n32h7xx_eth.h (1528U); n32h47x_48x has no such macro. */
#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
#ifndef ETH_MAX_PACKET_SIZE
#define ETH_MAX_PACKET_SIZE (1528U)
#endif
#endif
#define ETH_TX_BUF_SIZE (ETH_TX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
#define ETH_RX_BUF_SIZE (ETH_RX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c
+46 -45
View File
@@ -24,40 +24,17 @@
static uint32_t pin_irq_enable_mask = 0;
#if defined(GPIOK)
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 11u
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
#define __N32_PORT_MAX 8u
#endif
#elif defined(GPIOJ)
#define __N32_PORT_MAX 16u
#elif defined(GPIOI)
#define __N32_PORT_MAX 16u
#elif defined(GPIOH)
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 16u
#elif defined(SOC_SERIES_N32H49x)
#define __N32_PORT_MAX 6u
#elif defined(SOC_SERIES_N32H47x_48x)
#define __N32_PORT_MAX 7u
#endif
#elif defined(GPIOG)
#define __N32_PORT_MAX 16u
#elif defined(GPIOF)
#define __N32_PORT_MAX 16u
#elif defined(GPIOE)
#define __N32_PORT_MAX 16u
#elif defined(GPIOD)
#define __N32_PORT_MAX 16u
#elif defined(GPIOC)
#define __N32_PORT_MAX 16u
#elif defined(GPIOB)
#define __N32_PORT_MAX 16u
#elif defined(GPIOA)
#define __N32_PORT_MAX 16u
#else
#define __N32_PORT_MAX 0u
#error Unsupported N32 GPIO peripheral.
#endif
#define PIN_STPORT_MAX __N32_PORT_MAX
@@ -390,12 +367,12 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
break;
case PIN_IRQ_MODE_FALLING:
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_DOWN;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
@@ -476,7 +453,42 @@ rt_inline void pin_irq_hdr(int irqno)
void N32_GPIO_EXTI_Callback(uint16_t line_num)
{
#if defined(SOC_SERIES_N32H7xx)
#if defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
if (EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
EXTI_ClrITPendBit(line_num);
uint8_t index = 0;
uint32_t mask = line_num;
if (mask & 0xFF00)
{
index += 8;
mask >>= 8;
}
if (mask & 0xF0)
{
index += 4;
mask >>= 4;
}
if (mask & 0xC)
{
index += 2;
mask >>= 2;
}
if (mask & 0x2)
{
index += 1;
}
if ((index < 16) && (pin_irq_hdr_tab[index].pin != -1))
{
pin_irq_hdr(index);
}
}
#elif defined(SOC_SERIES_N32H7xx)
if (pin_irq_hdr_tab[line_num].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
@@ -484,17 +496,6 @@ void N32_GPIO_EXTI_Callback(uint16_t line_num)
pin_irq_hdr(line_num);
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
{
rt_int32_t idx = bit2bitno(line_num);
if (idx >= 0 && idx < (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab) && pin_irq_hdr_tab[idx].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
EXTI_ClrITPendBit(line_num);
pin_irq_hdr(idx);
}
}
#endif
}
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h
+1
View File
@@ -14,6 +14,7 @@
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c
+1299 -18
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h
+9
View File
@@ -40,7 +40,9 @@ struct n32_i2c_config
{
const char *name;
I2C_Module *Instance;
#if defined(SOC_SERIES_N32H7xx)
rt_uint32_t timing;
#endif
rt_uint32_t timeout;
IRQn_Type evirq_type;
IRQn_Type erirq_type;
@@ -51,9 +53,16 @@ struct n32_i2c_config
uint32_t periph;
void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd);
#if defined(SOC_SERIES_N32H7xx)
void (*I2CKerClkSource)(uint32_t CLK_source);
#endif
struct dma_config *dma_rx, *dma_tx;
#if defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
DMA_InitType dma_rx_init_str;
DMA_InitType dma_tx_init_str;
#endif
};
struct hard_i2c_transfer
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c
+353 -17
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.c
+458 -26
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.h
+23 -3
View File
@@ -12,12 +12,19 @@
#include <ipc/completion.h>
#include "drv_common.h"
#if defined(SOC_SERIES_N32H47x_48x)
#include "n32h47x_48x_xspi.h"
#elif defined(SOC_SERIES_N32H49x)
#include "n32h49x_xspi_v2.h"
#else
#include "n32h7xx_xspi_v2.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SOC_SERIES_N32H7xx)
struct mdma_config
{
MDMA_ChNumType mdma_channel;
@@ -26,10 +33,12 @@ struct mdma_config
uint32_t dmamux_request;
uint32_t hs_interface;
};
#endif
#define XSPI_USING_RX_DMA_FLAG (1 << 0)
#define XSPI_USING_TX_DMA_FLAG (1 << 1)
#if defined(SOC_SERIES_N32H7xx)
typedef enum
{
XSPI_Tx_Rx = 0U,
@@ -38,17 +47,24 @@ typedef enum
XSPI_Idle,
} XSPI_Work_Direct_t;
#endif
struct n32_xspi
{
#if defined(SOC_SERIES_N32H47x_48x)
XSPI_InitType InitStructure; /* v1: single combined init struct, global XSPI instance */
#else
XSPI_Module *xSPIx;
char *bus_name;
XSPI_InitType InitStructure;
XSPI_EnhancedInitType EnhInitStructure;
XSPI_XIPInitType XIPInitStructure;
#endif
char *bus_name;
struct rt_qspi_configuration *qspi_cfg;
struct rt_spi_configuration *cfg;
#if defined(SOC_SERIES_N32H7xx)
XSPI_XIPInitType XIPInitStructure;
XSPI_Work_Direct_t Direct;
rt_uint8_t xspi_dma_flag;
@@ -60,8 +76,10 @@ struct n32_xspi
MDMA_ChInitType RX_DMA_ChInitStr;
} dma;
rt_uint8_t slave_sel;
rt_uint8_t xip_enabled;
#endif
rt_uint8_t slave_sel;
struct rt_completion cpt;
};
@@ -89,6 +107,7 @@ struct n32_xspi_config
uint32_t Enhance_DDR;
};
#if defined(SOC_SERIES_N32H7xx)
struct xspi_xip_config
{
uint32_t XipInstructLen;
@@ -111,6 +130,7 @@ struct xspi_xip_config
#define XSPI_CTRL_ENTER_XIP 0x01
#define XSPI_CTRL_EXIT_XIP 0x02
#define XSPI_CTRL_GET_XIP_ADDR 0x03
#endif
rt_err_t rt_hw_xspi_device_attach(const char *bus_name, const char *device_name,
rt_uint8_t data_line_width,
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c
+15
View File
@@ -13,8 +13,14 @@
#ifdef BSP_USING_SDRAM
#include <sdram_port.h>
#if defined(SOC_SERIES_N32H7xx)
#include <n32h7xx_rcc.h>
#include <n32h7xx_sdram.h>
#elif defined(SOC_SERIES_N32H49x)
#include <n32h49x_rcc.h>
#include <n32h49x_sdram.h>
#endif
#define DRV_DEBUG
#define LOG_TAG "drv.sdram"
@@ -115,6 +121,7 @@ static SDRAM_DeviceType sdram_device;
* SDRAM Load Mode Register type (from N32 SDK bsp_sdram.h)
* Represents the value sent to the SDRAM chip via LOADMODE command.
*---------------------------------------------------------------------------*/
#if defined(SOC_SERIES_N32H7xx)
typedef union
{
uint32_t cmd;
@@ -128,6 +135,7 @@ typedef union
uint32_t Reserved : 22;
} Bits;
} SDRAM_LoadModeRegisterType;
#endif
/* Mode register field values (from N32 SDK bsp_sdram.h) */
#define LOADMODE_BURSTLEN_1 0
@@ -147,9 +155,16 @@ typedef union
*---------------------------------------------------------------------------*/
rt_weak void rt_hw_sdram_clock_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
/* Configure SDRAM delay chain (board-specific, default 0.2ns step) */
RCC_ConfigSDRAMDelay(RCC_SDRAM_DELAY_0_2NS);
RCC_EnableSDRAMDelayChain(ENABLE);
#elif defined(SOC_SERIES_N32H49x)
/* Configure SDRAM clock */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_SDRAM, ENABLE);
/* Configure SDRAM delay chain (board-specific, default 0.5) */
SDRAM_ConfigSampleDelay(SDRAM_DELAY_0_5_PERIOD);
#endif
}
/*----------------------------------------------------------------------------
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c
+1517 -200
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h
+47
View File
@@ -17,6 +17,7 @@
#include <drv_common.h>
#include "drv_dma.h"
#include <ipc/completion.h>
#include "drv_config.h"
#ifdef __cplusplus
extern "C" {
@@ -47,6 +48,20 @@ struct n32_spi_device
#define SPI_USING_RX_DMA_FLAG (1 << 0)
#define SPI_USING_TX_DMA_FLAG (1 << 1)
/* Max bytes of a single DMA block (12-bit BlkTfrSize) */
#define SPI_DMA_BLOCK_MAX (4095U)
/* Number of LLI chain nodes per DMA leg (sizes lli_tx/lli_rx) */
#define SPI_DMA_CHAIN_NODES (16U)
#define SPI_DMA_CHAIN_MAX (SPI_DMA_BLOCK_MAX * SPI_DMA_CHAIN_NODES)
/* Max elements of a single DMA arm: spixfer chunks every message at this
* size. A N32H7xx DMA arm stalls past ~4128 items at the 20MHz top rate
* (silicon-level: the LLI chain is verified intact and frozen mid-node;
* sharp 4128 PASS / 4136 FAIL boundary, and the ceiling scales with the
* bit clock so a 4096-item arm passes at every rate). 4096 items = 2 LLI
* nodes (4095+1) -- the same per-arm shape as a standalone 4096-element
* message. */
#define SPI_DMA_ARM_MAX (4096U)
typedef enum
{
SPI_Tx_Rx = 0U,
@@ -64,6 +79,7 @@ struct n32_spi
SPI_InitType SPI_InitStructure;
SPI_Work_Direct_t Direct;
#if defined(SOC_SERIES_N32H7xx)
struct
{
rt_bool_t DMA_Tx_Init;
@@ -71,9 +87,40 @@ struct n32_spi
rt_bool_t DMA_Rx_Init;
DMA_ChInitType RX_DMA_ChInitStr;
/* LLI node arrays: seamless single-task DMA for > SPI_DMA_BLOCK_MAX */
DMA_LinkListItemType lli_rx[SPI_DMA_CHAIN_NODES];
DMA_LinkListItemType lli_tx[SPI_DMA_CHAIN_NODES];
} dma;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
struct
{
rt_bool_t DMA_Tx_Init;
DMA_InitType TX_DMA_ChInitStr;
rt_bool_t DMA_Rx_Init;
DMA_InitType RX_DMA_ChInitStr;
} dma;
#endif
rt_uint8_t spi_dma_flag;
/* TRUE while a 4-wire full-duplex MASTER receive-only message is being
* armed: the TX DMA source is then the static 0xFF fill buffer, and
* n32_spi_dma_arm re-points every LLI TX node at its base. Read only
* inside n32_spi_dma_arm; set/cleared around the SPI_DMA_TransmitReceive
* call in SPI_DMA_Receive. Per-bus messages are serialized by the
* RT-Thread bus lock and no ISR reads the flag, so a plain rt_bool_t is
* race-free. Unused on non-H7 series. */
rt_bool_t fd_rxonly_dummy_tx;
/* TRUE while a non-first chunk of a 4-wire full-duplex message is being
* armed: spixfer keeps the SPI engine on across chunk boundaries (only
* the message tail disables), so SPI_DMA_TransmitReceive re-arms the
* live engine warm (no SPIEN drop/re-enable) instead of cold-starting
* it. Read only inside SPI_DMA_TransmitReceive; set at the top of every
* chunk in spixfer. Per-bus messages are serialized by the RT-Thread
* bus lock and no ISR reads the flag, so a plain rt_bool_t is
* race-free. Unused on non-H7 series. */
rt_bool_t fd_chunk_cont;
struct rt_spi_bus spi_bus;
struct rt_completion cpt;
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c
+53 -21
View File
@@ -161,36 +161,66 @@ static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_fl
#if defined(SOC_SERIES_N32H7xx)
rt_size_t read_len;
read_len = DMA_GetTransferredNumber(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel);
/* BTS (per-block byte count in CHNCTRL) is only valid within the current
* LLI block: the hardware loads the next block and wraps BTS the instant a
* block completes. Reading BTS inside the TC ISR may therefore see the
* already-wrapped value, and diffing it against the last value would
* produce a huge underflow count that permanently corrupts the FIFO put
* index. Correct scheme:
* - TC ISR only accumulates "actual bytes completed" (no BTS read, no RX
* report; the DMA IRQ has a higher priority than the UART IRQ, so the
* accumulated value is always up to date when the IDLE handler runs);
* - BTS is read only at IDLE (end of frame):
* cumulative = completed-block bytes + BTS
* bytes since last IDLE = cumulative difference.
* NOTE: the last LLI item of the ring may be shorter than 4095B
* (remain_len), so the TC ISR must add each block's real size by its index,
* otherwise the counter drifts per ring turn (16384B buffer -> 4091B). */
switch (isr_flag)
{
case UART_RX_DMA_IT_IDLE_FLAG:
{
if (uart->dma.rx_dma.block_has_recv_cnt != 0)
{
recv_len = read_len - uart->dma.rx_dma.block_has_recv_cnt;
}
else
{
recv_len = read_len;
}
uart->dma.rx_dma.block_has_recv_cnt = read_len;
rt_uint32_t read_len;
rt_uint32_t cum;
rt_uint32_t delta;
read_len = DMA_GetTransferredNumber(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel);
cum = uart->dma.rx_dma.lli_byte_base + read_len;
delta = cum - uart->dma.rx_dma.lli_last_cum; /* u32 wrap-safe subtraction */
uart->dma.rx_dma.lli_last_cum = cum;
/* A frame must fit into the FIFO/ring buffer, otherwise the DMA has
* already overwritten it: an illegal state, drop the report */
if (delta > 0 && delta <= serial->config.bufsz)
{
recv_len = delta;
}
else if (delta > 0)
{
LOG_E("%s RX DMA delta %u > bufsz %u, drop", uart->config->name, delta, serial->config.bufsz);
}
break;
}
case UART_RX_DMA_IT_BLOCK_TC_FLAG:
{
if (uart->dma.rx_dma.block_has_recv_cnt != 0)
/* Add the real size of the block that just completed: the tail item
* is remain_len bytes, all other items are DMA_BLOCK_SIZE bytes */
rt_uint16_t blk_num = uart->dma.rx_dma.block_num;
if (blk_num > 0)
{
recv_len = read_len - uart->dma.rx_dma.block_has_recv_cnt;
uart->dma.rx_dma.block_has_recv_cnt = 0;
}
else
{
recv_len = DMA_BLOCK_SIZE;
rt_uint16_t blk_idx = (rt_uint16_t)(uart->dma.rx_dma.lli_blk_cnt % blk_num);
if ((blk_idx == (rt_uint16_t)(blk_num - 1)) && uart->dma.rx_dma.remain_len != 0)
{
uart->dma.rx_dma.lli_byte_base += uart->dma.rx_dma.remain_len;
}
else
{
uart->dma.rx_dma.lli_byte_base += DMA_BLOCK_SIZE;
}
}
uart->dma.rx_dma.lli_blk_cnt++;
break;
}
@@ -950,7 +980,9 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN))
{
#if defined(SOC_SERIES_N32H7xx)
uart->dma.rx_dma.block_has_recv_cnt = 0;
uart->dma.rx_dma.lli_blk_cnt = 0;
uart->dma.rx_dma.lli_byte_base = 0;
uart->dma.rx_dma.lli_last_cum = 0;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
uart->dma.rx_dma.remaining_cnt = cfg->bufsz;
#endif /* SOC_SERIES_N32H7xx */
@@ -2194,7 +2226,7 @@ int rt_hw_usart_init(void)
uart_obj[i].dma.rx_dma.Read_LinkList[j].pNext = &uart_obj[i].dma.rx_dma.Read_LinkList[j + 1U];
}
/* The last block and block size ≠ BLOCK_SIZE */
/* The last block and block size != BLOCK_SIZE */
if ((j + 1U) == uart_obj[i].dma.rx_dma.block_num && uart_obj[i].dma.rx_dma.remain_len != 0U)
{
uart_obj[i].dma.rx_dma.Read_LinkList[j].BlkTfrSize = uart_obj[i].dma.rx_dma.remain_len;
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h
+19 -1
View File
@@ -73,7 +73,25 @@ struct n32_uart
{
rt_uint16_t block_num;
rt_uint16_t remain_len;
rt_size_t block_has_recv_cnt;
/* LLI ring accounting (maintained in the TC ISR; BTS is never read
* here: the hardware wraps BTS the instant a block completes, so
* reading BTS at TC and diffing it against the last value would
* underflow and permanently corrupt the FIFO put index):
* lli_blk_cnt number of completed LLI blocks (also used as
* the block index, modulo block_num)
* lli_byte_base actual bytes accumulated for completed blocks.
* NOTE: the last LLI item may be shorter than
* 4095B (remain_len; 4B when bufsz = 16384), so
* the TC ISR must add each block's real size.
* Otherwise the counter drifts +4095-remain_len
* bytes per ring turn (e.g. +4091B per turn for
* a 16384B buffer), eventually corrupting the
* FIFO read pointer.
* lli_last_cum cumulative bytes at the last IDLE report (the
* difference between two reports = frame len) */
rt_uint32_t lli_blk_cnt;
rt_uint32_t lli_byte_base;
rt_uint32_t lli_last_cum;
DMA_LinkListItemType *Read_LinkList;
} rx_dma;
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c
+36
View File
@@ -14,6 +14,14 @@
#ifdef RT_USING_WDT
#if defined(SOC_SERIES_N32H47x_48x)
#include "n32h47x_48x_iwdg.h"
#elif defined(SOC_SERIES_N32H49x)
#include "n32h49x_iwdg.h"
#elif defined(SOC_SERIES_N32H7xx)
#include "n32h7xx_iwdg.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
@@ -58,7 +66,9 @@ static rt_uint32_t wdt_get_prescaler_factor(rt_uint16_t prescaler)
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
#if defined(SOC_SERIES_N32H7xx)
n32_wdt.IWDGX_ClkCmd(n32_wdt.IWDG_Clk, ENABLE);
#endif
return RT_EOK;
}
@@ -73,7 +83,11 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
#if defined(SOC_SERIES_N32H7xx)
IWDG_ReloadKey(n32_wdt.IWDGx);
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
IWDG_ReloadKey();
#endif
break;
/* set watchdog timeout */
@@ -86,6 +100,11 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
}
reload_value = (*(rt_uint32_t *)arg);
if (reload_value == 0U)
{
LOG_W("wdg timeout must be greater than 0 s\n");
return -RT_EINVAL;
}
prescaler_factor = wdt_get_prescaler_factor(n32_wdt.Prescaler);
if (LSI_VALUE)
@@ -104,6 +123,7 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
reload_value = (reload_value * (LSI_VALUE / prescaler_factor)) - 1U;
/* Enable write access to IWDG_PR and IWDG_RLR registers */
#if defined(SOC_SERIES_N32H7xx)
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_ENABLE);
/* Set IWDG PREDIV */
IWDG_SetPrescalerDiv(n32_wdt.IWDGx, n32_wdt.Prescaler);
@@ -114,6 +134,18 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
/* Disable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_DISABLE);
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
IWDG_WriteConfig(IWDG_WRITE_ENABLE);
/* Set IWDG PREDIV */
IWDG_SetPrescalerDiv(n32_wdt.Prescaler);
/* Set Counter Reload Value */
IWDG_CntReload((uint16_t)reload_value);
/* Reload IWDG counter */
IWDG_ReloadKey();
/* Disable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(IWDG_WRITE_DISABLE);
#endif
}
}
else
@@ -135,7 +167,11 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
LOG_W("IWDG is already started\n");
return RT_EOK;
}
#if defined(SOC_SERIES_N32H7xx)
IWDG_Enable(n32_wdt.IWDGx);
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
IWDG_Enable();
#endif
n32_wdt.is_start = 1;
break;
bsp/n32/n32hxxx/n32h487zgl7-evb/.config
+24 -6
View File
@@ -158,15 +158,14 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_MEMPOOL is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
@@ -183,7 +182,7 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=512
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
CONFIG_RT_VER_NUM=0x50300
CONFIG_RT_VER_NUM=0x50301
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -584,6 +583,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# CONFIG_PKG_USING_LITETYPE is not set
# end of multimedia packages
#
@@ -1032,6 +1032,7 @@ CONFIG_PKG_N32H47X_48X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_QMI8658 is not set
# CONFIG_PKG_USING_ICM20948 is not set
# CONFIG_PKG_USING_SCD4X is not set
# CONFIG_PKG_USING_BMI270 is not set
# end of sensors drivers
#
@@ -1086,6 +1087,7 @@ CONFIG_PKG_N32H47X_48X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_CH390 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
@@ -1154,6 +1156,9 @@ CONFIG_PKG_N32H47X_48X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
# CONFIG_PKG_USING_LLMCHAT is not set
# CONFIG_PKG_USING_LIME_TM is not set
# CONFIG_PKG_USING_AIFES is not set
# CONFIG_PKG_USING_AGENT is not set
# end of AI packages
#
@@ -1488,6 +1493,8 @@ CONFIG_SOC_SERIES_N32H47x_48x=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_ETH is not set
# end of Onboard Peripheral Drivers
#
# On-chip Peripheral Drivers
@@ -1499,9 +1506,20 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_HARD_I2C is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_FDCAN is not set
# CONFIG_BSP_USING_NAND is not set
# CONFIG_BSP_USING_SDIO is not set
# end of On-chip Peripheral Drivers
#
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx
BIN
View File
Binary file not shown.
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c
+7 -2
View File
@@ -134,7 +134,12 @@ bool RCC_Configuration(void)
ClockStatus = RCC_WaitHsiStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSI,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1);
RCC_ConfigHse(RCC_HSE_ENABLE);
/* Wait till HSE is ready */
ClockStatus = RCC_WaitHseStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSE,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1);
/* Enable PLL */
RCC_EnablePll(ENABLE);
/* Wait till PLL is ready */
@@ -177,7 +182,7 @@ bool GPIO_Configuration(void)
GPIO_InitStruct(&GPIO_InitStructure);
/* Enable the GPIO clock*/
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOH, ENABLE);
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOH | RCC_AHB_PERIPHEN_GPIOC, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO,ENABLE);
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig
+359
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/n32h487zgl7-evb/board/SConscript
+1
View File
@@ -11,6 +11,7 @@ Cube_Config/USER/src/n32h47x_48x_cfg.c
path = [cwd]
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
path += [os.path.join(cwd, 'ports')]
CPPDEFINES = ['N32H488', 'CORE_CM4']
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/SConscript
+5 -1
View File
@@ -7,7 +7,11 @@ cwd = GetCurrentDir()
# add general drivers
src = []
path = [cwd]
if GetDepend(['BSP_USING_NAND']):
src += Glob('femc_timing.c')
if GetDepend(['BSP_USING_ETH']):
src += Glob('phy_reset.c')
CPPDEFINES = ['']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/femc_timing.c
+53
View File
@@ -0,0 +1,53 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-25 ox-horse first version
*/
#include "femc_timing.h"
#ifdef BSP_USING_NAND
/*
* FEMC NAND timing configuration (N32H47x/48x).
*
* Timing values are in HCLK cycles, taken from the Nations FEMC Nand_Flash
* demo (FEMC_Nand_Init): SET=4, WAIT=6, HOLD=5, HIZ=5,
* TCLR/TAR = CLE/ALE delay of 1 HCLK.
*
* Actual time (ns) = value * HCLK_period (ns). When porting to a different
* system clock, recalculate HCLK period from RCC_Configuration() and adjust
* all values below to satisfy the NAND datasheet timing.
*
* Registers written by FEMC_InitNand():
* FEMC_NCTRLx <- WaitFeatureEnable | MemDataWidth | EccEnable |
* EccPageSize | TCLRSetTime | TARSetTime
* FEMC_NCMEMTMx <- CommSpaceTimingStruct (timing)
* FEMC_NATTMEMTMx <- AttrSpaceTimingStruct (timing)
*/
void FEMC_Nand_Timing_Config(FEMC_NandInitType *nandInit,
FEMC_NandTimingInitType *timing)
{
/* Address setup time: 4 HCLK */
timing->SetTime = FEMC_NAND_SETUP_TIME(0x4);
/* Command assert width: 6 HCLK */
timing->WaitSetTime = FEMC_NAND_WAIT_TIME(0x6);
/* Address/data hold time: 5 HCLK */
timing->HoldSetTime = FEMC_NAND_HOLD_TIME(0x5);
/* Data bus HiZ time: 5 HCLK */
timing->HiZSetTime = FEMC_NAND_HIZ_TIME(0x5);
nandInit->CommSpaceTimingStruct = timing;
nandInit->AttrSpaceTimingStruct = timing;
/* CLE to RE delay (TCLR): 1 HCLK */
nandInit->TCLRSetTime = FEMC_NAND_CLE_DELAY_1HCLK;
/* ALE to RE delay (TAR): 1 HCLK */
nandInit->TARSetTime = FEMC_NAND_ALE_DELAY_1HCLK;
}
#endif /* BSP_USING_NAND */
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/femc_timing.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-25 ox-horse first version
*/
#ifndef __FEMC_TIMING_H__
#define __FEMC_TIMING_H__
#include "board.h"
/*
* Configure FEMC NAND timing parameters (N32H47x/48x).
*
* This fills the timing-related fields of the NAND init structures:
* - timing: SET/WAIT/HOLD/HIZ (then linked to nandInit's
* CommSpaceTimingStruct / AttrSpaceTimingStruct)
* - nandInit: TCLRSetTime / TARSetTime (CLE/ALE to RE delay)
*
* @note structures are of type FEMC_NandInitType / FEMC_NandTimingInitType
* (N32H47x/48x SDK), which differ from N32H7xx FEMC_TimingInitType.
*/
void FEMC_Nand_Timing_Config(FEMC_NandInitType *nandInit,
FEMC_NandTimingInitType *timing);
#ifdef __cplusplus
}
#endif
#endif /* __FEMC_TIMING_H__ */
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/phy_reset.c
+29
View File
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-15 ox-horse first version
*/
#include <board.h>
#include <drv_gpio.h>
#define RESET_IO GET_PIN(D, 3)
void phy_reset(void)
{
rt_pin_write(RESET_IO, PIN_LOW);
rt_thread_mdelay(50);
rt_pin_write(RESET_IO, PIN_HIGH);
}
int phy_init(void)
{
rt_pin_mode(RESET_IO, PIN_MODE_OUTPUT);
rt_pin_write(RESET_IO, PIN_HIGH);
return RT_EOK;
}
INIT_BOARD_EXPORT(phy_init);
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/usb_config.h
+69
View File
@@ -0,0 +1,69 @@
/*
* Copyright (c) 2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 ox-horse first version
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
/* ================ USB common Configuration ================ */
#ifdef __RTTHREAD__
#include <rtthread.h>
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
#endif
#ifndef CONFIG_USB_DBG_LEVEL
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* N32H47x_48x is a Cortex-M4 without cache, so no dcache or dma alignment
* is required, and no noncacheable section is needed. */
#define CONFIG_USB_ALIGN_SIZE 4
#define USB_NOCACHE_RAM_SECTION
/* use usb_memcpy default for high performance but cost more flash memory.
* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
*/
// #define CONFIG_USB_MEMCPY_DISABLE
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#endif
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ================ USB Device Port Configuration ================*/
/* FSDEV port (Synopsys USBFS) PMA access mode. The N32H4x USBFS
* (usb_fsdev_reg.h) re-arranges the register map but keeps the buffer
* descriptor table layout that matches the ST macro addressing with
* PMA_ACCESS=2, which is what usb_dc_fsdev.c requires. */
#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2
#endif
bsp/n32/n32hxxx/n32h487zgl7-evb/project.ewp
+7 -4
View File
@@ -364,7 +364,6 @@
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\Cube_Config\USER\inc</state>
@@ -384,6 +383,7 @@
<state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc</state>
<state>$PROJ_DIR$\packages\n32h47x_48x_cmsis_driver-latest\device</state>
<state>$PROJ_DIR$\applications\test_file</state>
<state>$PROJ_DIR$\..\..\..\..\components\net\utest</state>
</option>
<option>
@@ -1455,7 +1455,6 @@
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\Cube_Config\USER\inc</state>
@@ -1475,6 +1474,7 @@
<state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc</state>
<state>$PROJ_DIR$\packages\n32h47x_48x_cmsis_driver-latest\device</state>
<state>$PROJ_DIR$\applications\test_file</state>
<state>$PROJ_DIR$\..\..\..\..\components\net\utest</state>
</option>
<option>
@@ -2308,10 +2308,10 @@
<name>$PROJ_DIR$\..\..\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\src\memheap.c</name>
<name>$PROJ_DIR$\..\..\..\..\src\mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\src\mempool.c</name>
<name>$PROJ_DIR$\..\..\..\..\src\memheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\src\object.c</name>
@@ -2431,6 +2431,9 @@
<name>$PROJ_DIR$\packages\n32h47x_48x_cmsis_driver-latest\device\startup\startup_n32h47x_48x_EWARM.s</name>
</file>
</group>
<group>
<name>test_file</name>
</group>
<group>
<name>utc_UTest</name>
</group>
bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvoptx
+6 -6
View File
@@ -652,8 +652,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\src\memheap.c</PathWithFileName>
<FilenameWithoutPath>memheap.c</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\src\mem.c</PathWithFileName>
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@@ -664,8 +664,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\src\mempool.c</PathWithFileName>
<FilenameWithoutPath>mempool.c</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\src\memheap.c</PathWithFileName>
<FilenameWithoutPath>memheap.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@@ -897,7 +897,7 @@
<Group>
<GroupName>Libraries</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -1013,7 +1013,7 @@
<Group>
<GroupName>Libraries-CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvprojx
+6 -6
View File
@@ -337,9 +337,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>__RTTHREAD__, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, CORE_CM4, RT_USING_ARMLIBC, N32H488, RT_USING_LIBC</Define>
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, CORE_CM4, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, N32H488, __RTTHREAD__, RT_USING_ARMLIBC</Define>
<Undefine></Undefine>
<IncludePath>board;packages\n32h47x_48x_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\eventfd;packages\CMSIS-Core-latest\Include;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;board\ports;..\..\..\..\components\libc\posix\io\poll;packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\net\utest;..\libraries\N32_Drivers\drivers;..\..\..\..\components\drivers\smp_call;applications;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\posix\ipc;board\Cube_Config\USER\inc;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\libraries\N32_Drivers\drivers\config;..\libraries\N32_Drivers;.;..\..\..\..\components\libc\compilers\common\extension</IncludePath>
<IncludePath>..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\common;..\..\..\..\include;..\..\..\..\libcpu\arm\cortex-m4;packages\n32h47x_48x_cmsis_driver-latest\device;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\libraries\N32_Drivers\drivers;board\ports;packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;packages\CMSIS-Core-latest\Include;..\libraries\N32_Drivers;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\net\utest;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\libc\compilers\common\extension;..\libraries\N32_Drivers\drivers\config;applications;.;board;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;board\Cube_Config\USER\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -1604,9 +1604,9 @@
</FileOption>
</File>
<File>
<FileName>memheap.c</FileName>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\memheap.c</FilePath>
<FilePath>..\..\..\..\src\mem.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
@@ -1660,9 +1660,9 @@
</FileOption>
</File>
<File>
<FileName>mempool.c</FileName>
<FileName>memheap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\mempool.c</FilePath>
<FilePath>..\..\..\..\src\memheap.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
bsp/n32/n32hxxx/n32h487zgl7-evb/rtconfig.h
+5 -4
View File
@@ -95,11 +95,10 @@
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_MEMHEAP_AUTO_BINDING
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
@@ -107,7 +106,7 @@
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50301
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
@@ -433,6 +432,8 @@
/* Onboard Peripheral Drivers */
/* end of Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
bsp/n32/n32hxxx/n32h497zgl7-evb/.config
+27 -8
View File
@@ -159,14 +159,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
@@ -183,7 +180,7 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=512
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
CONFIG_RT_VER_NUM=0x50300
CONFIG_RT_VER_NUM=0x50301
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -584,6 +581,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# CONFIG_PKG_USING_LITETYPE is not set
# end of multimedia packages
#
@@ -1032,6 +1030,7 @@ CONFIG_PKG_N32H49X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_QMI8658 is not set
# CONFIG_PKG_USING_ICM20948 is not set
# CONFIG_PKG_USING_SCD4X is not set
# CONFIG_PKG_USING_BMI270 is not set
# end of sensors drivers
#
@@ -1086,6 +1085,7 @@ CONFIG_PKG_N32H49X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_CH390 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
@@ -1154,6 +1154,9 @@ CONFIG_PKG_N32H49X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
# CONFIG_PKG_USING_LLMCHAT is not set
# CONFIG_PKG_USING_LIME_TM is not set
# CONFIG_PKG_USING_AIFES is not set
# CONFIG_PKG_USING_AGENT is not set
# end of AI packages
#
@@ -1488,6 +1491,9 @@ CONFIG_SOC_SERIES_N32H49x=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_SDRAM is not set
# end of Onboard Peripheral Drivers
#
# On-chip Peripheral Drivers
@@ -1499,9 +1505,22 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_UART10 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_HARD_I2C is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_FDCAN is not set
# CONFIG_BSP_USING_NAND is not set
# CONFIG_BSP_USING_SDIO is not set
# end of On-chip Peripheral Drivers
#
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx
BIN
View File
Binary file not shown.
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c
+6 -1
View File
@@ -77,7 +77,12 @@ bool RCC_Configuration(void)
ClockStatus = RCC_WaitHsiStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSI,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1);
RCC_ConfigHse(RCC_HSE_ENABLE);
/* Wait till HSE is ready */
ClockStatus = RCC_WaitHseStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSE_DIV2,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1);
/* Enable PLL */
RCC_EnablePll(ENABLE);
/* Wait till PLL is ready */
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig
+440
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/n32h497zgl7-evb/board/SConscript
+4 -1
View File
@@ -11,8 +11,11 @@ Cube_Config/USER/src/n32h49x_cfg.c
path = [cwd]
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
path += [os.path.join(cwd, 'ports')]
CPPDEFINES = ['N32H49x', 'CORE_CM4']
# Capital X is intentional: N32H49X is the family marker used by the
# N32H4x USB fsdev port.
CPPDEFINES = ['N32H49X', 'CORE_CM4']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
bsp/n32/n32hxxx/n32h497zgl7-evb/board/board.h
+2
View File
@@ -15,10 +15,12 @@
#include "n32h49x_cfg.h"
#include "n32h49x_exti.h"
#include "misc.h"
#include "n32h49x_i2c.h"
#include "n32h49x_dma.h"
#include "n32h49x_pwr.h"
#include "n32h49x_dbg.h"
#include "n32h49x_flash.h"
#include "n32h49x_spi.h"
#include "drv_common.h"
#include "drv_gpio.h"
bsp/n32/n32hxxx/n32h497zgl7-evb/board/ports/SConscript
+5 -1
View File
@@ -7,7 +7,11 @@ cwd = GetCurrentDir()
# add general drivers
src = []
path = [cwd]
if GetDepend(['BSP_USING_NAND']):
src += Glob('femc_timing.c')
if GetDepend(['BSP_USING_ETH']):
src += Glob('phy_reset.c')
CPPDEFINES = ['']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
bsp/n32/n32hxxx/n32h497zgl7-evb/board/ports/femc_timing.c
+53
View File
@@ -0,0 +1,53 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-25 ox-horse first version
*/
#include "femc_timing.h"
#ifdef BSP_USING_NAND
/*
* FEMC NAND timing configuration (N32H49x).
*
* Timing values are in HCLK cycles, taken from the Nsing FEMC Nand_Flash
* demo (FEMC_Nand_Init): SET=4, WAIT=6, HOLD=5, HIZ=5,
* TCLR/TAR = CLE/ALE delay of 1 HCLK.
*
* Actual time (ns) = value * HCLK_period (ns). When porting to a different
* system clock, recalculate HCLK period from RCC_Configuration() and adjust
* all values below to satisfy the NAND datasheet timing.
*
* Registers written by FEMC_InitNand():
* FEMC_NCTRLx <- WaitFeatureEnable | MemDataWidth | EccEnable |
* EccPageSize | TCLRSetTime | TARSetTime
* FEMC_NCMEMTMx <- CommSpaceTimingStruct (timing)
* FEMC_NATTMEMTMx <- AttrSpaceTimingStruct (timing)
*/
void FEMC_Nand_Timing_Config(FEMC_NandInitType *nandInit,
FEMC_NandTimingInitType *timing)
{
/* Address setup time: 4 HCLK */
timing->SetTime = FEMC_NAND_SETUP_TIME(0x4);
/* Command assert width: 6 HCLK */
timing->WaitSetTime = FEMC_NAND_WAIT_TIME(0x6);
/* Address/data hold time: 5 HCLK */
timing->HoldSetTime = FEMC_NAND_HOLD_TIME(0x5);
/* Data bus HiZ time: 5 HCLK */
timing->HiZSetTime = FEMC_NAND_HIZ_TIME(0x5);
nandInit->CommSpaceTimingStruct = timing;
nandInit->AttrSpaceTimingStruct = timing;
/* CLE to RE delay (TCLR): 1 HCLK */
nandInit->TCLRSetTime = FEMC_NAND_CLE_DELAY_1HCLK;
/* ALE to RE delay (TAR): 1 HCLK */
nandInit->TARSetTime = FEMC_NAND_ALE_DELAY_1HCLK;
}
#endif /* BSP_USING_NAND */
bsp/n32/n32hxxx/n32h497zgl7-evb/board/ports/femc_timing.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-25 ox-horse first version
*/
#ifndef __FEMC_TIMING_H__
#define __FEMC_TIMING_H__
#include "board.h"
/*
* Configure FEMC NAND timing parameters (N32H49x).
*
* This fills the timing-related fields of the NAND init structures:
* - timing: SET/WAIT/HOLD/HIZ (then linked to nandInit's
* CommSpaceTimingStruct / AttrSpaceTimingStruct)
* - nandInit: TCLRSetTime / TARSetTime (CLE/ALE to RE delay)
*
* @note structures are of type FEMC_NandInitType / FEMC_NandTimingInitType
* (N32H49x SDK), which differ from N32H7xx FEMC_TimingInitType.
*/
void FEMC_Nand_Timing_Config(FEMC_NandInitType *nandInit,
FEMC_NandTimingInitType *timing);
#ifdef __cplusplus
}
#endif
#endif /* __FEMC_TIMING_H__ */
bsp/n32/n32hxxx/n32h497zgl7-evb/board/ports/phy_reset.c
+29
View File
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-15 ox-horse first version
*/
#include <board.h>
#include <drv_gpio.h>
#define RESET_IO GET_PIN(D, 3)
void phy_reset(void)
{
rt_pin_write(RESET_IO, PIN_LOW);
rt_thread_mdelay(50);
rt_pin_write(RESET_IO, PIN_HIGH);
}
int phy_init(void)
{
rt_pin_mode(RESET_IO, PIN_MODE_OUTPUT);
rt_pin_write(RESET_IO, PIN_HIGH);
return RT_EOK;
}
INIT_BOARD_EXPORT(phy_init);
bsp/n32/n32hxxx/n32h497zgl7-evb/board/ports/usb_config.h
+69
View File
@@ -0,0 +1,69 @@
/*
* Copyright (c) 2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-08-28 ox-horse first version
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
/* ================ USB common Configuration ================ */
#ifdef __RTTHREAD__
#include <rtthread.h>
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
#endif
#ifndef CONFIG_USB_DBG_LEVEL
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* N32H49x is a Cortex-M4 without cache, so no dcache or dma alignment
* is required, and no noncacheable section is needed. */
#define CONFIG_USB_ALIGN_SIZE 4
#define USB_NOCACHE_RAM_SECTION
/* use usb_memcpy default for high performance but cost more flash memory.
* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
*/
// #define CONFIG_USB_MEMCPY_DISABLE
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#endif
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ================ USB Device Port Configuration ================*/
/* FSDEV port (Synopsys USBFS) PMA access mode. The N32H4x USBFS
* (usb_fsdev_reg.h) re-arranges the register map but keeps the buffer
* descriptor table layout that matches the ST macro addressing with
* PMA_ACCESS=2, which is what usb_dc_fsdev.c requires. */
#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2
#endif
bsp/n32/n32hxxx/n32h497zgl7-evb/project.ewp
+8 -3
View File
@@ -225,6 +225,7 @@
<name>CCDefines</name>
<state />
<state>N32H49x</state>
<state>N32H49X</state>
<state>CORE_CM4</state>
<state>USE_STDPERIPH_DRIVER</state>
<state>__RTTHREAD__</state>
@@ -364,7 +365,6 @@
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\Cube_Config\USER\inc</state>
@@ -384,6 +384,7 @@
<state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc</state>
<state>$PROJ_DIR$\packages\n32h49x_cmsis_driver-latest\device</state>
<state>$PROJ_DIR$\applications\test_file</state>
<state>$PROJ_DIR$\..\..\..\..\components\net\utest</state>
</option>
<option>
@@ -1316,6 +1317,7 @@
<name>CCDefines</name>
<state />
<state>N32H49x</state>
<state>N32H49X</state>
<state>CORE_CM4</state>
<state>USE_STDPERIPH_DRIVER</state>
<state>__RTTHREAD__</state>
@@ -1455,7 +1457,6 @@
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\Cube_Config\USER\inc</state>
@@ -1475,6 +1476,7 @@
<state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc</state>
<state>$PROJ_DIR$\packages\n32h49x_cmsis_driver-latest\device</state>
<state>$PROJ_DIR$\applications\test_file</state>
<state>$PROJ_DIR$\..\..\..\..\components\net\utest</state>
</option>
<option>
@@ -2308,7 +2310,7 @@
<name>$PROJ_DIR$\..\..\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\src\memheap.c</name>
<name>$PROJ_DIR$\..\..\..\..\src\mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\src\mempool.c</name>
@@ -2431,6 +2433,9 @@
<name>$PROJ_DIR$\packages\n32h49x_cmsis_driver-latest\device\startup\startup_n32h49x_EWARM.s</name>
</file>
</group>
<group>
<name>test_file</name>
</group>
<group>
<name>utc_UTest</name>
</group>
bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvoptx
+2 -2
View File
@@ -647,8 +647,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\src\memheap.c</PathWithFileName>
<FilenameWithoutPath>memheap.c</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\src\mem.c</PathWithFileName>
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvprojx
+4 -4
View File
@@ -337,9 +337,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>N32H49x, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __STDC_LIMIT_MACROS, CORE_CM4, __RTTHREAD__, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER</Define>
<Define>USE_STDPERIPH_DRIVER, N32H49X, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, CORE_CM4, RT_USING_ARMLIBC, N32H49x, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\libraries\N32_Drivers\drivers\config;..\..\..\..\libcpu\arm\cortex-m4;packages\CMSIS-Core-latest\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\finsh;board\Cube_Config\USER\inc;..\..\..\..\components\libc\posix\ipc;..\libraries\N32_Drivers;..\..\..\..\libcpu\arm\common;..\..\..\..\components\net\utest;..\libraries\N32_Drivers\drivers;board\ports;packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc;..\..\..\..\components\drivers\include;.;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;board;packages\n32h49x_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;applications</IncludePath>
<IncludePath>..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board\ports;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\poll;board\Cube_Config\USER\inc;board;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\libc\compilers\common\include;packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc;applications;.;..\..\..\..\components\libc\compilers\common\extension;packages\CMSIS-Core-latest\Include;..\libraries\N32_Drivers\drivers;..\..\..\..\components\net\utest;..\libraries\N32_Drivers;..\..\..\..\components\libc\posix\io\eventfd;packages\n32h49x_cmsis_driver-latest\device;..\..\..\..\components\drivers\include;..\libraries\N32_Drivers\drivers\config;..\..\..\..\include;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -1604,9 +1604,9 @@
</FileOption>
</File>
<File>
<FileName>memheap.c</FileName>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\memheap.c</FilePath>
<FilePath>..\..\..\..\src\mem.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
bsp/n32/n32hxxx/n32h497zgl7-evb/rtconfig.h
+5 -5
View File
@@ -96,10 +96,8 @@
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_MEMHEAP_AUTO_BINDING
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
@@ -107,7 +105,7 @@
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50301
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
@@ -433,6 +431,8 @@
/* Onboard Peripheral Drivers */
/* end of Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
bsp/n32/n32hxxx/n32h760zil7-stb/.config
+20 -4
View File
@@ -180,7 +180,7 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=512
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
CONFIG_RT_VER_NUM=0x50300
CONFIG_RT_VER_NUM=0x50301
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -255,7 +255,7 @@ CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=512
# CONFIG_RT_USING_SERIAL_BYPASS is not set
# CONFIG_RT_USING_CAN is not set
@@ -597,6 +597,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# CONFIG_PKG_USING_LITETYPE is not set
# end of multimedia packages
#
@@ -1045,6 +1046,7 @@ CONFIG_PKG_N32H7XX_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_QMI8658 is not set
# CONFIG_PKG_USING_ICM20948 is not set
# CONFIG_PKG_USING_SCD4X is not set
# CONFIG_PKG_USING_BMI270 is not set
# end of sensors drivers
#
@@ -1099,6 +1101,7 @@ CONFIG_PKG_N32H7XX_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_CH390 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
@@ -1167,6 +1170,9 @@ CONFIG_PKG_N32H7XX_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
# CONFIG_PKG_USING_LLMCHAT is not set
# CONFIG_PKG_USING_LIME_TM is not set
# CONFIG_PKG_USING_AIFES is not set
# CONFIG_PKG_USING_AGENT is not set
# end of AI packages
#
@@ -1512,10 +1518,20 @@ CONFIG_SOC_SERIES_N32H7xx=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_UART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_UART10 is not set
# CONFIG_BSP_USING_UART11 is not set
# CONFIG_BSP_USING_UART12 is not set
# CONFIG_BSP_USING_UART13 is not set
# CONFIG_BSP_USING_UART14 is not set
# CONFIG_BSP_USING_UART15 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
# CONFIG_BSP_USING_HARD_I2C is not set
bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx
BIN
View File
Binary file not shown.
bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c
+8 -8
View File
@@ -183,15 +183,8 @@ bool GPIO_Configuration(void)
/*********Initialize USART1 GPIO function *********/
/********PA10->USART1.RX********/
/********PA9->USART1.TX********/
/*Initialize input GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure);
/********PA10->USART1.RX********/
/*Initialize AF_PP GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
@@ -201,6 +194,13 @@ bool GPIO_Configuration(void)
GPIO_InitStructure.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure);
/*Initialize input GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure);
/* NTFx CODE END */
return true;
bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig
+258
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx
-980
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx
+219 -1332
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h
+9 -2
View File
@@ -105,7 +105,7 @@
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50301
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
@@ -140,6 +140,14 @@
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
/* end of DFS: device virtual file system */
/* Device Drivers */
@@ -148,7 +156,6 @@
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 512
#define RT_USING_PIN
/* end of Device Drivers */
tools/ci/bsp_detail.yml
+34 -12
View File
@@ -1001,7 +1001,7 @@ msp432e401y-LaunchPad:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g43xcl-stb:
n32/n32gxx_lxx/n32g43xcl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1009,7 +1009,7 @@ n32/n32g43xcl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g457qel-stb:
n32/n32gxx_lxx/n32g457qel-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1017,7 +1017,7 @@ n32/n32g457qel-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g45xcl-stb:
n32/n32gxx_lxx/n32g45xcl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1025,7 +1025,7 @@ n32/n32g45xcl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g45xml-stb:
n32/n32gxx_lxx/n32g45xml-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1033,7 +1033,7 @@ n32/n32g45xml-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g45xrl-stb:
n32/n32gxx_lxx/n32g45xrl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1041,7 +1041,7 @@ n32/n32g45xrl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g45xvl-stb:
n32/n32gxx_lxx/n32g45xvl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1049,7 +1049,7 @@ n32/n32g45xvl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32g4frml-stb:
n32/n32gxx_lxx/n32g4frml-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1057,7 +1057,7 @@ n32/n32g4frml-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32l40xcl-stb:
n32/n32gxx_lxx/n32l40xcl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1065,7 +1065,7 @@ n32/n32l40xcl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32l436-evb:
n32/n32gxx_lxx/n32l436-evb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1073,7 +1073,7 @@ n32/n32l436-evb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32l43xml-stb:
n32/n32gxx_lxx/n32l43xml-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1081,7 +1081,7 @@ n32/n32l43xml-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32l43xrl-stb:
n32/n32gxx_lxx/n32l43xrl-stb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1089,7 +1089,7 @@ n32/n32l43xrl-stb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32wb45xl-evb:
n32/n32gxx_lxx/n32wb45xl-evb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
@@ -1097,6 +1097,28 @@ n32/n32wb45xl-evb:
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32hxxx/n32h487zgl7-evb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
iar: true
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32hxxx/n32h497zgl7-evb:
.config: true
README.md: true
gcc: arm-none-eabi-gcc
iar: true
mdk5: true
menuconfig: true
rtconfig.h: true
n32/n32hxxx/n32h760zil7-stb:
.config: true
gcc: arm-none-eabi-gcc
mdk5: true
menuconfig: true
rtconfig.h: true
n32g452xx/n32g452xx-mini-system:
.config: true
README.md: true
tools/ci/toolchain_bsp.yml
+16 -13
View File
@@ -126,18 +126,21 @@ arm-none-eabi-gcc:
- mm32l07x
- mm32l3xx
- msp432e401y-LaunchPad
- n32/n32g43xcl-stb
- n32/n32g457qel-stb
- n32/n32g45xcl-stb
- n32/n32g45xml-stb
- n32/n32g45xrl-stb
- n32/n32g45xvl-stb
- n32/n32g4frml-stb
- n32/n32l40xcl-stb
- n32/n32l436-evb
- n32/n32l43xml-stb
- n32/n32l43xrl-stb
- n32/n32wb45xl-evb
- n32/n32gxx_lxx/n32g43xcl-stb
- n32/n32gxx_lxx/n32g457qel-stb
- n32/n32gxx_lxx/n32g45xcl-stb
- n32/n32gxx_lxx/n32g45xml-stb
- n32/n32gxx_lxx/n32g45xrl-stb
- n32/n32gxx_lxx/n32g45xvl-stb
- n32/n32gxx_lxx/n32g4frml-stb
- n32/n32gxx_lxx/n32l40xcl-stb
- n32/n32gxx_lxx/n32l436-evb
- n32/n32gxx_lxx/n32l43xml-stb
- n32/n32gxx_lxx/n32l43xrl-stb
- n32/n32gxx_lxx/n32wb45xl-evb
- n32/n32hxxx/n32h487zgl7-evb
- n32/n32hxxx/n32h497zgl7-evb
- n32/n32hxxx/n32h760zil7-stb
- n32g452xx/n32g452xx-mini-system
- nrf5x/nrf51822
- nrf5x/nrf52832
@@ -323,7 +326,7 @@ arm-none-eabi-gcc:
- yichip/yc3121-pos
- yichip/yc3122-pos
- zynqmp-r5-axu4ev
count: 298
count: 301
download_url: https://github.com/RT-Thread/toolchains-ci/releases/download/v1.3/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2
avr32-gcc:
bsp: