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[bsp][nxp] support imxrt1180-evk board#11393
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This commit is contained in:
nxp-ran
GitHub
@@ -244,6 +244,8 @@
|
||||
"nxp/imx/imxrt/imxrt1064-nxp-evk",
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"nxp/imx/imxrt/imxrt1021-nxp-evk",
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"nxp/imx/imxrt/imxrt1170-nxp-evk",
|
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"nxp/imx/imxrt/imxrt1180-nxp-evk/cm33",
|
||||
"nxp/imx/imxrt/imxrt1180-nxp-evk/cm7",
|
||||
"nxp/mcx/mcxn/frdm-mcxn947",
|
||||
"nxp/mcx/mcxn/frdm-mcxn236",
|
||||
"nxp/mcx/mcxc/frdm-mcxc444",
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
# i.MX RT1180 EVK 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为 NXP i.MX RT1180 EVK 开发板提供的 BSP (板级支持包) 的初步说明。
|
||||
|
||||
目前支持CM33和CM7的独立编译，CM33作为主核，CM7作为从核。CM33的工程可以从External Flash直接XIP，CM7的工程可以加载到ITCM运行。
|
||||
|
||||
CM33对CM7的kick off将在后续版本中支持。
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||||
|
||||
主要内容如下：
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|
||||
- 开发板资源介绍
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||||
- BSP 快速上手
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||||
- 进阶使用方法
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|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
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|
||||
## 开发板介绍
|
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|
||||
双核i.MX RT1180采用主频达800MHz的Cortex®-M7内核和主频达240MHz的Arm Cortex-M33，同时提供一流的安全保障以及丰富的网络连接功能，包括双千兆以太网和多种工业通信接口。i.MX RT1180 MCU支持宽温度范围，适用于工业控制、电机驱动等市场。
|
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|
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## 外设支持
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|
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本 BSP 目前对外设仅支持UART，作为第一次push的测试，之后会逐步完善。外设支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :----------------- | :----------: | :------------------------------------|
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| USB 转串口 | 暂不支持 | |
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| SPI Flash | 暂不支持 | |
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| 以太网 | 暂不支持 | |
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||||
| **片上外设** | **支持情况** | **备注** |
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| GPIO | 暂不支持 | |
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| UART | 支持 | |
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| SPI | 暂不支持 | |
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||||
| I2C | 暂不支持 | |
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||||
| SDIO | 暂不支持 | |
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||||
| RTC | 暂不支持 | |
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| PWM | 暂不支持 | |
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| CAN | 暂不支持 | |
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|
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## 使用说明
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使用说明分为如下两个章节：
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|
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- 快速上手
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|
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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|
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK5 、IAR 以及 GCC 工程。下面以 IAR 开发环境为例，介绍如何将系统运行起来。
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**请注意！！！**
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在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的库，否则无法通过编译）：
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|
||||
```bash
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pkgs --update
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```
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||||
|
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生成IAR工程：scons --target=iar
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生成KEIL MDK5工程：scons --target=mdk5
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|
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或者直接编译GCC工程：scons -j8
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|
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#### 硬件连接
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使用数据线连接开发板到 PC，打开电源开关。
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#### 编译下载
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双击 project.eww 文件，打开 IAR 工程，编译并下载程序到开发板。
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> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
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#### 运行结果
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||||
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||||
下载程序成功之后，系统会自动运行。
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||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.2.2 build May 15 2026 17:19:35
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2006 - 2024 Copyright by RT-Thread team
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```
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### 进阶使用
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此 BSP 默认只开启了串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
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||||
1. 在 bsp 下打开 env 工具。
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2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
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3. 输入 `pkgs --update` 命令更新软件包。
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||||
4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。
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## 注意事项
|
||||
|
||||
暂无
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## 联系人信息
|
||||
|
||||
维护人:
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,47 @@
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[BREAKPOINTS]
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ForceImpTypeAny = 0
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ShowInfoWin = 1
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EnableFlashBP = 2
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BPDuringExecution = 0
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||||
[CFI]
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||||
CFISize = 0x00
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CFIAddr = 0x00
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[CPU]
|
||||
MonModeVTableAddr = 0xFFFFFFFF
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MonModeDebug = 0
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MaxNumAPs = 0
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||||
LowPowerHandlingMode = 0
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
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||||
ScriptFile=""
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||||
[FLASH]
|
||||
RMWThreshold = 0x400
|
||||
Loaders=""
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EraseType = 0x00
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
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||||
SkipProgOnCRCMatch = 1
|
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VerifyDownload = 1
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||||
AllowCaching = 1
|
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EnableFlashDL = 2
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Override = 1
|
||||
Device="MIMXRT1189xxx8_M33"
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[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
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RAMUsageLimit = 0x00
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||||
[SWO]
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||||
SWOLogFile=""
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[MEM]
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||||
RdOverrideOrMask = 0x00
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||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
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[RAM]
|
||||
VerifyDownload = 0x00
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||||
[MEM_MAP]
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[DYN_MEM_MAP]
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||||
NumUserRegion = 0x00
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||||
@@ -0,0 +1,11 @@
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mainmenu "RT-Thread Configuration"
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RTT_DIR := ../../../../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../../libraries/Kconfig"
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rsource "board/Kconfig"
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@@ -0,0 +1,14 @@
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# for module compiling
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import os
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from building import *
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||||
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cwd = GetCurrentDir()
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||||
objs = []
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list = os.listdir(cwd)
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||||
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||||
for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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||||
Return('objs')
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@@ -0,0 +1,88 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..')
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||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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||||
try:
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from building import *
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except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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||||
print(RTT_ROOT)
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exit(-1)
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||||
|
||||
def bsp_pkg_check():
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import subprocess
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||||
|
||||
check_paths = [
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os.path.join("packages", "nxp-imxrt-sdk-latest"),
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]
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||||
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||||
need_update = not all(os.path.exists(p) for p in check_paths)
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|
||||
if need_update:
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||||
print("\n===============================================================================")
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print("Dependency packages missing, please running 'pkgs --update'...")
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||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
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||||
print("===============================================================================")
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exit(1)
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||||
RegisterPreBuildingAction(bsp_pkg_check)
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||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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||||
if rtconfig.PLATFORM == 'armcc':
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||||
env = Environment(tools = ['mingw'],
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||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
# overwrite cflags, because cflags has '--C99'
|
||||
CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
else:
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./..')
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
imxrt_library = 'MIMXRT1180'
|
||||
rtconfig.BSP_LIBRARY_TYPE = imxrt_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join("packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,17 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
CPPDEFINES = ['__START=entry']
|
||||
else:
|
||||
CPPDEFINES = []
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-05-06 tyustli first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_gpio.h>
|
||||
#include <fsl_rgpio.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_kprintf("MIMXRT1180_CM33 Hello_World\r\n");
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,240 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config BSP_USING_QSPIFLASH
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MIMXRT1189CVM8C
|
||||
bool
|
||||
select SOC_IMXRT1180_SERIES
|
||||
select BSP_USING_QSPIFLASH
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
config SOC_MIMXRT1189CVM8C_CM33
|
||||
bool
|
||||
default y
|
||||
depends on SOC_MIMXRT1189CVM8C
|
||||
select ARCH_ARM_CORTEX_M33
|
||||
select ARCH_ARM_CORTEX_FPU
|
||||
select ARCH_ARM_CORTEX_SECURE
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_DMA
|
||||
bool "Enable DMA"
|
||||
default n
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
config BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
|
||||
config BSP_USING_USB
|
||||
bool "Enable USB"
|
||||
select RT_USING_USB_HOST
|
||||
default n
|
||||
|
||||
if BSP_USING_USB
|
||||
config BSP_USB0_HOST
|
||||
bool "Enable USB0"
|
||||
default n
|
||||
|
||||
config BSP_USB1_HOST
|
||||
bool "Enable USB1"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
select RT_USING_SDIO
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
if BSP_USING_SDIO
|
||||
config CODE_STORED_ON_SDCARD
|
||||
bool "Enable Code STORED On SDCARD"
|
||||
default n
|
||||
help
|
||||
"SD CARD work as boot devive"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_LPUART
|
||||
bool "Enable UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
if BSP_USING_LPUART
|
||||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default y
|
||||
|
||||
config BSP_LPUART1_RX_USING_DMA
|
||||
bool "Enable LPUART1 RX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_RX_USING_DMA
|
||||
int "Set LPUART1 RX DMA channel (0-32)"
|
||||
default 0
|
||||
|
||||
config BSP_LPUART1_TX_USING_DMA
|
||||
bool "Enable LPUART1 TX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_TX_USING_DMA
|
||||
int "Set LPUART1 TX DMA channel (0-32)"
|
||||
default 1
|
||||
|
||||
config BSP_USING_LPUART3
|
||||
bool "Enable LPUART3"
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_RX_USING_DMA
|
||||
bool "Enable LPUART3 RX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_RX_USING_DMA
|
||||
int "Set LPUART3 RX DMA channel (0-32)"
|
||||
default 0
|
||||
|
||||
config BSP_LPUART3_TX_USING_DMA
|
||||
bool "Enable LPUART3 TX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_TX_USING_DMA
|
||||
int "Set LPUART3 TX DMA channel (0-32)"
|
||||
default 1
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
select RT_USING_CAN
|
||||
default n
|
||||
if BSP_USING_CAN
|
||||
config BSP_USING_CAN3
|
||||
bool "Enable FLEXCAN3"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FLEXSPI
|
||||
bool "Enable FLEXSPI"
|
||||
default n
|
||||
if BSP_USING_FLEXSPI
|
||||
config BSP_USING_FLEXSPI1
|
||||
bool "Enable FLEXSPI1"
|
||||
default n
|
||||
config BSP_USING_FLEXSPI2
|
||||
bool "Enable FLEXSPI2"
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_ETH
|
||||
bool "Enable Ethernet"
|
||||
select RT_USING_NETDEV
|
||||
select RT_USING_LWIP
|
||||
default n
|
||||
|
||||
|
||||
if BSP_USING_ETH
|
||||
config BSP_USING_PHY
|
||||
select RT_USING_PHY
|
||||
bool "Enable ethernet phy"
|
||||
default y
|
||||
|
||||
if BSP_USING_PHY
|
||||
config PHY_USING_KSZ8081
|
||||
bool "i.MX RT1189EVK uses ksz8081 phy"
|
||||
default y
|
||||
|
||||
if PHY_USING_KSZ8081
|
||||
config PHY_KSZ8081_ADDRESS
|
||||
int "Specify address of phy device"
|
||||
default 2
|
||||
|
||||
config PHY_RESET_KSZ8081_PORT
|
||||
int "indicate port of reset"
|
||||
default 6
|
||||
|
||||
config PHY_RESET_KSZ8081_PIN
|
||||
int "indicate pin of reset"
|
||||
default 12
|
||||
|
||||
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
|
||||
bool "Enable the PHY ksz8081 RMII50M mode"
|
||||
depends on PHY_USING_KSZ8081
|
||||
default y
|
||||
endif
|
||||
endif
|
||||
|
||||
if BSP_USING_PHY
|
||||
config PHY_USING_RTL8211F
|
||||
bool "i.MX RT1189EVK uses rtl8211f phy"
|
||||
default y
|
||||
|
||||
if PHY_USING_RTL8211F
|
||||
config PHY_RTL8211F_ADDRESS
|
||||
int "Specify address of phy device"
|
||||
default 1
|
||||
|
||||
config PHY_RESET_RTL8211F_PORT
|
||||
int "indicate port of reset"
|
||||
default 5
|
||||
|
||||
config PHY_RESET_RTL8211F_PIN
|
||||
int "indicate pin of reset"
|
||||
default 14
|
||||
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FS
|
||||
bool "Enable File System"
|
||||
select RT_USING_DFS_DEVFS
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
if BSP_USING_FS
|
||||
config BSP_USING_SDCARD_FATFS
|
||||
bool "Enable SDCARD (FATFS)"
|
||||
select BSP_USING_SDIO
|
||||
select RT_USING_DFS_ELMFAT
|
||||
default n
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,366 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if __CORTEX_M == 7
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */
|
||||
#else
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */
|
||||
#endif
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if __CORTEX_M == 7
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */
|
||||
#else
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */
|
||||
#endif
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v15.0
|
||||
processor: MIMXRT1189xxxxx
|
||||
package_id: MIMXRT1189CVM8C
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.15.9
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_rgpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
|
||||
slew_rate: Slow}
|
||||
- {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
|
||||
slew_rate: Slow}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins, assigned for the Cortex-M33 core.
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
|
||||
|
||||
// /* GPIO configuration on GPIO_AD_27 (pin M16) */
|
||||
// rgpio_pin_config_t gpio4_pinM16_config = {
|
||||
// .pinDirection = kRGPIO_DigitalOutput,
|
||||
// .outputLogic = 1U,
|
||||
// };
|
||||
// /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
|
||||
// RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config);
|
||||
|
||||
// IOMUXC_SetPinMux(
|
||||
// IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
|
||||
// 0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
}
|
||||
|
||||
void BOARD_InitLeds(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
|
||||
|
||||
/* GPIO configuration on GPIO_AD_27 (pin M16) */
|
||||
rgpio_pin_config_t gpio4_pinM16_config = {
|
||||
.pinDirection = kRGPIO_DigitalOutput,
|
||||
.outputLogic = 1U,
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
|
||||
RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config);
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
|
||||
0U);
|
||||
}
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
void BOARD_InitLeds(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,31 @@
|
||||
Import('rtconfig')
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/clock_config.c
|
||||
MCUX_Config/pin_mux.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
|
||||
CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33']
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION']
|
||||
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
# CPPDEFINES += ['SDK_DEBUGCONSOLE']
|
||||
CPPDEFINES += ['NDEBUG']
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
CPPDEFINES += ['NDEBUG']
|
||||
# CPPDEFINES += ['FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,191 @@
|
||||
/*
|
||||
* Copyright 2021-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "pin_mux.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_rgpio.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "MIMXRT1180-EVK"
|
||||
#ifndef DEBUG_CONSOLE_UART_INDEX
|
||||
#define DEBUG_CONSOLE_UART_INDEX 1
|
||||
#endif
|
||||
|
||||
/* The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#ifndef BOARD_DEBUG_UART_CLK_ROOT
|
||||
#define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102
|
||||
#endif
|
||||
#ifndef BOARD_DEBUG_UART_BASEADDR
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||
#endif
|
||||
#ifndef BOARD_DEBUG_UART_INSTANCE
|
||||
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||
#endif
|
||||
#ifndef BOARD_UART_IRQ
|
||||
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||
#endif
|
||||
#ifndef BOARD_UART_IRQ_HANDLER
|
||||
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||
#endif
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||
#endif
|
||||
|
||||
/* Definitions for eRPC MU transport layer */
|
||||
#if defined(FSL_FEATURE_MU_SIDE_A)
|
||||
#define MU_BASE MU1_MUA
|
||||
#define MU_IRQ MU1_IRQn
|
||||
#define MU_IRQ_HANDLER MU1_IRQHandler
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_MU_SIDE_B)
|
||||
#define MU_BASE MU1_MUB
|
||||
#define MU_IRQ MU1_IRQn
|
||||
#define MU_IRQ_HANDLER MU1_IRQHandler
|
||||
#endif
|
||||
#define MU_IRQ_PRIORITY (2)
|
||||
|
||||
/*! @brief The USER_LED used for board */
|
||||
#define LOGIC_LED_ON (1U)
|
||||
#define LOGIC_LED_OFF (0U)
|
||||
#ifndef BOARD_USER_LED_GPIO
|
||||
#define BOARD_USER_LED_GPIO RGPIO4
|
||||
#endif
|
||||
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||
#define BOARD_USER_LED_GPIO_PIN (27U)
|
||||
#endif
|
||||
|
||||
#define USER_LED_INIT(output) \
|
||||
RGPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||
BOARD_USER_LED_GPIO->PDDR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||
#define USER_LED_OFF() \
|
||||
RGPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||
#define USER_LED_ON() RGPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||
#define USER_LED_TOGGLE() \
|
||||
RGPIO_PortToggle(BOARD_USER_LED_GPIO, 1u << BOARD_USER_LED_GPIO_PIN) /*!< Toggle target USER_LED */
|
||||
|
||||
/*! @brief Define the port interrupt number for the board switches */
|
||||
#ifndef BOARD_USER_BUTTON_GPIO
|
||||
#define BOARD_USER_BUTTON_GPIO RGPIO1
|
||||
#endif
|
||||
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||
#define BOARD_USER_BUTTON_GPIO_PIN (4U)
|
||||
#endif
|
||||
#define BOARD_USER_BUTTON_IRQ GPIO1_0_IRQn
|
||||
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO1_0_IRQHandler
|
||||
#define BOARD_USER_BUTTON_NAME "SW8"
|
||||
|
||||
#define BOARD_WAKEUP_BUTTON_NAME "SW4"
|
||||
|
||||
/*! @brief The board flash size */
|
||||
#define BOARD_FLASH_SIZE (0x1000000U)
|
||||
|
||||
/*! @brief The Ethernet PHY addresses. */
|
||||
#define BOARD_EP0_PHY_ADDR (0x03U)
|
||||
#define BOARD_SWT_PORT0_PHY_ADDR (0x02U)
|
||||
#define BOARD_SWT_PORT1_PHY_ADDR (0x05U)
|
||||
#define BOARD_SWT_PORT2_PHY_ADDR (0x04U)
|
||||
#define BOARD_SWT_PORT3_PHY_ADDR (0x07U)
|
||||
|
||||
/*! @brief The Ethernet PHY type of the board */
|
||||
#define BOARD_USE_NETC_PHY_RTL8201
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x07U)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
|
||||
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_INDEX (1)
|
||||
|
||||
#define BOARD_HAS_SDCARD (1U)
|
||||
|
||||
/* @Brief Board accelerator sensor configuration */
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C2
|
||||
/* Clock divider for LPI2C clock source */
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetRootClockFreq(kCLOCK_Root_Lpi2c0102))
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C2
|
||||
#define BOARD_CODEC_I2C_INSTANCE 2U
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (6U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ (24000000U)
|
||||
|
||||
/* SD card detection method when using wifi module. */
|
||||
#define BOARD_WIFI_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostDATA3
|
||||
|
||||
#define BOARD_BT_UART_INSTANCE 10
|
||||
#define BOARD_BT_UART_BAUDRATE 3000000
|
||||
#define BOARD_BT_UART_CLK_FREQ CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910);
|
||||
|
||||
/*! @brief The Ethernet port used by network examples, default use 1G port. */
|
||||
/* Below comment is for test script to easily define which port to be used, please don't delete. */
|
||||
/* @TEST_ANCHOR */
|
||||
#ifndef BOARD_NETWORK_USE_100M_ENET_PORT
|
||||
#define BOARD_NETWORK_USE_100M_ENET_PORT (0U)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_ConfigMPU(void);
|
||||
|
||||
void BOARD_FlexspiClockSafeConfig(void);
|
||||
AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider));
|
||||
AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base));
|
||||
AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base));
|
||||
|
||||
void EdgeLock_SetClock(uint8_t mux, uint8_t div);
|
||||
void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage);
|
||||
|
||||
void BOARD_NETC_Init(void);
|
||||
void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega);
|
||||
void BOARD_CommonSetting(void);
|
||||
|
||||
/* </RDTConfigurator>*/
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
|
||||
extern int Image$$ARM_LIB_HEAP$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
|
||||
#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit)
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__section_begin("HEAP"))
|
||||
#define HEAP_END (__section_end("HEAP"))
|
||||
#elif defined(__GNUC__)
|
||||
extern int __HeapBase;
|
||||
extern int __HeapLimit;
|
||||
#define HEAP_BEGIN ((void *)&__HeapBase)
|
||||
#define HEAP_END ((void *)&__HeapLimit)
|
||||
#endif
|
||||
|
||||
/*! @brief The board flash size */
|
||||
#define BOARD_FLASH_SIZE (0x1000000U)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
+1041
File diff suppressed because it is too large
Load Diff
+417
@@ -0,0 +1,417 @@
|
||||
/*
|
||||
* Copyright 2023-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
FUNC void _FLEXSPI1_ModuleReset(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0
|
||||
if( (reg & 0x02) == 0) // Module Enabled
|
||||
{
|
||||
reg = _RDWORD(0x425E0000);
|
||||
_WDWORD(0x425E0000, (reg | 0x1));
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x425E0000);
|
||||
} while ((reg & 0x1) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI1_WaitBusIdle(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0
|
||||
if( (reg & 0x02) == 0) // Module Enabled
|
||||
{
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x425E00E0);
|
||||
} while ((reg & 0x3) != 0x3);
|
||||
}
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI1_ClockInit(void)
|
||||
{
|
||||
_WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1
|
||||
|
||||
// Set flexspi1 root clock, use ROSC400, div = 4 = 1+3
|
||||
_WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI1_SetPinForQuadMode(void) {
|
||||
// Set 4 Pin Mode
|
||||
// IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS
|
||||
_WDWORD(0x42A1023C, 0x17);
|
||||
_WDWORD(0x42A10544, 0x1);
|
||||
// IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK
|
||||
_WDWORD(0x42A10240, 0x17);
|
||||
// IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B
|
||||
_WDWORD(0x42A10244, 0x17);
|
||||
// IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00
|
||||
_WDWORD(0x42A10248, 0x17);
|
||||
// IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01
|
||||
_WDWORD(0x42A1024C, 0x17);
|
||||
// IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02
|
||||
_WDWORD(0x42A10250, 0x17);
|
||||
// IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03
|
||||
_WDWORD(0x42A10254, 0x17);
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI1_ModuleInit(void) {
|
||||
|
||||
unsigned int reg;
|
||||
reg = _RDWORD(0x425E0000);
|
||||
_WDWORD(0x425E0000, (reg & 0xFFFFFFFD));
|
||||
|
||||
//FLEXSPI1->MCR0 = 0xFFFF8010;
|
||||
_WDWORD(0x425E0000, 0xFFFF8010);
|
||||
//FLEXSPI1->MCR2 = 0x200001F7;
|
||||
_WDWORD(0x425E0008, 0x200001F7);
|
||||
//FLEXSPI1->AHBCR = 0x78;
|
||||
_WDWORD(0x425E000C, 0x78);
|
||||
|
||||
//FLEXSPI1->FLSHCR0[0] = 0x00004000;
|
||||
_WDWORD(0x425E0060, 0x00004000);
|
||||
|
||||
//FLEXSPI1->FLSHCR4 = 0xC3;
|
||||
_WDWORD(0x425E0094, 0xC3);
|
||||
//FLEXSPI1->IPRXFCR = 0x1C;
|
||||
_WDWORD(0x425E00B8, 0x1C);
|
||||
|
||||
//FLEXSPI1->LUTKEY = 0x5AF05AF0UL;
|
||||
_WDWORD(0x425E0018, 0x5AF05AF0);
|
||||
//FLEXSPI1->LUTCR = 0x02;
|
||||
_WDWORD(0x425E001C, 0x02);
|
||||
|
||||
//FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad
|
||||
_WDWORD(0x425E0200, 0x0A1804EB);
|
||||
//FLEXSPI1->LUT[1] = 0x26043206;
|
||||
_WDWORD(0x425E0204, 0x26043206);
|
||||
//FLEXSPI1->LUT[2] = 0x00000000;
|
||||
_WDWORD(0x425E0208, 0x00000000);
|
||||
//FLEXSPI1->LUT[3] = 0x00000000;
|
||||
_WDWORD(0x425E020C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[4] = 0x00000406; // Write Enable
|
||||
_WDWORD(0x425E0210, 0x00000406);
|
||||
//FLEXSPI1->LUT[5] = 0x00000000;
|
||||
_WDWORD(0x425E0214, 0x00000000);
|
||||
//FLEXSPI1->LUT[6] = 0x00000000;
|
||||
_WDWORD(0x425E0218, 0x00000000);
|
||||
//FLEXSPI1->LUT[7] = 0x00000000;
|
||||
_WDWORD(0x425E021C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1
|
||||
_WDWORD(0x425E0220, 0x20040401);
|
||||
//FLEXSPI1->LUT[9] = 0x00000000;
|
||||
_WDWORD(0x425E0224, 0x00000000);
|
||||
//FLEXSPI1->LUT[10] = 0x00000000;
|
||||
_WDWORD(0x425E0228, 0x00000000);
|
||||
//FLEXSPI1->LUT[11] = 0x00000000;
|
||||
_WDWORD(0x425E022C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[12] = 0x24040405; // Read s1
|
||||
_WDWORD(0x425E0230, 0x24040405);
|
||||
//FLEXSPI1->LUT[13] = 0x00000000;
|
||||
_WDWORD(0x425E0234, 0x00000000);
|
||||
//FLEXSPI1->LUT[14] = 0x00000000;
|
||||
_WDWORD(0x425E0238, 0x00000000);
|
||||
//FLEXSPI1->LUT[15] = 0x00000000;
|
||||
_WDWORD(0x425E023C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[16] = 0x00000404; // Write Disable
|
||||
_WDWORD(0x425E0240, 0x00000404);
|
||||
//FLEXSPI1->LUT[17] = 0x00000000;
|
||||
_WDWORD(0x425E0244, 0x00000000);
|
||||
//FLEXSPI1->LUT[18] = 0x00000000;
|
||||
_WDWORD(0x425E0248, 0x00000000);
|
||||
//FLEXSPI1->LUT[19] = 0x00000000;
|
||||
_WDWORD(0x425E024C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2
|
||||
_WDWORD(0x425E0250, 0x20040431);
|
||||
//FLEXSPI1->LUT[21] = 0x00000000;
|
||||
_WDWORD(0x425E0254, 0x00000000);
|
||||
//FLEXSPI1->LUT[22] = 0x00000000;
|
||||
_WDWORD(0x425E0258, 0x00000000);
|
||||
//FLEXSPI1->LUT[23] = 0x00000000;
|
||||
_WDWORD(0x425E025C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[24] = 0x24040435; // Read s2
|
||||
_WDWORD(0x425E0260, 0x24040435);
|
||||
//FLEXSPI1->LUT[25] = 0x00000000;
|
||||
_WDWORD(0x425E0264, 0x00000000);
|
||||
//FLEXSPI1->LUT[26] = 0x00000000;
|
||||
_WDWORD(0x425E0268, 0x00000000);
|
||||
//FLEXSPI1->LUT[27] = 0x00000000;
|
||||
_WDWORD(0x425E026C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile
|
||||
_WDWORD(0x425E0270, 0x00000450);
|
||||
//FLEXSPI1->LUT[29] = 0x00000000;
|
||||
_WDWORD(0x425E0274, 0x00000000);
|
||||
//FLEXSPI1->LUT[30] = 0x00000000;
|
||||
_WDWORD(0x425E0278, 0x00000000);
|
||||
//FLEXSPI1->LUT[31] = 0x00000000;
|
||||
_WDWORD(0x425E027C, 0x00000000);
|
||||
|
||||
//FLEXSPI1->LUTKEY = 0x5AF05AF0UL;
|
||||
_WDWORD(0x425E0018, 0x5AF05AF0);
|
||||
//FLEXSPI1->LUTCR = 0x01;
|
||||
_WDWORD(0x425E001C, 0x01);
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI2_ModuleReset(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0
|
||||
if( (reg & 0x02) == 0) // Module Enabled
|
||||
{
|
||||
reg = _RDWORD(0x445E0000);
|
||||
_WDWORD(0x445E0000, (reg | 0x1));
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x445E0000);
|
||||
} while ((reg & 0x1) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI2_WaitBusIdle(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0
|
||||
if( (reg & 0x02) == 0) // Module Enabled
|
||||
{
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x445E00E0);
|
||||
} while ((reg & 0x3) != 0x3);
|
||||
}
|
||||
}
|
||||
|
||||
FUNC void _FlexSPI2_SetPinForOctalMode(void)
|
||||
{
|
||||
// Config IOMUX for FlexSPI2
|
||||
_WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03
|
||||
_WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02
|
||||
_WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01
|
||||
_WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00
|
||||
_WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00
|
||||
_WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01
|
||||
_WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02
|
||||
_WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03
|
||||
_WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B
|
||||
_WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS
|
||||
_WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK
|
||||
|
||||
//The input daisy!!
|
||||
_WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03
|
||||
_WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02
|
||||
_WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01
|
||||
_WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00
|
||||
_WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00
|
||||
_WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01
|
||||
_WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02
|
||||
_WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03
|
||||
_WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS
|
||||
_WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK
|
||||
|
||||
// PAD ctrl
|
||||
_WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03
|
||||
_WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02
|
||||
_WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01
|
||||
_WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00
|
||||
_WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00
|
||||
_WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01
|
||||
_WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02
|
||||
_WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03
|
||||
_WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B
|
||||
_WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS
|
||||
_WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI2_ClockInit(void)
|
||||
{
|
||||
_WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1
|
||||
|
||||
// Set flexspi2 root clock, use ROSC400, div = 2 = 1+1
|
||||
_WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2
|
||||
}
|
||||
|
||||
FUNC void _FLEXSPI2_ModuleInit(void)
|
||||
{
|
||||
// Config FlexSPI2 Registers
|
||||
|
||||
unsigned int reg;
|
||||
reg = _RDWORD(0x445E0000);
|
||||
_WDWORD(0x445E0000, (reg & 0xFFFFFFFD));
|
||||
|
||||
_FLEXSPI2_ModuleReset();
|
||||
|
||||
_WDWORD(0x445E0000, 0xFFFF3032); // MCR0
|
||||
_WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1
|
||||
_WDWORD(0x445E0008, 0x200001F7); // MCR2
|
||||
_WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable
|
||||
_WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0
|
||||
_WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0
|
||||
_WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0
|
||||
_WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0
|
||||
_WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0
|
||||
_WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0
|
||||
_WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0
|
||||
_WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0
|
||||
_WDWORD(0x445E00B8, 0x00000000); // IPRXFCR
|
||||
_WDWORD(0x445E00BC, 0x00000000); // IPTXFCR
|
||||
|
||||
_WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0
|
||||
_WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0
|
||||
_WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0
|
||||
_WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0
|
||||
|
||||
_FLEXSPI2_WaitBusIdle();
|
||||
|
||||
_WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0
|
||||
_WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1
|
||||
_WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2
|
||||
|
||||
_FLEXSPI2_WaitBusIdle();
|
||||
|
||||
_WDWORD(0x445E00C0, 0x00000079); // DLLCRA
|
||||
_WDWORD(0x445E0000, 0xFFFF3030); // MCR0
|
||||
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x445E00E8);
|
||||
} while (0x3 != (reg & 0x3));
|
||||
_Sleep_(1);
|
||||
// __delay(100);//100us
|
||||
|
||||
_WDWORD(0x445E0000, 0xFFFF3032); // MCR0
|
||||
_WDWORD(0x445E0094, 0x000000C2); // FLASHCR4
|
||||
_WDWORD(0x445E0094, 0x000000C6); // FLASHCR4
|
||||
_WDWORD(0x445E0000, 0xFFFF3030); // MCR0
|
||||
|
||||
_FLEXSPI2_WaitBusIdle();
|
||||
|
||||
_WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY
|
||||
_WDWORD(0x445E001C, 0x00000002); // LUTCR
|
||||
_WDWORD(0x445E0200, 0x8B1887A0); // LUT[0]
|
||||
_WDWORD(0x445E0204, 0xB7078F10); // LUT[1]
|
||||
_WDWORD(0x445E0208, 0x0000A704); // LUT[2]
|
||||
_WDWORD(0x445E020C, 0x00000000); // LUT[3]
|
||||
_WDWORD(0x445E0210, 0x8B188720); // LUT[4]
|
||||
_WDWORD(0x445E0214, 0xB7078F10); // LUT[5]
|
||||
_WDWORD(0x445E0218, 0x0000A304); // LUT[6]
|
||||
_WDWORD(0x445E021C, 0x00000000); // LUT[7]
|
||||
_WDWORD(0x445E0220, 0x8B1887E0); // LUT[8]
|
||||
_WDWORD(0x445E0224, 0xB7078F10); // LUT[9]
|
||||
_WDWORD(0x445E0228, 0x0000A704); // LUT[10]
|
||||
_WDWORD(0x445E022C, 0x00000000); // LUT[11]
|
||||
_WDWORD(0x445E0230, 0x8B188760); // LUT[12]
|
||||
_WDWORD(0x445E0234, 0xA3028F10); // LUT[13]
|
||||
_WDWORD(0x445E0238, 0x00000000); // LUT[14]
|
||||
_WDWORD(0x445E023C, 0x00000000); // LUT[15]
|
||||
_WDWORD(0x445E0240, 0x00000000); // LUT[16]
|
||||
_WDWORD(0x445E0244, 0x00000000); // LUT[17]
|
||||
_WDWORD(0x445E0248, 0x00000000); // LUT[18]
|
||||
_WDWORD(0x445E024C, 0x00000000); // LUT[19]
|
||||
_WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY
|
||||
_WDWORD(0x445E001C, 0x00000001); // LUTCR
|
||||
|
||||
/* Restore hyperram CR0 register */
|
||||
_WDWORD(0x445E00A0, 0x00001000); // IPCR0
|
||||
_WDWORD(0x445E00A4, 0x00030002); // IPCR1
|
||||
_WDWORD(0x445E00BC, 0x00000001); // IPTXFCR
|
||||
_WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0
|
||||
_WDWORD(0x445E0014, 0x00000040); // INTR
|
||||
_WDWORD(0x445E00B0, 0x00000001); // IPCMD
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x445E0014); // INTR
|
||||
} while ((reg & 0x1) == 0x0);
|
||||
_WDWORD(0x445E0014, 0x00000001); // INTR
|
||||
|
||||
/* Restore hyperram CR1 register */
|
||||
_WDWORD(0x445E00A0, 0x00001002); // IPCR0
|
||||
_WDWORD(0x445E00A4, 0x00030002); // IPCR1
|
||||
_WDWORD(0x445E00BC, 0x00000001); // IPTXFCR
|
||||
_WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1
|
||||
_WDWORD(0x445E0014, 0x00000040); // INTR
|
||||
_WDWORD(0x445E00B0, 0x00000001); // IPCMD
|
||||
do
|
||||
{
|
||||
reg = _RDWORD(0x445E0014); // INTR
|
||||
} while ((reg & 0x1) == 0x0);
|
||||
_WDWORD(0x445E0014, 0x00000001); // INTR
|
||||
|
||||
_FLEXSPI2_ModuleReset();
|
||||
}
|
||||
|
||||
FUNC void Flash_Init(void)
|
||||
{
|
||||
printf("***************************************************\r\n");
|
||||
printf("Init Flash\r\n");
|
||||
|
||||
_FLEXSPI1_WaitBusIdle();
|
||||
_FLEXSPI1_ModuleReset();
|
||||
|
||||
_FLEXSPI1_SetPinForQuadMode();
|
||||
_FLEXSPI1_ClockInit();
|
||||
_FLEXSPI1_ModuleInit();
|
||||
|
||||
printf("***************************************************\r\n");
|
||||
}
|
||||
|
||||
FUNC void HyperRAM_Init(void)
|
||||
{
|
||||
printf("***************************************************\r\n");
|
||||
printf("Init HyperRAM\r\n");
|
||||
|
||||
_FLEXSPI2_WaitBusIdle();
|
||||
_FLEXSPI2_ModuleReset();
|
||||
|
||||
_FlexSPI2_SetPinForOctalMode();
|
||||
_FLEXSPI2_ClockInit();
|
||||
_FLEXSPI2_ModuleInit();
|
||||
|
||||
printf("***************************************************\r\n");
|
||||
}
|
||||
|
||||
FUNC void ClearNVIC(void) {
|
||||
printf("***************************************************\r\n");
|
||||
printf("Clear NVIC\r\n");
|
||||
printf("***************************************************\r\n");
|
||||
memset(0xE000E180, 0x40, 0xFF);
|
||||
memset(0xE000E280, 0x40, 0xFF);
|
||||
}
|
||||
|
||||
FUNC void Setup_PC_SP(void)
|
||||
{
|
||||
SP = _RDWORD(0x2800B000); // Setup Stack Pointer
|
||||
PC = _RDWORD(0x2800B004); // Setup Program Counter
|
||||
_WDWORD(0xE000ED08, 0x2800B000); // Setup Vector Table Offset Register
|
||||
}
|
||||
|
||||
FUNC void Setup (void) {
|
||||
ClearNVIC();
|
||||
Flash_Init();
|
||||
HyperRAM_Init();
|
||||
Setup_PC_SP();
|
||||
}
|
||||
|
||||
FUNC void OnResetExec (void)
|
||||
{
|
||||
// executes upon RESET
|
||||
Setup();
|
||||
}
|
||||
|
||||
// Disable the software breakpoint for nor flash memory region
|
||||
SBC 0x28000000, 0x28FFFFFF, 0
|
||||
|
||||
Setup();
|
||||
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1189CVM8B_cm33
|
||||
** MIMXRT1189CVM8C_cm33
|
||||
** MIMXRT1189XVM8B_cm33
|
||||
** MIMXRT1189XVM8C_cm33
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1180RM, Rev 5, 01/2024
|
||||
** Version: rev. 2.0, 2024-01-18
|
||||
** Build: b250310
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2025 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Board memory map */
|
||||
|
||||
define symbol m_code_tcm_start = 0x0FFE0000;
|
||||
define symbol m_code_tcm_size = 0x00020000;
|
||||
|
||||
define symbol m_system_tcm_start = 0x20000000;
|
||||
define symbol m_system_tcm_size = 0x00020000;
|
||||
|
||||
define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */
|
||||
define symbol m_ocram1_size = 0x0007C000;
|
||||
|
||||
define symbol m_ocram2_start = 0x20500000;
|
||||
define symbol m_ocram2_size = 0x00040000;
|
||||
|
||||
/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */
|
||||
define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000;
|
||||
define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000;
|
||||
define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000;
|
||||
define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000;
|
||||
define symbol m_flash_start = 0x28000000;
|
||||
define symbol m_flash_size = 0x00800000;
|
||||
|
||||
define symbol m_core1_image_maximum_size = 0x00040000;
|
||||
|
||||
/* General definition */
|
||||
define symbol m_fcb_offset = 0x400;
|
||||
define symbol m_fcb_size = 0x200;
|
||||
define symbol m_fcb_start = m_flash_start + m_fcb_offset;
|
||||
define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1;
|
||||
|
||||
define symbol m_xmcd_offset = 0x800;
|
||||
define symbol m_xmcd_size = 0x400;
|
||||
define symbol m_xmcd_start = m_flash_start + m_xmcd_offset;
|
||||
define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1;
|
||||
|
||||
define symbol m_container_offset = 0x1000;
|
||||
define symbol m_container_size = 0x2000;
|
||||
define symbol m_container_start = m_flash_start + m_container_offset;
|
||||
define symbol m_container_end = m_container_start + m_container_size - 1;
|
||||
|
||||
define symbol app_image_offset = 0x0000B000;
|
||||
define symbol vector_table_size = 0x00000400;
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x01000;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x04000;
|
||||
}
|
||||
|
||||
define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0);
|
||||
define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1;
|
||||
define symbol m_qadata_start = m_system_tcm_start;
|
||||
define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1;
|
||||
define symbol m_ram_vector_table_start = m_code_tcm_start;
|
||||
|
||||
/* Target specific definition, code & data allocation */
|
||||
define symbol m_code_size = m_flash_size - app_image_offset;
|
||||
define symbol m_data_size = m_system_tcm_size;
|
||||
define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */
|
||||
define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */
|
||||
|
||||
define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0;
|
||||
|
||||
define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0;
|
||||
|
||||
define symbol m_text_start = m_flash_start + app_image_offset;
|
||||
define symbol m_text_end = m_text_start + m_code_size - 1;
|
||||
define symbol m_interrupts_start = m_text_start;
|
||||
|
||||
define symbol m_data_start = m_system_tcm_start;
|
||||
define symbol m_data_end = m_data_start + m_data_size - 1;
|
||||
|
||||
define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size;
|
||||
define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1;
|
||||
|
||||
define symbol m_heap_start = m_ocram1_start;
|
||||
define symbol m_heap_end = m_ncache_start - 1;
|
||||
|
||||
if (isdefinedsymbol(__use_shmem__)) {
|
||||
define symbol m_rpmsg_sh_mem_start = m_ocram2_start;
|
||||
define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1;
|
||||
}
|
||||
|
||||
/* Region definition */
|
||||
define memory mem with size = 4G;
|
||||
define region FCB_region = mem:[from m_fcb_start to m_fcb_end];
|
||||
define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end];
|
||||
define region CONTAINER_region = mem:[from m_container_start to m_container_end];
|
||||
define region TEXT_region = mem:[from m_text_start to m_text_end];
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
|
||||
define region HEAP_region = mem:[from m_heap_start to m_heap_end];
|
||||
define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
|
||||
define region QADATA_region = mem:[from m_qadata_start to m_qadata_end];
|
||||
if (isdefinedsymbol(__use_shmem__)) {
|
||||
define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end];
|
||||
}
|
||||
|
||||
/* Exported symbol definition */
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_ram_vector_table_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size;
|
||||
define exported symbol __NCACHE_REGION_START = m_ncache_start;
|
||||
define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
|
||||
define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region);
|
||||
define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region);
|
||||
define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region);
|
||||
if (isdefinedsymbol(__use_shmem__)) {
|
||||
define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start;
|
||||
define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end;
|
||||
define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start;
|
||||
define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1;
|
||||
}
|
||||
|
||||
/* Block definition */
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
define block QACCESS_CODE { section CodeQuickAccess };
|
||||
define block QACCESS_DATA { section DataQuickAccess };
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image };
|
||||
|
||||
define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK };
|
||||
|
||||
initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess };
|
||||
do not initialize { section .noinit };
|
||||
if (isdefinedsymbol(__use_shmem__)) {
|
||||
do not initialize { section rpmsg_sh_mem_section };
|
||||
}
|
||||
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container };
|
||||
|
||||
place in FCB_region { section .boot_hdr.conf };
|
||||
place in XMCD_region { section .boot_hdr.xmcd_data };
|
||||
place in CONTAINER_region { section .boot_hdr.container };
|
||||
place in TEXT_region { first block RO };
|
||||
place in QACODE_region { section .textrw, block QACCESS_CODE };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { block QACCESS_DATA };
|
||||
place in NCACHE_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
if (isdefinedsymbol(__heap_noncacheable__)) {
|
||||
place in NCACHE_region { last block HEAP };
|
||||
} else {
|
||||
place in HEAP_region { last block HEAP };
|
||||
}
|
||||
if (isdefinedsymbol(__use_shmem__)) {
|
||||
place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section };
|
||||
}
|
||||
@@ -0,0 +1,376 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1189CVM8B_cm33
|
||||
** MIMXRT1189XVM8B_cm33
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1180RM, Rev 2, 12/2022
|
||||
** Version: rev. 0.1, 2021-03-09
|
||||
** Build: b240109
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2024 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Board memory map */
|
||||
m_code_tcm_start = 0x0FFE0000;
|
||||
m_code_tcm_size = 0x00020000;
|
||||
m_system_tcm_start = 0x20000000;
|
||||
m_system_tcm_size = 0x00020000;
|
||||
m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */
|
||||
m_ocram1_size = 0x0007C000;
|
||||
m_ocram2_start = 0x20500000;
|
||||
m_ocram2_size = 0x00040000;
|
||||
|
||||
/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */
|
||||
m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000;
|
||||
m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000;
|
||||
m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000;
|
||||
m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000;
|
||||
m_flash_start = 0x28000000;
|
||||
m_flash_size = 0x01000000;
|
||||
|
||||
m_core1_image_maximum_size = 0x00040000;
|
||||
|
||||
/* General definition */
|
||||
m_fcb_offset = 0x400;
|
||||
m_fcb_size = 0x200;
|
||||
m_xmcd_offset = 0x800;
|
||||
m_xmcd_size = 0x400;
|
||||
m_container_offset = 0x1000;
|
||||
m_container_size = 0x2000;
|
||||
|
||||
m_fcb_start = m_flash_start + m_fcb_offset;
|
||||
m_fcb_end = m_fcb_start + m_fcb_size - 1;
|
||||
m_xmcd_start = m_flash_start + m_xmcd_offset;
|
||||
m_xmcd_end = m_xmcd_start + m_xmcd_size - 1;
|
||||
m_container_start = m_flash_start + m_container_offset;
|
||||
m_container_end = m_container_start + m_container_size - 1;
|
||||
|
||||
app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000;
|
||||
vector_table_size = 0x00000400;
|
||||
m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0);
|
||||
m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1;
|
||||
m_qadata_start = m_system_tcm_start;
|
||||
m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1;
|
||||
m_ram_vector_table_start = m_code_tcm_start;
|
||||
m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000;
|
||||
|
||||
/* Target specific definition, code & data allocation */
|
||||
m_code_size = m_flash_size - app_image_offset - vector_table_size;
|
||||
m_data_size = m_system_tcm_size;
|
||||
m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */
|
||||
m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */
|
||||
|
||||
m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : 0;
|
||||
|
||||
m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0;
|
||||
|
||||
m_interrupts_start = m_flash_start + app_image_offset;
|
||||
m_interrupts_end = m_interrupts_start + vector_table_size - 1;
|
||||
|
||||
m_text_start = m_interrupts_end + 1;
|
||||
m_text_end = m_text_start + m_code_size - 1;
|
||||
|
||||
m_data_start = m_system_tcm_start;
|
||||
m_data_end = m_data_start + m_data_size - 1;
|
||||
|
||||
m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size;
|
||||
m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0);
|
||||
|
||||
m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start;
|
||||
m_heap_end = m_heap_start + m_heap_size - 1;
|
||||
|
||||
m_rpmsg_sh_mem_start = m_ocram2_start;
|
||||
m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1;
|
||||
|
||||
/* Exported symbol definition */
|
||||
__VECTOR_TABLE = m_interrupts_start;
|
||||
__VECTOR_RAM = m_ram_vector_table_start;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size;
|
||||
__CONTAINER_IMG_OFFSET = m_interrupts_start - m_container_start;
|
||||
|
||||
__NCACHE_REGION_START = m_ncache_start;
|
||||
__NCACHE_REGION_SIZE = m_ncache_size;
|
||||
__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0;
|
||||
__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_fcb_data (RX) : ORIGIN = m_fcb_start, LENGTH = m_fcb_end - m_fcb_start + 1
|
||||
m_xmcd_data (RX) : ORIGIN = m_xmcd_start, LENGTH = m_xmcd_end - m_xmcd_start + 1
|
||||
m_container_data (RX) : ORIGIN = m_container_start, LENGTH = m_container_end - m_container_start + 1
|
||||
m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES
|
||||
m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1
|
||||
m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1
|
||||
m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1
|
||||
m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1
|
||||
m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1
|
||||
m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1
|
||||
m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1
|
||||
m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
.fcb :
|
||||
{
|
||||
KEEP(*(.boot_hdr.conf))
|
||||
} > m_fcb_data
|
||||
|
||||
.xmcd :
|
||||
{
|
||||
KEEP(*(.boot_hdr.xmcd_data))
|
||||
} > m_xmcd_data
|
||||
|
||||
.container :
|
||||
{
|
||||
KEEP(*(.boot_hdr.container))
|
||||
} > m_container_data
|
||||
|
||||
/* The startup code goes first */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__Vectors = .;
|
||||
KEEP(*(.isr_vector)) /* Vector table and startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
.interrupts_ram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. += __RAM_VECTOR_TABLE_SIZE_BYTES;
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts_ram
|
||||
|
||||
/* The program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
core1_image_start = .;
|
||||
KEEP (*(.core1_code))
|
||||
*(.core1_code*)
|
||||
core1_image_end = .;
|
||||
. = ALIGN(4) ;
|
||||
} > m_text
|
||||
|
||||
ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit")
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
|
||||
__data_flash_start = .; /* Symbol is used by startup for data initialization */
|
||||
.data : AT(__data_flash_start)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(DataQuickAccess) /* quick access data section */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */
|
||||
.ram_function : AT(__ram_function_flash_start)
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__ram_function_start__ = .;
|
||||
*(CodeQuickAccess)
|
||||
. = ALIGN(128);
|
||||
__ram_function_end__ = .;
|
||||
} > m_qacode
|
||||
|
||||
__noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
|
||||
.ncache.init : AT(__noncache_data_flash_start)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noncache_data_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncache_data_end__ = .; /* create a global symbol at ncache data end */
|
||||
} > m_ncache
|
||||
|
||||
.ncache :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noncache_bss_start__ = .; /* define a global symbol at ncache bss start */
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncache_bss_end__ = .; /* define a global symbol at ncache bss end */
|
||||
} > m_ncache
|
||||
|
||||
__qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__);
|
||||
.qadata : AT(__qadata_flash_start)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__qadata_start__ = .;
|
||||
. = ALIGN(4);
|
||||
__qadata_end__ = .;
|
||||
} > m_qadata
|
||||
|
||||
text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(text_data_end < text_end, "region m_text overflowed with text and data")
|
||||
|
||||
__CONTAINER_IMG_SIZE = text_data_end - m_interrupts_start;
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > m_data
|
||||
|
||||
.rpmsg :
|
||||
{
|
||||
*(.noinit.$rpmsg_sh_mem)
|
||||
} > m_rpmsg
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
end = .;
|
||||
. += m_heap_size;
|
||||
__HeapLimit = .; /* Add for _sbrk */
|
||||
} > m_heap
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackStart = .;
|
||||
. += m_stack_size;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - m_stack_size;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
PROVIDE (__stack_size = m_stack_size);
|
||||
ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,232 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1189CVM8B_cm33
|
||||
** MIMXRT1189CVM8C_cm33
|
||||
** MIMXRT1189XVM8B_cm33
|
||||
** MIMXRT1189XVM8C_cm33
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1180RM, Rev 5, 01/2024
|
||||
** Version: rev. 2.0, 2024-01-18
|
||||
** Build: b250310
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2025 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/* Board memory map */
|
||||
|
||||
#define m_code_tcm_start 0x0FFE0000
|
||||
#define m_code_tcm_size 0x00020000
|
||||
|
||||
#define m_system_tcm_start 0x20000000
|
||||
#define m_system_tcm_size 0x00020000
|
||||
|
||||
#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */
|
||||
#define m_ocram1_size 0x0007C000
|
||||
|
||||
#define m_ocram2_start 0x20500000
|
||||
#define m_ocram2_size 0x00040000
|
||||
|
||||
#if defined(__dual_image__)
|
||||
/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */
|
||||
#define m_sdram_start 0x81E00000
|
||||
#define m_sdram_size 0x00200000
|
||||
#define m_hyperram_start 0x04600000
|
||||
#define m_hyperram_size 0x00200000
|
||||
#else
|
||||
#define m_sdram_start 0x80000000
|
||||
#define m_sdram_size 0x02000000
|
||||
#define m_hyperram_start 0x04000000
|
||||
#define m_hyperram_size 0x00800000
|
||||
#endif
|
||||
|
||||
#define m_flash_start 0x28000000
|
||||
#define m_flash_size 0x00800000
|
||||
#define m_core1_image_maximum_size 0x00040000
|
||||
|
||||
/* General definition */
|
||||
#define app_image_offset 0x0000B000
|
||||
|
||||
#define m_fcb_offset 0x400
|
||||
#define m_fcb_size 0x200
|
||||
#define m_xmcd_offset 0x800
|
||||
#define m_xmcd_size 0x400
|
||||
#define m_container_offset 0x1000
|
||||
#define m_container_size 0x2000
|
||||
|
||||
#define vector_table_size 0x400
|
||||
#define m_ram_vector_table_start m_code_tcm_start
|
||||
|
||||
#if defined(__stack_size__)
|
||||
#define stack_size __stack_size__
|
||||
#else
|
||||
#define stack_size 0x01000
|
||||
#endif
|
||||
|
||||
#if defined(__heap_size__)
|
||||
#define heap_size __heap_size__
|
||||
#else
|
||||
#define heap_size 0x04000
|
||||
#endif
|
||||
|
||||
/* Target specific definition, code & data allocation */
|
||||
#if defined(__ram_vector_table__)
|
||||
#define m_ram_vector_table_size vector_table_size
|
||||
#else
|
||||
#define m_ram_vector_table_size 0
|
||||
#endif
|
||||
|
||||
#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size
|
||||
#define m_qadata_start m_system_tcm_start
|
||||
#define m_qacode_size m_code_tcm_size - (m_qacode_start - m_code_tcm_start)
|
||||
#define m_qadata_size 0
|
||||
|
||||
#define m_text_size m_flash_size - app_image_offset
|
||||
#define m_data_size m_system_tcm_size
|
||||
#if defined(__multicore__)
|
||||
#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */
|
||||
#define m_ocram1_size_for_cm7 0x40000
|
||||
#else
|
||||
#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */
|
||||
#define m_ocram1_size_for_cm7 0
|
||||
#endif
|
||||
#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */
|
||||
|
||||
#define m_fcb_start m_flash_start + m_fcb_offset
|
||||
#define m_xmcd_start m_flash_start + m_xmcd_offset
|
||||
#define m_container_start m_flash_start + m_container_offset
|
||||
#define m_text_start m_flash_start + app_image_offset
|
||||
#define m_interrupts_start m_text_start
|
||||
#define m_data_start m_system_tcm_start
|
||||
#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size
|
||||
#define m_heap_start m_ocram1_start
|
||||
|
||||
#if defined(__use_shmem__)
|
||||
#define m_shmem_start m_ocram2_start
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
; load region
|
||||
LR_m_header m_fcb_start (m_container_start) + (m_container_size) - (m_fcb_start)
|
||||
{
|
||||
; Flash Configuration Block
|
||||
FCB m_fcb_start FIXED m_fcb_size
|
||||
{
|
||||
.ANY (.boot_hdr.conf)
|
||||
}
|
||||
|
||||
; XMCD Block
|
||||
XMCD m_xmcd_start FIXED m_xmcd_size
|
||||
{
|
||||
.ANY (.boot_hdr.xmcd_data)
|
||||
}
|
||||
|
||||
; Container
|
||||
Container m_container_start FIXED m_container_size
|
||||
{
|
||||
.ANY (.boot_hdr.container)
|
||||
}
|
||||
|
||||
; Empty region added for container configuration
|
||||
ER_m_container_image_offset (m_text_start) - (m_container_start) EMPTY 0
|
||||
{
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
; load region
|
||||
LR_m_text m_text_start m_text_size
|
||||
{
|
||||
; load address = execution address
|
||||
VECTOR_ROM m_interrupts_start FIXED vector_table_size
|
||||
{
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
|
||||
VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size
|
||||
{
|
||||
}
|
||||
|
||||
; load address = execution address
|
||||
ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size
|
||||
{
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size
|
||||
{
|
||||
.ANY (.core1_code)
|
||||
}
|
||||
|
||||
ER_m_QuickAccessCode m_qacode_start m_qacode_size
|
||||
{
|
||||
.ANY (CodeQuickAccess)
|
||||
}
|
||||
|
||||
ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size
|
||||
{
|
||||
}
|
||||
|
||||
RW_m_data m_data_start m_data_size-stack_size
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (DataQuickAccess)
|
||||
}
|
||||
|
||||
; ncache data
|
||||
RW_m_ncache m_ncache_start m_ncache_size
|
||||
{
|
||||
.ANY (NonCacheable.init)
|
||||
.ANY (.bss.NonCacheable)
|
||||
}
|
||||
|
||||
#if defined(__heap_noncacheable__)
|
||||
; Heap region growing up
|
||||
ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
; Empty region added for MPU configuration
|
||||
RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(__use_shmem__)
|
||||
; shared memory data
|
||||
RPMSG_SH_MEM m_shmem_start m_shmem_size
|
||||
{
|
||||
.ANY (rpmsg_sh_mem_section)
|
||||
}
|
||||
|
||||
; Empty region added for MPU configuration
|
||||
RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(__heap_noncacheable__)
|
||||
; Heap region growing up
|
||||
ARM_LIB_HEAP m_heap_start EMPTY heap_size
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
; Stack region growing down
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size
|
||||
{
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
After Width: | Height: | Size: 64 KiB |
@@ -0,0 +1,434 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 12
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 4096
|
||||
|
||||
/* kservice options */
|
||||
|
||||
#define RT_USING_TINY_FFS
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_USING_CONSOLE_OUTPUT_CTL
|
||||
#define RT_VER_NUM 0x50300
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define ARCH_USING_HW_ATOMIC_8
|
||||
#define ARCH_USING_HW_ATOMIC_16
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_FPU
|
||||
#define ARCH_ARM_CORTEX_SECURE
|
||||
#define ARCH_ARM_CORTEX_M33
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 4096
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* WCH HAL & SDK Drivers */
|
||||
|
||||
/* end of WCH HAL & SDK Drivers */
|
||||
|
||||
/* AT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of AT32 HAL & SDK Drivers */
|
||||
|
||||
/* HC32 DDL Drivers */
|
||||
|
||||
/* end of HC32 DDL Drivers */
|
||||
|
||||
/* NXP HAL & SDK Drivers */
|
||||
|
||||
#define PKG_USING_NXP_IMXRT_DRIVER
|
||||
#define PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION
|
||||
/* end of NXP HAL & SDK Drivers */
|
||||
|
||||
/* NUVOTON Drivers */
|
||||
|
||||
/* end of NUVOTON Drivers */
|
||||
|
||||
/* GD32 Drivers */
|
||||
|
||||
/* end of GD32 Drivers */
|
||||
|
||||
/* HPMicro SDK */
|
||||
|
||||
/* end of HPMicro SDK */
|
||||
|
||||
/* FT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of FT32 HAL & SDK Drivers */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
#define SOC_IMXRT1180_SERIES
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define BSP_USING_QSPIFLASH
|
||||
#define SOC_MIMXRT1189CVM8C
|
||||
#define SOC_MIMXRT1189CVM8C_CM33
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_DMA
|
||||
#define BSP_USING_LPUART
|
||||
#define BSP_USING_LPUART1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* end of Onboard Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,197 @@
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m33'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armclang'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 9.2'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
# BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
|
||||
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS'
|
||||
LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
# AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
|
||||
# AFLAGS += ' -D__STARTUP_CLEAR_BSS'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g'
|
||||
AFLAGS += ' -g'
|
||||
# CFLAGS += ' -O1'
|
||||
CFLAGS += ' -O0'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
CXXFLAGS += CFLAGS
|
||||
|
||||
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
|
||||
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
|
||||
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
' -shared -fPIC -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU + '.fp.sp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.scf"'
|
||||
|
||||
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
|
||||
|
||||
CFLAGS += ' --diag_suppress=66,1296,186,6314'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' --c99'
|
||||
|
||||
POST_ACTION = 'fromelf -z $TARGET'
|
||||
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'armclang':
|
||||
# toolchains
|
||||
CC = 'armclang'
|
||||
CXX = 'armclang'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU
|
||||
CFLAGS = ' --target=arm-arm-none-eabi'
|
||||
CFLAGS += ' -mcpu=' + CPU
|
||||
CFLAGS += ' -mfpu=fpv5-sp-d16'
|
||||
CFLAGS += ' -mfloat-abi=hard'
|
||||
CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
|
||||
CFLAGS += ' -gdwarf-3 -ffunction-sections '
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
AFLAGS += ' -x assembler-with-cpp'
|
||||
AFLAGS += ' -Wa,-mimplicit-it=thumb'
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
|
||||
LFLAGS += ' --list rt-thread.map '
|
||||
LFLAGS += r' --strict --scatter "board/linker_scripts/link" '
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
|
||||
|
||||
EXEC_PATH += '/ARM/ARMCLANG/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O1' # armclang recommend
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' -D__FPU_PRESENT'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv5_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
|
||||
AFLAGS = ''
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu VFPv5_sp'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --redirect _Printf=_PrintfTiny'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
# sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,20 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
if GetDepend('BSP_USING_QSPIFLASH'):
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
LINKFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
LINKFLAGS += ' --keep=*(.boot_hdr.container)'
|
||||
# LINKFLAGS += ' --keep=*(.boot_hdr.xmcd_data)'
|
||||
LINKFLAGS += ' --keep=*(.boot_hdr.conf)'
|
||||
LINKFLAGS += ' --entry=Reset_Handler '
|
||||
LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"'
|
||||
LINKFLAGS += ' --predefine="-DXIP_EXTERNAL_FLASH=1"'
|
||||
|
||||
group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS)
|
||||
Return('group')
|
||||
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Copyright 2018-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "evkmimxrt1180_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \
|
||||
defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
/* clang-format on */
|
||||
|
||||
#if defined(USE_HYPERRAM)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.xmcd_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.xmcd_data"
|
||||
#endif
|
||||
|
||||
const uint32_t xmcd_data[] = {
|
||||
0xC002000C, /* FlexSPI instance 2 */
|
||||
0xC1000800, /* Option words = 2 */
|
||||
0x00010000 /* PINMUX Secondary group */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(USE_SDRAM)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.xmcd_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.xmcd_data"
|
||||
#endif
|
||||
|
||||
const uint32_t xmcd_data[] = {
|
||||
0xC010000D, /* SEMC -> SDRAM */
|
||||
0xA60001A1, /* SDRAM config */
|
||||
0x00008000, /* SDRAM config */
|
||||
0X00000001 /* SDRAM config */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FlexSPI nor flash configuration block
|
||||
* Note:
|
||||
* Below setting is special for EVK board flash, to achieve maximum access performance.
|
||||
* For other boards or flash, may leave it 0 or delete fdcb_data, which means auto probe.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
#define FLASH_DUMMY_CYCLES 0x06
|
||||
|
||||
const flexspi_nor_config_t qspi_flash_nor_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.controllerMiscOption = 0x10,
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = 16u * 1024u * 1024u,
|
||||
|
||||
.configModeType[0] = kDeviceConfigCmdType_Generic,
|
||||
|
||||
.lookupTable =
|
||||
{
|
||||
// Read LUTs
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
|
||||
// Read Status LUTs
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
|
||||
// Write Enable LUTs
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
|
||||
|
||||
// Erase Sector LUTs
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
|
||||
// Erase Block LUTs
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
|
||||
// Pape Program LUTs
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
|
||||
|
||||
// Erase Chip LUTs
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = 0x1,
|
||||
.blockSize = 64u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,190 @@
|
||||
/*
|
||||
* Copyright 2018-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_DEVICE driver version 2.0.4. */
|
||||
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||
/*@}*/
|
||||
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_Reversed = 2,
|
||||
kFlexSPIReadSampleClk_FlashProvidedDqs = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_80MHz = 4,
|
||||
kFlexSpiSerialClk_100MHz = 5,
|
||||
kFlexSpiSerialClk_120MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode
|
||||
uint8_t reserved0[5]; //!< Reserved for future use
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t FlashStateCtx; //!< Flash State Context after being configured
|
||||
uint32_t reserve1[10]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
|
||||
#endif /* __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ */
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright 2021-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_boot.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \
|
||||
defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
/* clang-format on */
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.container"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.container"
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
const container container_data =
|
||||
{
|
||||
{
|
||||
CNT_VERSION,
|
||||
CNT_SIZE,
|
||||
CNT_TAG_HEADER,
|
||||
CNT_FLAGS,
|
||||
CNT_SW_VER,
|
||||
CNT_FUSE_VER,
|
||||
CNT_NUM_IMG,
|
||||
sizeof(cnt_hdr) + CNT_NUM_IMG * sizeof(image_entry),
|
||||
0
|
||||
},
|
||||
{{
|
||||
IMAGE_OFFSET,
|
||||
IMAGE_SIZE,
|
||||
IMAGE_LOAD_ADDRESS,
|
||||
0x00000000,
|
||||
IMAGE_ENTRY_ADDRESS,
|
||||
0x00000000,
|
||||
IMG_FLAGS,
|
||||
0x0,
|
||||
{0},
|
||||
{0}
|
||||
}},
|
||||
{
|
||||
SGNBK_VERSION,
|
||||
SGNBK_SIZE,
|
||||
SGNBK_TAG,
|
||||
0x0,
|
||||
0x0,
|
||||
0x0,
|
||||
0x0
|
||||
}
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright 2021-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __FLEXSPI_NOR_BOOT_H__
|
||||
#define __FLEXSPI_NOR_BOOT_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*************************************
|
||||
* Container
|
||||
*************************************/
|
||||
/* Container header */
|
||||
#define CNT_TAG_HEADER 0x87
|
||||
#define CNT_SIZE (uint16_t)(sizeof(container))
|
||||
#define CNT_VERSION 0x00
|
||||
#define CNT_NUM_IMG 1
|
||||
#define CNT_FUSE_VER 0
|
||||
#define CNT_SW_VER 0
|
||||
#define CNT_FLAGS 0x00000000 // Container not authenticated
|
||||
|
||||
#define IMG_FLAGS 0x00000213 // Non-encrypted, SHA512, CM33, Executable
|
||||
|
||||
#define SGNBK_TAG 0x90
|
||||
#define SGNBK_SIZE (uint16_t)(sizeof(sign_block))
|
||||
#define SGNBK_VERSION 0x00
|
||||
|
||||
typedef struct __attribute__((packed)) _cnt_hdr_
|
||||
{
|
||||
uint8_t version;
|
||||
uint16_t length;
|
||||
uint8_t tag;
|
||||
|
||||
uint32_t flags;
|
||||
|
||||
uint16_t sw_ver;
|
||||
uint8_t fuse_ver;
|
||||
uint8_t num_images;
|
||||
|
||||
uint16_t sign_blk_offset;
|
||||
uint16_t reserved1;
|
||||
} cnt_hdr;
|
||||
|
||||
typedef struct __attribute__((packed)) _img_entry_
|
||||
{
|
||||
uint32_t offset;
|
||||
uint32_t size;
|
||||
uint32_t load_addr;
|
||||
uint32_t reserved1;
|
||||
uint32_t entry;
|
||||
uint32_t reserved2;
|
||||
uint32_t flags;
|
||||
uint32_t metadata;
|
||||
uint8_t hash[64];
|
||||
uint8_t iv[32];
|
||||
} image_entry;
|
||||
|
||||
typedef struct __attribute__((packed)) _sign_block_
|
||||
{
|
||||
uint8_t version;
|
||||
uint16_t length;
|
||||
uint8_t tag;
|
||||
|
||||
uint16_t cert_offset;
|
||||
uint16_t srk_offset;
|
||||
uint16_t sign_offset;
|
||||
uint16_t blob_offset;
|
||||
uint32_t reserved1;
|
||||
uint8_t data[0];
|
||||
} sign_block;
|
||||
|
||||
typedef struct __attribute__((packed)) _container_
|
||||
{
|
||||
cnt_hdr hdr;
|
||||
image_entry array[CNT_NUM_IMG];
|
||||
sign_block sign_block;
|
||||
} container;
|
||||
|
||||
/* Set resume entry */
|
||||
#if defined(__MCUXPRESSO)
|
||||
extern uint32_t app_image_offset[];
|
||||
extern uint32_t _image_size[];
|
||||
extern uint32_t _image_loadaddr[];
|
||||
extern uint32_t ResetISR[];
|
||||
#define IMAGE_OFFSET ((uint32_t)app_image_offset)
|
||||
#define IMAGE_SIZE ((uint32_t)_image_size)
|
||||
#define IMAGE_LOAD_ADDRESS ((uint32_t)_image_loadaddr)
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR)
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma section = "RO"
|
||||
extern uint32_t __CONTAINER_IMG_OFFSET[];
|
||||
extern uint32_t __CONTAINER_IMG_LOAD_ADDR[];
|
||||
extern uint32_t __CONTAINER_IMG_ENTRY_ADDR[];
|
||||
#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET)
|
||||
#define IMAGE_SIZE ((uint32_t)__section_size("RO"))
|
||||
#define IMAGE_LOAD_ADDRESS ((uint32_t)__CONTAINER_IMG_LOAD_ADDR)
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__CONTAINER_IMG_ENTRY_ADDR)
|
||||
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$ER_m_container_image_offset$$ZI$$Base[];
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Load$$LR$$LR_m_text$$Length[];
|
||||
#define IMAGE_OFFSET ((uint32_t)Image$$ER_m_container_image_offset$$ZI$$Base)
|
||||
#define IMAGE_SIZE ((uint32_t)Load$$LR$$LR_m_text$$Length)
|
||||
#define IMAGE_LOAD_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base)
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base)
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __CONTAINER_IMG_OFFSET[];
|
||||
extern uint32_t __CONTAINER_IMG_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET)
|
||||
#define IMAGE_SIZE ((uint32_t)__CONTAINER_IMG_SIZE)
|
||||
#define IMAGE_LOAD_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#endif
|
||||
|
||||
#endif /* __FLEXSPI_NOR_BOOT_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,45 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
MaxNumAPs = 0
|
||||
LowPowerHandlingMode = 0
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
RMWThreshold = 0x400
|
||||
Loaders=""
|
||||
EraseType = 0x00
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="ARM7"
|
||||
[GENERAL]
|
||||
MaxNumTransfers = 0x00
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
[RAM]
|
||||
VerifyDownload = 0x00
|
||||
[DYN_MEM_MAP]
|
||||
NumUserRegion = 0x00
|
||||
@@ -0,0 +1,10 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
RTT_DIR := ../../../../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../../libraries/Kconfig"
|
||||
rsource "board/Kconfig"
|
||||
@@ -0,0 +1,14 @@
|
||||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,88 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "nxp-imxrt-sdk-latest"),
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
DefaultEnvironment(tools=[])
|
||||
if rtconfig.PLATFORM == 'armcc':
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
# overwrite cflags, because cflags has '--C99'
|
||||
CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
else:
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./..')
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
imxrt_library = 'MIMXRT1180'
|
||||
rtconfig.BSP_LIBRARY_TYPE = imxrt_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join("packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,17 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
CPPDEFINES = ['__START=entry']
|
||||
else:
|
||||
CPPDEFINES = []
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-05-06 tyustli first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_gpio.h>
|
||||
#include <fsl_rgpio.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_kprintf("MIMXRT1180_CM7 Hello_World\r\n");
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,280 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config BSP_USING_QSPIFLASH
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MIMXRT1189CVM8C
|
||||
bool
|
||||
select SOC_IMXRT1180_SERIES
|
||||
select BSP_USING_QSPIFLASH
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
config SOC_MIMXRT1189CVM8C_CM7
|
||||
bool
|
||||
default y
|
||||
depends on SOC_MIMXRT1189CVM8C
|
||||
select ARCH_ARM_CORTEX_M7
|
||||
select ARCH_ARM_CORTEX_FPU
|
||||
|
||||
config BSP_USING_LCD_MIPI
|
||||
bool
|
||||
default n
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_DMA
|
||||
bool "Enable DMA"
|
||||
default n
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
config BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
|
||||
config BSP_USING_USB
|
||||
bool "Enable USB"
|
||||
select RT_USING_USB_HOST
|
||||
default n
|
||||
|
||||
if BSP_USING_USB
|
||||
config BSP_USB0_HOST
|
||||
bool "Enable USB0"
|
||||
default n
|
||||
|
||||
config BSP_USB1_HOST
|
||||
bool "Enable USB1"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
select RT_USING_SDIO
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
if BSP_USING_SDIO
|
||||
config CODE_STORED_ON_SDCARD
|
||||
bool "Enable Code STORED On SDCARD"
|
||||
default n
|
||||
help
|
||||
"SD CARD work as boot devive"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_LPUART
|
||||
bool "Enable UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
if BSP_USING_LPUART
|
||||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default y
|
||||
|
||||
config BSP_LPUART1_RX_USING_DMA
|
||||
bool "Enable LPUART1 RX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_RX_USING_DMA
|
||||
int "Set LPUART1 RX DMA channel (0-32)"
|
||||
default 0
|
||||
|
||||
config BSP_LPUART1_TX_USING_DMA
|
||||
bool "Enable LPUART1 TX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_TX_USING_DMA
|
||||
int "Set LPUART1 TX DMA channel (0-32)"
|
||||
default 1
|
||||
|
||||
config BSP_USING_LPUART3
|
||||
bool "Enable LPUART3"
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_RX_USING_DMA
|
||||
bool "Enable LPUART3 RX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_RX_USING_DMA
|
||||
int "Set LPUART3 RX DMA channel (0-32)"
|
||||
default 0
|
||||
|
||||
config BSP_LPUART3_TX_USING_DMA
|
||||
bool "Enable LPUART3 TX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_TX_USING_DMA
|
||||
int "Set LPUART3 TX DMA channel (0-32)"
|
||||
default 1
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
select RT_USING_CAN
|
||||
default n
|
||||
if BSP_USING_CAN
|
||||
config BSP_USING_CAN3
|
||||
bool "Enable FLEXCAN3"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FLEXSPI
|
||||
bool "Enable FLEXSPI"
|
||||
default n
|
||||
if BSP_USING_FLEXSPI
|
||||
config BSP_USING_FLEXSPI1
|
||||
bool "Enable FLEXSPI1"
|
||||
default n
|
||||
config BSP_USING_FLEXSPI2
|
||||
bool "Enable FLEXSPI2"
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_ETH
|
||||
bool "Enable Ethernet"
|
||||
select RT_USING_NETDEV
|
||||
select RT_USING_LWIP
|
||||
default n
|
||||
|
||||
|
||||
if BSP_USING_ETH
|
||||
config BSP_USING_PHY
|
||||
select RT_USING_PHY
|
||||
bool "Enable ethernet phy"
|
||||
default y
|
||||
|
||||
if BSP_USING_PHY
|
||||
config PHY_USING_KSZ8081
|
||||
bool "i.MX RT1176EVK uses ksz8081 phy"
|
||||
default y
|
||||
|
||||
if PHY_USING_KSZ8081
|
||||
config PHY_KSZ8081_ADDRESS
|
||||
int "Specify address of phy device"
|
||||
default 2
|
||||
|
||||
config PHY_RESET_KSZ8081_PORT
|
||||
int "indicate port of reset"
|
||||
default 6
|
||||
|
||||
config PHY_RESET_KSZ8081_PIN
|
||||
int "indicate pin of reset"
|
||||
default 12
|
||||
|
||||
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
|
||||
bool "Enable the PHY ksz8081 RMII50M mode"
|
||||
depends on PHY_USING_KSZ8081
|
||||
default y
|
||||
endif
|
||||
endif
|
||||
|
||||
if BSP_USING_PHY
|
||||
config PHY_USING_RTL8211F
|
||||
bool "i.MX RT1176EVK uses rtl8211f phy"
|
||||
default y
|
||||
|
||||
if PHY_USING_RTL8211F
|
||||
config PHY_RTL8211F_ADDRESS
|
||||
int "Specify address of phy device"
|
||||
default 1
|
||||
|
||||
config PHY_RESET_RTL8211F_PORT
|
||||
int "indicate port of reset"
|
||||
default 5
|
||||
|
||||
config PHY_RESET_RTL8211F_PIN
|
||||
int "indicate pin of reset"
|
||||
default 14
|
||||
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FS
|
||||
bool "Enable File System"
|
||||
select RT_USING_DFS_DEVFS
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
if BSP_USING_FS
|
||||
config BSP_USING_SDCARD_FATFS
|
||||
bool "Enable SDCARD (FATFS)"
|
||||
select BSP_USING_SDIO
|
||||
select RT_USING_DFS_ELMFAT
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_VGLITE
|
||||
bool "Enable VGLite"
|
||||
select RT_USING_PIN
|
||||
select BSP_USING_LCD_MIPI
|
||||
default n
|
||||
|
||||
if BSP_USING_VGLITE
|
||||
choice
|
||||
prompt "Select display panel"
|
||||
default DISPLAY_USING_RK055AHD091
|
||||
|
||||
config DISPLAY_USING_RK055AHD091
|
||||
bool "RK055AHD091-CTG (RK055HDMIPI4M 720 * 1280)"
|
||||
|
||||
config DISPLAY_USING_RK055IQH091
|
||||
bool "RK055IQH091-CTG (540 * 960)"
|
||||
|
||||
config DISPLAY_USING_RK055MHD091
|
||||
bool "RK055MHD091A0-CTG (RK055HDMIPI4MA0 720 * 1280)"
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Select display controller"
|
||||
default BSP_USING_LCDIFV2
|
||||
|
||||
config BSP_USING_ELCDIF
|
||||
bool "ELCDIF"
|
||||
|
||||
config BSP_USING_LCDIFV2
|
||||
bool "LCDIFV2"
|
||||
endchoice
|
||||
|
||||
config VGLITE_USING_ELM
|
||||
bool "Enable Elementary"
|
||||
default y
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if __CORTEX_M == 7
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */
|
||||
#else
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */
|
||||
#endif
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */
|
||||
#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */
|
||||
#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */
|
||||
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */
|
||||
#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */
|
||||
#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
|
||||
#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v15.0
|
||||
processor: MIMXRT1189xxxxx
|
||||
package_id: MIMXRT1189CVM8C
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.15.9
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
|
||||
slew_rate: Slow}
|
||||
- {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
|
||||
slew_rate: Slow}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins, assigned for the Cortex-M33 core.
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,27 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/clock_config.c
|
||||
MCUX_Config/pin_mux.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
|
||||
CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 'ARM_MATH_CM7']
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION']
|
||||
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
# CPPDEFINES += ['SDK_DEBUGCONSOLE']
|
||||
CPPDEFINES += ['NDEBUG']
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
CPPDEFINES += ['NDEBUG']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,297 @@
|
||||
/*
|
||||
* Copyright 2021-2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "pin_mux.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_rgpio.h"
|
||||
#include "fsl_cache.h"
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$RW_m_ncache$$Base[];
|
||||
/* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */
|
||||
extern uint32_t Image$$RW_m_ncache_aux$$Base[];
|
||||
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
|
||||
uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart;
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __base_NCACHE_REGION;
|
||||
extern uint32_t __top_NCACHE_REGION;
|
||||
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
|
||||
uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
|
||||
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||
extern uint32_t __NCACHE_REGION_START[];
|
||||
extern uint32_t __NCACHE_REGION_SIZE[];
|
||||
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
|
||||
uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
|
||||
#endif
|
||||
#if defined(__USE_SHMEM)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
|
||||
/* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
|
||||
extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[];
|
||||
uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
|
||||
uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart;
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __base_SHMEM_REGION;
|
||||
extern uint32_t __top_SHMEM_REGION;
|
||||
uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION);
|
||||
uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart;
|
||||
#elif defined(__ICCARM__) || defined(__GNUC__)
|
||||
extern uint32_t __RPMSG_SH_MEM_START[];
|
||||
extern uint32_t __RPMSG_SH_MEM_SIZE[];
|
||||
uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
|
||||
uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
|
||||
#endif
|
||||
#endif
|
||||
volatile uint32_t i;
|
||||
|
||||
/* Disable I cache and D cache */
|
||||
L1CACHE_DisableICache();
|
||||
L1CACHE_DisableDCache();
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
*
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outer cache
|
||||
* policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
*
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*
|
||||
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||||
* Refer to Arm errata 1013783-B for more details.
|
||||
*/
|
||||
|
||||
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB);
|
||||
|
||||
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U);
|
||||
#if defined(CACHE_MODE_WRITE_THROUGH)
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
|
||||
#else
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
|
||||
#endif
|
||||
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U);
|
||||
#if defined(CACHE_MODE_WRITE_THROUGH)
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
#else
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
#endif
|
||||
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
|
||||
#endif
|
||||
|
||||
#if defined(USE_HYPERRAM)
|
||||
MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U);
|
||||
#if defined(CACHE_MODE_WRITE_THROUGH)
|
||||
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||
#else
|
||||
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(USE_SDRAM)
|
||||
MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U);
|
||||
#if defined(CACHE_MODE_WRITE_THROUGH)
|
||||
/* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#else
|
||||
/* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
i = 0;
|
||||
while ((nonCacheSize >> i) > 0x1U)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||
assert(!(nonCacheStart % nonCacheSize));
|
||||
assert(nonCacheSize == (uint32_t)(1 << i));
|
||||
assert(i >= 5);
|
||||
|
||||
/* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||
}
|
||||
|
||||
#if defined(__USE_SHMEM)
|
||||
i = 0;
|
||||
while ((rpmsgShmemSize >> i) > 0x1U)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
{
|
||||
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||||
assert(!(rpmsgShmemStart % rpmsgShmemSize));
|
||||
assert(rpmsgShmemSize == (uint32_t)(1 << i));
|
||||
assert(i >= 5);
|
||||
|
||||
/* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
L1CACHE_EnableDCache();
|
||||
L1CACHE_EnableICache();
|
||||
}
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void imxrt_uart_pins_init(void)
|
||||
{
|
||||
#ifdef BSP_USING_LPUART1
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled */
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
imxrt_uart_pins_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright 2021-2025 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "pin_mux.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_rgpio.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
|
||||
extern int Image$$ARM_LIB_HEAP$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
|
||||
#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit)
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__section_begin("HEAP"))
|
||||
#define HEAP_END (__section_end("HEAP"))
|
||||
#elif defined(__GNUC__)
|
||||
extern int __HeapBase;
|
||||
extern int __HeapLimit;
|
||||
#define HEAP_BEGIN ((void *)&__HeapBase)
|
||||
#define HEAP_END ((void *)&__HeapLimit)
|
||||
#endif
|
||||
|
||||
/*! @brief The board flash size */
|
||||
#define BOARD_FLASH_SIZE (0x1000000U)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user