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format files in zynqmp-r5-axu4ev bsp

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Wang-Huachen
2021-05-14 14:42:21 +08:00
parent 97b6f10a45
commit 956664eed9
50 changed files with 5698 additions and 5698 deletions
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2
bsp/zynqmp-r5-axu4ev/applications/SConscript
View File

@@ -3,7 +3,7 @@ Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

260
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c
View File

@@ -20,7 +20,7 @@
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
* 64-bit changes.
* 64-bit changes.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
@@ -51,7 +51,7 @@
/************************** Function Prototypes ******************************/
void XEmacPs_StubHandler(void); /* Default handler routine */
void XEmacPs_StubHandler(void); /* Default handler routine */
/************************** Variable Definitions *****************************/
@@ -78,13 +78,13 @@ void XEmacPs_StubHandler(void); /* Default handler routine */
*
******************************************************************************/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
UINTPTR EffectiveAddress)
UINTPTR EffectiveAddress)
{
/* Verify arguments */
/* Verify arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
/* Set device base address and ID */
/* Set device base address and ID */
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
@@ -92,12 +92,12 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
InstancePtr->Config.RefClk = CfgPtr->RefClk;
#endif
/* Set callbacks to an initial stub routine */
/* Set callbacks to an initial stub routine */
InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
/* Reset the hardware and set default options */
/* Reset the hardware and set default options */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
XEmacPs_Reset(InstancePtr);
@@ -136,68 +136,68 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
{
u32 Reg;
/* Assert bad arguments and conditions */
/* Assert bad arguments and conditions */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
#if defined (XCLOCKING)
if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
Xil_ClockEnable(InstancePtr->Config.RefClk);
}
Xil_ClockEnable(InstancePtr->Config.RefClk);
}
#endif
/* Start DMA */
/* When starting the DMA channels, both transmit and receive sides
* need an initialized BD list.
*/
/* Start DMA */
/* When starting the DMA channels, both transmit and receive sides
* need an initialized BD list.
*/
if (InstancePtr->Version == 2) {
Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
InstancePtr->RxBdRing.BaseBdAddr);
XEMACPS_RXQBASE_OFFSET,
InstancePtr->RxBdRing.BaseBdAddr);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
InstancePtr->TxBdRing.BaseBdAddr);
}
XEMACPS_TXQBASE_OFFSET,
InstancePtr->TxBdRing.BaseBdAddr);
}
/* clear any existed int status */
/* clear any existed int status */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
XEMACPS_IXR_ALL_MASK);
XEMACPS_IXR_ALL_MASK);
/* Enable transmitter if not already enabled */
/* Enable transmitter if not already enabled */
if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
}
}
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
}
}
/* Enable receiver if not already enabled */
/* Enable receiver if not already enabled */
if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
}
}
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
}
}
/* Enable TX and RX interrupts */
XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
(u32)XEMACPS_IXR_TXCOMPL_MASK));
(u32)XEMACPS_IXR_TXCOMPL_MASK));
/* Enable TX Q1 Interrupts */
/* Enable TX Q1 Interrupts */
if (InstancePtr->Version > 2)
XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
/* Mark as started */
/* Mark as started */
InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
return;
@@ -236,19 +236,19 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Disable all interrupts */
/* Disable all interrupts */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
XEMACPS_IXR_ALL_MASK);
/* Disable the receiver & transmitter */
/* Disable the receiver & transmitter */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
XEMACPS_NWCTRL_OFFSET);
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
XEMACPS_NWCTRL_OFFSET, Reg);
/* Mark as stopped */
/* Mark as stopped */
InstancePtr->IsStarted = 0U;
#if defined (XCLOCKING)
Xil_ClockDisable(InstancePtr->Config.RefClk);
@@ -297,7 +297,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Stop the device and reset hardware */
/* Stop the device and reset hardware */
XEmacPs_Stop(InstancePtr);
InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
@@ -307,104 +307,104 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
InstancePtr->MaxMtuSize = XEMACPS_MTU;
InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
XEMACPS_TRL_SIZE;
XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
/* Setup hardware with default values */
/* Setup hardware with default values */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEMACPS_NWCTRL_STATCLR_MASK |
XEMACPS_NWCTRL_MDEN_MASK) &
(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
XEMACPS_NWCTRL_OFFSET,
(XEMACPS_NWCTRL_STATCLR_MASK |
XEMACPS_NWCTRL_MDEN_MASK) &
(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
XEMACPS_NWCFG_OFFSET);
Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
(u32)XEMACPS_NWCFG_FDEN_MASK |
(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
(u32)XEMACPS_NWCFG_FDEN_MASK |
(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET, Reg);
XEMACPS_NWCFG_OFFSET, Reg);
if (InstancePtr->Version > 2) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
XEMACPS_NWCFG_DWIDTH_64_MASK));
}
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
XEMACPS_NWCFG_DWIDTH_64_MASK));
}
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET,
(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
(u32)XEMACPS_DMACR_RXSIZE_MASK |
(u32)XEMACPS_DMACR_TXSIZE_MASK);
XEMACPS_DMACR_OFFSET,
(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
(u32)XEMACPS_DMACR_RXSIZE_MASK |
(u32)XEMACPS_DMACR_TXSIZE_MASK);
if (InstancePtr->Version > 2) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
#if defined(__aarch64__) || defined(__arch64__)
(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
#endif
(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
}
(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
}
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
if (InstancePtr->Version > 2)
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
XEMACPS_IXR_ALL_MASK);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
XEMACPS_ISR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
Reg);
Reg);
XEmacPs_ClearHash(InstancePtr);
for (i = 1U; i < 5U; i++) {
(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
}
(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
}
/* clear all counters */
/* clear all counters */
for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
i++) {
(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
i++) {
(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
}
}
/* Disable the receiver */
/* Disable the receiver */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
XEMACPS_NWCTRL_OFFSET);
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
XEMACPS_NWCTRL_OFFSET, Reg);
/* Sync default options with hardware but leave receiver and
/* Sync default options with hardware but leave receiver and
* transmitter disabled. They get enabled with XEmacPs_Start() if
* XEMACPS_TRANSMITTER_ENABLE_OPTION and
* XEMACPS_TRANSMITTER_ENABLE_OPTION and
* XEMACPS_RECEIVER_ENABLE_OPTION are set.
*/
(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
(u32)XEMACPS_RECEIVER_ENABLE_OPTION));
*/
(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
(u32)XEMACPS_RECEIVER_ENABLE_OPTION));
(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
}
@@ -436,9 +436,9 @@ void XEmacPs_StubHandler(void)
*
******************************************************************************/
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction)
u16 Direction)
{
/* Assert bad arguments and conditions */
/* Assert bad arguments and conditions */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
@@ -448,33 +448,33 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
}
if (QueueNum == 0x00U) {
if (Direction == XEMACPS_SEND) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
} else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
}
else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQ1BASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
if (Direction == XEMACPS_SEND) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
} else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
}
else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQ1BASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
#ifdef __aarch64__
if (Direction == XEMACPS_SEND) {
/* Set the MSB of TX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_TXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
} else {
/* Set the MSB of RX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_RXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
}
/* Set the MSB of TX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_TXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
} else {
/* Set the MSB of RX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_RXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
}
#endif
}
/** @} */

134
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h
View File

@@ -241,46 +241,46 @@
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
@@ -302,10 +302,10 @@
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
* 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
* hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
* hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
* 3.9 hk 01/23/19 Add RX watermark support
* 3.11 sd 02/14/20 Add clock support
*
@@ -313,8 +313,8 @@
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@@ -447,13 +447,13 @@ extern "C" {
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
@@ -464,8 +464,8 @@ extern "C" {
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
@@ -499,7 +499,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
u32 ErrorWord);
/*@}*/
@@ -507,12 +507,12 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
* describes whether Cache Coherent or not */
#if defined (XCLOCKING)
u32 RefClk; /**< Input clock */
u32 RefClk; /**< Input clock */
#endif
} XEmacPs_Config;
@@ -523,13 +523,13 @@ typedef struct {
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
@@ -599,8 +599,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@@ -620,8 +620,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@@ -641,8 +641,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@@ -662,8 +662,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@@ -740,17 +740,17 @@ typedef struct XEmacPs_Instance {
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
* @param High is the non-zero RX high watermark value. When SRAM fill level
* is above this, a pause frame will be sent.
* is above this, a pause frame will be sent.
* @param Low is the non-zero RX low watermark value. When SRAM fill level
* is below this, a zero length pause frame will be sent IF the last
* pause frame sent was non-zero.
* is below this, a zero length pause frame will be sent IF the last
* pause frame sent was non-zero.
*
* @return None
*
* @note
*
* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
* u16 Low)
* u16 Low)
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
@@ -780,12 +780,12 @@ typedef struct XEmacPs_Instance {
* Initialization functions in xemacps.c
*/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
@@ -797,7 +797,7 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
@@ -816,13 +816,13 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
u32 RegisterNum, u16 *PhyDataPtr);
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
u32 RegisterNum, u16 PhyData);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);

24
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bd.h
View File

@@ -51,8 +51,8 @@
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@@ -117,7 +117,7 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
@@ -153,10 +153,10 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
@@ -180,9 +180,9 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
@@ -239,8 +239,8 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))

508
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c
View File

File diff suppressed because it is too large Load Diff

38
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h
View File

@@ -22,14 +22,14 @@
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* changed to volatile.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@@ -41,21 +41,21 @@ extern "C" {
/** This is an internal structure used to maintain the DMA list */
typedef struct {
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
/**< BDA to load when channel is started */
volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
@@ -187,21 +187,21 @@ typedef struct {
* Scatter gather DMA related functions in xemacps_bdring.c
*/
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
u8 Direction);
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
XEmacPs_Bd * BdSetPtr);
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
XEmacPs_Bd ** BdSetPtr);
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);

828
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_control.c
View File

File diff suppressed because it is too large Load Diff

10
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c
View File

@@ -22,11 +22,11 @@
XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
{
{
XPAR_PSU_ETHERNET_3_DEVICE_ID,
XPAR_PSU_ETHERNET_3_BASEADDR,
XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
}
{
XPAR_PSU_ETHERNET_3_DEVICE_ID,
XPAR_PSU_ETHERNET_3_BASEADDR,
XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
}
};

34
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c
View File

@@ -62,35 +62,35 @@ void XEmacPs_ResetHw(u32 BaseAddr)
{
u32 RegVal;
/* Disable the interrupts */
/* Disable the interrupts */
XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
/* Stop transmission,disable loopback and Stop tx and Rx engines */
/* Stop transmission,disable loopback and Stop tx and Rx engines */
RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
(u32)XEMACPS_NWCTRL_RXEN_MASK|
(u32)XEMACPS_NWCTRL_HALTTX_MASK|
(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
/* Clear the statistic registers, flush the packets in DPRAM*/
(u32)XEMACPS_NWCTRL_RXEN_MASK|
(u32)XEMACPS_NWCTRL_HALTTX_MASK|
(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
/* Clear the statistic registers, flush the packets in DPRAM*/
RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
/* Clear the interrupt status */
/* Clear the interrupt status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
/* Clear the tx status */
/* Clear the tx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
(u32)XEMACPS_TXSR_TXCOMPL_MASK|
(u32)XEMACPS_TXSR_TXGO_MASK));
/* Clear the rx status */
(u32)XEMACPS_TXSR_TXCOMPL_MASK|
(u32)XEMACPS_TXSR_TXGO_MASK));
/* Clear the rx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
XEMACPS_RXSR_FRAMERX_MASK);
/* Clear the tx base address */
XEMACPS_RXSR_FRAMERX_MASK);
/* Clear the tx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
/* Clear the rx base address */
/* Clear the rx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
/* Update the network config register with reset value */
/* Update the network config register with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
/* Update the hash address registers with reset value */
/* Update the hash address registers with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
}

142
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h
View File

@@ -25,10 +25,10 @@
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
@@ -42,8 +42,8 @@
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
@@ -80,8 +80,8 @@ extern "C" {
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
@@ -250,47 +250,47 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
nanosecond counter */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
reg */
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
reg */
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
reg */
/* Define some bit positions for registers. */
@@ -298,7 +298,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
@@ -333,7 +333,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
@@ -382,19 +382,19 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
@@ -446,8 +446,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
/*@}*/
@@ -462,27 +462,27 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
@@ -498,22 +498,22 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/** @name RX watermark bit definitions
* @{
*/
#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
/*@}*/
/* Transmit buffer descriptor status words offset

208
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c
View File

@@ -20,16 +20,16 @@
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
* and 64-bit changes.
* and 64-bit changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
* there is no error. CR# 869403
@@ -77,7 +77,7 @@
*
*****************************************************************************/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef)
void *FuncPointer, void *CallBackRef)
{
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
@@ -86,24 +86,24 @@ LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
switch (HandlerType) {
case XEMACPS_HANDLER_DMASEND:
Status = (LONG)(XST_SUCCESS);
InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->SendRef = CallBackRef;
break;
Status = (LONG)(XST_SUCCESS);
InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->SendRef = CallBackRef;
break;
case XEMACPS_HANDLER_DMARECV:
Status = (LONG)(XST_SUCCESS);
InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->RecvRef = CallBackRef;
break;
Status = (LONG)(XST_SUCCESS);
InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->RecvRef = CallBackRef;
break;
case XEMACPS_HANDLER_ERROR:
Status = (LONG)(XST_SUCCESS);
InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
InstancePtr->ErrorRef = CallBackRef;
break;
Status = (LONG)(XST_SUCCESS);
InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
InstancePtr->ErrorRef = CallBackRef;
break;
default:
Status = (LONG)(XST_INVALID_PARAM);
break;
}
Status = (LONG)(XST_INVALID_PARAM);
break;
}
return Status;
}
@@ -130,113 +130,113 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* This ISR will try to handle as many interrupts as it can in a single
* call. However, in most of the places where the user's error handler
/* This ISR will try to handle as many interrupts as it can in a single
* call. However, in most of the places where the user's error handler
* is called, this ISR exits because it is expected that the user will
* reset the device in nearly all instances.
*/
*/
RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
XEMACPS_ISR_OFFSET);
/* Read Transmit Q1 ISR */
/* Read Transmit Q1 ISR */
if (InstancePtr->Version > 2)
RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET);
RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET);
/* Clear the interrupt status register */
/* Clear the interrupt status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
RegISR);
RegISR);
/* Receive complete interrupt */
/* Receive complete interrupt */
if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
/* Clear RX status register RX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET,
((u32)XEMACPS_RXSR_FRAMERX_MASK |
(u32)XEMACPS_RXSR_BUFFNA_MASK));
InstancePtr->RecvHandler(InstancePtr->RecvRef);
}
/* Clear RX status register RX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET,
((u32)XEMACPS_RXSR_FRAMERX_MASK |
(u32)XEMACPS_RXSR_BUFFNA_MASK));
InstancePtr->RecvHandler(InstancePtr->RecvRef);
}
/* Transmit Q1 complete interrupt */
/* Transmit Q1 complete interrupt */
if ((InstancePtr->Version > 2) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET,
XEMACPS_INTQ1SR_TXCOMPL_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET,
XEMACPS_INTQ1SR_TXCOMPL_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Transmit complete interrupt */
/* Transmit complete interrupt */
if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Receive error conditions interrupt */
/* Receive error conditions interrupt */
if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
/* Clear RX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, RegSR);
/* Clear RX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, RegSR);
/* Fix for CR # 692702. Write to bit 18 of net_ctrl
* register to flush a packet out of Rx SRAM upon
* an error for receive buffer not available. */
if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
RegCtrl =
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, RegCtrl);
}
/* Fix for CR # 692702. Write to bit 18 of net_ctrl
* register to flush a packet out of Rx SRAM upon
* an error for receive buffer not available. */
if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
RegCtrl =
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, RegCtrl);
}
if(RegSR != 0) {
InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
XEMACPS_RECV, RegSR);
}
}
if(RegSR != 0) {
InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
XEMACPS_RECV, RegSR);
}
}
/* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
* will be asserted the same time.
* Have to distinguish this bit to handle the real error condition.
*/
/* Transmit Q1 error conditions interrupt */
/* Transmit Q1 error conditions interrupt */
if ((InstancePtr->Version > 2) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear Interrupt Q1 status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegQ1ISR);
}
/* Clear Interrupt Q1 status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegQ1ISR);
}
/* Transmit error conditions interrupt */
/* Transmit error conditions interrupt */
if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
(!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, RegSR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegSR);
}
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, RegSR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegSR);
}
}
/** @} */

10
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c
View File

@@ -60,11 +60,11 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
u32 i;
for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
CfgPtr = &XEmacPs_ConfigTable[i];
break;
}
}
if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
CfgPtr = &XEmacPs_ConfigTable[i];
break;
}
}
return (XEmacPs_Config *)(CfgPtr);
}

364
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c
View File

File diff suppressed because it is too large Load Diff

106
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h
View File

@@ -15,10 +15,10 @@
* Controller.
*
* The GPIO Controller supports the following features:
* - 4 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
* - 4 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
@@ -63,12 +63,12 @@
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
@@ -96,8 +96,8 @@
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /* by using protection macros */
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@@ -123,37 +123,37 @@ extern "C" {
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/*@}*/
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#endif
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
@@ -166,10 +166,10 @@ extern "C" {
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
@@ -180,8 +180,8 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XGpioPs_Config;
/**
@@ -190,13 +190,13 @@ typedef struct {
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
u32 Platform; /**< Platform data */
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
u32 Platform; /**< Platform data */
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
} XGpioPs;
@@ -206,7 +206,7 @@ typedef struct {
/* Functions in xgpiops.c */
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
u32 EffectiveAddr);
/* Bank APIs in xgpiops.c */
u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
@@ -240,11 +240,11 @@ u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer);
XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
/* Pin APIs in xgpiops_intr.c */

8
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c
View File

@@ -22,10 +22,10 @@
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
{
{
XPAR_PSU_GPIO_0_DEVICE_ID,
XPAR_PSU_GPIO_0_BASEADDR
}
{
XPAR_PSU_GPIO_0_DEVICE_ID,
XPAR_PSU_GPIO_0_BASEADDR
}
};

2
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c
View File

@@ -56,7 +56,7 @@
*
* @return None
*
* @note None.
* @note None.
*
******************************************************************************/
void XGpioPs_ResetHw(u32 BaseAddress)

40
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h
View File

@@ -28,8 +28,8 @@
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /* by using protection macros */
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
@@ -48,17 +48,17 @@ extern "C" {
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
/* @} */
/** @name Register offsets for each Bank.
@@ -70,7 +70,7 @@ extern "C" {
/* @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
/** @name Interrupt type reset values for each bank
* @{
@@ -111,11 +111,11 @@ extern "C" {
*
* @return The 32-bit value of the register
*
* @note None.
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
@@ -128,11 +128,11 @@ extern "C" {
*
* @return None.
*
* @note None.
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/

408
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c
View File

File diff suppressed because it is too large Load Diff

36
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c
View File

@@ -55,8 +55,8 @@
* @param InstancePtr is a pointer to the XGpioPs instance.
*
* @return
* - XST_SUCCESS if the self-test passed.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the self-test passed.
* - XST_FAILURE otherwise.
*
*
******************************************************************************/
@@ -75,35 +75,35 @@ s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Disable the Interrupts for Bank 0 . */
/* Disable the Interrupts for Bank 0 . */
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
/*
* Get the Current Interrupt properties for Bank 0.
* Set them to a known value, read it back and compare.
*/
/*
* Get the Current Interrupt properties for Bank 0.
* Set them to a known value, read it back and compare.
*/
XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
&CurrentIntrPolarity, &CurrentIntrOnAny);
&CurrentIntrPolarity, &CurrentIntrOnAny);
XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
IntrTestValue, IntrTestValue);
IntrTestValue, IntrTestValue);
XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
&IntrPolarity, &IntrOnAny);
&IntrPolarity, &IntrOnAny);
if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
(IntrOnAny != IntrTestValue)) {
(IntrOnAny != IntrTestValue)) {
Status = XST_FAILURE;
}
Status = XST_FAILURE;
}
/*
* Restore the contents of all the interrupt registers modified in this
* test.
*/
/*
* Restore the contents of all the interrupt registers modified in this
* test.
*/
XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
CurrentIntrPolarity, CurrentIntrOnAny);
CurrentIntrPolarity, CurrentIntrOnAny);
XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);

16
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c
View File

@@ -13,7 +13,7 @@
* This file contains the implementation of the XGpioPs driver's static
* initialization functionality.
*
* @note None.
* @note None.
*
* <pre>
*
@@ -53,9 +53,9 @@ extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
* given device ID, or NULL if no match is found.
*
* @note None.
* @note None.
*
******************************************************************************/
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
@@ -64,11 +64,11 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XGpioPs_ConfigTable[Index];
break;
}
}
if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XGpioPs_ConfigTable[Index];
break;
}
}
return (XGpioPs_Config *)CfgPtr;
}

218
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
View File

@@ -24,14 +24,14 @@
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
* 2.3 sk 09/23/14 Send command for relative card address
* when re-initialization is done.CR# 819614.
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
* 2.4 sk 12/04/14 Added support for micro SD without
* WP/CD. CR# 810655.
* Checked for DAT Inhibit mask instead of CMD
* Inhibit mask in Cmd Transfer API.
* Added Support for SD Card v1.0
* 2.5 sg 07/09/15 Added SD 3.0 features
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
* 2.4 sk 12/04/14 Added support for micro SD without
* WP/CD. CR# 810655.
* Checked for DAT Inhibit mask instead of CMD
* Inhibit mask in Cmd Transfer API.
* Added Support for SD Card v1.0
* 2.5 sg 07/09/15 Added SD 3.0 features
* kvn 07/15/15 Modified the code according to MISRAC-2012.
* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -104,32 +104,32 @@
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param ConfigPtr is a reference to a structure containing information
* about a specific SD device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config.
* about a specific SD device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* ConfigPtr->Config.BaseAddress for this device.
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* ConfigPtr->Config.BaseAddress for this device.
*
* @return
* - XST_SUCCESS if successful.
* - XST_DEVICE_IS_STARTED if the device is already started.
* It must be stopped to re-initialize.
* - XST_SUCCESS if successful.
* - XST_DEVICE_IS_STARTED if the device is already started.
* It must be stopped to re-initialize.
*
* @note This function initializes the host controller.
* Initial clock of 400KHz is set.
* Voltage of 3.3V is selected as that is supported by host.
* Interrupts status is enabled and signal disabled by default.
* Default data direction is card to host and
* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
* @note This function initializes the host controller.
* Initial clock of 400KHz is set.
* Voltage of 3.3V is selected as that is supported by host.
* Interrupts status is enabled and signal disabled by default.
* Default data direction is card to host and
* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
*
******************************************************************************/
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr)
u32 EffectiveAddr)
{
s32 Status;
@@ -140,13 +140,13 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
InstancePtr->Config.RefClk = ConfigPtr->RefClk;
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* If this API is getting called twice, return value accordingly */
/* If this API is getting called twice, return value accordingly */
if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
Status = (s32)XST_DEVICE_IS_STARTED;
goto RETURN_PATH ;
}
Status = (s32)XST_DEVICE_IS_STARTED;
goto RETURN_PATH ;
}
/* Set some default values. */
/* Set some default values. */
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddr;
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
@@ -163,26 +163,26 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
InstancePtr->Dma64BitAddr = 0U;
InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
/* Host Controller version is read. */
/* Host Controller version is read. */
InstancePtr->HC_Version =
(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
/*
* Read capabilities register and update it in Instance pointer.
* It is sufficient to read this once on power on.
*/
/*
* Read capabilities register and update it in Instance pointer.
* It is sufficient to read this once on power on.
*/
InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_CAPS_OFFSET);
XSDPS_CAPS_OFFSET);
/* Reset the SD bus lines */
/* Reset the SD bus lines */
Status = XSdPs_ResetConfig(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
}
Status = XST_FAILURE;
goto RETURN_PATH ;
}
/* Configure the SD Host Controller */
/* Configure the SD Host Controller */
XSdPs_HostConfig(InstancePtr);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
@@ -205,12 +205,12 @@ RETURN_PATH:
* @param InstancePtr is a pointer to the instance to be worked on.
*
* @return
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because
* a) SD is already initialized
* b) There is no card inserted
* c) One of the steps (commands) in the
* initialization cycle failed
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because
* a) SD is already initialized
* b) There is no card inserted
* c) One of the steps (commands) in the
* initialization cycle failed
*
*
******************************************************************************/
@@ -221,7 +221,7 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Default settings */
/* Default settings */
InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
InstancePtr->CardType = XSDPS_CARD_SD;
InstancePtr->Switch1v8 = 0U;
@@ -231,34 +231,34 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* Change the clock frequency to 400 KHz */
/* Change the clock frequency to 400 KHz */
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
}
Status = XST_FAILURE;
goto RETURN_PATH ;
}
/* Identify the Card whether it is SD, MMC or eMMC */
/* Identify the Card whether it is SD, MMC or eMMC */
Status = XSdPs_IdentifyCard(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XST_FAILURE;
goto RETURN_PATH;
}
/* Initialize the identified card */
/* Initialize the identified card */
if (InstancePtr->CardType == XSDPS_CARD_SD) {
Status = XSdPs_SdCardInitialize(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
} else {
Status = XSdPs_MmcCardInitialize(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
}
Status = XSdPs_SdCardInitialize(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
} else {
Status = XSdPs_MmcCardInitialize(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
}
RETURN_PATH:
#if defined (XCLOCKING)
@@ -274,14 +274,14 @@ RETURN_PATH:
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* argument along with the command.
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or command or data inhibit is set
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or command or data inhibit is set
*
******************************************************************************/
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
@@ -295,19 +295,19 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* Setup the Read Transfer */
/* Setup the Read Transfer */
Status = XSdPs_SetupTransfer(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XST_FAILURE;
goto RETURN_PATH;
}
/* Read from the card */
/* Read from the card */
Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XST_FAILURE;
goto RETURN_PATH;
}
RETURN_PATH:
#if defined (XCLOCKING)
@@ -323,14 +323,14 @@ RETURN_PATH:
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* argument along with the command.
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or command or data inhibit is set
* - XST_SUCCESS if initialization was successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or command or data inhibit is set
*
******************************************************************************/
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
@@ -344,19 +344,19 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* Setup the Write Transfer */
/* Setup the Write Transfer */
Status = XSdPs_SetupTransfer(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XST_FAILURE;
goto RETURN_PATH;
}
/* Write to the card */
/* Write to the card */
Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XST_FAILURE;
goto RETURN_PATH;
}
RETURN_PATH:
#if defined (XCLOCKING)
@@ -376,7 +376,7 @@ RETURN_PATH:
*
* @return None
*
* @note None.
* @note None.
*
******************************************************************************/
s32 XSdPs_Idle(XSdPs *InstancePtr)
@@ -390,24 +390,24 @@ s32 XSdPs_Idle(XSdPs *InstancePtr)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
/* Check if the bus is idle */
/* Check if the bus is idle */
Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
| XSDPS_PSR_INHIBIT_DAT_MASK
| XSDPS_PSR_DAT_ACTIVE_MASK);
| XSDPS_PSR_INHIBIT_DAT_MASK
| XSDPS_PSR_DAT_ACTIVE_MASK);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
}
Status = XST_FAILURE;
goto RETURN_PATH ;
}
/* Disable the Bus Power */
/* Disable the Bus Power */
XSdPs_DisableBusPower(InstancePtr);
/* Reset Command and Data Lines */
/* Reset Command and Data Lines */
Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
}
Status = XST_FAILURE;
goto RETURN_PATH ;
}
Status = XST_SUCCESS;

124
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
View File

@@ -83,14 +83,14 @@
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
* 2.3 sk 09/23/14 Send command for relative card address
* when re-initialization is done.CR# 819614.
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
* 2.4 sk 12/04/14 Added support for micro SD without
* WP/CD. CR# 810655.
* Checked for DAT Inhibit mask instead of CMD
* Inhibit mask in Cmd Transfer API.
* Added Support for SD Card v1.0
* 2.5 sg 07/09/15 Added SD 3.0 features
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
* 2.4 sk 12/04/14 Added support for micro SD without
* WP/CD. CR# 810655.
* Checked for DAT Inhibit mask instead of CMD
* Inhibit mask in Cmd Transfer API.
* Added Support for SD Card v1.0
* 2.5 sg 07/09/15 Added SD 3.0 features
* kvn 07/15/15 Modified the code according to MISRAC-2012.
* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
@@ -155,9 +155,9 @@ extern "C" {
/************************** Constant Definitions *****************************/
#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
#define XSDPS_RESPOCR_READY 0x80000000U
#define XSDPS_ACMD41_HCS 0x40000000U
@@ -171,21 +171,21 @@ extern "C" {
#define UHS_SDR104_SUPPORT 0x8U
#define UHS_DDR50_SUPPORT 0x10U
#define WIDTH_4_BIT_SUPPORT 0x4U
#define SD_CLK_25_MHZ 25000000U
#define SD_CLK_19_MHZ 19000000U
#define SD_CLK_26_MHZ 26000000U
#define SD_CLK_25_MHZ 25000000U
#define SD_CLK_19_MHZ 19000000U
#define SD_CLK_26_MHZ 26000000U
#define EXT_CSD_DEVICE_TYPE_BYTE 196U
#define EXT_CSD_SEC_COUNT_BYTE1 212U
#define EXT_CSD_SEC_COUNT_BYTE2 213U
#define EXT_CSD_SEC_COUNT_BYTE3 214U
#define EXT_CSD_SEC_COUNT_BYTE4 215U
#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
#define EXT_CSD_SEC_COUNT_BYTE1 212U
#define EXT_CSD_SEC_COUNT_BYTE2 213U
#define EXT_CSD_SEC_COUNT_BYTE3 214U
#define EXT_CSD_SEC_COUNT_BYTE4 215U
#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
#define CSD_SPEC_VER_3 0x3U
#define SCR_SPEC_VER_3 0x80U
#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
#define CSD_SPEC_VER_3 0x3U
#define SCR_SPEC_VER_3 0x80U
#define ADDRESS_BEYOND_32BIT 0x100000000U
/**************************** Type Definitions *******************************/
@@ -196,25 +196,25 @@ typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u32 CardDetect; /**< Card Detect */
u32 WriteProtect; /**< Write Protect */
u32 BusWidth; /**< Bus Width */
u32 BankNumber; /**< MIO Bank selection for SD */
u32 HasEMIO; /**< If SD is connected to EMIO */
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u32 CardDetect; /**< Card Detect */
u32 WriteProtect; /**< Write Protect */
u32 BusWidth; /**< Bus Width */
u32 BankNumber; /**< MIO Bank selection for SD */
u32 HasEMIO; /**< If SD is connected to EMIO */
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
#if defined (XCLOCKING)
u32 RefClk; /**< Input clocks */
u32 RefClk; /**< Input clocks */
#endif
} XSdPs_Config;
/* ADMA2 32-Bit descriptor table */
typedef struct {
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
u32 Address; /**< Address of current dma transfer */
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
u32 Address; /**< Address of current dma transfer */
#ifdef __ICCARM__
#pragma data_alignment = 32
} XSdPs_Adma2Descriptor32;
@@ -224,9 +224,9 @@ typedef struct {
/* ADMA2 64-Bit descriptor table */
typedef struct {
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
u64 Address; /**< Address of current dma transfer */
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
u64 Address; /**< Address of current dma transfer */
#ifdef __ICCARM__
#pragma data_alignment = 32
} XSdPs_Adma2Descriptor64;
@@ -240,28 +240,28 @@ typedef struct {
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XSdPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Host_Caps; /**< Capabilities of host controller */
u32 Host_CapsExt; /**< Extended Capabilities */
u32 HCS; /**< High capacity support in card */
u8 CardType; /**< Type of card - SD/MMC/eMMC */
u8 Card_Version; /**< Card version */
u8 HC_Version; /**< Host controller version */
u8 BusWidth; /**< Current operating bus width */
u32 BusSpeed; /**< Current operating bus speed */
u8 Switch1v8; /**< 1.8V Switch support */
u32 CardID[4]; /**< Card ID Register */
u32 RelCardAddr; /**< Relative Card Address */
u32 CardSpecData[4]; /**< Card Specific Data Register */
u32 SectorCount; /**< Sector Count */
u32 SdCardConfig; /**< Sd Card Configuration Register */
u32 Mode; /**< Bus Speed Mode */
u32 OTapDelay; /**< Output Tap Delay */
u32 ITapDelay; /**< Input Tap Delay */
u64 Dma64BitAddr; /**< 64 Bit DMA Address */
u16 TransferMode; /**< Transfer Mode */
u32 SlcrBaseAddr; /**< SLCR base address*/
XSdPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Host_Caps; /**< Capabilities of host controller */
u32 Host_CapsExt; /**< Extended Capabilities */
u32 HCS; /**< High capacity support in card */
u8 CardType; /**< Type of card - SD/MMC/eMMC */
u8 Card_Version; /**< Card version */
u8 HC_Version; /**< Host controller version */
u8 BusWidth; /**< Current operating bus width */
u32 BusSpeed; /**< Current operating bus speed */
u8 Switch1v8; /**< 1.8V Switch support */
u32 CardID[4]; /**< Card ID Register */
u32 RelCardAddr; /**< Relative Card Address */
u32 CardSpecData[4]; /**< Card Specific Data Register */
u32 SectorCount; /**< Sector Count */
u32 SdCardConfig; /**< Sd Card Configuration Register */
u32 Mode; /**< Bus Speed Mode */
u32 OTapDelay; /**< Output Tap Delay */
u32 ITapDelay; /**< Input Tap Delay */
u64 Dma64BitAddr; /**< 64 Bit DMA Address */
u16 TransferMode; /**< Transfer Mode */
u32 SlcrBaseAddr; /**< SLCR base address*/
} XSdPs;
/***************** Macros (Inline Functions) Definitions *********************/
@@ -269,7 +269,7 @@ typedef struct {
/************************** Function Prototypes ******************************/
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr);
u32 EffectiveAddr);
s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);

1102
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
View File

File diff suppressed because it is too large Load Diff

44
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c
View File

@@ -22,28 +22,28 @@
XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
{
{
XPAR_PSU_SD_0_DEVICE_ID,
XPAR_PSU_SD_0_BASEADDR,
XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
XPAR_PSU_SD_0_HAS_CD,
XPAR_PSU_SD_0_HAS_WP,
XPAR_PSU_SD_0_BUS_WIDTH,
XPAR_PSU_SD_0_MIO_BANK,
XPAR_PSU_SD_0_HAS_EMIO,
XPAR_PSU_SD_0_IS_CACHE_COHERENT
},
{
XPAR_PSU_SD_1_DEVICE_ID,
XPAR_PSU_SD_1_BASEADDR,
XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
XPAR_PSU_SD_1_HAS_CD,
XPAR_PSU_SD_1_HAS_WP,
XPAR_PSU_SD_1_BUS_WIDTH,
XPAR_PSU_SD_1_MIO_BANK,
XPAR_PSU_SD_1_HAS_EMIO,
XPAR_PSU_SD_1_IS_CACHE_COHERENT
}
{
XPAR_PSU_SD_0_DEVICE_ID,
XPAR_PSU_SD_0_BASEADDR,
XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
XPAR_PSU_SD_0_HAS_CD,
XPAR_PSU_SD_0_HAS_WP,
XPAR_PSU_SD_0_BUS_WIDTH,
XPAR_PSU_SD_0_MIO_BANK,
XPAR_PSU_SD_0_HAS_EMIO,
XPAR_PSU_SD_0_IS_CACHE_COHERENT
},
{
XPAR_PSU_SD_1_DEVICE_ID,
XPAR_PSU_SD_1_BASEADDR,
XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
XPAR_PSU_SD_1_HAS_CD,
XPAR_PSU_SD_1_HAS_WP,
XPAR_PSU_SD_1_BUS_WIDTH,
XPAR_PSU_SD_1_MIO_BANK,
XPAR_PSU_SD_1_HAS_EMIO,
XPAR_PSU_SD_1_IS_CACHE_COHERENT
}
};

1588
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
View File

File diff suppressed because it is too large Load Diff

1098
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
View File

File diff suppressed because it is too large Load Diff

412
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c
View File

File diff suppressed because it is too large Load Diff

14
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c
View File

@@ -49,14 +49,14 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to look up the
* configuration for.
* configuration for.
*
* @return
*
* A pointer to the configuration found or NULL if the specified device ID was
* not found. See xsdps.h for the definition of XSdPs_Config.
*
* @note None.
* @note None.
*
******************************************************************************/
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
@@ -65,11 +65,11 @@ XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
u32 Index;
for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XSdPs_ConfigTable[Index];
break;
}
}
if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XSdPs_ConfigTable[Index];
break;
}
}
return (XSdPs_Config *)CfgPtr;
}
/** @} */

6
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h
View File

@@ -73,9 +73,9 @@ enum ethernet_link_status {
};
void eth_link_detect(struct netif *netif);
void lwip_raw_init();
int xemacif_input(struct netif *netif);
void xemacif_input_thread(struct netif *netif);
void lwip_raw_init();
int xemacif_input(struct netif *netif);
void xemacif_input_thread(struct netif *netif);
struct netif * xemac_add(struct netif *netif,
ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
unsigned char *mac_ethernet_address,

10
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h
View File

@@ -45,7 +45,7 @@ extern "C" {
#include "xstatus.h"
#include "sleep.h"
#include "xparameters.h"
#include "xparameters_ps.h" /* defines XPAR values */
#include "xparameters_ps.h" /* defines XPAR values */
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
@@ -55,7 +55,7 @@ extern "C" {
#include "xil_cache.h"
#include "xil_printf.h"
// #include "xscugic.h"
#include "xemacps.h" /* defines XEmacPs API */
#include "xemacps.h" /* defines XEmacPs API */
#include "netif/xpqueue.h"
#include "xlwipconfig.h"
@@ -88,7 +88,7 @@ extern "C" {
#define VERSAL_CRL_GEM0_REF_CTRL 0xFF5E0118
#define VERSAL_CRL_GEM1_REF_CTRL 0xFF5E011C
#define VERSAL_CRL_GEM_DIV_MASK 0x0003FF00
#define VERSAL_CRL_GEM_DIV_MASK 0x0003FF00
#define VERSAL_CRL_APB_GEM_DIV_SHIFT 8
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
@@ -116,11 +116,11 @@ void xemacps_error_handler(XEmacPs * Temac);
typedef struct {
XEmacPs emacps;
/* queue to store overflow packets */
/* queue to store overflow packets */
pq_queue_t *recv_q;
pq_queue_t *send_q;
/* pointers to memory holding buffer descriptors (used only with SDMA) */
/* pointers to memory holding buffer descriptors (used only with SDMA) */
void *rx_bdspace;
void *tx_bdspace;

6
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h
View File

@@ -43,9 +43,9 @@ typedef struct {
} pq_queue_t;
pq_queue_t* pq_create_queue();
int pq_enqueue(pq_queue_t *q, void *p);
void* pq_dequeue(pq_queue_t *q);
int pq_qlength(pq_queue_t *q);
int pq_enqueue(pq_queue_t *q, void *p);
void* pq_dequeue(pq_queue_t *q);
int pq_qlength(pq_queue_t *q);
#ifdef __cplusplus
}

2
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h
View File

@@ -41,7 +41,7 @@ struct xtopology_t {
unsigned emac_baseaddr;
enum xemac_types emac_type;
unsigned intc_baseaddr;
unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
unsigned scugic_baseaddr; /* valid only for Zynq */
unsigned scugic_emac_intr; /* valid only for GEM */
};

266
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c
View File

@@ -83,14 +83,14 @@ u32_t phyaddrforemac;
void
lwip_raw_init()
{
ip_init(); /* Doesn't do much, it should be called to handle future changes. */
ip_init(); /* Doesn't do much, it should be called to handle future changes. */
#if LWIP_UDP
udp_init(); /* Clears the UDP PCB list. */
udp_init(); /* Clears the UDP PCB list. */
#endif
#if LWIP_TCP
tcp_init(); /* Clears the TCP PCB list and clears some internal TCP timers. */
/* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
/* predefined regular intervals after this initialization. */
tcp_init(); /* Clears the TCP PCB list and clears some internal TCP timers. */
/* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
/* predefined regular intervals after this initialization. */
#endif
}
@@ -100,9 +100,9 @@ find_mac_type(unsigned base)
int i;
for (i = 0; i < xtopology_n_emacs; i++) {
if (xtopology[i].emac_baseaddr == base)
return xtopology[i].emac_type;
}
if (xtopology[i].emac_baseaddr == base)
return xtopology[i].emac_type;
}
return xemac_type_unknown;
}
@@ -113,9 +113,9 @@ xtopology_find_index(unsigned base)
int i;
for (i = 0; i < xtopology_n_emacs; i++) {
if (xtopology[i].emac_baseaddr == base)
return i;
}
if (xtopology[i].emac_baseaddr == base)
return i;
}
return -1;
}
@@ -135,66 +135,66 @@ xemac_add(struct netif *netif,
int i;
#ifdef OS_IS_FREERTOS
/* Start thread to detect link periodically for Hot Plug autodetect */
/* Start thread to detect link periodically for Hot Plug autodetect */
sys_thread_new("link_detect_thread", link_detect_thread, netif,
THREAD_STACKSIZE, tskIDLE_PRIORITY);
THREAD_STACKSIZE, tskIDLE_PRIORITY);
#endif
/* set mac address */
/* set mac address */
netif->hwaddr_len = 6;
for (i = 0; i < 6; i++)
netif->hwaddr[i] = mac_ethernet_address[i];
netif->hwaddr[i] = mac_ethernet_address[i];
/* initialize based on MAC type */
switch (find_mac_type(mac_baseaddr)) {
case xemac_type_xps_emaclite:
/* initialize based on MAC type */
switch (find_mac_type(mac_baseaddr)) {
case xemac_type_xps_emaclite:
#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xemacliteif_init,
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xemacliteif_init,
#if NO_SYS
ethernet_input
ethernet_input
#else
tcpip_input
tcpip_input
#endif
);
);
#else
return NULL;
return NULL;
#endif
case xemac_type_axi_ethernet:
case xemac_type_axi_ethernet:
#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xaxiemacif_init,
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xaxiemacif_init,
#if NO_SYS
ethernet_input
ethernet_input
#else
tcpip_input
tcpip_input
#endif
);
);
#else
return NULL;
return NULL;
#endif
#if defined (__arm__) || defined (__aarch64__)
case xemac_type_emacps:
case xemac_type_emacps:
#ifdef XLWIP_CONFIG_INCLUDE_GEM
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xemacpsif_init,
return netif_add(netif, ipaddr, netmask, gw,
(void*)(UINTPTR)mac_baseaddr,
xemacpsif_init,
#if NO_SYS
ethernet_input
ethernet_input
#else
tcpip_input
tcpip_input
#endif
);
);
#endif
#endif
default:
xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
mac_baseaddr);
return NULL;
}
default:
xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
mac_baseaddr);
return NULL;
}
}
#if 0
@@ -208,15 +208,15 @@ xemacif_input_thread(struct netif *netif)
{
struct xemac_s *emac = (struct xemac_s *)netif->state;
while (1) {
/* sleep until there are packets to process
* This semaphore is set by the packet receive interrupt
* routine.
*/
sys_sem_wait(&emac->sem_rx_data_available);
/* sleep until there are packets to process
* This semaphore is set by the packet receive interrupt
* routine.
*/
sys_sem_wait(&emac->sem_rx_data_available);
/* move all received packets to lwIP */
xemacif_input(netif);
}
/* move all received packets to lwIP */
xemacif_input(netif);
}
}
#endif
@@ -228,40 +228,40 @@ xemacif_input(struct netif *netif)
int n_packets = 0;
switch (emac->type) {
case xemac_type_xps_emaclite:
case xemac_type_xps_emaclite:
#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
n_packets = xemacliteif_input(netif);
break;
n_packets = xemacliteif_input(netif);
break;
#else
// print("incorrect configuration: xps_ethernetlite drivers not present?");
while(1);
return 0;
// print("incorrect configuration: xps_ethernetlite drivers not present?");
while(1);
return 0;
#endif
case xemac_type_axi_ethernet:
case xemac_type_axi_ethernet:
#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
n_packets = xaxiemacif_input(netif);
break;
n_packets = xaxiemacif_input(netif);
break;
#else
// print("incorrect configuration: axi_ethernet drivers not present?");
while(1);
return 0;
// print("incorrect configuration: axi_ethernet drivers not present?");
while(1);
return 0;
#endif
#if defined (__arm__) || defined (__aarch64__)
case xemac_type_emacps:
case xemac_type_emacps:
#ifdef XLWIP_CONFIG_INCLUDE_GEM
n_packets = xemacpsif_input(netif);
break;
n_packets = xemacpsif_input(netif);
break;
#else
xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
while(1);
return 0;
xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
while(1);
return 0;
#endif
#endif
default:
// print("incorrect configuration: unknown temac type");
while(1);
return 0;
}
default:
// print("incorrect configuration: unknown temac type");
while(1);
return 0;
}
return n_packets;
}
@@ -271,14 +271,14 @@ u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_LINK_STATUS)
return 1;
return 1;
return 0;
}
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
@@ -286,14 +286,14 @@ static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_LINK_STATUS)
return 1;
return 1;
return 0;
}
#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
@@ -301,14 +301,14 @@ static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_LINK_STATUS)
return 1;
return 1;
return 0;
}
#endif
@@ -318,14 +318,14 @@ u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
return 1;
return 1;
return 0;
}
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
@@ -333,14 +333,14 @@ static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
return 1;
return 1;
return 0;
}
#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
@@ -348,14 +348,14 @@ static u32_t phy_autoneg_status(XEmacLite *xemacp, u32_t phy_addr)
{
u16_t status;
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
/* Read Phy Status register twice to get the confirmation of the current
* link status.
*/
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
return 1;
return 1;
return 0;
}
#endif
@@ -377,43 +377,43 @@ void eth_link_detect(struct netif *netif)
#endif
if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
(eth_link_status == ETH_LINK_UNDEFINED))
return;
(eth_link_status == ETH_LINK_UNDEFINED))
return;
phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
eth_link_status = ETH_LINK_DOWN;
eth_link_status = ETH_LINK_DOWN;
switch (eth_link_status) {
case ETH_LINK_UNDEFINED:
case ETH_LINK_UP:
return;
case ETH_LINK_DOWN:
netif_set_link_down(netif);
eth_link_status = ETH_LINK_NEGOTIATING;
xil_printf("Ethernet Link down\r\n");
break;
case ETH_LINK_NEGOTIATING:
if (phy_link_status &&
phy_autoneg_status(xemacp, phyaddrforemac)) {
case ETH_LINK_UNDEFINED:
case ETH_LINK_UP:
return;
case ETH_LINK_DOWN:
netif_set_link_down(netif);
eth_link_status = ETH_LINK_NEGOTIATING;
xil_printf("Ethernet Link down\r\n");
break;
case ETH_LINK_NEGOTIATING:
if (phy_link_status &&
phy_autoneg_status(xemacp, phyaddrforemac)) {
/* Initiate Phy setup to get link speed */
/* Initiate Phy setup to get link speed */
#if defined(XLWIP_CONFIG_INCLUDE_GEM)
link_speed = phy_setup_emacps(xemacp,
phyaddrforemac);
XEmacPs_SetOperatingSpeed(xemacp, link_speed);
link_speed = phy_setup_emacps(xemacp,
phyaddrforemac);
XEmacPs_SetOperatingSpeed(xemacp, link_speed);
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
link_speed = phy_setup_axiemac(xemacp);
XAxiEthernet_SetOperatingSpeed(xemacp,
link_speed);
link_speed = phy_setup_axiemac(xemacp);
XAxiEthernet_SetOperatingSpeed(xemacp,
link_speed);
#endif
netif_set_link_up(netif);
eth_link_status = ETH_LINK_UP;
xil_printf("Ethernet Link up\r\n");
}
break;
}
netif_set_link_up(netif);
eth_link_status = ETH_LINK_UP;
xil_printf("Ethernet Link up\r\n");
}
break;
}
}
#ifdef OS_IS_FREERTOS
@@ -422,11 +422,11 @@ void link_detect_thread(void *p)
struct netif *netif = (struct netif *) p;
while (1) {
/* Call eth_link_detect() every second to detect Ethernet link
* change.
*/
eth_link_detect(netif);
vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
}
/* Call eth_link_detect() every second to detect Ethernet link
* change.
*/
eth_link_detect(netif);
vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
}
}
#endif

2
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h
View File

@@ -44,7 +44,7 @@
#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
ADVERTISE_10HALF | ADVERTISE_100HALF)
ADVERTISE_10HALF | ADVERTISE_100HALF)
#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)

452
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c
View File

File diff suppressed because it is too large Load Diff

710
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_dma.c
View File

File diff suppressed because it is too large Load Diff

206
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c
View File

@@ -55,11 +55,11 @@ XEmacPs_Config *xemacps_lookup_config(unsigned mac_base)
s32_t i;
for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
cfgptr = &XEmacPs_ConfigTable[i];
break;
}
}
if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
cfgptr = &XEmacPs_ConfigTable[i];
break;
}
}
return (cfgptr);
}
@@ -82,11 +82,11 @@ void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
XEmacPs_SetOptions(xemacpsp, XEMACPS_MULTICAST_OPTION);
#endif
/* set mac address */
/* set mac address */
status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
if (status != XST_SUCCESS) {
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
@@ -109,44 +109,44 @@ void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
#else
detect_phy(xemacpsp);
for (i = 31; i > 0; i--) {
if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
if (phymapemac0[i] == TRUE) {
link_speed = phy_setup_emacps(xemacpsp, i);
phyfoundforemac0 = TRUE;
phyaddrforemac = i;
}
} else {
if (phymapemac1[i] == TRUE) {
link_speed = phy_setup_emacps(xemacpsp, i);
phyfoundforemac1 = TRUE;
phyaddrforemac = i;
}
}
}
/* If no PHY was detected, use broadcast PHY address of 0 */
if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
if (phymapemac0[i] == TRUE) {
link_speed = phy_setup_emacps(xemacpsp, i);
phyfoundforemac0 = TRUE;
phyaddrforemac = i;
}
} else {
if (phymapemac1[i] == TRUE) {
link_speed = phy_setup_emacps(xemacpsp, i);
phyfoundforemac1 = TRUE;
phyaddrforemac = i;
}
}
}
/* If no PHY was detected, use broadcast PHY address of 0 */
if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
if (phyfoundforemac0 == FALSE)
link_speed = phy_setup_emacps(xemacpsp, 0);
} else {
if (phyfoundforemac1 == FALSE)
link_speed = phy_setup_emacps(xemacpsp, 0);
}
if (phyfoundforemac0 == FALSE)
link_speed = phy_setup_emacps(xemacpsp, 0);
} else {
if (phyfoundforemac1 == FALSE)
link_speed = phy_setup_emacps(xemacpsp, 0);
}
#endif
if (link_speed == XST_FAILURE) {
eth_link_status = ETH_LINK_DOWN;
xil_printf("Phy setup failure %s \n\r",__func__);
return;
} else {
eth_link_status = ETH_LINK_UP;
}
eth_link_status = ETH_LINK_DOWN;
xil_printf("Phy setup failure %s \n\r",__func__);
return;
} else {
eth_link_status = ETH_LINK_UP;
}
XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile s32_t wait;
for (wait=0; wait < 20000; wait++);
}
/* Setting the operating speed of the MAC needs a delay. */
{
volatile s32_t wait;
for (wait=0; wait < 20000; wait++);
}
}
void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
@@ -156,19 +156,19 @@ void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
xemacpsp = &xemacps->emacps;
/* set mac address */
/* set mac address */
status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
if (status != XST_SUCCESS) {
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile s32_t wait;
for (wait=0; wait < 20000; wait++);
}
/* Setting the operating speed of the MAC needs a delay. */
{
volatile s32_t wait;
for (wait=0; wait < 20000; wait++);
}
}
void setup_isr (struct xemac_s *xemac)
@@ -176,41 +176,41 @@ void setup_isr (struct xemac_s *xemac)
xemacpsif_s *xemacpsif;
xemacpsif = (xemacpsif_s *)(xemac->state);
/*
* Setup callbacks
*/
/*
* Setup callbacks
*/
XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND,
(void *) emacps_send_handler,
(void *) xemac);
(void *) emacps_send_handler,
(void *) xemac);
XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV,
(void *) emacps_recv_handler,
(void *) xemac);
(void *) emacps_recv_handler,
(void *) xemac);
XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR,
(void *) emacps_error_handler,
(void *) xemac);
(void *) emacps_error_handler,
(void *) xemac);
}
void start_emacps (xemacpsif_s *xemacps)
{
/* start the temac */
/* start the temac */
XEmacPs_Start(&xemacps->emacps);
}
void restart_emacps_transmitter (xemacpsif_s *xemacps) {
u32_t Reg;
Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
XEMACPS_NWCTRL_OFFSET);
Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
XEMACPS_NWCTRL_OFFSET, Reg);
Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
XEMACPS_NWCTRL_OFFSET);
Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
XEMACPS_NWCTRL_OFFSET, Reg);
}
void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
@@ -229,47 +229,47 @@ void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
if (ErrorWord != 0) {
switch (Direction) {
case XEMACPS_RECV:
if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
HandleEmacPsError(xemac);
}
if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
emacps_recv_handler(arg);
setup_rx_bds(xemacpsif, rxring);
}
if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
emacps_recv_handler(arg);
setup_rx_bds(xemacpsif, rxring);
}
break;
case XEMACPS_SEND:
if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
HandleEmacPsError(xemac);
}
if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
// process_sent_bds(xemacpsif, txring);
}
break;
}
}
switch (Direction) {
case XEMACPS_RECV:
if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
HandleEmacPsError(xemac);
}
if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
emacps_recv_handler(arg);
setup_rx_bds(xemacpsif, rxring);
}
if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
emacps_recv_handler(arg);
setup_rx_bds(xemacpsif, rxring);
}
break;
case XEMACPS_SEND:
if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
HandleEmacPsError(xemac);
}
if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
HandleTxErrors(xemac);
}
if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
// process_sent_bds(xemacpsif, txring);
}
break;
}
}
#ifdef OS_IS_FREERTOS
xInsideISR--;
#endif

938
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_physpeed.c
View File

File diff suppressed because it is too large Load Diff

12
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c
View File

@@ -44,14 +44,14 @@ pq_create_queue()
pq_queue_t *q = NULL;
if (i >= NUM_QUEUES) {
xil_printf("ERR: Max Queues allocated\n\r");
return q;
}
xil_printf("ERR: Max Queues allocated\n\r");
return q;
}
q = &pq_queue[i++];
if (!q)
return q;
return q;
q->head = q->tail = q->len = 0;
@@ -62,7 +62,7 @@ int
pq_enqueue(pq_queue_t *q, void *p)
{
if (q->len == PQ_QUEUE_SIZE)
return -1;
return -1;
q->data[q->head] = p;
q->head = (q->head + 1)%PQ_QUEUE_SIZE;
@@ -77,7 +77,7 @@ pq_dequeue(pq_queue_t *q)
int ptail;
if (q->len == 0)
return NULL;
return NULL;
ptail = q->tail;
q->tail = (q->tail + 1)%PQ_QUEUE_SIZE;

16
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c
View File

@@ -2,14 +2,14 @@
#include "xparameters.h"
struct xtopology_t xtopology[] = {
{
0xFF0E0000,
xemac_type_emacps,
0x0,
0x0,
0xF8F00100,
XPAR_XEMACPS_3_INTR,
},
{
0xFF0E0000,
xemac_type_emacps,
0x0,
0x0,
0xF8F00100,
XPAR_XEMACPS_3_INTR,
},
};
int xtopology_n_emacs = 1;

10
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
View File

@@ -20,7 +20,7 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
@@ -132,7 +132,7 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
*LocalAddr = Value;
}
/*****************************************************************************/
@@ -150,7 +150,7 @@ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
*LocalAddr = Value;
}
/*****************************************************************************/
@@ -170,7 +170,7 @@ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
@@ -191,7 +191,7 @@ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
*LocalAddr = Value;
}
#ifdef __cplusplus

2
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h
View File

@@ -13,4 +13,4 @@ extern "C" {
}
#endif
#endif /* end of protection macro */
#endif /* end of protection macro */

28
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
View File

@@ -1,5 +1,5 @@
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#include <rtdef.h>
#include <stdint.h>
@@ -12,25 +12,25 @@ extern "C" {
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
assigend to "IsReady" member of driver
instance to indicate that driver
instance is initialized and ready to use. */
instance to indicate that driver
instance is initialized and ready to use. */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
"IsStarted" member of driver instance
to indicate that driver instance is
started and it can be enabled. */
to indicate that driver instance is
started and it can be enabled. */
typedef rt_uint8_t u8;
typedef rt_uint16_t u16;
@@ -55,7 +55,7 @@ typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
/** @{ */
/**
@@ -73,15 +73,15 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#define NULL 0U
#endif
#ifdef __cplusplus
@@ -93,7 +93,7 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
}
#endif
#endif /* end of protection macro */
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_types".
*/

384
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
View File

@@ -48,103 +48,103 @@ extern "C" {
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID
#define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID
#define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID
#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID
#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID
#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID
#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID
#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID
#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID
#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID
#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID
#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID
#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID
#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
@@ -155,97 +155,97 @@ extern "C" {
*/
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_FPGA0_INT_ID 121U
#define XPS_FPGA1_INT_ID 122U
#define XPS_FPGA2_INT_ID 123U
#define XPS_FPGA3_INT_ID 124U
#define XPS_FPGA4_INT_ID 125U
#define XPS_FPGA5_INT_ID 126U
#define XPS_FPGA6_INT_ID 127U
#define XPS_FPGA7_INT_ID 128U
#define XPS_FPGA8_INT_ID 136U
#define XPS_FPGA9_INT_ID 137U
#define XPS_FPGA10_INT_ID 138U
#define XPS_FPGA11_INT_ID 139U
#define XPS_FPGA12_INT_ID 140U
#define XPS_FPGA13_INT_ID 141U
#define XPS_FPGA14_INT_ID 142U
#define XPS_FPGA15_INT_ID 143U
#define XPS_FPGA0_INT_ID 121U
#define XPS_FPGA1_INT_ID 122U
#define XPS_FPGA2_INT_ID 123U
#define XPS_FPGA3_INT_ID 124U
#define XPS_FPGA4_INT_ID 125U
#define XPS_FPGA5_INT_ID 126U
#define XPS_FPGA6_INT_ID 127U
#define XPS_FPGA7_INT_ID 128U
#define XPS_FPGA8_INT_ID 136U
#define XPS_FPGA9_INT_ID 137U
#define XPS_FPGA10_INT_ID 138U
#define XPS_FPGA11_INT_ID 139U
#define XPS_FPGA12_INT_ID 140U
#define XPS_FPGA13_INT_ID 141U
#define XPS_FPGA14_INT_ID 142U
#define XPS_FPGA15_INT_ID 143U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_NAND_INT_ID (14U + 32U)
#define XPS_QSPI_INT_ID (15U + 32U)
#define XPS_GPIO_INT_ID (16U + 32U)
#define XPS_I2C0_INT_ID (17U + 32U)
#define XPS_I2C1_INT_ID (18U + 32U)
#define XPS_SPI0_INT_ID (19U + 32U)
#define XPS_SPI1_INT_ID (20U + 32U)
#define XPS_UART0_INT_ID (21U + 32U)
#define XPS_UART1_INT_ID (22U + 32U)
#define XPS_CAN0_INT_ID (23U + 32U)
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
#define XPS_RTC_SEC_INT_ID (27U + 32U)
#define XPS_LPD_SWDT_INT_ID (52U + 32U)
#define XPS_CSU_WDT_INT_ID (53U + 32U)
#define XPS_FPD_SWDT_INT_ID (113U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
#define XPS_TTC1_0_INT_ID (39U + 32U)
#define XPS_TTC1_1_INT_ID (40U + 32U)
#define XPS_TTC1_2_INT_ID (41U + 32U)
#define XPS_TTC2_0_INT_ID (42U + 32U)
#define XPS_TTC2_1_INT_ID (43U + 32U)
#define XPS_TTC2_2_INT_ID (44U + 32U)
#define XPS_TTC3_0_INT_ID (45U + 32U)
#define XPS_TTC3_1_INT_ID (46U + 32U)
#define XPS_TTC3_2_INT_ID (47U + 32U)
#define XPS_SDIO0_INT_ID (48U + 32U)
#define XPS_SDIO1_INT_ID (49U + 32U)
#define XPS_AMS_INT_ID (56U + 32U)
#define XPS_GEM0_INT_ID (57U + 32U)
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
#define XPS_GEM1_INT_ID (59U + 32U)
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
#define XPS_GEM2_INT_ID (61U + 32U)
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
#define XPS_GEM3_INT_ID (63U + 32U)
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
#define XPS_USB3_0_WAKE_INT_ID (75U + 32U)
#define XPS_USB3_1_WAKE_INT_ID (76U + 32U)
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
#define XPS_CSU_DMA_INT_ID (86U + 32U)
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
#define XPS_FPD_CCI_INT_ID (154U + 32U)
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
#define XPS_APM0_INT_ID (123U + 32U)
#define XPS_APM1_INT_ID (25U + 32U)
#define XPS_APM2_INT_ID (25U + 32U)
#define XPS_APM5_INT_ID (123U + 32U)
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_NAND_INT_ID (14U + 32U)
#define XPS_QSPI_INT_ID (15U + 32U)
#define XPS_GPIO_INT_ID (16U + 32U)
#define XPS_I2C0_INT_ID (17U + 32U)
#define XPS_I2C1_INT_ID (18U + 32U)
#define XPS_SPI0_INT_ID (19U + 32U)
#define XPS_SPI1_INT_ID (20U + 32U)
#define XPS_UART0_INT_ID (21U + 32U)
#define XPS_UART1_INT_ID (22U + 32U)
#define XPS_CAN0_INT_ID (23U + 32U)
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
#define XPS_RTC_SEC_INT_ID (27U + 32U)
#define XPS_LPD_SWDT_INT_ID (52U + 32U)
#define XPS_CSU_WDT_INT_ID (53U + 32U)
#define XPS_FPD_SWDT_INT_ID (113U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
#define XPS_TTC1_0_INT_ID (39U + 32U)
#define XPS_TTC1_1_INT_ID (40U + 32U)
#define XPS_TTC1_2_INT_ID (41U + 32U)
#define XPS_TTC2_0_INT_ID (42U + 32U)
#define XPS_TTC2_1_INT_ID (43U + 32U)
#define XPS_TTC2_2_INT_ID (44U + 32U)
#define XPS_TTC3_0_INT_ID (45U + 32U)
#define XPS_TTC3_1_INT_ID (46U + 32U)
#define XPS_TTC3_2_INT_ID (47U + 32U)
#define XPS_SDIO0_INT_ID (48U + 32U)
#define XPS_SDIO1_INT_ID (49U + 32U)
#define XPS_AMS_INT_ID (56U + 32U)
#define XPS_GEM0_INT_ID (57U + 32U)
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
#define XPS_GEM1_INT_ID (59U + 32U)
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
#define XPS_GEM2_INT_ID (61U + 32U)
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
#define XPS_GEM3_INT_ID (63U + 32U)
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
#define XPS_USB3_0_WAKE_INT_ID (75U + 32U)
#define XPS_USB3_1_WAKE_INT_ID (76U + 32U)
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
#define XPS_CSU_DMA_INT_ID (86U + 32U)
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
#define XPS_FPD_CCI_INT_ID (154U + 32U)
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
#define XPS_APM0_INT_ID (123U + 32U)
#define XPS_APM1_INT_ID (25U + 32U)
#define XPS_APM2_INT_ID (25U + 32U)
#define XPS_APM5_INT_ID (123U + 32U)
/* REDEFINES for TEST APP */
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
@@ -268,7 +268,7 @@ extern "C" {
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
@@ -277,32 +277,32 @@ extern "C" {
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibility */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
@@ -312,7 +312,7 @@ extern "C" {
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
#endif
#define XPAR_SCUWDT_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus

8
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h
View File

@@ -1,5 +1,5 @@
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#include "xil_types.h"
#include "xparameters.h"
@@ -12,12 +12,12 @@ extern "C" {
#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
XPAR_PMC_TAP_VERSION_OFFSET)
XPAR_PMC_TAP_VERSION_OFFSET)
#else
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
XPAR_CSU_VER_OFFSET)
XPAR_CSU_VER_OFFSET)
#endif
#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
#define XPLAT_ZYNQ_ULTRA_MP 0x1

522
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h
View File

File diff suppressed because it is too large Load Diff

16
bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c
View File

@@ -184,9 +184,9 @@ static DSTATUS disk_initialize(
if (CardDetect)
{
/*
* Card detection check
* If the HC detects the No Card State, power will be cleared
*/
* Card detection check
* If the HC detects the No Card State, power will be cleared
*/
while (!((XSDPS_PSR_CARD_DPL_MASK |
XSDPS_PSR_CARD_STABLE_MASK |
XSDPS_PSR_CARD_INSRT_MASK) ==
@@ -198,8 +198,8 @@ static DSTATUS disk_initialize(
}
/*
* Initialize the host controller
*/
* Initialize the host controller
*/
SdConfig = XSdPs_LookupConfig((u16)pdrv);
if (NULL == SdConfig)
{
@@ -223,9 +223,9 @@ static DSTATUS disk_initialize(
}
/*
* Disk is initialized.
* Store the same in Stat.
*/
* Disk is initialized.
* Store the same in Stat.
*/
s &= (~STA_NOINIT);
Stat[pdrv] = s;

14
bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c
View File

@@ -21,7 +21,7 @@
#define XUARTPS_MAX_RATE 921600U
#define XUARTPS_MIN_RATE 110U
#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
#define ZynqMP_UART_INT_DISABLE(UART) \
(UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
@@ -92,12 +92,12 @@ static void rt_hw_uart_isr(int irqno, void *param)
static rt_err_t XUartPsSetBandRate(struct hw_uart_device *pdev, rt_uint32_t targetBandRate)
{
rt_uint32_t IterBAUDDIV; /* Iterator for available baud divisor values */
rt_uint32_t BRGR_Value; /* Calculated value for baud rate generator */
rt_uint32_t CalcBaudRate; /* Calculated baud rate */
rt_uint32_t BaudError; /* Diff between calculated and requested baud rate */
rt_uint32_t Best_BRGR = 0U; /* Best value for baud rate generator */
rt_uint8_t Best_BAUDDIV = 0U; /* Best value for baud divisor */
rt_uint32_t IterBAUDDIV; /* Iterator for available baud divisor values */
rt_uint32_t BRGR_Value; /* Calculated value for baud rate generator */
rt_uint32_t CalcBaudRate; /* Calculated baud rate */
rt_uint32_t BaudError; /* Diff between calculated and requested baud rate */
rt_uint32_t Best_BRGR = 0U; /* Best value for baud rate generator */
rt_uint8_t Best_BAUDDIV = 0U; /* Best value for baud divisor */
rt_uint32_t Best_Error = 0xFFFFFFFFU;
rt_uint32_t PercentError;
rt_uint32_t ModeReg;

4
bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h
View File

@@ -9,8 +9,8 @@
#define __REG8(x) (*((volatile rt_uint8_t *)(x)))
#define ZynqMP_CRL_APB_BASEADDR XPAR_PSU_CRL_APB_S_AXI_BASEADDR
#define ZynqMP_CRL_APB_IOPLL_CTRL 0x020
#define ZynqMP_CRL_APB_IOPLL_CFG 0x024
#define ZynqMP_CRL_APB_IOPLL_CTRL 0x020
#define ZynqMP_CRL_APB_IOPLL_CFG 0x024
#define ZynqMP_CRL_APB_UART0_REF_CTRL 0x074
#define ZynqMP_CRL_APB_UART1_REF_CTRL 0x078
#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL 0x0AC

4
bsp/zynqmp-r5-axu4ev/rtconfig.py
View File

@@ -9,8 +9,8 @@ if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# only support GNU GCC compiler
PLATFORM = 'gcc'
EXEC_PATH = '/opt/arm-none-eabi-gcc'
PLATFORM = 'gcc'
EXEC_PATH = '/opt/arm-none-eabi-gcc'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')