Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-03-27 17:45:13 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

AVR32 branch update for AVR32 Studio 2.6 with Atmel Software Framework included.

Browse Source 
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1594 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
Kyle.Hu.GZ@gmail.com
2011-07-04 02:38:23 +00:00
parent 6b6cecac2f
commit 93e50cd8aa
30 changed files with 10442 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

121
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/BOARDS/board.h Normal file
View File

@@ -0,0 +1,121 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include <avr32/io.h>
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
#define STK1000 6 //!< AT32AP7000 STK1000 board.
#define NGW100 7 //!< AT32AP7000 NGW100 board.
#define STK600_RCUC3L0 8 //!< STK600 RCUC3L0 board.
#define UC3L_EK 9 //!< AT32UC3L-EK board.
#define USER_BOARD 99 //!< User-reserved board (if any).
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board.
#define MC300 2 //!< AT32UC3 MC300 board.
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#if BOARD == EVK1100
#include "EVK1100/evk1100.h"
#elif BOARD == EVK1101
#include "EVK1101/evk1101.h"
#elif BOARD == UC3C_EK
#include "UC3C_EK/uc3c_ek.h"
#elif BOARD == EVK1104
#include "EVK1104/evk1104.h"
#elif BOARD == EVK1105
#include "EVK1105/evk1105.h"
#elif BOARD == STK1000
#include "STK1000/stk1000.h"
#elif BOARD == NGW100
#include "NGW100/ngw100.h"
#elif BOARD == STK600_RCUC3L0
#include "STK600/RCUC3L0/stk600_rcuc3l0.h"
#elif BOARD == UC3L_EK
#include "UC3L_EK/uc3l_ek.h"
#elif BOARD == USER_BOARD
// User-reserved area: #include the header file of your board here (if any).
#include "user_board.h"
#else
#error No known AVR32 board defined
#endif
#if (defined EXT_BOARD)
#if EXT_BOARD == EXT1102
#include "EXT1102/ext1102.h"
#elif EXT_BOARD == MC300
#include "MC300/mc300.h"
#elif EXT_BOARD == USER_EXT_BOARD
// User-reserved area: #include the header file of your extension board here
// (if any).
#endif
#endif
#ifndef FRCOSC
#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.
#endif
#endif // _BOARD_H_

1117
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.c Normal file
View File

File diff suppressed because it is too large Load Diff

1002
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.h Normal file
View File

File diff suppressed because it is too large Load Diff

458
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c Normal file
View File

@@ -0,0 +1,458 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO driver for AVR32 UC3.
*
* This file defines a useful set of functions for the GPIO.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include "gpio.h"
//! GPIO module instance.
#define GPIO AVR32_GPIO
/*! \name Peripheral Bus Interface
*/
//! @{
int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
{
int status = GPIO_SUCCESS;
unsigned int i;
for (i = 0; i < size; i++)
{
status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
gpiomap++;
}
return status;
}
int gpio_enable_module_pin(unsigned int pin, unsigned int function)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the correct function.
switch (function)
{
case 0: // A function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 1: // B function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 2: // C function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 3: // D function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
case 4: // E function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 5: // F function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 6: // G function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 7: // H function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
#endif
default:
return GPIO_INVALID_ARGUMENT;
}
// Disable GPIO control.
gpio_port->gperc = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
{
unsigned int i;
for (i = 0; i < size; i++)
{
gpio_enable_gpio_pin(gpiomap->pin);
gpiomap++;
}
}
void gpio_enable_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F);
gpio_port->gpers = 1 << (pin & 0x1F);
}
// The open-drain mode is not synthesized on the current AVR32 products.
// If one day some AVR32 products have this feature, the corresponding part
// numbers should be listed in the #if below.
// Note that other functions are available in this driver to use pins with open
// drain in GPIO mode. The advantage of the open-drain mode functions over these
// other functions is that they can be used not only in GPIO mode but also in
// module mode.
#if 0
void gpio_enable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmerc = 1 << (pin & 0x1F);
}
#endif
void gpio_enable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pderc = 1 << (pin & 0x1F);
#endif
}
void gpio_disable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
}
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
/*! \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->pderc = 1 << (pin & 0x1F);
}
/*! \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pderc = 1 << (pin & 0x1F);
}
#endif
int gpio_get_pin_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->pvr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ovr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;
}
void gpio_set_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_set_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0.
gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_enable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gfers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gferc = 1 << (pin & 0x1F);
}
/*! \brief Configure the edge detector of an input pin
*
* \param pin The pin number.
* \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE
* or \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Configure the edge detector.
switch (mode)
{
case GPIO_PIN_CHANGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_RISING_EDGE:
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_FALLING_EDGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
return GPIO_SUCCESS;
}
int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
// Configure the edge detector.
if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode))
return(GPIO_INVALID_ARGUMENT);
// Enable interrupt.
gpio_port->iers = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_disable_pin_interrupt(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ierc = 1 << (pin & 0x1F);
}
int gpio_get_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ifr >> (pin & 0x1F)) & 1;
}
void gpio_clear_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ifrc = 1 << (pin & 0x1F);
}
//#
//# Peripheral Event System Support.
//#
#if UC3L
int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
if(TRUE == use_igf)
{
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
}
else
{
// Disable the glitch filter.
gpio_port->gferc = 1 << (pin & 0x1F);
}
// Configure the edge detector.
return(gpio_configure_edge_detector(pin, mode));
}
#endif
//! @}

583
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h Normal file
View File

File diff suppressed because it is too large Load Diff

239
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x Normal file
View File

@@ -0,0 +1,239 @@
/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supported by an AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#if !__AVR32_UC__ && !__AVR32_AP__
#error Implementation of the AVR32 architecture not supported by the INTC driver.
#endif
#include <avr32/io.h>
//! @{
//! \verbatim
.section .exception, "ax", @progbits
// Start of Exception Vector Table.
// EVBA must be aligned with a power of two strictly greater than the EVBA-
// relative offset of the last vector.
.balign 0x200
// Export symbol.
.global _evba
.type _evba, @function
_evba:
.org 0x000
// Unrecoverable Exception.
_handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit.
_handle_TLB_Multiple_Hit:
rjmp $
.org 0x008
// Bus Error Data Fetch.
_handle_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
// Bus Error Instruction Fetch.
_handle_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
// NMI.
_handle_NMI:
rjmp $
.org 0x014
// Instruction Address.
_handle_Instruction_Address:
rjmp $
.org 0x018
// ITLB Protection.
_handle_ITLB_Protection:
rjmp $
.org 0x01C
// Breakpoint.
_handle_Breakpoint:
rjmp $
.org 0x020
// Illegal Opcode.
_handle_Illegal_Opcode:
rjmp $
.org 0x024
// Unimplemented Instruction.
_handle_Unimplemented_Instruction:
rjmp $
.org 0x028
// Privilege Violation.
_handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
_handle_Floating_Point:
rjmp $
.org 0x030
// Coprocessor Absent: UNUSED IN AVR32UC.
_handle_Coprocessor_Absent:
rjmp $
.org 0x034
// Data Address (Read).
_handle_Data_Address_Read:
rjmp $
.org 0x038
// Data Address (Write).
_handle_Data_Address_Write:
rjmp $
.org 0x03C
// DTLB Protection (Read).
_handle_DTLB_Protection_Read:
rjmp $
.org 0x040
// DTLB Protection (Write).
_handle_DTLB_Protection_Write:
rjmp $
.org 0x044
// DTLB Modified: UNUSED IN AVR32UC.
_handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read).
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write).
_handle_DTLB_Miss_Write:
rjmp $
.org 0x100
// Supervisor Call.
_handle_Supervisor_Call:
rjmp $
// Interrupt support.
// The interrupt controller must provide the offset address relative to EVBA.
// Important note:
// All interrupts call a C function named _get_interrupt_handler.
// This function will read group and interrupt line number to then return in
// R12 a pointer to a user-provided interrupt handler.
.balign 4
.irp priority, 0, 1, 2, 3
_int\priority:
#if __AVR32_UC__
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry. No other register is saved by hardware.
#elif __AVR32_AP__
// PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
// the CPU upon interrupt entry. No other register is saved by hardware.
pushm r8-r12, lr
#endif
mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
#if __AVR32_UC__
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
#elif __AVR32_AP__
breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch.
st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
popm r8-r12, lr, pc // Restore registers and jump to the handler.
spint\priority:
popm r8-r12, lr
#endif
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
.endr
// Constant data area.
.balign 4
// Values to store in the interrupt priority registers for the various interrupt priority levels.
// The interrupt priority registers contain the interrupt priority level and
// the EVBA-relative interrupt vector offset.
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
//! \endverbatim
//! @}

214
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c Normal file
View File

@@ -0,0 +1,214 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
// define _evba from exception.S
extern void _evba;
//! Values to store in the interrupt priority registers for the various interrupt priority levels.
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
//! Each line handler table contains a set of pointers to interrupt handlers.
#if (defined __GNUC__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#elif (defined __ICCAVR32__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#endif
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
//! Table containing for each interrupt group the number of interrupt request
//! lines and a pointer to the table of interrupt line handlers.
static const struct
{
unsigned int num_irqs;
volatile __int_handler *_int_line_handler_table;
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
{
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
#undef INSERT_INT_LINE_HANDLER_TABLE
};
/*! \brief Default interrupt handler.
*
* \note Taken and adapted from Newlib.
*/
#if (defined __GNUC__)
__attribute__((__interrupt__))
#elif (defined __ICCAVR32__)
__interrupt
#endif
static void _unhandled_interrupt(void)
{
// Catch unregistered interrupts.
while (TRUE);
}
/*! \brief Gets the interrupt handler of the current event at the \a int_level
* interrupt priority level (called from exception.S).
*
* \param int_level Interrupt priority level to handle.
*
* \return Interrupt handler to execute.
*
* \note Taken and adapted from Newlib.
*/
__int_handler _get_interrupt_handler(unsigned int int_level)
{
// ICR3 is mapped first, ICR0 last.
// Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
// pass a single argument to a function.
unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
unsigned int int_req = AVR32_INTC.irr[int_grp];
// As an interrupt may disappear while it is being fetched by the CPU
// (spurious interrupt caused by a delayed response from an MCU peripheral to
// an interrupt flag clear or interrupt disable instruction), check if there
// are remaining interrupt lines to process.
// If a spurious interrupt occurs, the status register (SR) contains an
// execution mode and interrupt level masks corresponding to a level 0
// interrupt, whatever the interrupt priority level causing the spurious
// event. This behavior has been chosen because a spurious interrupt has not
// to be a priority one and because it may not cause any trouble to other
// interrupts.
// However, these spurious interrupts place the hardware in an unstable state
// and could give problems in other/future versions of the CPU, so the
// software has to be written so that they never occur. The only safe way of
// achieving this is to always clear or disable peripheral interrupts with the
// following sequence:
// 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
// 2: Perform the bus access to the peripheral register that clears or
// disables the interrupt.
// 3: Wait until the interrupt has actually been cleared or disabled by the
// peripheral. This is usually performed by reading from a register in the
// same peripheral (it DOES NOT have to be the same register that was
// accessed in step 2, but it MUST be in the same peripheral), what takes
// bus system latencies into account, but peripheral internal latencies
// (generally 0 cycle) also have to be considered.
// 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
// Note that steps 1 and 4 are useless inside interrupt handlers as the
// corresponding interrupt level is automatically masked by IxM (unless IxM is
// explicitly cleared by the software).
//
// Get the right IRQ handler.
//
// If several interrupt lines are active in the group, the interrupt line with
// the highest number is selected. This is to be coherent with the
// prioritization of interrupt groups performed by the hardware interrupt
// controller.
//
// If no handler has been registered for the pending interrupt,
// _unhandled_interrupt will be selected thanks to the initialization of
// _int_line_handler_table_x by INTC_init_interrupts.
//
// exception.S will provide the interrupt handler with a clean interrupt stack
// frame, with nothing more pushed onto the stack. The interrupt handler must
// manage the `rete' instruction, what can be done thanks to pure assembly,
// inline assembly or the `__attribute__((__interrupt__))' C function
// attribute.
return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
}
//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
static __inline__ void INTC_init_evba(void)
{
Set_system_register(AVR32_EVBA, (int)&_evba );
}
void INTC_init_interrupts(void)
{
unsigned int int_grp, int_req;
INTC_init_evba();
// For all interrupt groups,
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
{
// For all interrupt request lines of each group,
for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
{
// Assign _unhandled_interrupt as default interrupt handler.
_int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
}
// Set the interrupt group priority register to its default value.
// By default, all interrupt groups are linked to the interrupt priority
// level 0 and to the interrupt vector _int0.
AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
}
}
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
{
// Determine the group of the IRQ.
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so
// that _get_interrupt_handler can retrieve it when the interrupt is vectored.
_int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
// Program the corresponding IPRX register to set the interrupt priority level
// and the interrupt vector offset that will be fetched by the core interrupt
// system.
// NOTE: The _intx functions are intermediate assembly functions between the
// core interrupt system and the user interrupt handler.
AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
}

100
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.h Normal file
View File

@@ -0,0 +1,100 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _INTC_H_
#define _INTC_H_
#include "compiler.h"
//! Maximal number of interrupt request lines per group.
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
//! Number of interrupt priority levels.
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//! Pointer to interrupt handler.
#if (defined __GNUC__)
typedef void (*__int_handler)(void);
#elif (defined __ICCAVR32__)
typedef void (__interrupt *__int_handler)(void);
#endif
/*! \brief Initializes the hardware interrupt controller driver.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_init_interrupts(void);
/*! \brief Registers an interrupt handler.
*
* \param handler Interrupt handler to register.
* \param irq IRQ of the interrupt handler to register.
* \param int_level Interrupt priority level to assign to the group of this IRQ.
*
* \warning The interrupt handler must manage the `rete' instruction, what can
* be done thanks to pure assembly, inline assembly or the
* `__attribute__((__interrupt__))' C function attribute.
*
* \warning If several interrupt handlers of a same group are registered with
* different priority levels, only the latest priority level set will
* be effective.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level);
#endif // __AVR32_ABI_COMPILER__
#endif // _INTC_H_

546
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c Normal file
View File

File diff suppressed because it is too large Load Diff

493
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h Normal file
View File

@@ -0,0 +1,493 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager driver.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _PM_H_
#define _PM_H_
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
/*! \brief Sets the MCU in the specified sleep mode.
*
* \param mode Sleep mode:
* \arg \c AVR32_PM_SMODE_IDLE: Idle;
* \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
* \arg \c AVR32_PM_SMODE_STANDBY: Standby;
* \arg \c AVR32_PM_SMODE_STOP: Stop;
* \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
* \arg \c AVR32_PM_SMODE_STATIC: Static.
*/
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
typedef struct
{
//! CPU frequency (input/output argument).
unsigned long cpu_f;
//! PBA frequency (input/output argument).
unsigned long pba_f;
//! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
unsigned long osc0_f;
//! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
unsigned long osc0_startup;
} pm_freq_param_t;
#define PM_FREQ_STATUS_FAIL (-1)
#define PM_FREQ_STATUS_OK (0)
/*! \brief Gets the MCU reset cause.
*
* \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
*
* \return The MCU reset cause which can be masked with the
* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
{
return pm->rcause;
}
/*!
* \brief This function will enable the external clock mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
*/
extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
/*!
* \brief This function will enable the oscillator 0 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk0(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 0 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc0 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc1 Oscillator 1 crystal frequency (Hz)
*/
extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
/*!
* \brief This function will enable the oscillator 1 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk1(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 1 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc1 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 32.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk32(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the osc32 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will select all the power manager clocks.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pbadiv Peripheral Bus A clock divisor enable
* \param pbasel Peripheral Bus A select
* \param pbbdiv Peripheral Bus B clock divisor enable
* \param pbbsel Peripheral Bus B select
* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
*/
extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
/*!
* \brief This function will setup a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
* \param osc_or_pll Use OSC (=0) or PLL (=1)
* \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
* \param diven Generic clock divisor enable
* \param div Generic clock divisor
*/
extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
/*!
* \brief This function will enable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will disable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will setup a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param mul PLL MUL in the PLL formula
* \param div PLL DIV in the PLL formula
* \param osc OSC number (0 for osc0, 1 for osc1)
* \param lockcount PLL lockount
*/
extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
/*!
* \brief This function will set a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
* \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
* \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
/*!
* \brief This function will get a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \return Option
*/
extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will enable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will disable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will wait for PLL0 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will wait for PLL1 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will switch the power manager main clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
*/
extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
/*!
* \brief Switch main clock to clock Osc0 (crystal mode)
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
* \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
/*! \brief Enables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
/*! \brief Disables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
/*! \brief Clears the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 No BOD interrupt.
* \retval 1 BOD interrupt pending.
*/
extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt enable status.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 BOD interrupt disabled.
* \retval 1 BOD interrupt enabled.
*/
extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
/*! \brief Gets the triggering threshold of the Brown-Out Detector.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \return Triggering threshold of the BOD. See the electrical characteristics
* in the part datasheet for actual voltage levels.
*/
extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
/*!
* \brief Read the content of the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
*
* \return The content of the chosen GPLP register.
*/
extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
/*!
* \brief Write into the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
* \param value Value to write
*/
extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
/*! \brief Enable the clock of a module.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param module The module to clock (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
/*! \brief Disable the clock of a module.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param module The module to shut down (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
* according to the user wishes.
*
* This function needs some parameters stored in a pm_freq_param_t structure:
* - cpu_f and pba_f are the wanted frequencies,
* - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
* - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
*
* The function will then configure the clocks using the following rules:
* - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
* to satisfy the CPU frequency,
* - It optimizes the configuration depending the various divide stages,
* - Then, the PBA frequency is configured from the CPU freq.
* - Note that HSB and PBB are configured with the same frequency as CPU.
* - Note also that the number of wait states of the flash read accesses is automatically set-up depending
* the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
*
* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
*
* \param param pointer on the configuration structure.
*
* \retval PM_FREQ_STATUS_OK Mode successfully initialized.
* \retval PM_FREQ_STATUS_FAIL The configuration can not be done.
*/
extern int pm_configure_clocks(pm_freq_param_t *param);
/*! \brief Automatically configure the USB clock.
*
* USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
* a 12 MHz crystal is connected to it.
*/
extern void pm_configure_usb_clock(void);
#endif // _PM_H_

268
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c Normal file
View File

@@ -0,0 +1,268 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager clocks configuration helper.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <string.h>
#include "compiler.h"
#include "pm.h"
extern void flashc_set_wait_state(unsigned int wait_state);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
extern void flashc_issue_command(unsigned int command, int page_number);
#endif
#define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
int pm_configure_clocks(pm_freq_param_t *param)
{
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Switch to external Oscillator 0
pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PM_FREQ_STATUS_OK;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return PM_FREQ_STATUS_FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return PM_FREQ_STATUS_FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
pm_pll_setup(&AVR32_PM
, 0 // pll
, mul // mul
, div // div
, 0 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
// PLL clock is lower than 160MHz: need to set pllopt.
, (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
, div2_en // pll_div2
, 0 // pll_wbwdisable
);
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
// Enable PLL0
pm_pll_enable(&AVR32_PM, 0);
// Wait for PLL0 locked
pm_wait_for_pll0_locked(&AVR32_PM);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
pm_cksel(&AVR32_PM
, b_div2_pba, div2_pba // PBA
, b_div2_cpu, div2_cpu // PBB
, b_div2_cpu, div2_cpu // HSB
);
if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
{
flashc_set_wait_state(1);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
else
{
flashc_set_wait_state(0);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
return PM_FREQ_STATUS_OK;
}
void pm_configure_usb_clock(void)
{
#if UC3A3
// Setup USB GCLK.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#else
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#endif
}

566
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c Normal file
View File

File diff suppressed because it is too large Load Diff

379
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h Normal file
View File

@@ -0,0 +1,379 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief High-level library abstracting features such as oscillators/pll/dfll
* configuration, clock configuration, System-sensible parameters
* configuration, buses clocks configuration, sleep mode, reset.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _POWER_CLOCKS_LIB_H_
#define _POWER_CLOCKS_LIB_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <avr32/io.h>
#include "compiler.h"
#ifndef AVR32_PM_VERSION_RESETVALUE
// Support for UC3A, UC3A3, UC3B parts.
#include "pm.h"
#else
//! Device-specific data
#if UC3L
#include "pm_uc3l.h"
#include "scif_uc3l.h"
#include "flashcdw.h"
#elif UC3C
#include "pm_uc3c.h"
#include "scif_uc3c.h"
#include "flashc.h"
#endif
#endif
/*! \name Clocks Management
*/
//! @{
//! The different oscillators
typedef enum
{
PCL_OSC0 = 0,
PCL_OSC1 = 1
} pcl_osc_t;
//! The different DFLLs
typedef enum
{
PCL_DFLL0 = 0,
PCL_DFLL1 = 1
} pcl_dfll_t;
//! Possible Main Clock Sources
typedef enum
{
PCL_MC_RCSYS, // Default main clock source, supported by all (aka Slow Clock)
PCL_MC_OSC0, // Supported by all
PCL_MC_OSC1, // Supported by UC3C only
PCL_MC_OSC0_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)
PCL_MC_OSC1_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)
PCL_MC_OSC0_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC0 as reference)
PCL_MC_OSC1_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC1 as reference)
PCL_MC_DFLL0, // Supported by UC3L
PCL_MC_DFLL1, // Not supported yet
PCL_MC_RC120M, // Supported by UC3L, UC3C
PCL_MC_RC8M, // Supported by UC3C
PCL_MC_CRIPOSC // Supported by UC3C
} pcl_mainclk_t;
//! Input and output parameters to configure clocks with pcl_configure_clocks().
// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies.
#ifndef AVR32_PM_VERSION_RESETVALUE
// Support for UC3A, UC3A3, UC3B parts.
#define pcl_freq_param_t pm_freq_param_t // See pm.h
#else
// Support for UC3C, UC3L parts.
typedef struct
{
//! Main clock source selection (input argument).
pcl_mainclk_t main_clk_src;
//! Target CPU frequency (input/output argument).
unsigned long cpu_f;
//! Target PBA frequency (input/output argument).
unsigned long pba_f;
//! Target PBB frequency (input/output argument).
unsigned long pbb_f;
//! Target PBC frequency (input/output argument).
unsigned long pbc_f;
//! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
unsigned long osc0_f;
//! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
unsigned long osc0_startup;
//! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency)
unsigned long dfll_f;
//! Other parameters that might be necessary depending on the device (implementation-dependent).
// For the UC3L DFLL setup, this parameter should be pointing to a structure of
// type (scif_gclk_opt_t *).
void *pextra_params;
} pcl_freq_param_t;
#endif
//! Define "not supported" for the lib.
#define PCL_NOT_SUPPORTED (-10000)
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
*
* This function needs some parameters stored in a pcl_freq_param_t structure:
* - main_clk_src is the id of the main clock source to use,
* - cpu_f and pba_f and pbb_f are the wanted frequencies,
* - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
* - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
* - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.
*
* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
*
* \note: since it is dynamically computing the appropriate field values of the
* configuration registers from the parameters structure, this function is not
* optimal in terms of code size. For a code size optimal solution, it is better
* to create a new function from pcl_configure_clocks() and modify it to use
* preprocessor computation from pre-defined target frequencies.
*
* \param param pointer on the configuration structure.
*
* \retval 0 Success.
* \retval <0 The configuration cannot be performed.
*/
extern long int pcl_configure_clocks(pcl_freq_param_t *param);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
*
* This function needs some parameters stored in a pcl_freq_param_t structure:
* - cpu_f and pba_f and pbb_f are the wanted frequencies
*
* Supported main clock sources: PCL_MC_RCSYS
*
* Supported synchronous clocks frequencies:
* 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
*
* \note: by default, this implementation doesn't perform thorough checks on the
* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
*
* \note: since it is dynamically computing the appropriate field values of the
* configuration registers from the parameters structure, this function is not
* optimal in terms of code size. For a code size optimal solution, it is better
* to create a new function from pcl_configure_clocks_rcsys() and modify it to use
* preprocessor computation from pre-defined target frequencies.
*
* \param param pointer on the configuration structure.
*
* \retval 0 Success.
* \retval <0 The configuration cannot be performed.
*/
extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
*
* This function needs some parameters stored in a pcl_freq_param_t structure:
* - cpu_f and pba_f and pbb_f are the wanted frequencies
*
* Supported main clock sources: PCL_MC_RC120M
*
* Supported synchronous clocks frequencies:
* 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
*
* \note: by default, this implementation doesn't perform thorough checks on the
* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
*
* \note: since it is dynamically computing the appropriate field values of the
* configuration registers from the parameters structure, this function is not
* optimal in terms of code size. For a code size optimal solution, it is better
* to create a new function from pcl_configure_clocks_rc120m() and modify it to
* use preprocessor computation from pre-defined target frequencies.
*
* \param param pointer on the configuration structure.
*
* \retval 0 Success.
* \retval <0 The configuration cannot be performed.
*/
extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock
*
* This function needs some parameters stored in a pcl_freq_param_t structure:
* - cpu_f and pba_f and pbb_f are the wanted frequencies,
* - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
* - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
*
* Supported main clock sources: PCL_MC_OSC0
*
* Supported synchronous clocks frequencies:
* (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
* 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
*
* \note: by default, this implementation doesn't perform thorough checks on the
* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
*
* \note: since it is dynamically computing the appropriate field values of the
* configuration registers from the parameters structure, this function is not
* optimal in terms of code size. For a code size optimal solution, it is better
* to create a new function from pcl_configure_clocks_osc0() and modify it to use
* preprocessor computation from pre-defined target frequencies.
*
* \param param pointer on the configuration structure.
*
* \retval 0 Success.
* \retval <0 The configuration cannot be performed.
*/
extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock
*
* This function needs some parameters stored in a pcl_freq_param_t structure:
* - cpu_f and pba_f and pbb_f are the wanted frequencies,
* - dfll_f is the target DFLL frequency to set-up
*
* \note: when the DFLL0 is to be used as main source clock for the synchronous clocks,
* the target frequency of the DFLL should be chosen to be as high as possible
* within the specification range (for stability reasons); the target cpu and pbx
* frequencies will then be reached by appropriate division ratio.
*
* Supported main clock sources: PCL_MC_DFLL0
*
* Supported synchronous clocks frequencies:
* (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
* 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
*
* \note: by default, this implementation doesn't perform thorough checks on the
* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
*
* \note: since it is dynamically computing the appropriate field values of the
* configuration registers from the parameters structure, this function is not
* optimal in terms of code size. For a code size optimal solution, it is better
* to create a new function from pcl_configure_clocks_dfll0() and modify it to
* use preprocessor computation from pre-defined target frequencies.
*
* \param param pointer on the configuration structure.
*
* \retval 0 Success.
* \retval <0 The configuration cannot be performed.
*/
extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param);
/*! \brief Switch the main clock source to Osc0 configured in crystal mode
*
* \param osc The oscillator to enable and switch to.
* \param fcrystal Oscillator external crystal frequency (Hz)
* \param startup Oscillator startup time.
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup);
/*! \brief Enable the clock of a module.
*
* \param module The module to clock (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
* or look in the module section).
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module)
#else
// Implementation for UC3C, UC3L parts.
#define pcl_enable_module(module) pm_enable_module(module)
#endif
/*! \brief Disable the clock of a module.
*
* \param module The module to shut down (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
* or look in the module section).
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
#define pcl_disable_module(module) pm_disable_module(&AVR32_PM, module)
#else
// Implementation for UC3C, UC3L parts.
#define pcl_disable_module(module) pm_disable_module(module)
#endif
/*! \brief Configure the USB Clock
*
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long int pcl_configure_usb_clock(void);
//! @}
/*! \name Power Management
*/
//! @{
/*!
* \brief Read the content of the GPLP registers
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
*
* \return The content of the chosen GPLP register.
*/
extern unsigned long pcl_read_gplp(unsigned long gplp);
/*!
* \brief Write into the GPLP registers
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
* \param value Value to write
*/
extern void pcl_write_gplp(unsigned long gplp, unsigned long value);
//! @}
#ifdef __cplusplus
}
#endif
#endif // _POWER_CLOCKS_LIB_H_

914
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.c Normal file
View File

File diff suppressed because it is too large Load Diff

889
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.h Normal file
View File

File diff suppressed because it is too large Load Diff

63
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h Normal file
View File

@@ -0,0 +1,63 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief NEWLIB_ADDONS CPU include file for AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef __AVR32_NEWLIB_ADDONS_CPU_H__
#define __AVR32_NEWLIB_ADDONS_CPU_H__
#include <_ansi.h>
_BEGIN_STD_C
#define CPU_HZ get_cpu_hz()
void udelay(unsigned long usec);
void set_cpu_hz(unsigned int clk_hz);
unsigned int get_cpu_hz();
_END_STD_C
#endif

120
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h Normal file
View File

@@ -0,0 +1,120 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief NEWLIB_ADDONS exceptions include file for AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__
#define __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__
#include <_ansi.h>
_BEGIN_STD_C
/*
Exception vector offsets
*/
#define EVBA_UNRECOVERABLE 0x000
#define EVBA_TLB_MULTIPLE 0x004
#define EVBA_BUS_ERROR_DATA 0x008
#define EVBA_BUS_ERROR_INSTR 0x00C
#define EVBA_NMI 0x010
#define EVBA_INSTR_ADDR 0x014
#define EVBA_ITLB_MISS 0x050
#define EVBA_ITLB_PROT 0x018
#define EVBA_BREAKPOINT 0x01C
#define EVBA_ILLEGAL_OPCODE 0x020
#define EVBA_UNIMPLEMENTED 0x024
#define EVBA_PRIVILEGE_VIOL 0x028
#define EVBA_FLOATING_POINT 0x02C
#define EVBA_COP_ABSENT 0x030
#define EVBA_SCALL 0x100
#define EVBA_DATA_ADDR_R 0x034
#define EVBA_DATA_ADDR_W 0x038
#define EVBA_DTLB_MISS_R 0x060
#define EVBA_DTLB_MISS_W 0x070
#define EVBA_DTLB_PROT_R 0x03C
#define EVBA_DTLB_PROT_W 0x040
#define EVBA_DTLB_MODIFIED 0x044
/*
Define the form of the function used when registering exceptions.
The function should return the address which the exception should
return to after the exception processing.
*/
typedef unsigned int (*__exception_handler)(int /*evba_offset*/, int /*return address*/);
/*
Define the form of the function used when registering a scall handler.
*/
typedef void (*__scall_handler)(int /*code*/, int /*p1*/, int /*p2*/
, int /*p3*/, int /*p4*/);
/*
Function for registering an exception handler for the exception with
offset given by evba_offset.
*/
void _register_exception_handler(__exception_handler handler, int evba_offset);
/*
Function for registering a scall handler which can be a arbirary
function which uses r8-r12 for parameters.
*/
void _register_scall_handler(__scall_handler handler);
/*
Initialize exceptions. Must be called before registering exception handlers
and needed to enable exceptions. 'evba' is the pointer to the exception
vector. 'handler_table' is a pointer to an array where the pointers to
the exception handlers are stored. This array must be at least 0x104 bytes
and word aligned.
*/
void init_exceptions(void *evba, void *handler_table);
_END_STD_C
#endif

82
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h Normal file
View File

@@ -0,0 +1,82 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief NEWLIB_ADDONS interrupts include file for AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__
#define __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__
#include <_ansi.h>
_BEGIN_STD_C
#define INT_GRPS 64
#define INT_LINES 32
#define INTPR_BASE (__intc_base__ + 0x0000)
#define INTREQ_BASE (__intc_base__ + 64*4)
#define INTCAUSE_BASE (__intc_base__ + 2*64*4)
//Register offsets
#define INTLEVEL 30
#define AUTOVECTOR 0
#define AUTOVECTOR_BITS 14
//Priorities
#define INT0 0
#define INT1 1
#define INT2 2
#define INT3 3
typedef void (*__newlib_int_handler)(int /* int_grp*/, void */*user_handle*/);
__newlib_int_handler register_interrupt(__newlib_int_handler handler, int int_grp, int line, int priority,
.../* void *user_handle*/);
void init_interrupts();
void set_interrupts_base(void *base);
_END_STD_C
#endif

174
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h Normal file
View File

@@ -0,0 +1,174 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief NEWLIB_ADDONS miscellaneous macros include file for AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef __AVR32_NEWLIB_ADDONS_IO_H__
#define __AVR32_NEWLIB_ADDONS_IO_H__
#include <_ansi.h>
_BEGIN_STD_C
typedef char u8;
typedef unsigned int u32;
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
#define writeb(v,a) __raw_writeb(v,a)
#define writew(v,a) __raw_writew(v,a)
#define writel(v,a) __raw_writel(v,a)
#define readb(a) __raw_readb(a)
#define readw(a) __raw_readw(a)
#define readl(a) __raw_readl(a)
/* Memory segments when segmentation is enabled */
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
/* Returns the privileged segment base of a given address */
#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
/* Returns the physical address of a PnSEG (n=1,2) address */
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
/*
* Map an address to a certain privileged segment
*/
#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
#define cached(addr) P1SEGADDR(addr)
#define uncached(addr) P2SEGADDR(addr)
#define physaddr(addr) PHYSADDR(addr)
#define BF(field, value) \
({ union { \
struct { \
unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \
unsigned long __val: field ## _SIZE ; \
}; \
unsigned long __ul; \
} __tmp; \
__tmp.__ul = 0; \
__tmp.__val = value; \
__tmp.__ul;})
#define BF_D(field, value) \
({ union { \
struct { \
unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \
unsigned long long __val: field ## _SIZE ; \
}; \
unsigned long long __ul; \
} __tmp; \
__tmp.__ul = 0; \
__tmp.__val = value; \
__tmp.__ul;})
#define BFINS(var, field, value) \
{ union {\
struct { \
unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \
unsigned long __val: field ## _SIZE ; \
}; \
unsigned long __ul; \
} __tmp; \
__tmp.__ul = var; \
__tmp.__val = value; \
var = __tmp.__ul;}
#define BFEXT(var, field) \
({ union {\
struct { \
unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \
unsigned long __val: field ## _SIZE ; \
}; \
unsigned long __ul; \
} __tmp; \
__tmp.__ul = var; \
__tmp.__val; })
#define BFINS_D(var, field, value) \
{ union {\
struct { \
unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \
unsigned long long __val: field ## _SIZE ; \
}; \
unsigned long long __ul; \
} __tmp; \
__tmp.__ul = var; \
__tmp.__val = value; \
var = __tmp.__ul;}
#define BFEXT_D(var, field) \
({ union {\
struct { \
unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \
unsigned long long __val: field ## _SIZE ; \
}; \
unsigned long long __ul; \
} __tmp; \
__tmp.__ul = var; \
__tmp.__val; })
_END_STD_C
#endif

208
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h Normal file
View File

@@ -0,0 +1,208 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief NEWLIB_ADDONS USART include file for AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef __AVR32_NEWLIB_ADDONS_USART_H__
#define __AVR32_NEWLIB_ADDONS_USART_H__
#include <_ansi.h>
#include "nlao_io.h"
_BEGIN_STD_C
struct usart3 {
volatile u32 us_cr;
volatile u32 us_mr;
volatile u32 us_ier;
volatile u32 us_idr;
volatile u32 us_imr;
volatile u32 us_csr;
volatile u32 us_rhr;
volatile u32 us_thr;
volatile u32 us_brgr;
volatile u32 us_rtor;
volatile u32 us_ttgr;
volatile u32 us_reserved[5];
volatile u32 us_fidi;
volatile u32 us_ner;
volatile u32 us_xxr;
volatile u32 us_if;
};
/* Register offsets */
#define US_CR 0x0000
#define US_MR 0x0004
#define US_IER 0x0008
#define US_IDR 0x000c
#define US_IMR 0x0010
#define US_CSR 0x0014
#define US_RHR 0x0018
#define US_THR 0x001c
#define US_BRGR 0x0020
#define US_RTOR 0x0024
#define US_TTGR 0x0028
#define US_FIDI 0x0040
#define US_NER 0x0044
#define US_XXR 0x0048
#define US_IF 0x004c
#define US_RPR 0x0100
#define US_RCR 0x0104
#define US_TPR 0x0108
#define US_TCR 0x010c
#define US_RNPR 0x0110
#define US_RNCR 0x0114
#define US_TNPR 0x0118
#define US_TNCR 0x011c
#define US_PTCR 0x0120
#define US_PTSR 0x0124
/* USART3 Control Register */
#define US_CR_RSTRX (1 << 2)
#define US_CR_RSTTX (1 << 3)
#define US_CR_RXEN (1 << 4)
#define US_CR_RXDIS (1 << 5)
#define US_CR_TXEN (1 << 6)
#define US_CR_TXDIS (1 << 7)
#define US_CR_RSTSTA (1 << 8)
#define US_CR_STTBRK (1 << 9)
#define US_CR_STPBRK (1 << 10)
#define US_CR_DTREN (1 << 16)
#define US_CR_DTRDIS (1 << 17)
#define US_CR_RTSEN (1 << 18)
#define US_CR_RTSDIS (1 << 19)
/* USART3 Mode Register */
#define US_MR_MODE (15 << 0)
#define US_MR_MODE_NORMAL ( 0 << 0)
#define US_MR_MODE_HWFLOW ( 2 << 0)
#define US_MR_CLKS ( 3 << 4)
#define US_MR_CLKS_CLOCK ( 0 << 4)
#define US_MR_CLKS_FDIV1 ( 1 << 4)
#define US_MR_CLKS_SLOW ( 2 << 4)
#define US_MR_CLKS_EXT ( 3 << 4)
#define US_MR_CHRL_5BITS ( 0 << 6)
#define US_MR_CHRL_6BITS ( 1 << 6)
#define US_MR_CHRL_7BITS ( 2 << 6)
#define US_MR_CHRL_8BITS ( 3 << 6)
#define US_MR_SYNC ( 1 << 8)
#define US_MR_PAR_EVEN ( 0 << 9)
#define US_MR_PAR_ODD ( 1 << 9)
#define US_MR_PAR_SPACE ( 2 << 9)
#define US_MR_PAR_MARK ( 3 << 9)
#define US_MR_PAR_NONE ( 4 << 9)
#define US_MR_PAR_MDROP ( 6 << 9)
#define US_MR_NBSTOP_1BIT ( 0 << 12)
#define US_MR_NBSTOP_1_5BIT ( 1 << 12)
#define US_MR_NBSTOP_2BITS ( 2 << 12)
#define US_MR_OVER ( 1 << 19)
#define US_MR_OVER_X16 ( 0 << 19)
#define US_MR_OVER_X8 ( 1 << 19)
/* USART3 Channel Status Register */
#define US_CSR_RXRDY (1 << 0)
#define US_CSR_TXRDY (1 << 1)
#define US_CSR_RXBRK (1 << 2)
#define US_CSR_ENDRX (1 << 3)
#define US_CSR_ENDTX (1 << 4)
#define US_CSR_OVRE (1 << 5)
#define US_CSR_FRAME (1 << 6)
#define US_CSR_PARE (1 << 7)
#define US_CSR_TXEMPTY (1 << 9)
#define US_CSR_TXBUFE (1 << 11)
#define US_CSR_RXBUFF (1 << 12)
#define US_CSR_RIIC (1 << 16)
#define US_CSR_DSRIC (1 << 17)
#define US_CSR_DCDIC (1 << 18)
#define US_CSR_CTSIC (1 << 19)
#define US_CSR_RI (1 << 20)
#define US_CSR_DSR (1 << 21)
#define US_CSR_DCD (1 << 22)
#define US_CSR_CTS (1 << 23)
/* USART3 Baud Rate Generator Register */
#define US_BRGR_CD_OFFSET 0
#define US_BRGR_FP_OFFSET 16
#define US_BRGR_CD_SIZE 16
#define US_BRGR_FP_SIZE 3
#define US_BRGR_CD (0xFFFF << 0)
#define US_BRGR_FP ( 7 << 16)
/*USART3 PDC Transfer Control Register */
#define US_PTCR_RXTEN (1 << 0)
#define US_PTCR_RXTDIS (1 << 1)
#define US_PTCR_TXTEN (1 << 8)
#define US_PTCR_TXTDIS (1 << 9)
/*USART3 PDC Transfer Status Register */
#define US_PTSR_RXTEN (1 << 0)
#define US_PTSR_TXTEN (1 << 8)
int usart_init(int baudrate);
void usart_putc(char c);
void usart_puts(const char *s);
int usart_getc(void);
int usart_tstc(void);
void usart_setbrg(int baudrate, int cpu_clock);
void set_usart_base(void *usart_base);
_END_STD_C
#endif /* MERLIN_USART3_H */

328
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h Normal file
View File

@@ -0,0 +1,328 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor macro repeating utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _MREPEAT_H_
#define _MREPEAT_H_
#include "preprocessor.h"
//! Maximal number of repetitions supported by MREPEAT.
#define MREPEAT_LIMIT 256
/*! \brief Macro repeat.
*
* This macro represents a horizontal repetition construct.
*
* \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
* \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
* the current repetition number and the auxiliary data argument.
* \param data Auxiliary data passed to macro.
*
* \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
*/
#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
#define MREPEAT0( macro, data)
#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
#endif // _MREPEAT_H_

55
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h Normal file
View File

@@ -0,0 +1,55 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_
#include "tpaste.h"
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_

75
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h Normal file
View File

@@ -0,0 +1,75 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor stringizing utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_
/*! \brief Stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* May be used only within macros with the token passed as an argument if the token is \#defined.
*
* For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
* and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
* writing "A0".
*/
#define STRINGZ(x) #x
/*! \brief Absolute stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* No restriction of use if the token is \#defined.
*
* For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
* equivalent to writing "A0".
*/
#define ASTRINGZ(x) STRINGZ(x)
#endif // _STRINGZ_H_

95
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h Normal file
View File

@@ -0,0 +1,95 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor token pasting utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _TPASTE_H_
#define _TPASTE_H_
/*! \name Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
*
* For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
* UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
* equivalent to writing U32.
*/
//! @{
#define TPASTE2( a, b) a##b
#define TPASTE3( a, b, c) a##b##c
#define TPASTE4( a, b, c, d) a##b##c##d
#define TPASTE5( a, b, c, d, e) a##b##c##d##e
#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
//! @}
/*! \name Absolute Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* No restriction of use if the tokens are \#defined.
*
* For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
* as 32 is equivalent to writing U32.
*/
//! @{
#define ATPASTE2( a, b) TPASTE2( a, b)
#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
//! @}
#endif // _TPASTE_H_

1145
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/compiler.h Normal file
View File

File diff suppressed because it is too large Load Diff

203
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/parts.h Normal file
View File

@@ -0,0 +1,203 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Arch file for AVR32.
*
* This file defines common AVR32 UC3 series.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _ARCH_H_
#define _ARCH_H_
// UC3 A Series
#define UC3A0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A0128__) || \
defined (__AVR32_UC3A0256__) || \
defined (__AVR32_UC3A0512__) || \
defined (__AVR32_UC3A0512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A0128__) || \
defined (__AT32UC3A0256__) || \
defined (__AT32UC3A0512__) || \
defined (__AT32UC3A0512ES__)))
#define UC3A1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A1128__) || \
defined (__AVR32_UC3A1256__) || \
defined (__AVR32_UC3A1512__) || \
defined (__AVR32_UC3A1512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A1128__) || \
defined (__AT32UC3A1256__) || \
defined (__AT32UC3A1512__) || \
defined (__AT32UC3A1512ES__)))
#define UC3A3 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A364__) || \
defined (__AVR32_UC3A364S__) || \
defined (__AVR32_UC3A3128__) || \
defined (__AVR32_UC3A3128S__) || \
defined (__AVR32_UC3A3256__) || \
defined (__AVR32_UC3A3256S__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A364__) || \
defined (__AT32UC3A364S__) || \
defined (__AT32UC3A3128__) || \
defined (__AT32UC3A3128S__) || \
defined (__AT32UC3A3256__) || \
defined (__AT32UC3A3256S__)))
#define UC3A (UC3A0 || UC3A1 || UC3A3)
// UC3 B Series
#define UC3B0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3B064__) || \
defined (__AVR32_UC3B0128__) || \
defined (__AVR32_UC3B0256__) || \
defined (__AVR32_UC3B0256ES__) || \
defined (__AVR32_UC3B0512__) || \
defined (__AVR32_UC3B0512REVC_))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3B064__) || \
defined (__AT32UC3B0128__) || \
defined (__AT32UC3B0256__) || \
defined (__AT32UC3B0256ES__) || \
defined (__AT32UC3B0512__) || \
defined (__AT32UC3B0512REVC__)))
#define UC3B1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3B164__) || \
defined (__AVR32_UC3B1128__) || \
defined (__AVR32_UC3B1256__) || \
defined (__AVR32_UC3B1256ES__) || \
defined (__AVR32_UC3B1512__) || \
defined (__AVR32_UC3B1512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3B164__) || \
defined (__AT32UC3B1128__) || \
defined (__AT32UC3B1256__) || \
defined (__AT32UC3B1256ES__) || \
defined (__AT32UC3B1512__) || \
defined (__AT32UC3B1512REVC__)))
#define UC3B (UC3B0 || UC3B1 )
// UC3 C Series
#define UC3C0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C064C__) || \
defined (__AVR32_UC3C0128C__) || \
defined (__AVR32_UC3C0256C__) || \
defined (__AVR32_UC3C0512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C064C__) || \
defined (__AT32UC3C0128C__) || \
defined (__AT32UC3C0256C__) || \
defined (__AT32UC3C0512C__)))
#define UC3C1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C164C__) || \
defined (__AVR32_UC3C1128C__) || \
defined (__AVR32_UC3C1256C__) || \
defined (__AVR32_UC3C1512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C164C__) || \
defined (__AT32UC3C1128C__) || \
defined (__AT32UC3C1256C__) || \
defined (__AT32UC3C1512C__)))
#define UC3C2 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C264C__) || \
defined (__AVR32_UC3C2128C__) || \
defined (__AVR32_UC3C2256C__) || \
defined (__AVR32_UC3C2512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C264C__) || \
defined (__AT32UC3C2128C__) || \
defined (__AT32UC3C2256C__) || \
defined (__AT32UC3C2512C__)))
#define UC3C (UC3C0 || UC3C1 || UC3C2)
// UC3 L Device series
#define UC3L0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L016__) || \
defined (__AVR32_UC3L032__) || \
defined (__AVR32_UC3L064__) || \
defined (__AVR32_UC3L064REVB__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L016__) || \
defined (__AT32UC3L032__) || \
defined (__AT32UC3L064__) || \
defined (__AT32UC3L064REVB__)))
#define UC3L1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L116__) || \
defined (__AVR32_UC3L132__) || \
defined (__AVR32_UC3L164__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L116__) || \
defined (__AT32UC3L132__) || \
defined (__AT32UC3L164__)))
#define UC3L2 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L216__) || \
defined (__AVR32_UC3L232__) || \
defined (__AVR32_UC3L264__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L216__) || \
defined (__AT32UC3L232__) || \
defined (__AT32UC3L264__)))
#define UC3L3 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L316__) || \
defined (__AVR32_UC3L332__) || \
defined (__AVR32_UC3L364__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L316__) || \
defined (__AT32UC3L332__) || \
defined (__AT32UC3L364__)))
#define UC3L (UC3L0 || UC3L1 || UC3L2 || UC3L3)
#endif // _ARCH_H_

6
bsp/avr32uc3b0/application.c
View File

@@ -25,12 +25,12 @@ static void rt_thread_entry_led1(void* parameter)
/* led on */
rt_kprintf("LED1 on\r\n");
gpio_tgl_gpio_pin(AVR32_PIN_PA08);
rt_thread_delay(50); /* sleep 0.5 second and switch to other thread */
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
/* led off */
rt_kprintf("LED1 off\r\n");
gpio_tgl_gpio_pin(AVR32_PIN_PA08);
rt_thread_delay(50);
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
@@ -41,7 +41,7 @@ void rt_thread_entry_led2(void* parameter)
while (1)
{
/* led on */
rt_kprintf("LED2 on, count = %d\r\n", count);
rt_kprintf("LED2 on");
gpio_tgl_gpio_pin(AVR32_PIN_PA07);
rt_thread_delay(RT_TICK_PER_SECOND);

1
bsp/avr32uc3b0/rtconfig.h
View File

@@ -72,6 +72,7 @@
/* SECTION: Console options */
/* the buffer size of console*/
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */

2
libcpu/avr32/uc3/exception.x
View File

@@ -71,7 +71,7 @@
// Export symbol.
.global _evba
.type _evba, @function
_evba:
_evba:
.org 0x000
// Unrecoverable Exception.

1
libcpu/avr32/uc3/serial.c
View File

@@ -19,7 +19,6 @@
#include "serial.h"
#include "compiler.h"
#include "usart.h"
#include "pdca.h"
struct rt_device _rt_usart_device;
struct avr32_serial_int_rx _rt_usart_rx;