[hc32] Add the ev_hc32f4a8_lqfp176 board and modify some bsp drivers. (#10233)

* [hc32] Add the ev_hc32f4a8_lqfp176 board and modify some bsp drivers.
2026-10-02 14:23:19 +08:00 · 2025-04-29 14:23:01 +08:00
parent 396eaa32f6
commit 928e47395d
110 changed files with 22724 additions and 763 deletions
@@ -53,6 +53,7 @@
        "at32/at32m412-start",
        "at32/at32m416-start",
        "hc32/ev_hc32f4a0_lqfp176",
+        "hc32/ev_hc32f4a8_lqfp176",
        "hc32/ev_hc32f448_lqfp80",
        "hc32/ev_hc32f460_lqfp100_v2",
        "hc32/ev_hc32f472_lqfp100",
@@ -20,8 +20,8 @@
 extern "C" {
 #endif

-
-#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (4)
 #define HC32_FLASH_SIZE                 (256 * 1024)
 #define HC32_FLASH_START_ADDRESS        (0)
 #define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
@@ -157,7 +157,7 @@ void CanPhyEnable(void)
    TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
 #endif
 }
-rt_err_t rt_hw_board_can_init(CM_MCAN_TypeDef *MCANx)
+rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
 {
    rt_err_t result = RT_EOK;

@@ -9,8 +9,8 @@
 * 2024-02-20     CDT          first version
 */

-#ifndef __CAN_CONFIG_H__
-#define __CAN_CONFIG_H__
+#ifndef __MCAN_CONFIG_H__
+#define __MCAN_CONFIG_H__

 #include <rtthread.h>
 #include "irq_config.h"
@@ -21,16 +21,6 @@ extern "C" {

 /***********************************************************************************************/
 /***********************************************************************************************/
-// The arguments of RT command RT_CAN_CMD_SET_CANFD
-#define MCAN_FD_CLASSICAL                   0       /* CAN classical */
-#define MCAN_FD_ISO_FD_NO_BRS               1       /* ISO CAN FD without BRS */
-#define MCAN_FD_ISO_FD_BRS                  2       /* ISO CAN FD with BRS */
-#define MCAN_FD_NON_ISO_FD_NO_BRS           3       /* non-ISO CAN FD without BRS */
-#define MCAN_FD_NON_ISO_FD_BRS              4       /* non-ISO CAN FD with BRS */
-
-#define MCAN_FD_ARG_MIN                     MCAN_FD_ISO_FD_NO_BRS
-#define MCAN_FD_ARG_MAX                     MCAN_FD_NON_ISO_FD_BRS
-
 /* The default configuration for MCANs. Users can modify the configurations based on the application.
   For the message RAM:
   1. MCAN1 and MCAN2 share 2048 bytes message RAM
@@ -59,7 +49,7 @@ extern "C" {
 #endif

 #ifdef BSP_USING_MCAN1
-#define MCAN1_NAME                      ("can1")
+#define MCAN1_NAME                      ("mcan1")
 #define MCAN1_WORK_MODE                 (RT_CAN_MODE_NORMAL)
 #define MCAN1_TX_PRIV_MODE              RT_CAN_MODE_NOPRIV      /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */

@@ -77,7 +67,7 @@ extern "C" {
 #endif /* BSP_USING_MCAN1 */

 #ifdef BSP_USING_MCAN2
-#define MCAN2_NAME                      ("can2")
+#define MCAN2_NAME                      ("mcan2")
 #define MCAN2_WORK_MODE                 (RT_CAN_MODE_NORMAL)
 #define MCAN2_TX_PRIV_MODE              RT_CAN_MODE_NOPRIV      /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */

@@ -234,9 +224,9 @@ extern "C" {
 #define MCAN_FD_CFG_1M_5M                                   \
    {                                                       \
    .u32NominalPrescaler = 1,                               \
-    .u32NominalTimeSeg1 = 64,                               \
-    .u32NominalTimeSeg2 = 16,                               \
-    .u32NominalSyncJumpWidth = 16,                          \
+    .u32NominalTimeSeg1 = 32,                               \
+    .u32NominalTimeSeg2 = 8,                                \
+    .u32NominalSyncJumpWidth = 8,                           \
    .u32DataPrescaler = 1,                                  \
    .u32DataTimeSeg1 = 6,                                   \
    .u32DataTimeSeg2 = 2,                                   \
@@ -249,9 +239,9 @@ extern "C" {
 #define MCAN_FD_CFG_1M_8M                                   \
    {                                                       \
    .u32NominalPrescaler = 1,                               \
-    .u32NominalTimeSeg1 = 64,                               \
-    .u32NominalTimeSeg2 = 16,                               \
-    .u32NominalSyncJumpWidth = 16,                          \
+    .u32NominalTimeSeg1 = 32,                               \
+    .u32NominalTimeSeg2 = 8,                                \
+    .u32NominalSyncJumpWidth = 8,                           \
    .u32DataPrescaler = 1,                                  \
    .u32DataTimeSeg1 = 4,                                   \
    .u32DataTimeSeg2 = 1,                                   \
@@ -344,12 +334,12 @@ extern "C" {

 #ifdef RT_CAN_USING_CANFD
 #define MCAN1_BAUD_RATE_CFG             MCAN_FD_CFG_1M_4M
-#define MCAN1_NOMINAL_BAUD_RATE         MCANFD_NOMINAL_BAUD_1M
-#define MCAN1_DATA_BAUD_RATE            MCANFD_DATA_BAUD_4M
+#define MCAN1_NOMINAL_BAUD_RATE         CANFD_DATA_BAUD_1M
+#define MCAN1_DATA_BAUD_RATE            CANFD_DATA_BAUD_4M

 #define MCAN2_BAUD_RATE_CFG             MCAN_FD_CFG_1M_4M
-#define MCAN2_NOMINAL_BAUD_RATE         MCANFD_NOMINAL_BAUD_1M
-#define MCAN2_DATA_BAUD_RATE            MCANFD_DATA_BAUD_4M
+#define MCAN2_NOMINAL_BAUD_RATE         CANFD_DATA_BAUD_1M
+#define MCAN2_DATA_BAUD_RATE            CANFD_DATA_BAUD_4M

 #else
 #define MCAN1_BAUD_RATE_CFG             MCAN_CC_CFG_1M
@@ -369,6 +359,6 @@ extern "C" {
 }
 #endif

-#endif /* __CAN_CONFIG_H__ */
+#endif /* __MCAN_CONFIG_H__ */


@@ -195,181 +195,6 @@ extern "C" {
 #endif /* SPI3_RX_DMA_CONFIG */
 #endif /* BSP_SPI3_RX_USING_DMA */

-#ifdef BSP_USING_SPI4
-#ifndef SPI4_BUS_CONFIG
-#define SPI4_BUS_CONFIG                                     \
-    {                                                       \
-        .Instance = CM_SPI4,                                \
-        .bus_name = "spi4",                                 \
-        .clock    = FCG1_PERIPH_SPI4,                       \
-        .timeout  = 5000UL,                                 \
-        .err_irq.irq_config =                               \
-        {                                                   \
-            .irq_num    = BSP_SPI4_ERR_IRQ_NUM,             \
-            .irq_prio   = BSP_SPI4_ERR_IRQ_PRIO,            \
-            .int_src    = INT_SRC_SPI4_SPEI,                \
-        },                                                  \
-    }
-#endif /* SPI4_BUS_CONFIG */
-#endif /* BSP_USING_SPI4 */
-
-#ifdef BSP_SPI4_TX_USING_DMA
-#ifndef SPI4_TX_DMA_CONFIG
-#define SPI4_TX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI4_TX_DMA_INSTANCE,             \
-        .channel        = SPI4_TX_DMA_CHANNEL,              \
-        .clock          = SPI4_TX_DMA_CLOCK,                \
-        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
-        .flag           = SPI4_TX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI4_TX_DMA_IRQn,                 \
-            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
-            .int_src    = SPI4_TX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI4_TX_DMA_CONFIG */
-#endif /* BSP_SPI4_TX_USING_DMA */
-
-#ifdef BSP_SPI4_RX_USING_DMA
-#ifndef SPI4_RX_DMA_CONFIG
-#define SPI4_RX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI4_RX_DMA_INSTANCE,             \
-        .channel        = SPI4_RX_DMA_CHANNEL,              \
-        .clock          = SPI4_RX_DMA_CLOCK,                \
-        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
-        .flag           = SPI4_RX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI4_RX_DMA_IRQn,                 \
-            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
-            .int_src    = SPI4_RX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI4_RX_DMA_CONFIG */
-#endif /* BSP_SPI4_RX_USING_DMA */
-
-#ifdef BSP_USING_SPI5
-#ifndef SPI5_BUS_CONFIG
-#define SPI5_BUS_CONFIG                                     \
-    {                                                       \
-        .Instance = CM_SPI5,                                \
-        .bus_name = "spi5",                                 \
-        .clock    = FCG1_PERIPH_SPI5,                       \
-        .timeout  = 5000UL,                                 \
-        .err_irq.irq_config =                               \
-        {                                                   \
-            .irq_num    = BSP_SPI5_ERR_IRQ_NUM,             \
-            .irq_prio   = BSP_SPI5_ERR_IRQ_PRIO,            \
-            .int_src    = INT_SRC_SPI5_SPEI,                \
-        },                                                  \
-    }
-#endif /* SPI5_BUS_CONFIG */
-#endif /* BSP_USING_SPI5 */
-
-#ifdef BSP_SPI5_TX_USING_DMA
-#ifndef SPI5_TX_DMA_CONFIG
-#define SPI5_TX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI5_TX_DMA_INSTANCE,             \
-        .channel        = SPI5_TX_DMA_CHANNEL,              \
-        .clock          = SPI5_TX_DMA_CLOCK,                \
-        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
-        .flag           = SPI5_TX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI5_TX_DMA_IRQn,                 \
-            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
-            .int_src    = SPI5_TX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI5_TX_DMA_CONFIG */
-#endif /* BSP_SPI5_TX_USING_DMA */
-
-#ifdef BSP_SPI5_RX_USING_DMA
-#ifndef SPI5_RX_DMA_CONFIG
-#define SPI5_RX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI5_RX_DMA_INSTANCE,             \
-        .channel        = SPI5_RX_DMA_CHANNEL,              \
-        .clock          = SPI5_RX_DMA_CLOCK,                \
-        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
-        .flag           = SPI5_RX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI5_RX_DMA_IRQn,                 \
-            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
-            .int_src    = SPI5_RX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI5_RX_DMA_CONFIG */
-#endif /* BSP_SPI5_RX_USING_DMA */
-
-#ifdef BSP_USING_SPI6
-#ifndef SPI6_BUS_CONFIG
-#define SPI6_BUS_CONFIG                                     \
-    {                                                       \
-        .Instance = CM_SPI6,                                \
-        .bus_name = "spi6",                                 \
-        .clock    = FCG1_PERIPH_SPI6,                       \
-        .timeout  = 5000UL,                                 \
-        .err_irq.irq_config =                               \
-        {                                                   \
-            .irq_num    = BSP_SPI6_ERR_IRQ_NUM,             \
-            .irq_prio   = BSP_SPI6_ERR_IRQ_PRIO,            \
-            .int_src    = INT_SRC_SPI6_SPEI,                \
-        },                                                  \
-    }
-#endif /* SPI6_BUS_CONFIG */
-#endif /* BSP_USING_SPI6 */
-
-#ifdef BSP_SPI6_TX_USING_DMA
-#ifndef SPI6_TX_DMA_CONFIG
-#define SPI6_TX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI6_TX_DMA_INSTANCE,             \
-        .channel        = SPI6_TX_DMA_CHANNEL,              \
-        .clock          = SPI6_TX_DMA_CLOCK,                \
-        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
-        .flag           = SPI6_TX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI6_TX_DMA_IRQn,                 \
-            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
-            .int_src    = SPI6_TX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI6_TX_DMA_CONFIG */
-#endif /* BSP_SPI6_TX_USING_DMA */
-
-#ifdef BSP_SPI6_RX_USING_DMA
-#ifndef SPI6_RX_DMA_CONFIG
-#define SPI6_RX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI6_RX_DMA_INSTANCE,             \
-        .channel        = SPI6_RX_DMA_CHANNEL,              \
-        .clock          = SPI6_RX_DMA_CLOCK,                \
-        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
-        .flag           = SPI6_RX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI6_RX_DMA_IRQn,                 \
-            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
-            .int_src    = SPI6_RX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI6_RX_DMA_CONFIG */
-#endif /* BSP_SPI6_RX_USING_DMA */
-
-
 #ifdef __cplusplus
 }
 #endif
@@ -24,7 +24,7 @@ extern "C" {
 #include "adc_config.h"
 #include "dac_config.h"
 #include "gpio_config.h"
-#include "can_config.h"
+#include "mcan_config.h"
 #include "pm_config.h"
 #include "i2c_config.h"
 #include "qspi_config.h"
@@ -20,7 +20,8 @@ extern "C" {
 #endif


-#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (4)
 #define HC32_FLASH_SIZE                 (512 * 1024)
 #define HC32_FLASH_START_ADDRESS        (0)
 #define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
@@ -21,7 +21,8 @@ extern "C" {
 #endif


-#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (4)
 #define HC32_FLASH_SIZE                 (512 * 1024)
 #define HC32_FLASH_START_ADDRESS        (0)
 #define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
@@ -20,9 +20,6 @@ extern "C" {

 #ifdef BSP_USING_CAN1
 #define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
-#ifdef RT_CAN_USING_CANFD
-#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
-#endif
 #define CAN1_NAME                       ("can1")
 #ifndef CAN1_INIT_PARAMS
 #define CAN1_INIT_PARAMS                                    \
@@ -35,9 +32,6 @@ extern "C" {

 #ifdef BSP_USING_CAN2
 #define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
-#ifdef RT_CAN_USING_CANFD
-#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
-#endif
 #define CAN2_NAME                       ("can2")
 #ifndef CAN2_INIT_PARAMS
 #define CAN2_INIT_PARAMS                                    \
@@ -50,9 +44,6 @@ extern "C" {

 #ifdef BSP_USING_CAN3
 #define CAN3_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
-#ifdef RT_CAN_USING_CANFD
-#define CAN3_CANFD_MODE                 (CAN_FD_MD_ISO)
-#endif
 #define CAN3_NAME                       ("can3")
 #ifndef CAN3_INIT_PARAMS
 #define CAN3_INIT_PARAMS                                    \
@@ -253,123 +253,6 @@ extern "C" {
 #endif /* SPI4_RX_DMA_CONFIG */
 #endif /* BSP_SPI4_RX_USING_DMA */

-#ifdef BSP_USING_SPI5
-#ifndef SPI5_BUS_CONFIG
-#define SPI5_BUS_CONFIG                                     \
-    {                                                       \
-        .Instance = CM_SPI5,                                \
-        .bus_name = "spi5",                                 \
-        .clock    = FCG1_PERIPH_SPI5,                       \
-        .timeout  = 5000UL,                                 \
-        .err_irq.irq_config =                               \
-        {                                                   \
-            .irq_num    = BSP_SPI5_ERR_IRQ_NUM,             \
-            .irq_prio   = BSP_SPI5_ERR_IRQ_PRIO,            \
-            .int_src    = INT_SRC_SPI5_SPEI,                \
-        },                                                  \
-    }
-#endif /* SPI5_BUS_CONFIG */
-#endif /* BSP_USING_SPI5 */
-
-#ifdef BSP_SPI5_TX_USING_DMA
-#ifndef SPI5_TX_DMA_CONFIG
-#define SPI5_TX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI5_TX_DMA_INSTANCE,             \
-        .channel        = SPI5_TX_DMA_CHANNEL,              \
-        .clock          = SPI5_TX_DMA_CLOCK,                \
-        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
-        .flag           = SPI5_TX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI5_TX_DMA_IRQn,                 \
-            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
-            .int_src    = SPI5_TX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI5_TX_DMA_CONFIG */
-#endif /* BSP_SPI5_TX_USING_DMA */
-
-#ifdef BSP_SPI5_RX_USING_DMA
-#ifndef SPI5_RX_DMA_CONFIG
-#define SPI5_RX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI5_RX_DMA_INSTANCE,             \
-        .channel        = SPI5_RX_DMA_CHANNEL,              \
-        .clock          = SPI5_RX_DMA_CLOCK,                \
-        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
-        .flag           = SPI5_RX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI5_RX_DMA_IRQn,                 \
-            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
-            .int_src    = SPI5_RX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI5_RX_DMA_CONFIG */
-#endif /* BSP_SPI5_RX_USING_DMA */
-
-#ifdef BSP_USING_SPI6
-#ifndef SPI6_BUS_CONFIG
-#define SPI6_BUS_CONFIG                                     \
-    {                                                       \
-        .Instance = CM_SPI6,                                \
-        .bus_name = "spi6",                                 \
-        .clock    = FCG1_PERIPH_SPI6,                       \
-        .timeout  = 5000UL,                                 \
-        .err_irq.irq_config =                               \
-        {                                                   \
-            .irq_num    = BSP_SPI6_ERR_IRQ_NUM,             \
-            .irq_prio   = BSP_SPI6_ERR_IRQ_PRIO,            \
-            .int_src    = INT_SRC_SPI6_SPEI,                \
-        },                                                  \
-    }
-#endif /* SPI6_BUS_CONFIG */
-#endif /* BSP_USING_SPI6 */
-
-#ifdef BSP_SPI6_TX_USING_DMA
-#ifndef SPI6_TX_DMA_CONFIG
-#define SPI6_TX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI6_TX_DMA_INSTANCE,             \
-        .channel        = SPI6_TX_DMA_CHANNEL,              \
-        .clock          = SPI6_TX_DMA_CLOCK,                \
-        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
-        .flag           = SPI6_TX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI6_TX_DMA_IRQn,                 \
-            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
-            .int_src    = SPI6_TX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI6_TX_DMA_CONFIG */
-#endif /* BSP_SPI6_TX_USING_DMA */
-
-#ifdef BSP_SPI6_RX_USING_DMA
-#ifndef SPI6_RX_DMA_CONFIG
-#define SPI6_RX_DMA_CONFIG                                  \
-    {                                                       \
-        .Instance       = SPI6_RX_DMA_INSTANCE,             \
-        .channel        = SPI6_RX_DMA_CHANNEL,              \
-        .clock          = SPI6_RX_DMA_CLOCK,                \
-        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
-        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
-        .flag           = SPI6_RX_DMA_TRANS_FLAG,           \
-        .irq_config     =                                   \
-        {                                                   \
-            .irq_num    = SPI6_RX_DMA_IRQn,                 \
-            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
-            .int_src    = SPI6_RX_DMA_INT_SRC,              \
-        }                                                   \
-    }
-#endif /* SPI6_RX_DMA_CONFIG */
-#endif /* BSP_SPI6_RX_USING_DMA */
-
-
 #ifdef __cplusplus
 }
 #endif
@@ -20,7 +20,8 @@ extern "C" {
 #endif


-#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (4)
 #define HC32_FLASH_SIZE                 (2 * 1024 * 1024)
 #define HC32_FLASH_START_ADDRESS        (0)
 #define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
@@ -20,9 +20,6 @@ extern "C" {

 #ifdef BSP_USING_CAN1
 #define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
-#ifdef RT_CAN_USING_CANFD
-#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
-#endif
 #define CAN1_NAME                       ("can1")
 #ifndef CAN1_INIT_PARAMS
 #define CAN1_INIT_PARAMS                                    \
@@ -35,9 +32,6 @@ extern "C" {

 #ifdef BSP_USING_CAN2
 #define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
-#ifdef RT_CAN_USING_CANFD
-#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
-#endif
 #define CAN2_NAME                       ("can2")
 #ifndef CAN2_INIT_PARAMS
 #define CAN2_INIT_PARAMS                                    \
@@ -258,6 +258,30 @@ extern "C" {
 #define I2C4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC7
 #endif

+/* DMA1 ch8 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_TX_DMA_INSTANCE            CM_DMA1
+#define SPI5_TX_DMA_CHANNEL             DMA_CH8
+#define SPI5_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI5_TX_DMA_TRIG_SELECT         AOS_DMA1_8
+#define SPI5_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH8
+#define SPI5_TX_DMA_IRQn                BSP_DMA1_CH8_IRQ_NUM
+#define SPI5_TX_DMA_INT_PRIO            BSP_DMA1_CH8_IRQ_PRIO
+#define SPI5_TX_DMA_INT_SRC             INT_SRC_DMA1_TC8
+#endif
+
+/* DMA1 ch9 */
+#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
+#define SPI6_TX_DMA_INSTANCE            CM_DMA1
+#define SPI6_TX_DMA_CHANNEL             DMA_CH9
+#define SPI6_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI6_TX_DMA_TRIG_SELECT         AOS_DMA1_9
+#define SPI6_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH9
+#define SPI6_TX_DMA_IRQn                BSP_DMA1_CH9_IRQ_NUM
+#define SPI6_TX_DMA_INT_PRIO            BSP_DMA1_CH9_IRQ_PRIO
+#define SPI6_TX_DMA_INT_SRC             INT_SRC_DMA1_TC9
+#endif
+
 /* DMA2 ch0 */
 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
 #define UART1_RX_DMA_INSTANCE           CM_DMA2
@@ -74,6 +74,12 @@ extern "C" {
 /* DMA1 ch7 */
 #define BSP_DMA1_CH7_IRQ_NUM            INT019_IRQn
 #define BSP_DMA1_CH7_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch8 */
+#define BSP_DMA1_CH8_IRQ_NUM            INT020_IRQn
+#define BSP_DMA1_CH8_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch9 */
+#define BSP_DMA1_CH9_IRQ_NUM            INT021_IRQn
+#define BSP_DMA1_CH9_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 /* DMA2 ch0 */
 #define BSP_DMA2_CH0_IRQ_NUM            INT044_IRQn
@@ -235,6 +241,16 @@ extern "C" {
 #define BSP_SPI4_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
 #endif

+#if defined(BSP_USING_SPI5)
+#define BSP_SPI5_ERR_IRQ_NUM            INT098_IRQn
+#define BSP_SPI5_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI6)
+#define BSP_SPI6_ERR_IRQ_NUM            INT099_IRQn
+#define BSP_SPI6_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
 #if defined(BSP_USING_UART8)
 #define BSP_UART8_RXERR_IRQ_NUM         INT017_IRQn
 #define BSP_UART8_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/libraries</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/platform</name>
+      <type>2</type>
+      <locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/tests</name>
+      <type>2</type>
+      <locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>
@@ -0,0 +1,12 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+rsource "board/Kconfig"
@@ -0,0 +1,113 @@
+# XHSC EV_F4A8_LQ176 开发板 BSP 说明
+
+## 简介
+
+本文档为小华半导体为 EV_F4A8_LQ176 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+EV_F4A8_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A8SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A8SITB 的芯片性能。
+
+开发板外观如下图所示：
+
+ ![board](figures/board.jpg)
+
+EV_F4A8_LQ176 开发板常用 **板载资源** 如下：
+
+- MCU：HC32F4A8SITB，主频240MHz，2048KB FLASH，512KB RAM
+- 外部RAM：IS62WV51216(SRAM, 1MB) W9825G6KH(SDRAM, 8MB)
+- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 8MB)
+- 常用外设
+  - LED：3 个， user LED(LED0,LED1,LED2)。
+  - 按键：6个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。
+- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口
+- 调试接口：板载DAP调试器、标准JTAG/SWD。
+
+开发板更多详细信息请参考小华半导体半导体[EV_F4A8_LQ176](https://www.xhsc.com.cn)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| USB 转串口    |      支持     |          使用 UART1                  |
+| LED           |     支持     |           LED                        |
+| SDRAM | 支持 | IS42S16400J |
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| CAN           |     支持     |                                       |
+| GPIO          |     支持     | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
+| WDT | 支持 |  |
+| SPI           |     支持     |              SPI1~6                   |
+| SDIO | 支持 |  |
+| UART V1 & V2         |     支持     |              UART1~10                 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用Type-A to MircoUSB线连接开发板和PC供电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。
+
+USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.0 build Apr 24 2022 13:32:39
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+
+## 联系人信息
+
+维护人:
+
+-  [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
@@ -0,0 +1,49 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+def find_keyword_replace(file_path, keyword, replace, split_num, split_char):
+    with open(file_path, 'r', encoding='utf-8') as file:
+        lines = file.readlines()
+
+    for i, line in enumerate(lines):
+        if keyword in line:
+            parts = line.split(split_char)
+            parts[split_num] = replace
+            new_line = split_char.join(parts)
+            lines[i] = new_line
+
+    with open(file_path, 'w', encoding='utf-8') as file:
+        file.writelines(lines)
+
+Import('PACKAGES_PATH')
+replace = PACKAGES_PATH.split("\\")[-1]
+
+if rtconfig.PLATFORM in ['gcc']:
+    file_path = os.path.join(cwd, 'jlink', 'ev_hc32f4a8_lqfp176 Debug.launch')
+    svd_keyword = 'HC32F4A8.svd'
+    split_num = 3
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    file_path = os.path.join(cwd, 'template.uvprojx')
+    svd_keyword = 'HC32F4A8.SFR'
+    split_num = 2
+elif rtconfig.PLATFORM in ['iccarm']:
+    file_path = os.path.join(cwd, 'project.ewd')
+    svd_keyword = 'HC32F4A8.svd'
+    split_num = 3
+    board_keyword = 'FlashHC32F4A8xI.board'
+    find_keyword_replace(file_path, board_keyword, replace, split_num, '/')
+
+find_keyword_replace(file_path, svd_keyword, replace, split_num, '/')
+
+Return('objs')
@@ -0,0 +1,65 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f4a8_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+# include platform
+platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
+objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
+
+# include tests
+test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
+objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED_GREEN pin: PC9 */
+#define LED_GREEN_PIN GET_PIN(C, 9)
+
+
+int main(void)
+{
+    /* set LED_GREEN_PIN pin mode to output */
+    rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-10-27     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+
@@ -0,0 +1,21 @@
+import os
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+path =  [cwd]
+path += [cwd + '/ports']
+path += [cwd + '/config']
+path += [cwd + '/config/usb_config']
+
+CPPDEFINES = ['HC32F4A8', '__DEBUG']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ * 2024-06-11     CDT          remove CLK_Delay for usb, as it is already included in ddl API
+ */
+
+#include "board.h"
+#include "board_config.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
+#define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+    EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+    EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+    EFM_PrefetchCmd(ENABLE);
+#endif
+    /* Reset the VBAT area */
+    PWC_VBAT_Reset();
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    stc_clock_xtal_init_t stcXtalInit;
+    stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    stc_clock_pllx_init_t stcPLLAInit;
+#endif
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif
+
+    /* PCLK0, HCLK  Max 240MHz */
+    /* PCLK1, PCLK4 Max 120MHz */
+    /* PCLK2, PCLK3 Max 60MHz  */
+    /* EX BUS Max 120MHz */
+    CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
+                    (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
+                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | \
+                     CLK_HCLK_DIV1));
+
+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    /* Config Xtal and enable Xtal */
+    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv    = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8State  = CLK_XTAL_ON;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /* VCO = (8/1)*120 = 960MHz*/
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+    /* Highspeed SRAM set to 0 Read/Write wait cycle */
+    SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
+    /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
+    SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
+    /* 0-wait @ 40MHz */
+    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
+    /* 4 cycles for 200 ~ 250MHz */
+    GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
+    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    /* PLLX for USB */
+    (void)CLK_PLLxStructInit(&stcPLLAInit);
+    /* VCO = (8/2)*120 = 480MHz*/
+    stcPLLAInit.u8PLLState = CLK_PLL_ON;
+    stcPLLAInit.PLLCFGR = 0UL;
+    stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    (void)CLK_PLLxInit(&stcPLLAInit);
+#endif
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
+}
+
+/** Peripheral Clock Configuration
+*/
+void PeripheralClock_Config(void)
+{
+#if defined(BSP_USING_CAN1)
+    CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_CAN2)
+    CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(BSP_USING_MCAN1)
+    CLK_SetCANClockSrc(CLK_MCAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_MCAN2)
+    CLK_SetCANClockSrc(CLK_MCAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(RT_USING_ADC)
+    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
+#endif
+}
+
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
+{
+    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+}
+
+/*@}*/
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (16)
+#define HC32_FLASH_SIZE                 (2 * 1024 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
+#define HC32_SRAM_SIZE                  (512)
+#define HC32_SRAM_END                   (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN                      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN                      (&__bss_end)
+#endif
+
+#define HEAP_END                        HC32_SRAM_END
+
+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC1_INIT_PARAMS */
+
+#if defined (BSP_ADC1_USING_DMA)
+#ifndef ADC1_EOCA_DMA_CONFIG
+#define ADC1_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC1_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC1_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC1_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC1_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC1_EOCA,                    \
+        .flag                           = ADC1_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC1_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC1_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC1_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC1_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC1_USING_DMA */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC2_INIT_PARAMS */
+
+#if defined (BSP_ADC2_USING_DMA)
+#ifndef ADC2_EOCA_DMA_CONFIG
+#define ADC2_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC2_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC2_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC2_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC2_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC2_EOCA,                    \
+        .flag                           = ADC2_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC2_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC2_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC2_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC2_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC2_USING_DMA */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_INIT_PARAMS
+#define ADC3_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc3",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC3_INIT_PARAMS */
+#if defined (BSP_ADC3_USING_DMA)
+#ifndef ADC3_EOCA_DMA_CONFIG
+#define ADC3_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC3_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC3_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC3_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC3_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC3_EOCA,                    \
+        .flag                           = ADC3_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC3_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC3_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC3_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC3_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC3_USING_DMA */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#define CAN1_NAME                       ("can1")
+#ifndef CAN1_INIT_PARAMS
+#define CAN1_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN1_INIT_PARAMS */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#define CAN2_NAME                       ("can2")
+#ifndef CAN2_INIT_PARAMS
+#define CAN2_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN2_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN2_INIT_PARAMS */
+#endif /* BSP_USING_CAN2 */
+
+/* Bit time config
+  Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+
+  Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+  TQ = u32Prescaler / CANClock.
+  Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+
+  The following bit time configures are based on CAN Clock 40M
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD                         \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 20,                                  \
+        .u32TimeSeg2 = 5,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 4,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 8,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 16,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 20,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 40,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 100,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 200,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac1",                                 \
+    }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac2",                                 \
+    }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ETH_CONFIG_H__
+#define __ETH_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_ETH)
+
+#ifndef ETH_IRQ_CONFIG
+#define ETH_IRQ_CONFIG                                      \
+    {                                                       \
+        .irq_num    = BSP_ETH_IRQ_NUM,                      \
+        .irq_prio   = BSP_ETH_IRQ_PRIO,                     \
+        .int_src    = INT_SRC_ETH_GLB_INT,                  \
+    }
+#endif /* ETH_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ETH_CONFIG_H__ */
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT0_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT0_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ0,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT1_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT1_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ1,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT2_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT2_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ2,                   \
+    }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT3_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT3_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ3,                   \
+    }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT4_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT4_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ4,                   \
+    }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT5_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT5_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ5,                   \
+    }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT6_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT6_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ6,                   \
+    }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT7_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT7_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ7,                   \
+    }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT8_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT8_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ8,                   \
+    }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT9_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT9_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ9,                   \
+    }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT10_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT10_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ10,                  \
+    }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT11_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT11_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ11,                  \
+    }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT12_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT12_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ12,                  \
+    }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT13_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT13_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ13,                  \
+    }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT14_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT14_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ14,                  \
+    }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT15_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT15_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ15,                  \
+    }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ * 2024-06-13     CDT          disable pm tickless timer
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK           (0UL)
+#endif
+
+/**
+ * @brief  run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG                                                        \
+    {                                                                          \
+       .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg                                \
+    }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief  sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG                                                      \
+{                                                                              \
+    .pwc_sleep_type = PWC_SLEEP_WFE_INT,                                       \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief  sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG                                                      \
+{                                                                              \
+    {                                                                          \
+        .u16Clock = PWC_STOP_CLK_KEEP,                                         \
+        .u8StopDrv = PWC_STOP_DRV_HIGH,                                        \
+        .u16ExBusHold = PWC_STOP_EXBUS_HIZ,                                    \
+        .u16FlashWait = PWC_STOP_FLASH_WAIT_ON,                                \
+    },                                                                         \
+    .pwc_stop_type = PWC_STOP_WFE_INT,                                         \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief  sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG                                                   \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD1,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief  sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG                                                  \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD3,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-04-15     CDT          first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_QSPI,                                \
+        .clock    = FCG1_PERIPH_QSPI,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_QSPI_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_QSPI_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_QSPI_INTR,                \
+        },                                                  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS                                        \
+    {                                                           \
+        .u32PrefetchMode   = QSPI_PREFETCH_MD_INVD,             \
+        .u32SetupTime      = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5,   \
+        .u32ReleaseTime    = QSPI_QSSN_RELEASE_DELAY_QSCK32,    \
+        .u32IntervalTime   = QSPI_QSSN_INTERVAL_QSCK1,          \
+    }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL               QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                     \
+    {                                                       \
+        .Instance       = QSPI_DMA_INSTANCE,                \
+        .channel        = QSPI_DMA_CHANNEL,                 \
+        .clock          = QSPI_DMA_CLOCK,                   \
+        .trigger_select = QSPI_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_AOS_STRG,                 \
+        .flag           = QSPI_DMA_TRANS_FLAG,              \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = QSPI_DMA_IRQn,                    \
+            .irq_prio   = QSPI_DMA_INT_PRIO,                \
+            .int_src    = QSPI_DMA_INT_SRC,                 \
+        }                                                   \
+    }
+#endif /* QSPI_DMA_CONFIG */
+
+/* unit: half-word, DMA data width of QSPI transmitting is 16bit */
+#ifndef QSPI_DMA_TX_BUFSIZE
+#define QSPI_DMA_TX_BUFSIZE             256
+#endif /* QSPI_DMA_TX_BUFSIZE */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_QSPI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-04-15     CDT          first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_SDIO1)
+#ifndef SDIO1_BUS_CONFIG
+#define SDIO1_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio1",                                  \
+        .instance   = CM_SDIOC1,                                \
+        .clock      = FCG1_PERIPH_SDIOC1,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO1_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO1_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC1_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_RX_DMA_INSTANCE,            \
+            .channel        = SDIO1_RX_DMA_CHANNEL,             \
+            .clock          = SDIO1_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_TX_DMA_INSTANCE,            \
+            .channel        = SDIO1_TX_DMA_CHANNEL,             \
+            .clock          = SDIO1_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO1_BUS_CONFIG */
+#endif /* BSP_USING_SDIO1 */
+
+#if defined(BSP_USING_SDIO2)
+#ifndef SDIO2_BUS_CONFIG
+#define SDIO2_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio2",                                  \
+        .instance   = CM_SDIOC2,                                \
+        .clock      = FCG1_PERIPH_SDIOC2,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO2_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO2_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC2_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_RX_DMA_INSTANCE,            \
+            .channel        = SDIO2_RX_DMA_CHANNEL,             \
+            .clock          = SDIO2_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_TX_DMA_INSTANCE,            \
+            .channel        = SDIO2_TX_DMA_CHANNEL,             \
+            .clock          = SDIO2_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO2_BUS_CONFIG */
+#endif /* BSP_USING_SDIO2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-01-10     CDT          first version
+ */
+
+#ifndef __IC_CONFIG_H__
+#define __IC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
+#define IC1_NAME "ic1"
+#define INPUT_CAPTURE_CFG_TMR6_1                                                \
+{                                                                               \
+    .name = IC1_NAME,                                                           \
+    .ch = TMR6_CH_A,                                                            \
+    .clk_div = TMR6_CLK_DIV32,                                                  \
+    .first_edge = TMR6_CAPT_COND_PWMA_RISING,                                   \
+    .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM,                        \
+    .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO,                      \
+    .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM,                        \
+    .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO,                      \
+}
+#endif
+
+#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
+#define IC2_NAME "ic2"
+#define INPUT_CAPTURE_CFG_TMR6_2                                                \
+{                                                                               \
+    .name = IC2_NAME,                                                           \
+    .ch = TMR6_CH_A,                                                            \
+    .clk_div = TMR6_CLK_DIV32,                                                  \
+    .first_edge = TMR6_CAPT_COND_TRIGB_RISING,                                  \
+    .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM,                        \
+    .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO,                      \
+    .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM,                        \
+    .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO,                      \
+}
+#endif
+
+#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
+#define IC3_NAME "ic3"
+#define INPUT_CAPTURE_CFG_TMR6_3                                                \
+{                                                                               \
+    .name = IC3_NAME,                                                           \
+    .ch = TMR6_CH_B,                                                            \
+    .clk_div = TMR6_CLK_DIV16,                                                  \
+    .first_edge = TMR6_CAPT_COND_TRIGC_FALLING,                                 \
+    .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM,                        \
+    .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO,                      \
+    .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM,                        \
+    .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO,                      \
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IC_CONFIG_H__ */
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_APP_CONF_H__
+#define __USB_APP_CONF_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "rtconfig.h"
+
+/* USB MODE CONFIGURATION */
+/*
+USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment
+(1) If only defined USB_FS_MODE:
+    MCU USBFS core work in full speed using internal PHY.
+(2) If only defined USB_HS_MODE:
+    MCU USBHS core work in full speed using internal PHY.
+(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY
+    MCU USBHS core work in high speed using external PHY.
+(4) Other combination:
+    Not support, forbid!!
+*/
+
+#if defined(BSP_USING_USBHS)
+#define USB_HS_MODE
+#endif
+#if defined(BSP_USING_USBFS)
+#define USB_FS_MODE
+#endif
+#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS)
+#define USB_FS_MODE
+#endif
+
+#if defined(BSP_USING_USBD)
+#define USE_DEVICE_MODE
+#endif
+#if defined(BSP_USING_USBH)
+#define USE_HOST_MODE
+#endif
+#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH)
+#define USE_DEVICE_MODE
+#endif
+
+#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN)
+#define USB_HS_EXTERNAL_PHY
+#endif
+
+#ifndef USB_HS_MODE
+#ifndef USB_FS_MODE
+#error  "USB_HS_MODE or USB_FS_MODE should be defined"
+#endif
+#endif
+
+#ifndef USE_DEVICE_MODE
+#ifndef USE_HOST_MODE
+#error  "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD)
+/* USB DEVICE FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                         (128U)
+#define TX0_FIFO_FS_SIZE                        (32U)
+#define TX1_FIFO_FS_SIZE                        (32U)
+#define TX2_FIFO_FS_SIZE                        (32U)
+#define TX3_FIFO_FS_SIZE                        (32U)
+#define TX4_FIFO_FS_SIZE                        (32U)
+#define TX5_FIFO_FS_SIZE                        (32U)
+#define TX6_FIFO_FS_SIZE                        (32U)
+#define TX7_FIFO_FS_SIZE                        (32U)
+#define TX8_FIFO_FS_SIZE                        (32U)
+#define TX9_FIFO_FS_SIZE                        (32U)
+#define TX10_FIFO_FS_SIZE                       (32U)
+#define TX11_FIFO_FS_SIZE                       (32U)
+#define TX12_FIFO_FS_SIZE                       (32U)
+#define TX13_FIFO_FS_SIZE                       (32U)
+#define TX14_FIFO_FS_SIZE                       (32U)
+#define TX15_FIFO_FS_SIZE                       (32U)
+
+#if ((RX_FIFO_FS_SIZE + \
+      TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
+      TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \
+      TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \
+      TX15_FIFO_FS_SIZE) > 640U)
+#error  "The USB max FIFO size is 640 x 4 Bytes!"
+#endif
+#endif
+
+#ifdef USB_HS_MODE
+#define RX_FIFO_HS_SIZE                         (512U)
+#define TX0_FIFO_HS_SIZE                        (64U)
+#define TX1_FIFO_HS_SIZE                        (64U)
+#define TX2_FIFO_HS_SIZE                        (64U)
+#define TX3_FIFO_HS_SIZE                        (64U)
+#define TX4_FIFO_HS_SIZE                        (64U)
+#define TX5_FIFO_HS_SIZE                        (64U)
+#define TX6_FIFO_HS_SIZE                        (64U)
+#define TX7_FIFO_HS_SIZE                        (64U)
+#define TX8_FIFO_HS_SIZE                        (64U)
+#define TX9_FIFO_HS_SIZE                        (64U)
+#define TX10_FIFO_HS_SIZE                       (64U)
+#define TX11_FIFO_HS_SIZE                       (64U)
+#define TX12_FIFO_HS_SIZE                       (64U)
+#define TX13_FIFO_HS_SIZE                       (64U)
+#define TX14_FIFO_HS_SIZE                       (64U)
+#define TX15_FIFO_HS_SIZE                       (64U)
+
+#if ((RX_FIFO_HS_SIZE + \
+      TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \
+      TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \
+      TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \
+      TX15_FIFO_HS_SIZE) > 2048U)
+#error  "The USB max FIFO size is 2048 x 4 Bytes!"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD_VBUS_SENSING)
+#define VBUS_SENSING_ENABLED
+#endif
+#endif
+
+#if defined(BSP_USING_USBH)
+/* USB HOST FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                          (128U)
+#define TXH_NP_FS_FIFOSIZ                        (32U)
+#define TXH_P_FS_FIFOSIZ                         (64U)
+
+#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U)
+#error  "The USB max FIFO size is 640 x 4 Bytes!"
+#endif
+#endif
+
+#ifdef USB_HS_MODE
+#define RX_FIFO_HS_SIZE                          (512U)
+#define TXH_NP_HS_FIFOSIZ                        (128U)
+#define TXH_P_HS_FIFOSIZ                         (256U)
+
+#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U)
+#error  "The USB max FIFO size is 2048 x 4 Bytes!"
+#endif
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_APP_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_BSP_H__
+#define __USB_BSP_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "hc32_ll_utility.h"
+
+extern void usb_udelay(const uint32_t usec);
+extern void usb_mdelay(const uint32_t msec);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_BSP_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dma_config.h"
+#include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
+#include "dac_config.h"
+#include "gpio_config.h"
+#include "eth_config.h"
+#include "can_config.h"
+#include "mcan_config.h"
+#include "sdio_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"
+#include "tmr_capture_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,112 @@
+/***************************************************************************//**
+ * \file HC32F4A8.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+/*###ICF### Section handled by ICF editor, don't touch! *****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+  error "Link location not defined or not supported!";
+}
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFE0000;
+define symbol ram1_end_address  = 0x2005FFFF;
+
+if(isdefinedsymbol(_LINK_RAM_)) {
+  define symbol ram_start_reserve = 0x20000;
+  define symbol rom1_base_address = ram1_base_address;
+  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
+  define symbol rom2_base_address = 0x0;
+  define symbol rom2_end_address  = 0x0;
+  define symbol rom3_base_address = 0x0;
+  define symbol rom3_end_address = 0x0;
+} else {
+  define symbol ram_start_reserve = 0x0;
+  define symbol rom1_base_address = 0x0;
+  define symbol rom3_base_address = 0x03000000;
+  define symbol rom3_end_address = 0x030017FF;
+  if (isdefinedsymbol(_HC32F4A8_2M_)) {
+    define symbol rom1_end_address  = 0x001FFFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F4A8_1M_SINGLE_)) {
+    define symbol rom1_end_address  = 0x000FFFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F4A8_1M_DUAL_)) {
+    define symbol rom1_end_address  = 0x0007FFFF;
+    define symbol rom2_base_address = 0x00100000;
+    define symbol rom2_end_address  = 0x0017FFFF;
+  }
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
+define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
+define symbol __ICFEDIT_region_IROM3_end__   = rom3_end_address;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__     = 0x2000;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__       = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
+define memory mem with size = 4G;
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
+                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region OTP_region       =   mem:[from __ICFEDIT_region_IROM3_start__   to __ICFEDIT_region_IROM3_end__];
+define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
+                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in OTP_region   { readonly section .otp_data };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
@@ -0,0 +1,22 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00200000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x00200000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFE0000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFE0008 0x0007FFF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
+
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &hc32_onchip_flash,                                              \
+    &ext_nor_flash0,                                                 \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                 \
+{                                                                                      \
+    {FAL_PART_MAGIC_WROD,          "app",   "onchip_flash",   0,  2 * 1024 * 1024, 0}, \
+    {FAL_PART_MAGIC_WROD,   "filesystem",         "w25q64",   0,  8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-04-11     CDT          first version
+ */
+
+#ifndef __NAND_PORT_H__
+#define __NAND_PORT_H__
+
+/******************** NAND chip information ***********************************/
+#define NAND_BYTES_PER_PAGE             2048UL
+#define NAND_SPARE_AREA_SIZE            64UL
+#define NAND_PAGES_PER_BLOCK            64UL
+#define NAND_BYTES_PER_BLOCK            (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
+#define NAND_BLOCKS_PER_PLANE           1024UL
+#define NAND_PLANE_PER_DEVICE           2UL
+#define NAND_DEVICE_BLOCKS              (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
+#define NAND_DEVICE_PAGES               (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
+
+/******************** EXMC_NFC configure **************************************/
+/* chip: EXMC_NFC_BANK0~7 */
+#define NAND_EXMC_NFC_BANK              EXMC_NFC_BANK0
+
+/* density:2Gbit */
+#define NAND_EXMC_NFC_BANK_CAPACITY     EXMC_NFC_BANK_CAPACITY_2GBIT
+
+/* device width: 8-bit */
+#define NAND_EXMC_NFC_MEMORY_WIDTH      EXMC_NFC_MEMORY_WIDTH_8BIT
+
+/* page size: 2KByte */
+#define NAND_EXMC_NFC_PAGE_SIZE         EXMC_NFC_PAGE_SIZE_2KBYTE
+
+/* row address cycle: 3 */
+#define NAND_EXMC_NFC_ROW_ADDR_CYCLE    EXMC_NFC_3_ROW_ADDR_CYCLE
+
+/* ECC mode */
+#define NAND_EXMC_NFC_ECC_MD            EXMC_NFC_1BIT_ECC
+
+/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) */
+/* TS: ALE/CLE/CE setup time(min=10ns) */
+#define NAND_TS                         1U
+
+/* TWP: WE# pulse width (min=10ns) */
+#define NAND_TWP                        1U
+
+/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
+#define NAND_TRP                        2U
+
+/* TTH: ALE/CLE/CE hold time (min=5ns) */
+#define NAND_TH                         1U
+
+/* TWH: WE# pulse width HIGH (min=10ns) */
+#define NAND_TWH                        1U
+
+/* TRH: RE# pulse width HIGH (min=7ns) */
+#define NAND_TRH                        1U
+
+/* TRR: Ready to RE# LOW (min=20ns) */
+#define NAND_TRR                        2U
+
+/* TWB: WE# HIGH to busy (max=100ns) */
+#define NAND_TWB                        1U
+
+/* TWB: WE# HIGH to busy (max=100ns) */
+#define NAND_TRB                        1U
+
+/* TCCS: Change read column and Change write column delay */
+#define NAND_TCCS                       5U
+
+/* TWTR: WE# HIGH to RE# LOW (min=60ns) */
+#define NAND_TWTR                       4U
+
+/* TRTW: RE# HIGH to WE# LOW (min=100ns) */
+#define NAND_TRTW                       7U
+
+/* TADL: ALE to data start (min=70ns) */
+#define NAND_TADL                       5U
+
+#endif
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-04-07     CDT          first version
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+
+/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */
+#define SDRAM_CHIP                      EXMC_DMC_CHIP0
+/* bank address */
+#define SDRAM_BANK_ADDR                 (0x80000000UL)
+/* size(kbyte):32MB = 32*1024*1KBytes */
+#define SDRAM_SIZE                      (32UL * 1024UL * 1024UL)
+/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */
+#define SDRAM_AUTO_PRECHARGE_PIN        EXMC_DMC_AUTO_PRECHARGE_A10
+/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */
+#define SDRAM_DATA_WIDTH                EXMC_DMC_MEMORY_WIDTH_16BIT
+/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */
+#define SDRAM_COLUMN_BITS               EXMC_DMC_COLUMN_BITS_NUM9
+/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */
+#define SDRAM_ROW_BITS                  EXMC_DMC_ROW_BITS_NUM13
+/* cas latency clock number: 2, 3 */
+#define SDRAM_CAS_LATENCY               2UL
+/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */
+#define SDRAM_BURST_LENGTH              EXMC_DMC_BURST_1BEAT
+
+/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */
+#define SDRAM_MODEREG_OPERATING_MODE    SDRAM_MODEREG_OPERATING_MODE_STANDARD
+/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */
+#define SDRAM_MODEREG_BURST_TYPE        SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL
+/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */
+#define SDRAM_MODEREG_WRITEBURST_MODE   SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED
+
+/* timing configuration(EXCLK clock frequency: 60MHz) */
+/* refresh rate counter (EXCLK clock) */
+#define SDRAM_REFRESH_COUNT             (900U)
+/* TMDR: mode register command time (EXCLK clock) */
+#define SDRAM_TMDR                      2U
+/* TRAS: RAS to precharge delay time (EXCLK clock) */
+#define SDRAM_TRAS                      3U
+/* TRC:  active bank x to active bank x delay time (EXCLK clock) */
+#define SDRAM_TRC                       4U
+/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */
+#define SDRAM_TRCD_B                    3U
+#define SDRAM_TRCD_P                    0U
+/* TRFC: autorefresh command time (EXCLK clock) */
+#define SDRAM_TRFC_B                    4U
+#define SDRAM_TRFC_P                    0U
+/* TRP:  precharge to RAS delay time (EXCLK clock) */
+#define SDRAM_TRP_B                     3U
+#define SDRAM_TRP_P                     0U
+/* TRRD: active bank x to active bank y delay time (EXCLK clock) */
+#define SDRAM_TRRD                      2U
+/* TWR: write to precharge delay time (EXCLK clock). */
+#define SDRAM_TWR                       2U
+/* TWTR: write to read delay time (EXCLK clock). */
+#define SDRAM_TWTR                      1U
+/* TXP: exit power-down command time (EXCLK clock). */
+#define SDRAM_TXP                       1U
+/* TXSR: exit self-refresh command time (EXCLK clock). */
+#define SDRAM_TXSR                      5U
+/* TESR: self-refresh command time (EXCLK clock). */
+#define SDRAM_TESR                      5U
+
+/* memory mode register */
+#define SDRAM_MODEREG_BURST_LENGTH_1              (0x0000U)
+#define SDRAM_MODEREG_BURST_LENGTH_2              (0x0001U)
+#define SDRAM_MODEREG_BURST_LENGTH_4              (0x0002U)
+#define SDRAM_MODEREG_BURST_LENGTH_8              (0x0004U)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL       (0x0000U)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED      (0x0008U)
+#define SDRAM_MODEREG_CAS_LATENCY_2               (0x0020U)
+#define SDRAM_MODEREG_CAS_LATENCY_3               (0x0030U)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD     (0x0000U)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED  (0x0000U)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE      (0x0200U)
+
+#endif
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __TCA9539_PORT_H__
+#define __TCA9539_PORT_H__
+
+#include "tca9539.h"
+
+/**
+ * @defgroup HC32F4A8_EV_IO_Function_Sel Expand IO function definition
+ * @{
+ */
+#define EIO_USBFS_OC                    (TCA9539_IO_PIN0)   /* USBFS over-current, input */
+#define EIO_USBHS_OC                    (TCA9539_IO_PIN1)   /* USBHS over-current, input */
+#define EIO_SDIC1_CD                    (TCA9539_IO_PIN2)   /* SDIC1 card detect, input */
+#define EIO_SCI_CD                      (TCA9539_IO_PIN3)   /* Smart card detect, input */
+#define EIO_TOUCH_INT                   (TCA9539_IO_PIN4)   /* Touch screen interrupt, input */
+#define EIO_LIN_SLEEP                   (TCA9539_IO_PIN5)   /* LIN PHY sleep, output */
+#define EIO_RTCS_CTRST                  (TCA9539_IO_PIN6)   /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
+#define EIO_LCD_RST                     (TCA9539_IO_PIN7)   /* LCD panel reset, output */
+
+#define EIO_CAM_RST                     (TCA9539_IO_PIN0)   /* Camera module reset, output */
+#define EIO_CAM_STB                     (TCA9539_IO_PIN1)   /* Camera module standby, output */
+#define EIO_USB3300_RST                 (TCA9539_IO_PIN2)   /* USBHS PHY USB3300 reset, output */
+#define EIO_ETH_RST                     (TCA9539_IO_PIN3)   /* ETH PHY reset, output */
+#define EIO_CAN_STB                     (TCA9539_IO_PIN4)   /* CAN PHY standby, output */
+#define EIO_LED_RED                     (TCA9539_IO_PIN5)   /* Red LED, output */
+#define EIO_LED_YELLOW                  (TCA9539_IO_PIN6)   /* Yellow LED, output */
+#define EIO_LED_BLUE                    (TCA9539_IO_PIN7)   /* Blue LED, output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
+ * @{
+ */
+#define LED_RED_PORT                    (TCA9539_IO_PORT1)
+#define LED_RED_PIN                     (EIO_LED_RED)
+#define LED_YELLOW_PORT                 (TCA9539_IO_PORT1)
+#define LED_YELLOW_PIN                  (EIO_LED_YELLOW)
+#define LED_BLUE_PORT                   (TCA9539_IO_PORT1)
+#define LED_BLUE_PIN                    (EIO_LED_BLUE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup  BSP CAN PHY STB port/pin definition
+ * @{
+ */
+#define CAN1_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN1_STB_PIN                    (TCA9539_IO_PIN4)
+#define CAN2_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN2_STB_PIN                    (TCA9539_IO_PIN5)
+/**
+ * @}
+ */
+
+#endif
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;peripherals/&gt;&#13;&#10;"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F4A8"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/./packages/hc32f4a8_ddl-latest/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F4A8.svd"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/project"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+        <listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+    <stringAttribute key="org.eclipse.embedcdt.debug.gdbjtag.core.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;peripherals&gt;&#13;&#10;    &lt;peripheral name=&quot;GPIO&quot;/&gt;&#13;&#10;&lt;/peripherals&gt;&#13;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
@@ -0,0 +1,179 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A8_2M -FS00 -FL0200000 -FP0($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_2M.FLM) -FF1HC32F4A8_otp -FS13000000 -FL11800 -FP1($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    else:
+        EXEC_PATH   = r'C:/Users/XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
@@ -0,0 +1,179 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A8_2M -FS00 -FL0200000 -FP0($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_2M.FLM) -FF1HC32F4A8_otp -FS13000000 -FL11800 -FP1($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
@@ -20,7 +20,8 @@ extern "C" {
 #endif


-#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_ERASE_GRANULARITY    (8 * 1024)
+#define HC32_FLASH_WRITE_GRANULARITY    (4)
 #define HC32_FLASH_SIZE                 (2 * 1024 * 1024)
 #define HC32_FLASH_START_ADDRESS        (0)
 #define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
@@ -231,6 +231,30 @@ extern "C" {
 #define I2C4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC7
 #endif

+/* DMA1 ch8 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_TX_DMA_INSTANCE            CM_DMA1
+#define SPI5_TX_DMA_CHANNEL             DMA_CH8
+#define SPI5_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI5_TX_DMA_TRIG_SELECT         AOS_DMA1_8
+#define SPI5_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH8
+#define SPI5_TX_DMA_IRQn                BSP_DMA1_CH8_IRQ_NUM
+#define SPI5_TX_DMA_INT_PRIO            BSP_DMA1_CH8_IRQ_PRIO
+#define SPI5_TX_DMA_INT_SRC             INT_SRC_DMA1_TC8
+#endif
+
+/* DMA1 ch9 */
+#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
+#define SPI6_TX_DMA_INSTANCE            CM_DMA1
+#define SPI6_TX_DMA_CHANNEL             DMA_CH9
+#define SPI6_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI6_TX_DMA_TRIG_SELECT         AOS_DMA1_9
+#define SPI6_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH9
+#define SPI6_TX_DMA_IRQn                BSP_DMA1_CH9_IRQ_NUM
+#define SPI6_TX_DMA_INT_PRIO            BSP_DMA1_CH9_IRQ_PRIO
+#define SPI6_TX_DMA_INT_SRC             INT_SRC_DMA1_TC9
+#endif
+
 /* DMA2 ch0 */
 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
 #define UART1_RX_DMA_INSTANCE           CM_DMA2
@@ -74,6 +74,12 @@ extern "C" {
 /* DMA1 ch7 */
 #define BSP_DMA1_CH7_IRQ_NUM            INT019_IRQn
 #define BSP_DMA1_CH7_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch8 */
+#define BSP_DMA1_CH8_IRQ_NUM            INT020_IRQn
+#define BSP_DMA1_CH8_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch9 */
+#define BSP_DMA1_CH9_IRQ_NUM            INT021_IRQn
+#define BSP_DMA1_CH9_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT

 /* DMA2 ch0 */
 #define BSP_DMA2_CH0_IRQ_NUM            INT044_IRQn
@@ -235,6 +241,16 @@ extern "C" {
 #define BSP_SPI4_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
 #endif

+#if defined(BSP_USING_SPI5)
+#define BSP_SPI5_ERR_IRQ_NUM            INT098_IRQn
+#define BSP_SPI5_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI6)
+#define BSP_SPI6_ERR_IRQ_NUM            INT099_IRQn
+#define BSP_SPI6_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
 #if defined(BSP_USING_UART8)
 #define BSP_UART8_RXERR_IRQ_NUM         INT017_IRQn
 #define BSP_UART8_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
@@ -38,11 +38,11 @@ if GetDepend(['RT_USING_ADC']):
 if GetDepend(['RT_USING_DAC']):
    src += ['drv_dac.c']

-if GetDepend(['RT_USING_CAN', 'BSP_USING_CAN']):
-    src += ['drv_can.c']
-
-if GetDepend(['RT_USING_CAN', 'BSP_USING_MCAN']):
-    src += ['drv_mcan.c']
+if GetDepend(['RT_USING_CAN']):
+    if GetDepend(['BSP_USING_CAN']):
+        src += ['drv_can.c']
+    if GetDepend(['BSP_USING_MCAN']):
+        src += ['drv_mcan.c']

 if GetDepend(['RT_USING_RTC']):
    src += ['drv_rtc.c']
@@ -28,7 +28,7 @@
 #define TSEG1_MAX_FOR_CAN2_0                                (65U)
 #define TSEG2_MIN_FOR_CAN2_0                                (1U)
 #define TSEG2_MAX_FOR_CAN2_0                                (8U)
-#if defined(HC32F4A0) || defined(HC32F472)
+#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
    #define TSJW_MIN_FOR_CAN2_0                             (1U)
    #define TSJW_MAX_FOR_CAN2_0                             (16U)
 #elif defined(HC32F460)
@@ -78,6 +78,9 @@
                                                             baud == (CANFD_DATA_BAUD_4M) ||                   \
                                                             baud == (CANFD_DATA_BAUD_5M) ||                   \
                                                             baud == (CANFD_DATA_BAUD_8M))
+#define IS_CAN_FRAME(frame)                                  ((frame) == CAN_FRAME_CLASSIC ||                  \
+                                                              (frame) == CAN_FRAME_ISO_FD  ||                  \
+                                                              (frame) == CAN_FRAME_NON_ISO_FD)

 #define CAN_BIT_TIMING_CANFD_ARBITRATION                    (1U << 1)
 #define CAN_BIT_TIMING_CANFD_DATA                           (1U << 2)
@@ -85,7 +88,7 @@
 #endif

 #define NUM_PRESCALE_MAX                                    (256U)
-#if defined(HC32F4A0)
+#if defined(HC32F4A0) || defined(HC32F4A8)
    #define CAN_FILTER_COUNT                                (16U)
    #define CAN1_INT_SRC                                    (INT_SRC_CAN1_HOST)
    #define CAN2_INT_SRC                                    (INT_SRC_CAN2_HOST)
@@ -206,24 +209,24 @@ static const struct canfd_baud_rate_tab _g_baudrate_fd[] =
 {
    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 1U, 64U, 16U, 16U},
    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 32U, 8U, 8U},
-    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U},
-    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U},
-    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U},
-    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U},
+    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U},
+    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U},
+    {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U},
    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 2U, 64U, 16U, 16U},
    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 64U, 16U, 16U},
-    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_DATA_BAUD_1M, 1U, 32U, 8U, 8U},
-    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U},
-    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U},
-    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U},
-    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U},
+    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 2U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U},
+    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U},
+    {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U},
    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 4U, 64U, 16U},
    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 2U, 64U, 16U},
-    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_DATA_BAUD_1M, 2U, 32U, 8U, 8U},
-    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U},
-    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U},
-    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U},
-    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U},
+    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 4U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U},
+    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U},
+    {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U},
 };
 #endif

@@ -233,7 +236,7 @@ static can_device _g_can_dev_array[] =
    {
        {0},
        CAN1_INIT_PARAMS,
-#if defined(HC32F4A0) || defined(HC32F472)
+#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
        .instance = CM_CAN1,
 #elif defined (HC32F460)
        .instance = CM_CAN,
@@ -741,26 +744,6 @@ static void _init_ll_struct_canfd(can_device *p_can_dev)
    }
    RT_ASSERT((p_can_dev->ll_init.pstcCanFd != RT_NULL));
    CAN_FD_StructInit(p_can_dev->ll_init.pstcCanFd);
-    switch ((rt_uint32_t)p_can_dev->instance)
-    {
-#ifdef BSP_USING_CAN1
-    case (rt_uint32_t)CM_CAN1:
-        p_can_dev->ll_init.pstcCanFd->u8Mode = CAN1_CANFD_MODE;
-        break;
-#endif
-#ifdef BSP_USING_CAN2
-    case (rt_uint32_t)CM_CAN2:
-        p_can_dev->ll_init.pstcCanFd->u8Mode = CAN2_CANFD_MODE;
-        break;
-#endif
-#ifdef BSP_USING_CAN3
-    case (rt_uint32_t)CM_CAN3:
-        p_can_dev->ll_init.pstcCanFd->u8Mode = CAN3_CANFD_MODE;
-        break;
-#endif
-    default:
-        break;
-    }
 }

 static rt_err_t _config_can_bit_timing(can_device *p_can_dev, void *arg)
@@ -814,11 +797,23 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg)
        p_can_dev->rt_can.config.baud_rate = argval;
        break;
    case RT_CAN_CMD_SET_CANFD:
+        argval = (rt_uint32_t) arg;
        if (p_can_dev->rt_can.config.enable_canfd == argval)
        {
            break;
        }
-        p_can_dev->rt_can.config.enable_canfd = (rt_uint32_t) argval;
+
+        RT_ASSERT(IS_CAN_FRAME(argval));
+        if (argval != CAN_FRAME_CLASSIC)
+        {
+            p_can_dev->ll_init.pstcCanFd->u8Mode = (argval == CAN_FRAME_ISO_FD) ? CAN_FD_MD_ISO : CAN_FD_MD_BOSCH;
+        }
+        CAN_Init(p_can_dev->instance, &p_can_dev->ll_init);
+        p_can_dev->rt_can.config.enable_canfd = argval;
+        argval = (argval > CAN_FRAME_CLASSIC) ? ENABLE : DISABLE;
+#if defined(HC32F472) || defined(HC32F4A8)
+        CAN_FD_Cmd(p_can_dev->instance, (en_functional_state_t)argval);
+#endif
        break;
    case RT_CAN_CMD_SET_BAUD_FD:
        argval = (rt_uint32_t) arg;
@@ -1271,7 +1266,7 @@ void CAN3_Handler(void)
 static void _enable_can_clock(void)
 {
 #if defined(BSP_USING_CAN1)
-#if defined(HC32F4A0) || defined(HC32F472)
+#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE);
 #elif defined(HC32F460)
    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN, ENABLE);
@@ -1332,7 +1327,7 @@ static void _init_ll_struct_filter(can_device *p_can_dev)
    p_can_dev->ll_init.u16FilterSelect = CAN_FILTER1;
 }

-static void _init_struct_by_static_cfg(can_device *p_can_dev)
+static void _init_default_cfg(can_device *p_can_dev)
 {
    struct can_configure rt_can_config  = CANDEFAULTCONFIG;

@@ -1347,16 +1342,15 @@ static void _init_struct_by_static_cfg(can_device *p_can_dev)
    rt_can_config.sndboxnumber = 1;
    p_can_dev->rt_can.config = rt_can_config;

+    CAN_StructInit(&p_can_dev->ll_init);
    if (p_can_dev->init.single_trans_mode)
    {
        p_can_dev->ll_init.u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_ENABLE;
    }
-
 #ifdef RT_CAN_USING_CANFD
    _init_ll_struct_canfd(p_can_dev);
 #endif
    _init_ll_struct_filter(p_can_dev);
-
 }

 extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx);
@@ -1370,8 +1364,7 @@ int rt_hw_can_init(void)
    uint32_t i = 0;
    for (; i < CAN_INDEX_MAX; i++)
    {
-        CAN_StructInit(&_g_can_dev_array[i].ll_init);
-        _init_struct_by_static_cfg(&_g_can_dev_array[i]);
+        _init_default_cfg(&_g_can_dev_array[i]);

        /* register CAN device */
        rt_hw_board_can_init(_g_can_dev_array[i].instance);
@@ -42,6 +42,10 @@ extern "C" {
 #define CANFD_DATA_BAUD_5M              (5*1000*1000UL)
 #define CANFD_DATA_BAUD_8M              (8*1000*1000UL)

+#define CAN_FRAME_CLASSIC               (0x0U)
+#define CAN_FRAME_ISO_FD                (0x2U)
+#define CAN_FRAME_NON_ISO_FD            (0x4U)
+
 /* hc32 can device */
 struct can_dev_init_params
 {
@@ -358,9 +358,7 @@ static void hc32_eth_irq_handle(stc_eth_handle_t *eth_handle)
        result = eth_device_ready(&(hc32_eth_device.parent));
        if (result != RT_EOK)
        {
-#if defined (RT_USING_ULOG) || defined (ULOG_USING_ISR_LOG)
            LOG_I("eth rx complete callback err = %d", result);
-#endif
        }
        /* Clear the Eth DMA Rx IT pending bits */
        ETH_DMA_ClearStatus(ETH_DMA_FLAG_RIS | ETH_DMA_FLAG_NIS);
@@ -467,9 +465,7 @@ static void eth_phy_irq_handler(void *args)
    rt_uint16_t status = 0;

    ETH_PHY_ReadReg(&EthHandle, PHY_IISDR, &status);
-#if defined (RT_USING_ULOG) || defined (ULOG_USING_ISR_LOG)
    LOG_D("phy interrupt status reg is 0x%X", status);
-#endif
 #endif
    hc32_phy_link_change();
 }
@@ -76,11 +76,11 @@ int hc32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
 */
 int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 {
-    uint8_t u8MemBuf[4] = {0xFF, 0xFF, 0xFF, 0xFF};
+    uint8_t u8MemBuf[HC32_FLASH_WRITE_GRANULARITY];
    rt_err_t result = RT_EOK;
    rt_uint32_t newAddr = addr, offsetVal = 0;
    rt_uint32_t index = 0, u32Cnt = 0;
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    rt_uint32_t FirstSector = 0, NumOfSectors = 0;
 #endif

@@ -94,9 +94,13 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
        return -RT_EINVAL;
    }

+    for (u32Cnt = 0; u32Cnt < HC32_FLASH_WRITE_GRANULARITY; u32Cnt++)
+    {
+        u8MemBuf[u32Cnt] = 0xFF;
+    }
    /* EFM_FWMC write enable */
    EFM_FWMC_Cmd(ENABLE);
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    /* calculate sector information */
    FirstSector = addr / EFM_SECTOR_SIZE,
    NumOfSectors = GetSectorNum(addr, size);
@@ -104,22 +108,22 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
    EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE);
 #endif
    /* Word align */
-    if (0U != (addr % 4))
+    if (0U != (addr % HC32_FLASH_WRITE_GRANULARITY))
    {
-        newAddr = (addr / 4 + 1U) * 4;
+        newAddr = (addr / HC32_FLASH_WRITE_GRANULARITY + 1U) * HC32_FLASH_WRITE_GRANULARITY;
        offsetVal = newAddr - addr;
        if (offsetVal >= size)
        {
            result = -RT_ERROR;
-            index = 4 - offsetVal;
-            if (LL_OK == EFM_ReadByte(newAddr - 4, u8MemBuf, index))
+            index = HC32_FLASH_WRITE_GRANULARITY - offsetVal;
+            if (LL_OK == EFM_ReadByte(newAddr - HC32_FLASH_WRITE_GRANULARITY, u8MemBuf, index))
            {
                for (u32Cnt = 0; u32Cnt < size; u32Cnt++)
                {
                    u8MemBuf[index + u32Cnt] = buf[u32Cnt];
                }
                /* program */
-                if (LL_OK == EFM_Program(newAddr - 4, u8MemBuf, 4))
+                if (LL_OK == EFM_Program(newAddr - HC32_FLASH_WRITE_GRANULARITY, u8MemBuf, HC32_FLASH_WRITE_GRANULARITY))
                {
                    result = RT_EOK;
                }
@@ -139,7 +143,7 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
    }

 __exit:
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    /* Sectors enable write protection */
    EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE);
 #endif
@@ -165,7 +169,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
    rt_err_t result = RT_EOK;
    rt_uint32_t NumOfSectors = 0;
    rt_uint32_t SectorVal = 0, u32Addr = addr;
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    rt_uint32_t FirstSector = 0;
 #endif

@@ -183,7 +187,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
    EFM_FWMC_Cmd(ENABLE);
    /* calculate sector information */
    NumOfSectors = GetSectorNum(addr, size);
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    FirstSector = addr / EFM_SECTOR_SIZE,
    /* Sectors disable write protection */
    EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE);
@@ -198,7 +202,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
        }
        u32Addr += EFM_SECTOR_SIZE;
    }
-#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
    /* Sectors enable write protection */
    EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE);
 #endif
@@ -223,9 +227,9 @@ const struct fal_flash_dev hc32_onchip_flash =
    .name       = "onchip_flash",
    .addr       = HC32_FLASH_START_ADDRESS,
    .len        = HC32_FLASH_SIZE,
-    .blk_size   = HC32_FLASH_SIZE_GRANULARITY,
+    .blk_size   = HC32_FLASH_ERASE_GRANULARITY,
    .ops        = {NULL, fal_flash_read, fal_flash_write, fal_flash_erase},
-    .write_gran = 4
+    .write_gran = HC32_FLASH_WRITE_GRANULARITY
 };

 static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
@@ -24,7 +24,7 @@
 #define GPIO_PORT(pin)                  ((uint8_t)(((pin) >> 4) & 0x0F))
 #define GPIO_PIN(pin)                   ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin)))

-#if defined (HC32F4A0)
+#if defined (HC32F4A0) || defined (HC32F4A8)
    #define PIN_MAX_NUM                     ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1)
 #elif defined (HC32F460)
    #define PIN_MAX_NUM                     ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
@@ -67,7 +67,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
    stcIrqSignConfig.pfnCallback = irq_hdr;
    if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
 nvic_config:
-#elif defined (HC32F460) || defined (HC32F4A0)
+#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
    stcIrqSignConfig.enIRQn      = irq_config->irq_num;
    stcIrqSignConfig.enIntSrc    = irq_config->int_src;
    stcIrqSignConfig.pfnCallback = irq_hdr;
@@ -47,10 +47,6 @@ struct hc32_irq_config
 rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
                                  void (*irq_hdr)(void),
                                  rt_bool_t irq_enable);
-#if defined (HC32F448) || defined (HC32F472)
-rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
-        rt_bool_t irq_enable);
-#endif

 #ifdef __cplusplus
 }
@@ -15,35 +15,17 @@
 extern "C" {
 #endif

-#include <board.h>
-#include <rtdevice.h>
-#include <rtthread.h>
+#include "drv_can.h"

-/* Attention !!!
-* If RT_CAN_USING_CANFD is enabled, RT_CAN_CMD_SET_BITTIMING is more recommended
-* than RT_CAN_CMD_SET_BAUD_FD.
-* because sample point is not specified by config when using RT_CAN_CMD_SET_BAUD_FD
-* but in range [MCAN_SAMPLEPOINT_MIN/1000, MCAN_SAMPLEPOINT_MAX/1000]
-* this may not match with your application
-*/
-#define MCAN_SAMPLEPOINT_MIN            (700U)
-#define MCAN_SAMPLEPOINT_MAX            (850U)
+/* The arguments of RT command RT_CAN_CMD_SET_CANFD */
+#define MCAN_FD_CLASSICAL                   0       /* CAN classical */
+#define MCAN_FD_ISO_FD_NO_BRS               1       /* ISO CAN FD without BRS */
+#define MCAN_FD_ISO_FD_BRS                  2       /* ISO CAN FD with BRS */
+#define MCAN_FD_NON_ISO_FD_NO_BRS           3       /* non-ISO CAN FD without BRS */
+#define MCAN_FD_NON_ISO_FD_BRS              4       /* non-ISO CAN FD with BRS */

-#define MCAN_CLOCK_SRC_20M              (20*1000*1000UL)
-#define MCAN_CLOCK_SRC_40M              (40*1000*1000UL)
-#define MCAN_CLOCK_SRC_80M              (80*1000*1000UL)
-
-#define MCANFD_NOMINAL_BAUD_500K        (500*1000UL)
-#define MCANFD_NOMINAL_BAUD_1M          (1000*1000UL)
-
-#define MCANFD_DATA_BAUD_1M             (1*1000*1000UL)
-#define MCANFD_DATA_BAUD_2M             (2*1000*1000UL)
-#define MCANFD_DATA_BAUD_4M             (4*1000*1000UL)
-#define MCANFD_DATA_BAUD_5M             (5*1000*1000UL)
-#define MCANFD_DATA_BAUD_8M             (8*1000*1000UL)
-
-
-int rt_hw_mcan_init(void);
+#define MCAN_FD_ARG_MIN                     MCAN_FD_ISO_FD_NO_BRS
+#define MCAN_FD_ARG_MAX                     MCAN_FD_NON_ISO_FD_BRS

 #ifdef __cplusplus
 }
@@ -266,6 +266,7 @@ static rt_err_t _nand_read_page(struct rt_mtd_nand_device *device,
                                rt_uint32_t spare_len)
 {
    rt_err_t result = RT_EOK;
+    stc_exmc_nfc_column_t stcColumn;
    struct rthw_nand *hw_nand = (struct rthw_nand *)device;

    RT_ASSERT(device != RT_NULL);
@@ -312,8 +313,11 @@ static rt_err_t _nand_read_page(struct rt_mtd_nand_device *device,
    {
        RT_ASSERT(spare_len <= device->oob_free);

-        if (LL_OK != EXMC_NFC_Read(hw_nand->nfc_bank, page, (rt_uint32_t)device->page_size,
-                                   (rt_uint32_t *)spare, (spare_len >> 2), DISABLE, NAND_READ_TIMEOUT))
+        stcColumn.u32Bank = hw_nand->nfc_bank;
+        stcColumn.u32Page = page;
+        stcColumn.u32Column = (rt_uint32_t)device->page_size;
+        if (LL_OK != EXMC_NFC_Read(&stcColumn, (rt_uint32_t *)spare,
+                                   (spare_len >> 2), DISABLE, NAND_READ_TIMEOUT))
        {
            result = -RT_EIO;
            goto _exit;
@@ -334,6 +338,7 @@ static rt_err_t _nand_write_page(struct rt_mtd_nand_device *device,
                                 rt_uint32_t spare_len)
 {
    rt_err_t result = RT_EOK;
+    stc_exmc_nfc_column_t stcColumn;
    struct rthw_nand *hw_nand = (struct rthw_nand *)device;

    RT_ASSERT(device != RT_NULL);
@@ -376,8 +381,11 @@ static rt_err_t _nand_write_page(struct rt_mtd_nand_device *device,
    {
        RT_ASSERT(spare_len <= device->oob_free);

-        if (LL_OK != EXMC_NFC_Write(hw_nand->nfc_bank, page, (rt_uint32_t)device->page_size,
-                                    (rt_uint32_t *)spare, (spare_len >> 2), DISABLE, NAND_WRITE_TIMEOUT))
+        stcColumn.u32Bank = hw_nand->nfc_bank;
+        stcColumn.u32Page = page;
+        stcColumn.u32Column = (rt_uint32_t)device->page_size;
+        if (LL_OK != EXMC_NFC_Write(&stcColumn, (rt_uint32_t *)spare,
+                                    (spare_len >> 2), DISABLE, NAND_WRITE_TIMEOUT))
        {
            result = -RT_EIO;
            goto _exit;
@@ -10,6 +10,7 @@
 * 2024-02-28     CDT          support HC32F448
 * 2024-02-29     CDT          Support multi line write/read
 * 2024-04-18     CDT          support HC32F472
+ * 2025-04-14     CDT          support HC32F4A8
 */

 /*******************************************************************************
@@ -327,7 +328,7 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi
        /* Set custom read mode */
        QSPI_SetReadMode(QSPI_RD_MD_CUSTOM_FAST_RD);
 #endif
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
        if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_MULTI))
        {
            return LL_ERR_INVD_PARAM;
@@ -350,7 +351,7 @@ static void hc32_qspi_word_to_byte(uint32_t u32Word, uint8_t *pu8Byte, uint8_t u
    while ((u32ByteNum--) != 0UL);
 }

-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F4A8)
 static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line)
 {
    rt_uint32_t dcom_protocol_line;
@@ -378,7 +379,7 @@ static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8
 #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
    (void)protocol_line;
    QSPI_WriteDirectCommValue(value);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
    QSPI_WriteDirectCommValue(hc32_qspi_get_dcom_protocol_line(protocol_line), value);
 #endif
 }
@@ -434,7 +435,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
    /* Enter direct communication mode */
    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
    /* Enter direct communication mode */
    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
@@ -487,7 +488,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
        DMA_StructInit(&stcDmaInit);
 #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
        stcDmaInit.u32DataWidth     = DMA_DATAWIDTH_8BIT;
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
        rt_uint16_t dcom_line = (rt_uint16_t)hc32_qspi_get_dcom_protocol_line(message->qspi_data_lines);
        stcDmaInit.u32DataWidth     = DMA_DATAWIDTH_16BIT;
 #endif
@@ -509,7 +510,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q

 #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
            src_addr = (rt_uint32_t)&pu8WriteBuf[u32TxIndex];
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
            if (u32DmaTransSize > qspi_bus->config->dma_tx_buf_size)
            {
                LOG_E("qspi dma transmit size over buffer size!");
@@ -563,7 +564,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
    /* Exit direct communication mode */
    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
    /* Exit direct communication mode */
    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
@@ -584,7 +585,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
    uint32_t u32RxIndex = 0U;
    rt_uint32_t u32TimeoutCnt;
 #endif
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F4A8)
    rt_uint32_t u32ReadMd;
 #endif

@@ -593,7 +594,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
    /* Enter direct communication mode */
    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
    if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) ||
            (message->qspi_data_lines == 4))
    {
@@ -707,7 +708,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
    /* Exit direct communication mode */
    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
 #endif
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F4A8)
    if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) ||
            (message->qspi_data_lines == 4))
    {
@@ -1094,7 +1095,7 @@ static void hc32_get_qspi_info(void)
 #ifdef BSP_QSPI_USING_DMA
    static struct dma_config qspi_dma = QSPI_DMA_CONFIG;
    qspi_config.dma_qspi    = &qspi_dma;
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F4A8)
    qspi_config.dma_tx_buf_size = QSPI_DMA_TX_BUFSIZE;
    qspi_config.dma_tx_buf = rt_malloc(qspi_config.dma_tx_buf_size << 1);
 #endif
@@ -39,7 +39,7 @@ struct hc32_qspi_config
    struct hc32_qspi_irq_config err_irq;
 #ifdef BSP_QSPI_USING_DMA
    struct dma_config           *dma_qspi;
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F4A8)
    rt_uint16_t                 *dma_tx_buf;
    rt_uint16_t                 dma_tx_buf_size;    /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
 #endif
@@ -685,7 +685,7 @@ static rt_uint32_t _sdio_clock_get(CM_SDIOC_TypeDef *SDIOCx)
    rt_uint32_t clk;

    (void)SDIOCx;
-#if defined (HC32F4A0)
+#if defined (HC32F4A0) || defined (HC32F4A8)
    clk = CLK_GetBusClockFreq(CLK_BUS_PCLK1);
 #elif defined (HC32F460)
    clk = CLK_GetBusClockFreq(CLK_BUS_EXCLK);
@@ -84,9 +84,9 @@ static rt_int32_t _sdram_verify_clock_frequency(void)
 {
    rt_int32_t ret = RT_EOK;

-#if defined (HC32F4A0)
-    /* EXCLK max frequency for SDRAM: 40MHz */
-    if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (40 * 1000000))
+#if defined (HC32F4A0) || defined (HC32F4A8)
+    /* EXCLK max frequency for SDRAM */
+    if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > EXMC_EXCLK_DMC_MAX_FREQ)
    {
        ret = -RT_ERROR;
    }
@@ -124,7 +124,9 @@ static rt_int32_t _sdram_init(void)

    /* configure DMC width && refresh period & chip & timing. */
    (void)EXMC_DMC_StructInit(&stcDmcInit);
+#if defined (HC32F4A0)
    stcDmcInit.u32SampleClock          = EXMC_DMC_SAMPLE_CLK_EXTCLK;
+#endif
    stcDmcInit.u32RefreshPeriod        = SDRAM_REFRESH_COUNT;
    stcDmcInit.u32ColumnBitsNumber     = SDRAM_COLUMN_BITS;
    stcDmcInit.u32RowBitsNumber        = SDRAM_ROW_BITS;
@@ -27,6 +27,11 @@ extern "C" {
 /*******************************************************************************
 * Global pre-processor symbols/macros ('#define')
 ******************************************************************************/
+#if defined (HC32F4A0)
+#define EXMC_EXCLK_DMC_MAX_FREQ             (40UL * 1000000UL)
+#elif defined (HC32F4A8)
+#define EXMC_EXCLK_DMC_MAX_FREQ             (120UL * 1000000UL)
+#endif

 /*******************************************************************************
 * Global variable definitions ('extern')
@@ -9,6 +9,7 @@
 * 2023-09-30     CDT          Delete dma transmit interrupt
 * 2024-02-20     CDT          support HC32F448
 * 2024-04-16     CDT          support HC32F472
+ * 2025-04-09     CDT          support HC32F4A8
 */

 /*******************************************************************************
@@ -32,12 +33,16 @@
 /*******************************************************************************
 * Local pre-processor symbols/macros ('#define')
 ******************************************************************************/
-//#define DRV_DEBUG
+// #define DRV_DEBUG
 #define LOG_TAG                         "drv.spi"
 #include <drv_log.h>

 /* SPI max division */
-#define SPI_MAX_DIV_VAL                 (0x7U)  /* Div256 */
+#if defined(HC32F4A0) || defined(HC32F460)
+    #define SPI_MAX_DIV_VAL                 (0x7U)  /* Div256 */
+#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8)
+    #define SPI_MAX_DIV_VAL                 (0x39U)
+#endif

 #ifdef BSP_SPI_USING_DMA
    #define DMA_CH_REG(reg_base, ch)    (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL)))
@@ -205,13 +210,24 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
            break;
        }
    }
+#if defined(HC32F4A0) || defined(HC32F460)
    stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG2_MBR_POS);
+#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8)
+    if (u32Cnt <= 15U)
+    {
+        stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG1_CLKDIV_POS);
+    }
+    else
+    {
+        stcSpiInit.u32BaudRatePrescaler = (((7U + ((u32Cnt - 15U) & 0x07U)) << SPI_CFG1_CLKDIV_POS) | ((1U + ((u32Cnt - 15U) >> 3U)) << SPI_CFG2_MBR_POS));
+    }
+#endif
    /* slave limit */
    if ((cfg->mode & RT_SPI_SLAVE) && (stcSpiInit.u32BaudRatePrescaler < SPI_BR_CLK_DIV8))
    {
        stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8;
    }
-    LOG_D("Bus freq: %d, SPI freq: %d, BaudRatePrescaler: %d", u32BusFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler);
+    LOG_D("Bus freq: %d, SPI freq: %d, BaudRatePrescaler: %d, u32Cnt: %d", u32BusFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler, u32Cnt);

    /* spi port init */
    rt_hw_spi_board_init(spi_instance);
@@ -312,7 +328,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
    {
        SPI_Cmd(SPIx, ENABLE);
    }
-#elif defined (HC32F448) || defined (HC32F472)
+#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
    if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE)
    {
        SPI_Cmd(SPIx, ENABLE);
@@ -333,7 +349,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
    {
        CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
    }
-#elif defined (HC32F448) || defined (HC32F472)
+#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
    if (SPI_SEND_ONLY == u32Mode)
    {
        SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
@@ -352,7 +368,7 @@ static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx)
 {
 #if defined (HC32F460) || defined (HC32F4A0)
    return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
-#elif defined (HC32F448) || defined (HC32F472)
+#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
    return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
 #else
 #error "Please select first the target HC32xxxx device used in your application."
@@ -473,6 +489,8 @@ static int32_t hc32_spi_dma_trans(struct hc32_spi_config *spi_config, const uint
    while ((RESET == DMA_GetTransCompleteStatus(DmaInstance, DmaFlag)) &&
            (u32TimeoutCnt < spi_config->timeout))
    {
+        rt_thread_mdelay(1);
+        u32TimeoutCnt++;
    }
    if (u32TimeoutCnt >= spi_config->timeout)
    {
@@ -542,7 +560,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
        if (message->send_buf && message->recv_buf)
        {
            hc32_spi_set_trans_mode(spi_instance, SPI_FULL_DUPLEX);
-            if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (send_length > 32))
+            if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX))
            {
                state = hc32_spi_dma_trans(spi_drv->config, send_buf, recv_buf, send_length);
            }
@@ -555,7 +573,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
        else if (message->send_buf)
        {
            hc32_spi_set_trans_mode(spi_instance, SPI_SEND_ONLY);
-            if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (send_length > 32))
+            if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX)
            {
                state = hc32_spi_dma_trans(spi_drv->config, send_buf, RT_NULL, send_length);
            }
@@ -599,6 +617,8 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
                    while ((RESET == SPI_GetStatus(spi_instance, SPI_FLAG_IDLE)) &&
                            (u32TimeoutCnt < spi_drv->config->timeout))
                    {
+                        rt_thread_mdelay(1);
+                        u32TimeoutCnt++;
                    }
                    if (u32TimeoutCnt >= spi_drv->config->timeout)
                    {
@@ -657,7 +677,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,

 static void hc32_spi_err_irq_handle(struct hc32_spi *spi)
 {
-#if defined (HC32F448) ||defined (HC32F472)
+#if defined (HC32F448) ||defined (HC32F472) || defined (HC32F4A8)
 #define SPI_FLAG_OVERLOAD       SPI_FLAG_OVERRUN
 #define SPI_FLAG_UNDERLOAD      SPI_FLAG_UNDERRUN
 #endif
@@ -748,6 +768,12 @@ static void hc32_spi4_err_irq_handler(void)
    rt_interrupt_leave();
 }
 #endif /* BSP_USING_SPI4 */
+#if defined (HC32F472)
+void SPI4_Handler(void)
+{
+    hc32_spi4_err_irq_handler();
+}
+#endif /* HC32F472 */

 #if defined(BSP_USING_SPI5)
 static void hc32_spi5_err_irq_handler(void)
@@ -884,9 +910,9 @@ static int hc32_hw_spi_bus_init(void)
        spi_bus_obj[i].config = &spi_config[i];
        spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
        /* register the handle */
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
        hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE);
-#elif defined (HC32F488)
+#elif defined (HC32F448) || defined (HC32F472)
        INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE);
        NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num);
 #endif
@@ -41,7 +41,7 @@ struct hc32_uart_rxto
    rt_uint32_t                 channel;
    rt_uint32_t                 clock;
    rt_size_t                   timeout_bits;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
    struct hc32_irq_config      irq_config;
    func_ptr_t                  irq_callback;
 #endif
@@ -53,7 +53,7 @@ struct hc32_uart_config
    const char                  *name;
    CM_USART_TypeDef            *Instance;
    rt_uint32_t                 clock;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
    struct hc32_uart_irq_config rxerr_irq;
    struct hc32_uart_irq_config rx_irq;
    struct hc32_uart_irq_config tx_irq;
@@ -41,7 +41,7 @@ struct hc32_uart_rxto
    rt_uint32_t                 channel;
    rt_uint32_t                 clock;
    rt_size_t                   timeout_bits;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
    struct hc32_irq_config      irq_config;
    func_ptr_t                  irq_callback;
 #endif
@@ -53,7 +53,7 @@ struct hc32_uart_config
    const char                  *name;
    CM_USART_TypeDef            *Instance;
    rt_uint32_t                 clock;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
    struct hc32_uart_irq_config rxerr_irq;
    struct hc32_uart_irq_config rx_irq;
    struct hc32_uart_irq_config tx_irq;
@@ -23,7 +23,7 @@
    #include "dev_spi_flash_sfud.h"
 #endif

-#if defined(HC32F4A0) || defined(HC32F448)
+#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8)
    #define SPI_BUS_NAME                "spi1"
    #define SPI_FLASH_DEVICE_NAME       "spi10"
    #define SPI_FLASH_CHIP              "w25q64"
@@ -27,7 +27,7 @@
 #define BSP_TCA9539_I2C_BUS_NAME        "i2c1"
 #define BSP_TCA9539_DEV_ADDR            (0x74U)

-#if defined(HC32F4A0)
+#if defined(HC32F4A0) || defined(HC32F4A8)
    #define TCA9539_RST_PIN             (45)    /* PC13 */
 #elif defined(HC32F448)
    #define TCA9539_RST_PIN             (31)    /* PB15 */
@@ -43,7 +43,7 @@ if GetDepend(['BSP_USING_ADC']):
 if GetDepend(['BSP_USING_DAC']):
    src += ['test_dac.c']

-if GetDepend(['BSP_USING_CAN']):
+if GetDepend(['BSP_USING_CAN']) or GetDepend(['BSP_USING_MCAN']):
    src += ['test_can.c']

 if GetDepend(['BSP_USING_RTC']):
--- a/Show More
+++ b/Show More