[dm2.0] add new bsp for rk platform

bsp/rockchip/rk3500/Kconfig

@@ -0,0 +1,31 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$BSP_DIR/driver/Kconfig"
+
+config SOC_RK3568
+    bool
+    select ARCH_ARMV8
+    select ARCH_CPU_64BIT
+    select RT_USING_CACHE
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_ARM_BOOTWITH_FLUSH_CACHE
+    default y
+

bsp/rockchip/rk3500/README.md

@@ -0,0 +1,75 @@
+
+
+
+
+# RK3568 BSP Introduction
+
+[中文页]() | English
+
+## 1. Introduction
+
+RK3568 is a general-purpose SOC, quad-core 64-bit Cortex-A55 processor, with 22nm lithography process, has frequency up to 2.0GHz and Mali G52 GPU, support 4K decoding and 1080P encoding. Support mangy interfaces such as SATA/PCIE/USB3.0, an 0.8T NPU for lightweight AI applications. Support dual Gigabit Ethernet ports, LPDDR4 memory, etc.
+
+This project ported RT-Thread on RK3568, you can use the RADXA ROCK 3A version of the RK3568 in low-priced, which can even replace the Raspberry Pi 4B.
+
+## 2. Compiling
+
+Usage ARM Developer GNU ToolChain, it support Linux and Windows:
+
+```plaintext
+https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads/
+```
+
+
+
+Download the `xxx-aarch64-none-elf` of x86_64 hosted platform, set the `RTT_EXEC_PATH` is system environment after decompress the binary.
+
+Enter directory `rt-thread/bsp/qemu-virt64-aarch64` and input:
+
+```plaintext
+scons
+```
+
+
+
+## 3. Execution
+
+RK3568 has different Kernel install methods according to different boardsit, recommend to install into the SD card: ([Official](https://wiki.t-firefly.com/en/ROC-RK3568-PC/hardware_doc.html)|[RADXA ROCK 3A](https://wiki.radxa.com/Rock3/install/microSD)).
+
+After install Kernel, storage the `rtthread.bin` to EFI partition (the second partition), and add this line in the front of `boot.cmd` in this partition:
+
+```shell
+fatload mmc 1:1 0x208000 /rtthread.bin;dcache flush;go 0x208000
+```
+
+
+
+After modifying the script, build a binary script `boot.scr ` in this partition:
+
+```shell
+# Install the uboot-mkimage package on Linux, or use MSYS2 to install the u-boot-tools package on Windows
+mkimage -C none -A arm -T script -d boot.cmd boot.scr
+```
+
+
+
+According to different boards, the serial port can support up to UART0~9, this project uses UART2 ([Official](https://wiki.t-firefly.com/en/ROC-RK3568-PC/debug.html)|[RADXA ROCK 3A](https://wiki.radxa.com/Rock3/dev/serial-console)) by default, the baud rate is 1500000, please make sure that the serial port used supports this baud rate.
+
+```plaintext
+heap: [0x002663f0 - 0x042663f0]
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.0 build Mar 19 2022 17:17:29
+ 2006 - 2022 Copyright by RT-Thread team
+Hi, this is RT-Thread!!
+msh />
+```
+
+
+
+## 4. Condition
+
+| Driver | Condition | Remark  |
+| ------ | --------- | ------- |
+| UART   | Support   | UART0~9 |

bsp/rockchip/rk3500/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/rockchip/rk3500/SConstruct

@@ -0,0 +1,29 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/rockchip/rk3500/applications/SConscript

@@ -0,0 +1,14 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group += SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/rockchip/rk3500/applications/main.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+
+    return 0;
+}

bsp/rockchip/rk3500/driver/Kconfig

@@ -0,0 +1,7 @@
+menu "RT-Thread rockchip RK3500 drivers"
+
+source "$BSP_DIR/driver/clk/Kconfig"
+source "$BSP_DIR/driver/uart8250/Kconfig"
+source "$BSP_DIR/driver/reset/Kconfig"
+source "$BSP_DIR/driver/hwtimer/Kconfig"
+endmenu

bsp/rockchip/rk3500/driver/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+list    = os.listdir(cwd)
+CPPPATH = [cwd]
+objs    = []
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+objs = objs + group
+
+Return('objs')

bsp/rockchip/rk3500/driver/board.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-3-08      GuEe-GUI     the first version
+ */
+#include <setup.h>
+#include <board.h>
+#include <psci.h>
+
+void rt_hw_board_init(void)
+{
+#if RT_VER_NUM < 0x50200
+    rt_fdt_commit_memregion_early(&(rt_region_t)
+    {
+        .name = "memheap",
+        .start = (rt_size_t)rt_kmem_v2p(HEAP_BEGIN),
+        .end = (rt_size_t)rt_kmem_v2p(HEAP_END),
+    }, RT_TRUE);
+#endif
+    rt_hw_common_setup();
+}
+
+void reboot(void)
+{
+    psci_system_reboot();
+}
+MSH_CMD_EXPORT(reboot, reboot...);
+
+void rt_hw_cpu_shutdown(void)
+{
+    psci_system_off();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, shutdown, shutdown...);

bsp/rockchip/rk3500/driver/board.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtdef.h>
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define HEAP_BEGIN  (void *)&__bss_end
+#define HEAP_END    ((void *)HEAP_BEGIN + 64 * 1024 * 1024)
+
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */

bsp/rockchip/rk3500/driver/clk/Kconfig

@@ -0,0 +1,15 @@
+menuconfig RT_CLK_ROCKCHIP
+    bool "Rockchip clock controller common"
+    select RT_USING_OFW
+    select RT_USING_RESET
+    default n
+
+config RT_CLK_ROCKCHIP_RK3568
+    bool "Rockchip RK3568 clock controller support"
+    depends on RT_CLK_ROCKCHIP
+    default n
+
+config RT_CLK_ROCKCHIP_RK3588
+    bool "Rockchip RK3588 clock controller support"
+    depends on RT_CLK_ROCKCHIP
+    default n

bsp/rockchip/rk3500/driver/clk/SConscript

@@ -0,0 +1,16 @@
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = []
+
+if GetDepend(['RT_CLK_ROCKCHIP_RK3568']):
+    src += ['clk-rk3568.c']
+
+if GetDepend(['RT_CLK_ROCKCHIP_RK3588']):
+    src += ['clk-rk3588.c']
+
+group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/rockchip/rk3500/driver/clk/clk-mmc-phase.c

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-3-08      GuEe-GUI     the first version
+ */
+
+#define ROCKCHIP_MMC_DELAY_SEL          RT_BIT(11)
+#define ROCKCHIP_MMC_DEGREE_OFFSET      1
+#define ROCKCHIP_MMC_DEGREE_MASK        (0x3 << ROCKCHIP_MMC_DEGREE_OFFSET)
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET    3
+#define ROCKCHIP_MMC_DELAYNUM_MASK      (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+/*
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+#define PSECS_PER_SEC 1000000000000LL
+
+#define RK3288_MMC_CLKGEN_DIV 2
+
+rt_inline rt_ubase_t rk_clk_mmc_recalc(rt_ubase_t parent_rate)
+{
+    return parent_rate / RK3288_MMC_CLKGEN_DIV;
+}
+
+static rt_err_t rk_clk_mmc_set_phase(rt_ubase_t rate, void *reg, int shift,
+        int degrees)
+{
+    rt_uint32_t raw_value, delay;
+    rt_uint8_t nineties, remainder, delay_num;
+
+    /*
+     * The below calculation is based on the output clock from
+     * MMC host to the card, which expects the phase clock inherits
+     * the clock rate from its parent, namely the output clock
+     * provider of MMC host. However, things may go wrong if
+     * (1) It is orphan.
+     * (2) It is assigned to the wrong parent.
+     *
+     * This check help debug the case (1), which seems to be the
+     * most likely problem we often face and which makes it difficult
+     * for people to debug unstable mmc tuning results.
+     */
+    if (!rate)
+    {
+        LOG_E("Invalid CLK rate in phase setting");
+
+        return -RT_EINVAL;
+    }
+
+    nineties = degrees / 90;
+    remainder = (degrees % 90);
+
+    /*
+     * Due to the inexact nature of the "fine" delay, we might
+     * actually go non-monotonic.  We don't go _too_ monotonic
+     * though, so we should be OK.  Here are options of how we may
+     * work:
+     *
+     * Ideally we end up with:
+     *   1.0, 2.0, ..., 69.0, 70.0, ...,  89.0, 90.0
+     *
+     * On one extreme (if delay is actually 44ps):
+     *   .73, 1.5, ..., 50.6, 51.3, ...,  65.3, 90.0
+     * The other (if delay is actually 77ps):
+     *   1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
+     *
+     * It's possible we might make a delay that is up to 25
+     * degrees off from what we think we're making.  That's OK
+     * though because we should be REALLY far from any bad range.
+     */
+
+    /*
+     * Convert to delay; do a little extra work to make sure we
+     * don't overflow 32-bit / 64-bit numbers.
+     */
+    delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
+    delay *= remainder;
+    delay = RT_DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
+                (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
+
+    delay_num = (rt_uint8_t)rt_min_t(rt_uint32_t, delay, 255);
+
+    raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+    raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+    raw_value |= nineties;
+    HWREG32(reg) = HIWORD_UPDATE(raw_value, 0x07ff, shift);
+
+    return RT_EOK;
+}
+
+static rt_base_t rk_clk_mmc_get_phase(rt_ubase_t rate, void *reg, int shift)
+{
+    rt_uint16_t degrees;
+    rt_uint32_t raw_value, delay_num = 0;
+
+    /* Constant signal, no measurable phase shift */
+    if (!rate)
+    {
+        return 0;
+    }
+
+    raw_value = HWREG32(reg) >> shift;
+    degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+    if (raw_value & ROCKCHIP_MMC_DELAY_SEL)
+    {
+        /* degrees/delaynum * 1000000 */
+        rt_ubase_t factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+                36 * (rate / 10000);
+
+        delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+        delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
+        degrees += RT_DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
+    }
+
+    return degrees % 360;
+}

bsp/rockchip/rk3500/driver/clk/clk-rk3568.h

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-3-08      GuEe-GUI     the first version
+ */
+
+#ifndef __ROCKCHIP_CLK3568_H__
+#define __ROCKCHIP_CLK3568_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "reset/reset.h"
+#include <stdlib.h>
+#include "../rockchip.h"
+
+#define HZ      100
+#define KHZ     1000
+#define MHZ     1000000
+#define OSC_HZ  (24 * MHZ)
+
+struct rk_cpu_rate_table
+{
+    rt_ubase_t rate;
+    rt_uint32_t aclk_div;
+    rt_uint32_t pclk_div;
+};
+
+struct rk_pll_rate_table
+{
+    rt_ubase_t rate;
+    rt_uint32_t nr;
+    rt_uint32_t nf;
+    rt_uint32_t no;
+    rt_uint32_t nb;
+
+    rt_uint32_t fbdiv;
+    rt_uint32_t postdiv1;
+    rt_uint32_t refdiv;
+    rt_uint32_t postdiv2;
+    rt_uint32_t dsmpd;
+    rt_uint32_t frac;
+};
+
+struct rk_pll_clock
+{
+    rt_uint32_t id;
+    rt_uint32_t con_offset;
+    rt_uint32_t mode_offset;
+    rt_uint32_t mode_shift;
+    rt_uint32_t lock_shift;
+    rt_uint32_t pll_flags;
+    struct rk_pll_rate_table *rate_table;
+    rt_uint32_t mode_mask;
+};
+
+struct rk_clk_gate
+{
+    const char *name;
+    const char *parent_name;
+
+    int con_idx;
+    int con_bit;
+};
+
+#define GATE(_id, _name,    \
+_pname, _con_idx, _con_bit) \
+[_id] =                     \
+{                           \
+    .name = _name,          \
+    .parent_name = _pname,  \
+    .con_idx = _con_idx,    \
+    .con_bit = _con_bit,    \
+}
+
+
+#define CPUCLK_RATE(_rate,  \
+    _aclk_div, _pclk_div)   \
+{                           \
+    .rate     = _rate##U,   \
+    .aclk_div = _aclk_div,  \
+    .pclk_div = _pclk_div,  \
+}
+
+#define PLL_RATE(_rate, _refdiv, _fbdiv,    \
+    _postdiv1, _postdiv2, _dsmpd, _frac)    \
+{                                           \
+    .rate     = _rate##U,                   \
+    .fbdiv    = _fbdiv,                     \
+    .postdiv1 = _postdiv1,                  \
+    .refdiv   = _refdiv,                    \
+    .postdiv2 = _postdiv2,                  \
+    .dsmpd    = _dsmpd,                     \
+    .frac     = _frac,                      \
+}
+
+#define PLL(_id, _con, _mode, _mshift,  \
+    _lshift, _pflags, _rtable)          \
+{                                       \
+    .id          = _id,                 \
+    .con_offset  = _con,                \
+    .mode_offset = _mode,               \
+    .mode_shift  = _mshift,             \
+    .lock_shift  = _lshift,             \
+    .pll_flags   = _pflags,             \
+    .rate_table  = _rtable,             \
+}
+
+#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
+
+#define ROCKCHIP_SOFTRST_HIWORD_MASK    RT_BIT(0)
+
+#endif /* __ROCKCHIP_CLK3568_H__ */

bsp/rockchip/rk3500/driver/clk/clk-rk3588.h

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-3-08      GuEe-GUI     the first version
+ */
+
+#ifndef __ROCKCHIP_CLK_H__
+#define __ROCKCHIP_CLK_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "reset/reset.h"
+#include <stdlib.h>
+#include "../rockchip.h"
+
+#define HZ      100
+#define KHZ     1000
+#define MHZ     1000000
+#define OSC_HZ  (24 * MHZ)
+
+struct rk_cpu_rate_table
+{
+    rt_ubase_t rate;
+    rt_uint32_t aclk_div;
+    rt_uint32_t pclk_div;
+};
+
+struct rk_pll_rate_table
+{
+    rt_ubase_t rate;
+    union {
+        struct {
+            /* for RK3066 */
+            rt_uint32_t nr;
+            rt_uint32_t nf;
+            rt_uint32_t no;
+            rt_uint32_t nb;
+        };
+        struct {
+            /* for RK3036/RK3399 */
+            rt_uint32_t fbdiv;
+            rt_uint32_t postdiv1;
+            rt_uint32_t refdiv;
+            rt_uint32_t postdiv2;
+            rt_uint32_t dsmpd;
+            rt_uint32_t frac;
+        };
+        struct {
+            /* for RK3588 */
+            rt_uint32_t m;
+            rt_uint32_t p;
+            rt_uint32_t s;
+            rt_uint32_t k;
+        };
+    };
+};
+
+enum rk_pll_type {
+    pll_rk3036,
+    pll_rk3066,
+    pll_rk3328,
+    pll_rk3366,
+    pll_rk3399,
+    pll_rk3588,
+};
+
+typedef rt_uint32_t rk_pll_type_t;
+
+struct rk_pll_clock
+{
+    rt_uint32_t id;
+    rt_uint32_t con_offset;
+    rt_uint32_t mode_offset;
+    rt_uint32_t mode_shift;
+    rt_uint32_t lock_shift;
+    rk_pll_type_t type;
+    rt_uint32_t pll_flags;
+    struct rk_pll_rate_table *rate_table;
+    rt_uint32_t mode_mask;
+};
+struct rk_clk_gate
+{
+    const char *name;
+    const char *parent_name;
+
+    int con_idx;
+    int con_bit;
+};
+
+#define GATE(_id, _name,    \
+_pname, _con_idx, _con_bit) \
+[_id] =                     \
+{                           \
+    .name = _name,          \
+    .parent_name = _pname,  \
+    .con_idx = _con_idx,    \
+    .con_bit = _con_bit,    \
+}
+
+
+#define CPUCLK_RATE(_rate,  \
+    _aclk_div, _pclk_div)   \
+{                           \
+    .rate     = _rate##U,   \
+    .aclk_div = _aclk_div,  \
+    .pclk_div = _pclk_div,  \
+}
+
+#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv,    \
+    _postdiv1, _postdiv2, _dsmpd, _frac)    \
+{                                           \
+    .rate     = _rate##U,                   \
+    .fbdiv    = _fbdiv,       \
+    .postdiv1 = _postdiv1,    \
+    .refdiv   = _refdiv,      \
+    .postdiv2 = _postdiv2,    \
+    .dsmpd    = _dsmpd,       \
+    .frac     = _frac,        \
+}
+
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k)  \
+{                                               \
+    .rate   = _rate##U,                         \
+    .p = _p,                        \
+    .m = _m,                        \
+    .s = _s,                        \
+    .k = _k,                        \
+}
+
+#define PLL(_type, _id, _con, _mode, _mshift,  \
+    _lshift, _pflags, _rtable)          \
+{                                       \
+    .type        = _type,               \
+    .id          = _id,                 \
+    .con_offset  = _con,                \
+    .mode_offset = _mode,               \
+    .mode_shift  = _mshift,             \
+    .lock_shift  = _lshift,             \
+    .pll_flags   = _pflags,             \
+    .rate_table  = _rtable,             \
+}
+
+#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
+
+#define ROCKCHIP_SOFTRST_HIWORD_MASK    RT_BIT(0)
+
+#endif /* __ROCKCHIP_CLK_H__ */

bsp/rockchip/rk3500/driver/clk/softrst.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-26     GuEe-GUI     first version
+ */
+
+struct rockchip_softrst
+{
+    void *regs;
+    int num_per_reg;
+    rt_uint8_t flags;
+
+    struct rt_spinlock lock;
+};
+
+static rt_err_t rockchip_softrst_assert(struct rt_reset_control *rstc)
+{
+    int bank, offset;
+    struct rockchip_softrst *softrst = rstc->rstcer->priv;
+
+    bank = rstc->id / softrst->num_per_reg;
+    offset = rstc->id % softrst->num_per_reg;
+
+    if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK)
+    {
+        HWREG32(softrst->regs + (bank * 4)) = RT_BIT(offset) | (RT_BIT(offset) << 16);
+    }
+    else
+    {
+        rt_uint32_t reg;
+        rt_ubase_t level;
+
+        level = rt_spin_lock_irqsave(&softrst->lock);
+
+        reg = HWREG32(softrst->regs + (bank * 4));
+        HWREG32(softrst->regs + (bank * 4)) = reg | RT_BIT(offset);
+
+        rt_spin_unlock_irqrestore(&softrst->lock, level);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rockchip_softrst_deassert(struct rt_reset_control *rstc)
+{
+    int bank, offset;
+    struct rockchip_softrst *softrst = rstc->rstcer->priv;
+
+    bank = rstc->id / softrst->num_per_reg;
+    offset = rstc->id % softrst->num_per_reg;
+
+    if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK)
+    {
+        HWREG32(softrst->regs + (bank * 4)) = (RT_BIT(offset) << 16);
+    }
+    else
+    {
+        rt_uint32_t reg;
+        rt_ubase_t level;
+
+        level = rt_spin_lock_irqsave(&softrst->lock);
+
+        reg = HWREG32(softrst->regs + (bank * 4));
+        HWREG32(softrst->regs + (bank * 4)) = reg & ~RT_BIT(offset);
+
+        rt_spin_unlock_irqrestore(&softrst->lock, level);
+    }
+
+    return RT_EOK;
+}
+
+static const struct rt_reset_control_ops rockchip_softrst_ops =
+{
+    .assert     = rockchip_softrst_assert,
+    .deassert   = rockchip_softrst_deassert,
+};
+
+static rt_err_t rk_register_softrst(struct rt_reset_controller *rstcer,
+        struct rt_ofw_node *np, void *regs, rt_uint8_t flags)
+{
+    rt_err_t err;
+    struct rockchip_softrst *softrst = rt_calloc(1, sizeof(*softrst));
+
+    if (!softrst)
+    {
+        return -RT_ENOMEM;
+    }
+
+    rstcer->priv = softrst;
+
+    rt_spin_lock_init(&softrst->lock);
+
+    softrst->regs = regs;
+    softrst->flags = flags;
+    softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 : 32;
+
+    rstcer->ofw_node = np;
+    rstcer->ops = &rockchip_softrst_ops;
+
+    if ((err = rt_reset_controller_register(rstcer)))
+    {
+        rt_free(softrst);
+    }
+
+    return err;
+}

bsp/rockchip/rk3500/driver/hwtimer/Kconfig

@@ -0,0 +1,5 @@
+config RT_HWTIMER_ROCKCHIP
+    bool "RockChip Timer"
+    depends on RT_USING_DM
+    depends on RT_USING_HWTIMER
+    default n

bsp/rockchip/rk3500/driver/hwtimer/SConscript

@@ -0,0 +1,13 @@
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = []
+
+if GetDepend(['RT_HWTIMER_ROCKCHIP']):
+    src += ['hwtimer-rockchip_timer.c']
+
+group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/rockchip/rk3500/driver/reset/Kconfig

@@ -0,0 +1,5 @@
+config RT_USING_RESET
+    bool "Using Reset Controller support"
+    depends on RT_USING_DM
+    select RT_USING_OFW
+    default n

bsp/rockchip/rk3500/driver/reset/SConscript

@@ -0,0 +1,13 @@
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = []
+
+if GetDepend(['RT_USING_RESET']):
+    src += ['reset.c']
+
+group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/rockchip/rk3500/driver/reset/reset.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-26     GuEe-GUI     first version
+ */
+
+#ifndef __RESET_H__
+#define __RESET_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <drivers/ofw.h>
+#include <drivers/clk.h>
+
+struct rt_reset_control_ops;
+
+struct rt_reset_controller
+{
+    rt_list_t list;
+    rt_list_t rstc_nodes;
+
+    const char *name;
+    const struct rt_reset_control_ops *ops;
+
+    struct rt_ofw_node *ofw_node;
+    void *priv;
+
+    struct rt_spinlock spinlock;
+};
+
+/*
+ * It seems that most reset controllers are coupled to CLK.
+ * So we need a generic extends object.
+ */
+struct rt_reset_controller_clk_node
+{
+    struct rt_clk_node parent;
+
+    struct rt_reset_controller rstcer;
+};
+
+struct rt_reset_control
+{
+    rt_list_t list;
+
+    struct rt_reset_controller *rstcer;
+
+    int id;
+    const char *con_id;
+    rt_bool_t is_array;
+    rt_bool_t deassert;
+
+    void *priv;
+};
+
+struct rt_reset_control_ops
+{
+    /*
+     * rt_ofw_cell_args return:
+     *  args[0] = rstc.id
+     */
+    rt_err_t    (*ofw_parse)(struct rt_reset_control *, struct rt_ofw_cell_args *args);
+    /* API */
+    rt_err_t    (*reset)(struct rt_reset_control *rstc);
+    rt_err_t    (*assert)(struct rt_reset_control *rstc);
+    rt_err_t    (*deassert)(struct rt_reset_control *rstc);
+    int         (*status)(struct rt_reset_control *rstc);
+};
+
+rt_err_t rt_reset_controller_register(struct rt_reset_controller *rstcer);
+rt_err_t rt_reset_controller_unregister(struct rt_reset_controller *rstcer);
+
+rt_err_t rt_reset_control_reset(struct rt_reset_control *rstc);
+rt_err_t rt_reset_control_assert(struct rt_reset_control *rstc);
+rt_err_t rt_reset_control_deassert(struct rt_reset_control *rstc);
+int rt_reset_control_status(struct rt_reset_control *rstc);
+
+rt_ssize_t rt_reset_control_get_count(struct rt_device *dev);
+struct rt_reset_control *rt_reset_control_get_array(struct rt_device *dev);
+struct rt_reset_control *rt_reset_control_get_by_index(struct rt_device *dev, int index);
+struct rt_reset_control *rt_reset_control_get_by_name(struct rt_device *dev, const char *name);
+void rt_reset_control_put(struct rt_reset_control *rstc);
+
+struct rt_reset_control *rt_ofw_get_reset_control_array(struct rt_ofw_node *np);
+struct rt_reset_control *rt_ofw_get_reset_control_by_index(struct rt_ofw_node *np, int index);
+struct rt_reset_control *rt_ofw_get_reset_control_by_name(struct rt_ofw_node *np, const char *name);
+
+#endif /* __RESET_H__ */

bsp/rockchip/rk3500/driver/rockchip.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-3-08      GuEe-GUI     the first version
+ */
+
+#ifndef __ROCKCHIP_H__
+#define __ROCKCHIP_H__
+
+#include <rthw.h>
+
+#define rk_clrsetreg(addr, clr, set)    HWREG32(addr) = (((clr) | (set)) << 16 | (set))
+#define rk_clrreg(addr, clr)            HWREG32(addr) = ((clr) << 16)
+#define rk_setreg(addr, set)            HWREG32(addr) = ((set) << 16 | (set))
+
+#define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
+
+#endif /* __ROCKCHIP_H__ */

bsp/rockchip/rk3500/driver/uart8250/8250.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-16     GuEe-GUI     first version
+ */
+
+#ifndef __SERIAL_8250_H__
+#define __SERIAL_8250_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <ioremap.h>
+#include "regs.h"
+#include "serial_dm.h"
+
+enum
+{
+    PORT_IO,
+    PORT_MMIO,
+    PORT_MMIO16,
+    PORT_MMIO32,
+    PORT_MMIO32BE,
+};
+
+struct serial8250
+{
+    struct rt_serial_device parent;
+    struct rt_clk *clk;
+
+    int irq;
+    void *base;
+    rt_size_t size;
+    rt_uint32_t freq;       /* frequency */
+    rt_uint32_t regshift;   /* reg offset shift */
+    rt_uint8_t iotype;      /* io access style */
+
+    struct rt_spinlock spinlock;
+
+    rt_uint32_t (*serial_in)(struct serial8250 *, int offset);
+    void (*serial_out)(struct serial8250 *, int offset, int value);
+    rt_err_t (*handle_irq)(struct serial8250 *, int irq);
+
+    /* Free all resource (and parent) by child */
+    void (*remove)(struct serial8250 *);
+    void *data;
+};
+
+#define serial8250_alloc(obj) rt_calloc(1, sizeof(typeof(*obj)))
+#define raw_to_serial8250(raw_serial) rt_container_of(raw_serial, struct serial8250, parent)
+
+rt_err_t serial8250_config(struct serial8250 *serial, const char *options);
+rt_err_t serial8250_setup(struct serial8250 *serial);
+rt_err_t serial8250_remove(struct serial8250 *serial);
+
+rt_uint32_t serial8250_in(struct serial8250 *serial, int offset);
+void serial8250_out(struct serial8250 *serial, int offset, int value);
+
+rt_err_t serial8250_uart_configure(struct rt_serial_device *raw_serial, struct serial_configure *cfg);
+rt_err_t serial8250_uart_control(struct rt_serial_device *raw_serial, int cmd, void *arg);
+int serial8250_uart_putc(struct rt_serial_device *raw_serial, char c);
+int serial8250_uart_getc(struct rt_serial_device *raw_serial);
+
+int serial8250_early_putc(struct rt_serial_device *raw_serial, char c);
+rt_err_t serial8250_early_fdt_setup(struct serial8250 *serial, struct rt_fdt_earlycon *con, const char *options);
+
+extern struct serial8250 early_serial8250;
+extern const struct rt_uart_ops serial8250_uart_ops;
+
+#endif /* __SERIAL_8250_H__ */

bsp/rockchip/rk3500/driver/uart8250/Kconfig

@@ -0,0 +1,3 @@
+config RT_SERIAL_8250
+    bool "8250 Serila Family"
+    default n

bsp/rockchip/rk3500/driver/uart8250/SConscript

@@ -0,0 +1,13 @@
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+
+src     = ['core.c', 'early.c']
+
+if GetDepend(['RT_SERIAL_8250']):
+    src += ['8250-dw.c']
+    src += ['fiq-debugger.c']
+
+group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/rockchip/rk3500/driver/uart8250/early.c

@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-16     GuEe-GUI     first version
+ */
+
+#include "8250.h"
+
+struct serial8250 early_serial8250 = { 0 };
+
+static rt_uint32_t serial8250_early_in(struct serial8250 *serial, int offset)
+{
+    return serial8250_in(serial, offset);
+}
+
+static void serial8250_early_out(struct serial8250 *serial, int offset, int value)
+{
+    serial8250_out(serial, offset, value);
+}
+
+int serial8250_early_putc(struct rt_serial_device *raw_serial, char c)
+{
+    if (raw_serial)
+    {
+        /* FIFO and shifting register empty */
+        const int uart_lsr_both_empty = (UART_LSR_TEMT | UART_LSR_THRE);
+        struct serial8250 *serial = rt_container_of(raw_serial, struct serial8250, parent);
+
+        serial8250_early_out(serial, UART_TX, c);
+
+        while ((serial8250_early_in(serial, UART_LSR) & uart_lsr_both_empty) != uart_lsr_both_empty)
+        {
+            rt_hw_cpu_relax();
+        }
+    }
+
+    return 1;
+}
+
+static void init_serial(struct serial8250 *serial)
+{
+    unsigned char c;
+    rt_uint32_t ier, divisor;
+
+    serial8250_early_out(serial, UART_LCR, 0x3);    /* 8n1 */
+    ier = serial8250_early_in(serial, UART_IER);
+    serial8250_early_out(serial, UART_IER, ier & UART_IER_UUE); /* no interrupt */
+    serial8250_early_out(serial, UART_FCR, 0);      /* no fifo */
+    serial8250_early_out(serial, UART_MCR, 0x3);    /* DTR + RTS */
+
+    if (serial->freq)
+    {
+        divisor = RT_DIV_ROUND_CLOSEST(serial->freq, 16 * serial->parent.config.baud_rate);
+        c = serial8250_early_in(serial, UART_LCR);
+        serial8250_early_out(serial, UART_LCR, c | UART_LCR_DLAB);
+        serial8250_early_out(serial, UART_DLL, divisor & 0xff);
+        serial8250_early_out(serial, UART_DLM, (divisor >> 8) & 0xff);
+        serial8250_early_out(serial, UART_LCR, c & ~UART_LCR_DLAB);
+    }
+}
+
+static void serial8250_early_kick(struct rt_fdt_earlycon *con, int why)
+{
+    struct serial8250 *serial = raw_to_serial8250(con->data);
+
+    switch (why)
+    {
+    case FDT_EARLYCON_KICK_UPDATE:
+        serial->base = rt_ioremap((void *)con->mmio, con->size);
+        break;
+
+    case FDT_EARLYCON_KICK_COMPLETED:
+        rt_iounmap(serial->base);
+        break;
+
+    default:
+        break;
+    }
+}
+
+rt_err_t serial8250_early_fdt_setup(struct serial8250 *serial, struct rt_fdt_earlycon *con, const char *options)
+{
+    rt_err_t ret = RT_EOK;
+
+    if (!serial->base && con)
+    {
+        serial8250_config(serial, options);
+        con->mmio = (rt_ubase_t)serial->base;
+        con->size = serial->size;
+    }
+
+    if (serial->base && con)
+    {
+        serial->base = rt_ioremap_early((void *)serial->base, serial->size);
+    }
+
+    if (serial->base && con)
+    {
+        con->console_putc = (typeof(con->console_putc))&serial8250_early_putc;
+        con->console_kick = serial8250_early_kick;
+        con->data = &serial->parent;
+
+        if (!serial->parent.config.baud_rate)
+        {
+            /* assume the device was initialized, only mask interrupts */
+            rt_uint32_t ier = serial8250_early_in(serial, UART_IER);
+            serial8250_early_out(serial, UART_IER, ier & UART_IER_UUE);
+        }
+        else
+        {
+            init_serial(serial);
+        }
+    }
+    else
+    {
+        ret = -RT_ERROR;
+    }
+
+    return ret;
+}
+
+static void common_init(struct serial8250 *serial, struct rt_fdt_earlycon *con)
+{
+    serial->base = (void *)con->mmio;
+    serial->size = con->size;
+    serial->iotype = PORT_MMIO32;
+}
+
+static rt_err_t common_early_setup(struct rt_fdt_earlycon *con, const char *options)
+{
+    struct serial8250 *serial = &early_serial8250;
+
+    common_init(serial, con);
+    serial->regshift = 2;
+    fdt_getprop_u32(con->fdt, con->nodeoffset, "reg-shift", &serial->regshift, RT_NULL);
+
+    return serial8250_early_fdt_setup(serial, con, options);
+}
+RT_FDT_EARLYCON_EXPORT(bcm2835aux, "uart8250", "brcm,bcm2835-aux-uart", common_early_setup);
+RT_FDT_EARLYCON_EXPORT(tegra20, "uart8250", "nvidia,tegra20-uart", common_early_setup);
+RT_FDT_EARLYCON_EXPORT(dw8250, "uart8250", "snps,dw-apb-uart", common_early_setup);
+RT_FDT_EARLYCON_EXPORT(ns16550a, "uart8250", "ns16550a", common_early_setup);
+RT_FDT_EARLYCON_EXPORT(ns16550, "uart8250", "ns16550", common_early_setup);
+
+#ifdef RT_USING_8250_OMAP
+static rt_err_t omap8250_early_setup(struct rt_fdt_earlycon *con, const char *options)
+{
+    struct serial8250 *serial = &early_serial8250;
+
+    common_init(serial, con);
+    serial->regshift = 2;
+
+    return serial8250_early_fdt_setup(serial, con, options);
+}
+RT_FDT_EARLYCON_EXPORT(omap8250, "uart8250", "ti,omap2-uart", omap8250_early_setup);
+RT_FDT_EARLYCON_EXPORT(omap8250, "uart8250", "ti,omap3-uart", omap8250_early_setup);
+RT_FDT_EARLYCON_EXPORT(omap8250, "uart8250", "ti,omap4-uart", omap8250_early_setup);
+#endif /* RT_USING_8250_OMAP */

bsp/rockchip/rk3500/driver/uart8250/serial_dm.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-16     GuEe-GUI     first version
+ */
+
+#ifndef __SERIAL_DM_H__
+#define __SERIAL_DM_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <posix/string.h>
+
+int serial_dev_set_name(struct rt_serial_device *sdev);
+
+void *serial_base_from_args(char *str);
+struct serial_configure serial_cfg_from_args(char *str);
+
+#define serial_for_each_args(arg, args)                                 \
+    for (char *context = (arg = (typeof(arg))args, (void *)RT_NULL),    \
+        *context_end = strchrnul((char *)args, ' ');                 \
+         (arg = strtok_r(arg, ",", &context)) && arg < context_end;     \
+         arg = RT_NULL)
+
+#endif /* __SERIAL_DM_H__ */

bsp/rockchip/rk3500/rtconfig.py

@@ -0,0 +1,57 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..')
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
+
+EXEC_PATH   = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
+
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    CPP     = PREFIX + 'cpp'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always'
+    CPPFLAGS= ' -E -P -x assembler-with-cpp'
+    CFLAGS = DEVICE + ' -Wall -Wno-cpp'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--no-warn-rwx-segments -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        CPPFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -ggdb'
+        CPPFLAGS += ' -O2 -ggdb'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'md5sum rtthread.bin\n'