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Merge pull request #4089 from thread-liu/step4-ev1

Browse Source 
[add] complicated dirvers for STM32MP157A-EV1 board
This commit is contained in:
Bernard Xiong
2020-12-02 23:39:29 +08:00
committed by GitHub
parent dae7f1af9b c5612fd2e1
commit 926a06d347
17 changed files with 4333 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/stm32/libraries/STM32MPxx_HAL/SConscript
+1 -11
View File
@@ -35,10 +35,6 @@ if GetDepend(['RT_USING_SERIAL']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c']
#if GetDepend(['RT_USING_SPI']):
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c']
if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pccard.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pcd.c']
@@ -49,11 +45,6 @@ if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
if GetDepend(['RT_USING_CAN']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_can.c']
#if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c']
# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c']
if GetDepend(['BSP_USING_ETH']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c']
@@ -73,10 +64,9 @@ if GetDepend(['RT_USING_WDT']):
if GetDepend(['RT_USING_SDIO']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_delayblock.c']
if GetDepend(['RT_USING_AUDIO']):
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2s_ex.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai.c']
src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c']
bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h
+4 -2
View File
@@ -57,8 +57,8 @@
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
@@ -153,6 +153,8 @@
#define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#define USE_SD_TRANSCEIVER 1U
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
+433 -1
View File
@@ -26,7 +26,9 @@
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
DMA_HandleTypeDef hdma_sai2_a = {0};
DMA_HandleTypeDef hdma_sai2_b = {0};
DMA_HandleTypeDef hdma_sai4_a = {0};
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
@@ -965,6 +967,436 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c)
}
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspInit 0 */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE END SDMMC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDMMC1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
/**SDMMC1 GPIO Configuration
PB9 ------> SDMMC1_CDIR
PC7 ------> SDMMC1_D123DIR
PC8 ------> SDMMC1_D0
PC9 ------> SDMMC1_D1
PC10 ------> SDMMC1_D2
PC11 ------> SDMMC1_D3
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
PE4 ------> SDMMC1_CKIN
PF2 ------> SDMMC1_D0DIR
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_SDIO1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Alternate = GPIO_AF8_SDIO1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
__HAL_RCC_SDMMC1_FORCE_RESET();
__HAL_RCC_SDMMC1_RELEASE_RESET();
/* SDMMC1 interrupt Init */
HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspInit 1 */
/* USER CODE END SDMMC1_MspInit 1 */
}
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspInit 0 */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE END SDMMC2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDMMC2_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/**SDMMC2 GPIO Configuration
PB14 ------> SDMMC2_D0
PB15 ------> SDMMC2_D1
PB3 ------> SDMMC2_D2
PB4 ------> SDMMC2_D3
PA8 ------> SDMMC2_D4
PA9 ------> SDMMC2_D5
PE5 ------> SDMMC2_D6
PD3 ------> SDMMC2_D7
PE3 ------> SDMMC2_CK
PG6 ------> SDMMC2_CMD
*/
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
__HAL_RCC_SDMMC2_FORCE_RESET();
__HAL_RCC_SDMMC2_RELEASE_RESET();
/* SDMMC2 interrupt Init */
HAL_NVIC_SetPriority(SDMMC2_IRQn, 0X05, 0);
HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
/* USER CODE BEGIN SDMMC2_MspInit 1 */
/* USER CODE END SDMMC2_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDMMC1)
{
/* USER CODE BEGIN SDMMC1_MspDeInit 0 */
/* USER CODE END SDMMC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC1_CLK_DISABLE();
/**SDMMC1 GPIO Configuration
PB9 ------> SDMMC1_CDIR
PC7 ------> SDMMC1_D123DIR
PC8 ------> SDMMC1_D0
PC9 ------> SDMMC1_D1
PC10 ------> SDMMC1_D2
PC11 ------> SDMMC1_D3
PC12 ------> SDMMC1_CK
PD2 ------> SDMMC1_CMD
PE4 ------> SDMMC1_CKIN
PF2 ------> SDMMC1_D0DIR
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2);
/* SDMMC1 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
/* USER CODE BEGIN SDMMC1_MspDeInit 1 */
/* USER CODE END SDMMC1_MspDeInit 1 */
}
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspDeInit 0 */
/* USER CODE END SDMMC2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC2_CLK_DISABLE();
/**SDMMC2 GPIO Configuration
PB14 ------> SDMMC2_D0
PB15 ------> SDMMC2_D1
PB3 ------> SDMMC2_D2
PB4 ------> SDMMC2_D3
PA8 ------> SDMMC2_D4
PA9 ------> SDMMC2_D5
PE5 ------> SDMMC2_D6
PD3 ------> SDMMC2_D7
PE3 ------> SDMMC2_CK
PG6 ------> SDMMC2_CMD
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6);
/* SDMMC2 interrupt DeInit */
HAL_NVIC_DisableIRQ(SDMMC2_IRQn);
/* USER CODE BEGIN SDMMC2_MspDeInit 1 */
/* USER CODE END SDMMC2_MspDeInit 1 */
}
}
void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/* SAI2 */
if (hsai->Instance==SAI2_Block_A)
{
/* Peripheral clock enable */
if(IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_SAI2_CLK_ENABLE();
/**SAI2_A_Block_A GPIO Configuration
PE0 ------> SAI2_MCLK_A
PI7 ------> SAI2_FS_A
PI5 ------> SAI2_SCK_A
PI6 ------> SAI2_SD_A
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_5|GPIO_PIN_6;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
/* Configure DMA used for SAI2 */
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
hdma_sai2_a.Instance = DMA1_Stream0;
hdma_sai2_a.Init.Request = DMA_REQUEST_SAI2_A;
hdma_sai2_a.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_sai2_a.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai2_a.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai2_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai2_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai2_a.Init.Mode = DMA_CIRCULAR;
hdma_sai2_a.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai2_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai2_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai2_a.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai2_a.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai2_a);
if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmatx,hdma_sai2_a);
__HAL_DMA_ENABLE(&hdma_sai2_a);
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
}
if (hsai->Instance==SAI2_Block_B)
{
/* Peripheral clock enable */
if (IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_SAI2_CLK_ENABLE();
/**SAI2_B_Block_B GPIO Configuration
PE12 ------> SAI2_MCLK_B
PE13 ------> SAI2_FS_B
PE14 ------> SAI2_SCK_B
PF11 ------> SAI2_SD_B
*/
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI2;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
/* Peripheral DMA init*/
hdma_sai2_b.Instance = DMA1_Stream1;
hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B;
hdma_sai2_b.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_sai2_b.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai2_b.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai2_b.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai2_b.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai2_b.Init.Mode = DMA_CIRCULAR;
hdma_sai2_b.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai2_b.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai2_b);
if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
__HAL_DMA_ENABLE(&hdma_sai2_b);
HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
}
/* SAI4 */
if(hsai->Instance==SAI4_Block_A)
{
/* Peripheral clock enable */
if(IS_ENGINEERING_BOOT_MODE())
{
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI4;
PeriphClkInit.Sai4ClockSelection = RCC_SAI4CLKSOURCE_PLL3_Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_SAI4_CLK_ENABLE();
/**SAI4_A_Block_A GPIO Configuration
PB5 ------> SAI4_SD_A
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_SAI4;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral DMA init*/
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
hdma_sai4_a.Instance = DMA1_Stream2;
hdma_sai4_a.Init.Request = DMA_REQUEST_SAI4_A;
hdma_sai4_a.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_sai4_a.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sai4_a.Init.MemInc = DMA_MINC_ENABLE;
hdma_sai4_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_sai4_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_sai4_a.Init.Mode = DMA_CIRCULAR;
hdma_sai4_a.Init.Priority = DMA_PRIORITY_HIGH;
hdma_sai4_a.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
hdma_sai4_a.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_sai4_a.Init.MemBurst = DMA_MBURST_SINGLE;
hdma_sai4_a.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_DeInit(&hdma_sai4_a);
if (HAL_DMA_Init(&hdma_sai4_a) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hsai,hdmatx,hdma_sai4_a);
__HAL_DMA_ENABLE(&hdma_sai4_a);
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0x02, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
}
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
bsp/stm32/stm32mp157a-st-ev1/board/Kconfig
+42 -3
View File
@@ -33,6 +33,45 @@ menu "Onboard Peripheral Drivers"
select RT_USING_OPENAMP
default n
config BSP_USING_GBE
bool "Enable Ethernet"
default n
select RT_USING_LWIP
menuconfig BSP_USING_SDMMC
bool "Enable SDMMC"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select BSP_USING_PMIC
if BSP_USING_SDMMC
menuconfig BSP_USING_SD_CARD
bool "Enable sd card"
default n
if BSP_USING_SD_CARD
config SD_USING_DFS
bool "sd card fatfs"
default n
endif
menuconfig BSP_USING_EMMC
bool "Enable eMMC (32 Gbits)"
default n
if BSP_USING_EMMC
config EMMC_USING_DFS
bool "emmc card fatfs"
default n
endif
endif
config BSP_USING_AUDIO
bool "Enable Audio Device (WM8994)"
select RT_USING_AUDIO
select BSP_USING_PMIC
select BSP_USING_I2C
select BSP_USING_I2C2
default n
endmenu
menu "On-chip Peripheral Drivers"
@@ -48,11 +87,11 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_UART
config BSP_USING_UART3
bool "Enable UART3"
default y
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
@@ -62,7 +101,7 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART4
bool "Enable UART4"
default y
default n
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
bsp/stm32/stm32mp157a-st-ev1/board/SConscript
+16
View File
@@ -19,6 +19,19 @@ if GetDepend(['BSP_USING_PMIC']):
if GetDepend(['BSP_USING_NAND']):
src += Glob('ports/drv_nand.c')
if GetDepend(['BSP_USING_GBE']):
src += Glob('ports/eth/drv_eth.c')
if GetDepend(['BSP_USING_SD_CARD']):
src += Glob('ports/drv_sdcard.c')
if GetDepend(['BSP_USING_EMMC']):
src += Glob('ports/drv_emmc.c')
if GetDepend(['BSP_USING_AUDIO']):
src += Glob('ports/drv_wm8994.c')
src += Glob('ports/drv_sound.c')
if GetDepend(['BSP_USING_OPENAMP']):
src += Glob('CubeMX_Config/CM4/Src/ipcc.c')
src += Glob('CubeMX_Config/CM4/Src/openamp.c')
@@ -45,6 +58,9 @@ if GetDepend(['BSP_USING_OPENAMP']):
path += [cwd + '/ports/OpenAMP/virtual_driver']
path += [cwd + '/CubeMX_Config/CM4/Inc']
if GetDepend(['BSP_USING_GBE']):
path += [cwd + '/ports/eth']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
bsp/stm32/stm32mp157a-st-ev1/board/board.h
+1 -1
View File
@@ -32,7 +32,7 @@ extern "C" {
#if defined(BSP_USING_OPENAMP)
#define STM32_SRAM_BEGIN (uint32_t)0x10020000
#define STM32_SRAM_BEGIN (uint32_t)0x10030000
#else
#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
#endif
bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf
+1 -6
View File
@@ -5,7 +5,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_text_start__ = 0x10000000;
define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF;
define symbol __ICFEDIT_region_text_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_data_start__ = 0x10030000;
define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF;
/*-Sizes-*/
@@ -28,11 +28,6 @@ define symbol __OPENAMP_region_size__ = 0x8000;
export symbol __OPENAMP_region_start__;
export symbol __OPENAMP_region_size__;
define symbol __SDMMC_region_start__ = 0x10048000;
define symbol __SDMMC_region_size__ = 0x1FFFF;
export symbol __SDMMC_region_start__;
export symbol __SDMMC_region_size__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c
+37 -1
View File
@@ -12,6 +12,7 @@
#ifdef BSP_USING_OPENAMP
#include <finsh.h>
#include <drv_openamp.h>
#include <openamp.h>
#include <virt_uart.h>
@@ -235,7 +236,10 @@ int rt_hw_openamp_init(void)
rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL);
rt_console_set_device("openamp");
if (RT_CONSOLE_DEVICE_NAME == "openamp")
{
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}
return RT_EOK;
}
@@ -289,4 +293,36 @@ static int creat_openamp_thread(void)
}
INIT_APP_EXPORT(creat_openamp_thread);
#ifdef FINSH_USING_MSH
static int console(int argc, char **argv)
{
rt_err_t result = RT_EOK;
if (argc > 1)
{
if (!strcmp(argv[1], "set"))
{
rt_kprintf("console change to %s\n", argv[2]);
rt_console_set_device(argv[2]);
finsh_set_device(argv[2]);
}
else
{
rt_kprintf("Unknown command. Please enter 'console' for help\n");
result = -RT_ERROR;
}
}
else
{
rt_kprintf("Usage: \n");
rt_kprintf("console set <name> - change console by name\n");
result = -RT_ERROR;
}
return result;
}
MSH_CMD_EXPORT(console, set console name);
#endif /* FINSH_USING_MSH */
#endif
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c
+593
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File diff suppressed because it is too large Load Diff
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h
+104
View File
@@ -0,0 +1,104 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-16 thread-liu first version
*/
#ifndef __DRV_EMMC_H__
#define __DRV_EMMC_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include <string.h>
#include <drivers/mmcsd_core.h>
#include <drivers/sdio.h>
#define SDIO_BUFF_SIZE 4096
#ifndef EMMC_BASE_ADDRESS
#define EMMC_BASE_ADDRESS (SDMMC2)
#endif
#ifndef EMMC_CLOCK_FREQ
#define EMMC_CLOCK_FREQ (99U * 1000 * 1000)
#endif
#ifndef EMMC_MAX_FREQ
#define EMMC_MAX_FREQ (50 * 1000 * 1000)
#endif
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define SDMMC_ERRORS \
(SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
#define SDIO_MASKR_ALL \
(SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU)
struct stm32_sdio
{
volatile rt_uint32_t power; /* offset 0x00 */
volatile rt_uint32_t clkcr; /* offset 0x04 */
volatile rt_uint32_t arg; /* offset 0x08 */
volatile rt_uint32_t cmd; /* offset 0x0C */
volatile rt_uint32_t respcmd; /* offset 0x10 */
volatile rt_uint32_t resp1; /* offset 0x14 */
volatile rt_uint32_t resp2; /* offset 0x18 */
volatile rt_uint32_t resp3; /* offset 0x1C */
volatile rt_uint32_t resp4; /* offset 0x20 */
volatile rt_uint32_t dtimer; /* offset 0x24 */
volatile rt_uint32_t dlen; /* offset 0x28 */
volatile rt_uint32_t dctrl; /* offset 0x2C */
volatile rt_uint32_t dcount; /* offset 0x30 */
volatile rt_uint32_t sta; /* offset 0x34 */
volatile rt_uint32_t icr; /* offset 0x38 */
volatile rt_uint32_t mask; /* offset 0x3C */
volatile rt_uint32_t acktimer; /* offset 0x40 */
volatile rt_uint32_t reserved0[3]; /* offset 0x44 ~ 0x4C */
volatile rt_uint32_t idmatrlr; /* offset 0x50 */
volatile rt_uint32_t idmabsizer; /* offset 0x54 */
volatile rt_uint32_t idmabase0r; /* offset 0x58 */
volatile rt_uint32_t idmabase1r; /* offset 0x5C */
volatile rt_uint32_t reserved1[1]; /* offset 0x60 */
volatile rt_uint32_t idmalar;
volatile rt_uint32_t idmabar;
volatile rt_uint32_t reserved2[5];
volatile rt_uint32_t fifo;
volatile rt_uint32_t reserved3[220];
volatile rt_uint32_t verr;
volatile rt_uint32_t ipidr;
volatile rt_uint32_t sidr;
};
typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
struct stm32_sdio_des
{
struct stm32_sdio *hw_sdio;
sdio_clk_get clk_get;
};
/* stm32 sdio dirver class */
struct stm32_sdio_class
{
struct stm32_sdio_des *des;
const struct stm32_sdio_config *cfg;
struct rt_mmcsd_host host;
};
extern void stm32_mmcsd_change(void);
#endif /* __DRV_SDIO_H__ */
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c
+3 -1
View File
@@ -19,6 +19,8 @@
#define LOG_TAG "drv.pmic"
#include <drv_log.h>
#define I2C_NAME "i2c3"
static struct rt_i2c_bus_device *pmic_dev = RT_NULL;
/* i2c read reg */
@@ -884,7 +886,7 @@ static int pmic_init(void)
{
BSP_PMIC_MspInit();
result = rt_hw_pmic_init("i2c3");
result = rt_hw_pmic_init(I2C_NAME);
if(result != RT_EOK)
{
LOG_D("stpmic init failed: %02x", result);
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c
+413
View File
@@ -0,0 +1,413 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-04 thread-liu the first version
*/
#include "board.h"
#if defined(BSP_USING_SD_CARD)
#include <dfs_fs.h>
#define DRV_DEBUG
//#define SDMMC_TX_DUMP
//#define SDMMC_RX_DUMP
#define LOG_TAG "drv.sdmmc"
#include <drv_log.h>
static SD_HandleTypeDef SDCARD_Handler = {0};
static HAL_SD_CardInfoTypeDef SDCardInfo = {0};
struct stm32_sd
{
struct rt_device sdcard;
struct rt_semaphore sd_lock;
volatile rt_uint8_t write_flage;
volatile rt_uint8_t read_flage;
volatile rt_base_t level;
};
static struct stm32_sd sd_device;
#define SD_TIMEOUT ((uint32_t)30 * 1000)
#define DETECT_PIN GET_PIN(G, 1)
#define LDO_PIN GET_PIN(F, 14)
struct rt_completion tx_comp;
struct rt_completion rx_comp;
/* SYSRAM SDMMC1/2 accesses */
#define SDIO_BUFF_SIZE 512
#if defined(__CC_ARM) || defined(__CLANG_ARM)
__attribute__((at(0x2FFC0000)))
#elif defined ( __GNUC__ )
__attribute__((at(0x2FFC0000)))
#elif defined(__ICCARM__)
#pragma location = 0x2FFC0000
#endif
static rt_uint32_t cache_buf[SDIO_BUFF_SIZE];
#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
{
unsigned char *buf = (unsigned char *)ptr;
int i, j;
for (i = 0; i < buflen; i += 16)
{
rt_kprintf("%08X: ", i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%02X ", buf[i + j]);
else
rt_kprintf(" ");
rt_kprintf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
rt_kprintf("\n");
}
}
#endif
static rt_err_t rt_hw_sd_is_detected(void)
{
return rt_pin_read(DETECT_PIN);
}
static rt_err_t rt_hw_sd_init(void)
{
/* sd ldo*/
rt_pin_mode(LDO_PIN, PIN_MODE_OUTPUT);
/* sd detect */
rt_pin_mode(DETECT_PIN, PIN_MODE_INPUT_PULLUP);
/* judge we have a sd card */
if (rt_hw_sd_is_detected() != 0x00)
{
LOG_E("can't find sd card!");
return RT_ERROR;
}
SDCARD_Handler.Instance = SDMMC1;
HAL_SD_DeInit(&SDCARD_Handler);
/* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock
else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV].
SDMMC Kernel Clock = 99MHz, SDMMC Clock frequency = 50MHz */
SDCARD_Handler.Init.ClockDiv = 1;
SDCARD_Handler.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
SDCARD_Handler.Init.ClockEdge = SDMMC_CLOCK_EDGE_FALLING;
SDCARD_Handler.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
SDCARD_Handler.Init.BusWide = SDMMC_BUS_WIDE_4B;
if (HAL_SD_Init(&SDCARD_Handler) != RT_EOK)
{
LOG_E("sd device init error!");
return RT_ERROR;
}
if (HAL_SD_ConfigWideBusOperation(&SDCARD_Handler, SDMMC_BUS_WIDE_4B) != RT_EOK)
{
LOG_E("sd bus config error!");
return RT_ERROR;
}
if (HAL_SD_GetCardInfo(&SDCARD_Handler, &SDCardInfo) != RT_EOK)
{
LOG_E("sd get card info error!");
return RT_ERROR;
}
rt_thread_mdelay(100);
if(HAL_SD_GetCardState(&SDCARD_Handler) != HAL_SD_CARD_TRANSFER)
{
LOG_E("sd get card state error!");
return RT_ERROR;
}
return RT_EOK;
}
static void rt_hw_sd_deinit(void)
{
HAL_SD_DeInit(&SDCARD_Handler);
}
static rt_err_t sdcard_wait_ok(void)
{
rt_uint32_t tick_start = 0;
tick_start = rt_tick_get();
while ((rt_tick_get() - tick_start) < SD_TIMEOUT)
{
if (HAL_SD_GetCardState(&SDCARD_Handler) == HAL_SD_CARD_TRANSFER)
{
return HAL_OK;
}
}
return HAL_ERROR;
}
void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
{
if (status == SET)
{
rt_pin_write(LDO_PIN, PIN_HIGH);
}
else
{
rt_pin_write(LDO_PIN, PIN_LOW);
}
}
static rt_err_t rt_sdcard_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
if (rt_sem_init(&sd->sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
{
LOG_E("init sd lock semaphore failed\n");
}
return RT_EOK;
}
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
/**
* @brief Reads Sector(s)
* @param dev : sd dev
* @param sector: Sector address (LBA) Data buffer to store read data
* @param *buffer: Data buffer to store read data
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, rt_size_t count)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
rt_uint8_t ret = RT_EOK;
volatile uint32_t tickstart = 0;
sd->read_flage = 0;
rt_memset(cache_buf, 0x00, BLOCKSIZE * count);
ret = sdcard_wait_ok();
if (ret != RT_EOK)
{
LOG_D("sdmmc busy!");
return 0;
}
rt_sem_take(&sd->sd_lock, RT_WAITING_FOREVER);
ret = HAL_SD_ReadBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (uint32_t)sector, count);
rt_sem_release(&sd->sd_lock);
/* Wait that writing process is completed or a timeout occurs */
tickstart = rt_tick_get();
if (ret == HAL_OK)
{
while ((sd->read_flage == 0) && (rt_tick_get() - tickstart) < SD_TIMEOUT)
{
}
/* over time */
if (sd->read_flage == 0)
{
return 0;
}
else
{
sd->read_flage = 0;
tickstart = rt_tick_get();
while ((rt_tick_get() - tickstart) < SD_TIMEOUT)
{
if (sdcard_wait_ok() == RT_EOK)
{
sd->level=rt_hw_interrupt_disable();
rt_memcpy((rt_uint8_t *)(buffer), cache_buf, BLOCKSIZE * count);
rt_hw_interrupt_enable(sd->level);
#if defined(SDMMC_RX_DUMP)
rt_kprintf("\nsd rx: \n");
dump_hex(cache_buf, BLOCKSIZE * count);
#endif
return count;
}
}
}
}
return 0;
}
/**
* @brief Writes block(s) to a specified address in an SD card, in DMA mode.
* @param dev SD device
* @param sector Block index from where data is to be written P
* @param *buffer Pointer to the buffer that will contain the data to transmit
* @param count Number of SD blocks to write
* @retval BSP status
*/
static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *buffer, rt_size_t count)
{
RT_ASSERT(dev != RT_NULL);
struct stm32_sd *sd = (struct stm32_sd *)dev;
rt_uint32_t i = 0;
rt_uint8_t ret = RT_EOK;
for (i = 0; i < count; i++)
{
sd->level = rt_hw_interrupt_disable();
rt_memset(cache_buf, 0x00, BLOCKSIZE);
rt_memcpy(cache_buf, (rt_uint32_t *)((uintptr_t)buffer + BLOCKSIZE * i), BLOCKSIZE);
rt_hw_interrupt_enable(sd->level);
#if defined(SDMMC_TX_DUMP)
rt_kprintf("\nsd tx: \n");
dump_hex(cache_buf, BLOCKSIZE);
#endif
ret = sdcard_wait_ok();
if (ret != RT_EOK)
{
LOG_D("sdmmc busy!");
return 0;
}
rt_completion_init(&tx_comp);
ret = HAL_SD_WriteBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (rt_uint32_t)(sector + i), 1);
if (ret != HAL_OK)
{
rt_kprintf("sd write error!\n");
return 0;
}
rt_completion_wait(&tx_comp,RT_WAITING_FOREVER);
}
return count;
}
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
geometry->bytes_per_sector = 512;
geometry->block_size = SDCARD_Handler.SdCard.BlockSize;
geometry->sector_count = SDCARD_Handler.SdCard.BlockNbr;
}
return RT_EOK;
}
void SDMMC1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_SD_IRQHandler(&SDCARD_Handler);
rt_interrupt_leave();
}
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
if (hsd->Instance == SDCARD_Handler.Instance)
{
sd_device.read_flage = 1;
}
}
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
if (hsd->Instance == SDCARD_Handler.Instance)
{
rt_completion_done(&tx_comp);
}
}
int rt_hw_sdcard_init(void)
{
if (rt_hw_sd_init() != RT_EOK)
{
rt_hw_sd_deinit();
LOG_E("sdcard init failed");
return RT_ERROR;
}
/* register sdcard device */
sd_device.sdcard.type = RT_Device_Class_Block;
sd_device.sdcard.init = rt_sdcard_init;
sd_device.sdcard.open = rt_sdcard_open;
sd_device.sdcard.close = rt_sdcard_close;
sd_device.sdcard.read = rt_sdcard_read;
sd_device.sdcard.write = rt_sdcard_write;
sd_device.sdcard.control = rt_sdcard_control;
/* no private */
sd_device.sdcard.user_data = &SDCardInfo;
rt_device_register(&sd_device.sdcard, "sd_card", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
LOG_I("sd card init success!");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_sdcard_init);
#if defined(SD_USING_DFS)
int mnt_init(void)
{
rt_device_t sd_dev = RT_NULL;
LOG_I("init sd card file system.");
#if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP)
rt_thread_delay(3000);
#else
rt_thread_delay(RT_TICK_PER_SECOND);
#endif
sd_dev = rt_device_find("sd_card");
if (sd_dev == RT_NULL)
{
LOG_E("can't find sd deivce name!");
return RT_ERROR;
}
if (dfs_mount("sd_card", "/", "elm", 0, 0) != 0)
{
rt_kprintf("file system mount failed!\n");
}
else
{
rt_kprintf("file system mount success!\n");
}
return 0;
}
INIT_APP_EXPORT(mnt_init);
#endif
#endif
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c
+572
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c
+782
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h
+80
View File
@@ -0,0 +1,80 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-02 thread-liu first version
*/
#ifndef __DRV_WM8994_H__
#define __DRV_WM8994_H__
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
enum{
GET_ID,
SET_FREQUENCE,
SET_VOLUME,
GET_VOLUME,
SET_MUTE,
SET_RESET,
START_PLAY,
SET_PLAY_TYPE,
};
/* codec device play type */
#define DEVICE_NONE ((uint16_t)0x0000)
#define OUTPUT_DEVICE_SPEAKER ((uint16_t)0x0001)
#define OUTPUT_DEVICE_HEADPHONE ((uint16_t)0x0002)
#define OUTPUT_DEVICE_BOTH ((uint16_t)0x0004)
#define OUTPUT_DEVICE_AUTO ((uint16_t)0x0008)
#define INPUT_DEVICE_DIGITAL_MICROPHONE_1 ((uint16_t)0x0010)
#define INPUT_DEVICE_DIGITAL_MICROPHONE_2 ((uint16_t)0x0020)
#define INPUT_DEVICE_INPUT_LINE_1 ((uint16_t)0x0040)
#define INPUT_DEVICE_INPUT_LINE_2 ((uint16_t)0x0080)
#define INPUT_DEVICE_DIGITAL_MIC1_MIC2 ((uint16_t)0x0100)
/* volume levels values */
#define DEFAULT_VOLMIN 0x00
#define DEFAULT_VOLMAX 0xFF
#define DEFAULT_VOLSTEP 0x04
#define AUDIO_PAUSE 0
#define AUDIO_RESUME 1
/* Codec POWER DOWN modes */
#define CODEC_PDWN_HW 1
#define CODEC_PDWN_SW 2
/* MUTE commands */
#define AUDIO_MUTE_ON 1
#define AUDIO_MUTE_OFF 0
/* AUDIO FREQUENCY */
#define AUDIO_FREQUENCY_192K ((uint32_t)192000)
#define AUDIO_FREQUENCY_96K ((uint32_t)96000)
#define AUDIO_FREQUENCY_48K ((uint32_t)48000)
#define AUDIO_FREQUENCY_44K ((uint32_t)44100)
#define AUDIO_FREQUENCY_32K ((uint32_t)32000)
#define AUDIO_FREQUENCY_22K ((uint32_t)22050)
#define AUDIO_FREQUENCY_16K ((uint32_t)16000)
#define AUDIO_FREQUENCY_11K ((uint32_t)11025)
#define AUDIO_FREQUENCY_8K ((uint32_t)8000)
#define VOLUME_CONVERT(Volume) (((Volume) > 100)? 100:((uint8_t)(((Volume) * 63) / 100)))
#define VOLUME_IN_CONVERT(Volume) (((Volume) >= 100)? 239:((uint8_t)(((Volume) * 240) / 100)))
#define WM8994_ID 0x8994
#define WM8994_CHIPID_ADDR 0x00
#ifdef __cplusplus
}
#endif
#endif
bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c
+870
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h
+381
View File
@@ -0,0 +1,381 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-20 thread-liu the first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Transmit descriptor
**/
typedef struct
{
uint32_t tdes0;
uint32_t tdes1;
uint32_t tdes2;
uint32_t tdes3;
} TxDmaDesc;
/**
* @brief Receive descriptor
**/
typedef struct
{
uint32_t rdes0;
uint32_t rdes1;
uint32_t rdes2;
uint32_t rdes3;
} RxDmaDesc;
enum {
PHY_LINK = (1 << 0),
PHY_10M = (1 << 1),
PHY_100M = (1 << 2),
PHY_1000M = (1 << 3),
PHY_FULL_DUPLEX = (1 << 4),
PHY_HALF_DUPLEX = (1 << 5)
};
#define RTL8211E_PHY_ADDR 7 /* PHY address */
#define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */
#define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */
#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */
/* Register access macros */
#define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
#define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
#define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
#define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
#define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
#define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
#define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
#define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)
#define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
#define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
#define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
#define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
/* Transmit normal descriptor (read format) */
#define ETH_TDES0_BUF1AP 0xFFFFFFFF
#define ETH_TDES1_BUF2AP 0xFFFFFFFF
#define ETH_TDES2_IOC 0x80000000
#define ETH_TDES2_TTSE 0x40000000
#define ETH_TDES2_B2L 0x3FFF0000
#define ETH_TDES2_VTIR 0x0000C000
#define ETH_TDES2_B1L 0x00003FFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_FD 0x20000000
#define ETH_TDES3_LD 0x10000000
#define ETH_TDES3_CPC 0x0C000000
#define ETH_TDES3_SAIC 0x03800000
#define ETH_TDES3_THL 0x00780000
#define ETH_TDES3_TSE 0x00040000
#define ETH_TDES3_CIC 0x00030000
#define ETH_TDES3_FL 0x00007FFF
/* Transmit normal descriptor (write-back format) */
#define ETH_TDES0_TTSL 0xFFFFFFFF
#define ETH_TDES1_TTSH 0xFFFFFFFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_FD 0x20000000
#define ETH_TDES3_LD 0x10000000
#define ETH_TDES3_TTSS 0x00020000
#define ETH_TDES3_ES 0x00008000
#define ETH_TDES3_JT 0x00004000
#define ETH_TDES3_FF 0x00002000
#define ETH_TDES3_PCE 0x00001000
#define ETH_TDES3_LOC 0x00000800
#define ETH_TDES3_NC 0x00000400
#define ETH_TDES3_LC 0x00000200
#define ETH_TDES3_EC 0x00000100
#define ETH_TDES3_CC 0x000000F0
#define ETH_TDES3_ED 0x00000008
#define ETH_TDES3_UF 0x00000004
#define ETH_TDES3_DB 0x00000002
#define ETH_TDES3_IHE 0x00000001
/* Transmit context descriptor */
#define ETH_TDES0_TTSL 0xFFFFFFFF
#define ETH_TDES1_TTSH 0xFFFFFFFF
#define ETH_TDES2_IVT 0xFFFF0000
#define ETH_TDES2_MSS 0x00003FFF
#define ETH_TDES3_OWN 0x80000000
#define ETH_TDES3_CTXT 0x40000000
#define ETH_TDES3_OSTC 0x08000000
#define ETH_TDES3_TCMSSV 0x04000000
#define ETH_TDES3_CDE 0x00800000
#define ETH_TDES3_IVLTV 0x00020000
#define ETH_TDES3_VLTV 0x00010000
#define ETH_TDES3_VT 0x0000FFFF
/* Receive normal descriptor (read format) */
#define ETH_RDES0_BUF1AP 0xFFFFFFFF
#define ETH_RDES2_BUF2AP 0xFFFFFFFF
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_IOC 0x40000000
#define ETH_RDES3_BUF2V 0x02000000
#define ETH_RDES3_BUF1V 0x01000000
/* Receive normal descriptor (write-back format) */
#define ETH_RDES0_IVT 0xFFFF0000
#define ETH_RDES0_OVT 0x0000FFFF
#define ETH_RDES1_OPC 0xFFFF0000
#define ETH_RDES1_TD 0x00008000
#define ETH_RDES1_TSA 0x00004000
#define ETH_RDES1_PV 0x00002000
#define ETH_RDES1_PFT 0x00001000
#define ETH_RDES1_PMT 0x00000F00
#define ETH_RDES1_IPCE 0x00000080
#define ETH_RDES1_IPCB 0x00000040
#define ETH_RDES1_IPV6 0x00000020
#define ETH_RDES1_IPV4 0x00000010
#define ETH_RDES1_IPHE 0x00000008
#define ETH_RDES1_PT 0x00000007
#define ETH_RDES2_L3L4FM 0xE0000000
#define ETH_RDES2_L4FM 0x10000000
#define ETH_RDES2_L3FM 0x08000000
#define ETH_RDES2_MADRM 0x07F80000
#define ETH_RDES2_HF 0x00040000
#define ETH_RDES2_DAF 0x00020000
#define ETH_RDES2_SAF 0x00010000
#define ETH_RDES2_VF 0x00008000
#define ETH_RDES2_ARPRN 0x00000400
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_CTXT 0x40000000
#define ETH_RDES3_FD 0x20000000
#define ETH_RDES3_LD 0x10000000
#define ETH_RDES3_RS2V 0x08000000
#define ETH_RDES3_RS1V 0x04000000
#define ETH_RDES3_RS0V 0x02000000
#define ETH_RDES3_CE 0x01000000
#define ETH_RDES3_GP 0x00800000
#define ETH_RDES3_RWT 0x00400000
#define ETH_RDES3_OE 0x00200000
#define ETH_RDES3_RE 0x00100000
#define ETH_RDES3_DE 0x00080000
#define ETH_RDES3_LT 0x00070000
#define ETH_RDES3_ES 0x00008000
#define ETH_RDES3_PL 0x00007FFF
/* Receive context descriptor */
#define ETH_RDES0_RTSL 0xFFFFFFFF
#define ETH_RDES1_RTSH 0xFFFFFFFF
#define ETH_RDES3_OWN 0x80000000
#define ETH_RDES3_CTXT 0x40000000
#define RTL8211E_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */
#define RTL8211E_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */
#define RTL8211E_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */
#define RTL8211E_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */
#define RTL8211E_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */
#define RTL8211E_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */
#define RTL8211E_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/
#define RTL8211E_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/
#define RTL8211E_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */
#define RTL8211E_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */
#define RTL8211E_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */
#define RTL8211E_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */
#define RTL8211E_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */
#define RTL8211E_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */
#define RTL8211E_PHYCR ((uint16_t)0x0010U)
#define RTL8211E_PHYSR ((uint16_t)0x0011U)
#define RTL8211E_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */
#define RTL8211E_INSR ((uint16_t)0x0013U) /* Interrupt Status Register. */
#define RTL8211E_RXERC ((uint16_t)0x0018U)
#define RTL8211E_LDPSR ((uint16_t)0x001BU)
#define RTL8211E_EPAGSR ((uint16_t)0x001EU)
#define RTL8211E_PAGSR ((uint16_t)0x001FU)
/* Basic Mode Control register */
#define RTL8211E_BMCR_RESET 0x8000
#define RTL8211E_BMCR_LOOPBACK 0x4000
#define RTL8211E_BMCR_SPEED_SEL_LSB 0x2000
#define RTL8211E_BMCR_AN_EN 0x1000
#define RTL8211E_BMCR_POWER_DOWN 0x0800
#define RTL8211E_BMCR_ISOLATE 0x0400
#define RTL8211E_BMCR_RESTART_AN 0x0200
#define RTL8211E_BMCR_DUPLEX_MODE 0x0100
#define RTL8211E_BMCR_COL_TEST 0x0080
#define RTL8211E_BMCR_SPEED_SEL_MSB 0x0040
/* Basic Mode Status register */
#define RTL8211E_BMSR_100BT4 0x8000
#define RTL8211E_BMSR_100BTX_FD 0x4000
#define RTL8211E_BMSR_100BTX_HD 0x2000
#define RTL8211E_BMSR_10BT_FD 0x1000
#define RTL8211E_BMSR_10BT_HD 0x0800
#define RTL8211E_BMSR_100BT2_FD 0x0400
#define RTL8211E_BMSR_100BT2_HD 0x0200
#define RTL8211E_BMSR_EXTENDED_STATUS 0x0100
#define RTL8211E_BMSR_PREAMBLE_SUPPR 0x0040
#define RTL8211E_BMSR_AN_COMPLETE 0x0020
#define RTL8211E_BMSR_REMOTE_FAULT 0x0010
#define RTL8211E_BMSR_AN_CAPABLE 0x0008
#define RTL8211E_BMSR_LINK_STATUS 0x0004
#define RTL8211E_BMSR_JABBER_DETECT 0x0002
#define RTL8211E_BMSR_EXTENDED_CAPABLE 0x0001
/* PHY Identifier 1 register */
#define RTL8211E_PHYID1_OUI_MSB 0xFFFF
#define RTL8211E_PHYID1_OUI_MSB_DEFAULT 0x001C
/* PHY Identifier 2 register */
#define RTL8211E_PHYID2_OUI_LSB 0xFC00
#define RTL8211E_PHYID2_OUI_LSB_DEFAULT 0xC800
#define RTL8211E_PHYID2_MODEL_NUM 0x03F0
#define RTL8211E_PHYID2_MODEL_NUM_DEFAULT 0x0110
#define RTL8211E_PHYID2_REVISION_NUM 0x000F
#define RTL8211E_PHYID2_REVISION_NUM_DEFAULT 0x0005
/* Auto-Negotiation Advertisement register */
#define RTL8211E_ANAR_NEXT_PAGE 0x8000
#define RTL8211E_ANAR_REMOTE_FAULT 0x2000
#define RTL8211E_ANAR_ASYM_PAUSE 0x0800
#define RTL8211E_ANAR_PAUSE 0x0400
#define RTL8211E_ANAR_100BT4 0x0200
#define RTL8211E_ANAR_100BTX_FD 0x0100
#define RTL8211E_ANAR_100BTX_HD 0x0080
#define RTL8211E_ANAR_10BT_FD 0x0040
#define RTL8211E_ANAR_10BT_HD 0x0020
#define RTL8211E_ANAR_SELECTOR 0x001F
#define RTL8211E_ANAR_SELECTOR_DEFAULT 0x0001
/* Auto-Negotiation Link Partner Ability register */
#define RTL8211E_ANLPAR_NEXT_PAGE 0x8000
#define RTL8211E_ANLPAR_ACK 0x4000
#define RTL8211E_ANLPAR_REMOTE_FAULT 0x2000
#define RTL8211E_ANLPAR_ASYM_PAUSE 0x0800
#define RTL8211E_ANLPAR_PAUSE 0x0400
#define RTL8211E_ANLPAR_100BT4 0x0200
#define RTL8211E_ANLPAR_100BTX_FD 0x0100
#define RTL8211E_ANLPAR_100BTX_HD 0x0080
#define RTL8211E_ANLPAR_10BT_FD 0x0040
#define RTL8211E_ANLPAR_10BT_HD 0x0020
#define RTL8211E_ANLPAR_SELECTOR 0x001F
#define RTL8211E_ANLPAR_SELECTOR_DEFAULT 0x0001
/* Auto-Negotiation Expansion register */
#define RTL8211E_ANER_PAR_DETECT_FAULT 0x0010
#define RTL8211E_ANER_LP_NEXT_PAGE_ABLE 0x0008
#define RTL8211E_ANER_NEXT_PAGE_ABLE 0x0004
#define RTL8211E_ANER_PAGE_RECEIVED 0x0002
#define RTL8211E_ANER_LP_AN_ABLE 0x0001
/* Auto-Negotiation Next Page Transmit register */
#define RTL8211E_ANNPTR_NEXT_PAGE 0x8000
#define RTL8211E_ANNPTR_MSG_PAGE 0x2000
#define RTL8211E_ANNPTR_ACK2 0x1000
#define RTL8211E_ANNPTR_TOGGLE 0x0800
#define RTL8211E_ANNPTR_MESSAGE 0x07FF
/* Auto-Negotiation Next Page Receive register */
#define RTL8211E_ANNPRR_NEXT_PAGE 0x8000
#define RTL8211E_ANNPRR_ACK 0x4000
#define RTL8211E_ANNPRR_MSG_PAGE 0x2000
#define RTL8211E_ANNPRR_ACK2 0x1000
#define RTL8211E_ANNPRR_TOGGLE 0x0800
#define RTL8211E_ANNPRR_MESSAGE 0x07FF
/* 1000Base-T Control register */
#define RTL8211E_GBCR_TEST_MODE 0xE000
#define RTL8211E_GBCR_MS_MAN_CONF_EN 0x1000
#define RTL8211E_GBCR_MS_MAN_CONF_VAL 0x0800
#define RTL8211E_GBCR_PORT_TYPE 0x0400
#define RTL8211E_GBCR_1000BT_FD 0x0200
/* 1000Base-T Status register */
#define RTL8211E_GBSR_MS_CONF_FAULT 0x8000
#define RTL8211E_GBSR_MS_CONF_RES 0x4000
#define RTL8211E_GBSR_LOCAL_RECEIVER_STATUS 0x2000
#define RTL8211E_GBSR_REMOTE_RECEIVER_STATUS 0x1000
#define RTL8211E_GBSR_LP_1000BT_FD 0x0800
#define RTL8211E_GBSR_LP_1000BT_HD 0x0400
#define RTL8211E_GBSR_IDLE_ERR_COUNT 0x00FF
/* MMD Access Control register */
#define RTL8211E_MMDACR_FUNC 0xC000
#define RTL8211E_MMDACR_FUNC_ADDR 0x0000
#define RTL8211E_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
#define RTL8211E_MMDACR_FUNC_DATA_POST_INC_W 0xC000
#define RTL8211E_MMDACR_DEVAD 0x001F
/* 1000Base-T Extended Status register */
#define RTL8211E_GBESR_1000BX_FD 0x8000
#define RTL8211E_GBESR_1000BX_HD 0x4000
#define RTL8211E_GBESR_1000BT_FD 0x2000
#define RTL8211E_GBESR_1000BT_HD 0x1000
/* PHY Specific Control register */
#define RTL8211E_PHYCR_RXC_DIS 0x8000
#define RTL8211E_PHYCR_FPR_FAIL_SEL 0x7000
#define RTL8211E_PHYCR_ASSERT_CRS_ON_TX 0x0800
#define RTL8211E_PHYCR_FORCE_LINK_GOOD 0x0400
#define RTL8211E_PHYCR_CROSSOVER_EN 0x0040
#define RTL8211E_PHYCR_MDI_MODE 0x0020
#define RTL8211E_PHYCR_CLK125_DIS 0x0010
#define RTL8211E_PHYCR_JABBER_DIS 0x0001
/* PHY Specific Status register */
#define RTL8211E_PHYSR_SPEED 0xC000
#define RTL8211E_PHYSR_SPEED_10MBPS 0x0000
#define RTL8211E_PHYSR_SPEED_100MBPS 0x4000
#define RTL8211E_PHYSR_SPEED_1000MBPS 0x8000
#define RTL8211E_PHYSR_DUPLEX 0x2000
#define RTL8211E_PHYSR_PAGE_RECEIVED 0x1000
#define RTL8211E_PHYSR_SPEED_DUPLEX_RESOLVED 0x0800
#define RTL8211E_PHYSR_LINK 0x0400
#define RTL8211E_PHYSR_MDI_CROSSOVER_STATUS 0x0040
#define RTL8211E_PHYSR_PRE_LINKOK 0x0002
#define RTL8211E_PHYSR_JABBER 0x0001
/* Interrupt Status register */
#define RTL8211E_INER_AN_ERROR 0x8000
#define RTL8211E_INER_PAGE_RECEIVED 0x1000
#define RTL8211E_INER_AN_COMPLETE 0x0800
#define RTL8211E_INER_LINK_STATUS 0x0400
#define RTL8211E_INER_SYMBOL_ERROR 0x0200
#define RTL8211E_INER_FALSE_CARRIER 0x0100
#define RTL8211E_INER_JABBER 0x0001
/* Interrupt Status register */
#define RTL8211E_INSR_AN_ERROR 0x8000
#define RTL8211E_INSR_PAGE_RECEIVED 0x1000
#define RTL8211E_INSR_AN_COMPLETE 0x0800
#define RTL8211E_INSR_LINK_STATUS 0x0400
#define RTL8211E_INSR_SYMBOL_ERROR 0x0200
#define RTL8211E_INSR_FALSE_CARRIER 0x0100
#define RTL8211E_INSR_JABBER 0x0001
/* Link Down Power Saving register */
#define RTL8211E_LDPSR_POWER_SAVE_MODE 0x0001
/* Extension Page Select register */
#define RTL8211E_EPAGSR_EXT_PAGE_SEL 0x00FF
#ifdef __cplusplus
}
#endif
#endif