mirror of
https://github.com/RT-Thread/rt-thread.git
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为复旦微电子FM33LC0XX添加BSP。包含UART驱动，已经在板子上测试通过。
This commit is contained in:
1
550
bsp/fm33lc0xx/.config
Normal file
550
bsp/fm33lc0xx/.config
Normal file
File diff suppressed because it is too large
Load Diff
40
bsp/fm33lc0xx/DebugConfig/rt-thread_STM32F072RBTx.dbgconf
Normal file
40
bsp/fm33lc0xx/DebugConfig/rt-thread_STM32F072RBTx.dbgconf
Normal file
@@ -0,0 +1,40 @@
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// File: STM32F0x1_0x2_0x8.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F0x1/STM32F0x2/STM32F0x8 Reference manual (RM0091)
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// refer to STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB datasheets
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// STM32F091xB/xC, STM32F042x4/x6, STM32F072x8/xB, STM32F038x6 datasheets
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// STM32F048x6, STM32F058x8, STM32F078xB, STM32F098xC datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// </h>
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DbgMCU_CR = 0x00000006;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.25> DBG_CAN_STOP <i> CAN stopped when core is halted
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// <o.21> DBG_I2C1_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM17_STOP <i> TIM17 counter stopped when core is halted
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// <o.17> DBG_TIM16_STOP <i> TIM16 counter stopped when core is halted
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// <o.16> DBG_TIM15_STOP <i> TIM15 counter stopped when core is halted
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// <o.11> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <<< end of configuration section >>>
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22
bsp/fm33lc0xx/Kconfig
Normal file
22
bsp/fm33lc0xx/Kconfig
Normal file
@@ -0,0 +1,22 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "libraries/Kconfig"
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source "board/Kconfig"
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15
bsp/fm33lc0xx/SConscript
Normal file
15
bsp/fm33lc0xx/SConscript
Normal file
@@ -0,0 +1,15 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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60
bsp/fm33lc0xx/SConstruct
Normal file
60
bsp/fm33lc0xx/SConstruct
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@@ -0,0 +1,60 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map rt-thread.map'])
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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stm32_library = 'FM33LC0xx_FL_Driver'
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rtconfig.BSP_LIBRARY_TYPE = stm32_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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9
bsp/fm33lc0xx/applications/SConscript
Normal file
9
bsp/fm33lc0xx/applications/SConscript
Normal file
@@ -0,0 +1,9 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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45
bsp/fm33lc0xx/applications/main.c
Normal file
45
bsp/fm33lc0xx/applications/main.c
Normal file
@@ -0,0 +1,45 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 zylx first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "fm33lc0xx_fl_gpio.h"
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#include "fm33lc0xx_fl_flash.h"
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#include "main.h"
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static void LED_init(void)
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{
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FL_GPIO_InitTypeDef GPIO_InitStruct = {0};
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FL_GPIO_SetOutputPin(GPIOD,FL_GPIO_PIN_4);
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GPIO_InitStruct.pin = FL_GPIO_PIN_4;
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GPIO_InitStruct.mode = FL_GPIO_MODE_OUTPUT;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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FL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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}
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int main(void)
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{
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LED_init();
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while (1)
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{
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FL_GPIO_SetOutputPin(GPIOD,FL_GPIO_PIN_4);
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rt_thread_mdelay(500);
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FL_GPIO_ResetOutputPin(GPIOD,FL_GPIO_PIN_4);
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rt_thread_mdelay(500);
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}
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// return RT_EOK;
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}
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39
bsp/fm33lc0xx/applications/main.h
Normal file
39
bsp/fm33lc0xx/applications/main.h
Normal file
@@ -0,0 +1,39 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file : main.h
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* @brief : Header for main.c file.
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* This file contains the common defines of the application.
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******************************************************************************
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* @attention
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*
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* Copyright (c) [2019] [Fudan Microelectronics]
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* THIS SOFTWARE is licensed under the Mulan PSL v1.
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* can use this software according to the terms and conditions of the Mulan PSL v1.
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* You may obtain a copy of Mulan PSL v1 at:
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* http://license.coscl.org.cn/MulanPSL
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
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* PURPOSE.
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* See the Mulan PSL v1 for more details.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MAIN_H
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#define __MAIN_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MAIN_H */
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/************************ (C) COPYRIGHT FMSH *****END OF FILE****/
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45
bsp/fm33lc0xx/board/Kconfig
Normal file
45
bsp/fm33lc0xx/board/Kconfig
Normal file
@@ -0,0 +1,45 @@
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menu "Hardware Drivers Config"
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config SOC_FM33LC0XX
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bool
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select SOC_SERIES_FM33LC0XX
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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menu "Onboard Peripheral Drivers"
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endmenu
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menu "On-chip Peripheral Drivers"
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menuconfig BSP_USING_UART
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bool "Enable UART"
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default y
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select RT_USING_SERIAL
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if BSP_USING_UART
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config BSP_USING_UART0
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bool "Enable UART0"
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default n
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config BSP_USING_UART1
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bool "Enable UART1"
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default y
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config BSP_USING_UART4
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bool "Enable UART4"
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default n
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config BSP_USING_UART5
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bool "Enable UART5"
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default y
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endif
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source "libraries/HAL_Drivers/Kconfig"
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endmenu
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menu "Board extended module Drivers"
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endmenu
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endmenu
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29
bsp/fm33lc0xx/board/SConscript
Normal file
29
bsp/fm33lc0xx/board/SConscript
Normal file
@@ -0,0 +1,29 @@
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import os
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import rtconfig
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from building import *
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|
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Import('SDK_LIB')
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|
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cwd = GetCurrentDir()
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|
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# add general drivers
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src = Split('''
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board.c
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''')
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|
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path = [cwd]
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|
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startup_path_prefix = SDK_LIB
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|
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/gcc/startup_fm33lc0xx.s']
|
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elif rtconfig.CROSS_TOOL == 'keil':
|
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src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/ARM/startup_fm33lc0xx.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/iar/startup_fm33lc0xx.s']
|
||||
|
||||
# FM33LC0XX
|
||||
# You can select chips from the list above
|
||||
CPPDEFINES = ['FM33LC0XX']
|
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
Return('group')
|
||||
154
bsp/fm33lc0xx/board/board.c
Normal file
154
bsp/fm33lc0xx/board/board.c
Normal file
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-21 zylx first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
FL_ErrorStatus FL_UART_GPIO_Init(UART_Type *UARTx)
|
||||
{
|
||||
FL_ErrorStatus status = FL_FAIL;
|
||||
FL_GPIO_InitTypeDef GPIO_InitStruct;
|
||||
if(UARTx == UART0)
|
||||
{
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_13;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOA, &GPIO_InitStruct );
|
||||
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_14;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOA, &GPIO_InitStruct );
|
||||
}
|
||||
else if(UARTx == UART1)
|
||||
{
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_13;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
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GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOB, &GPIO_InitStruct );
|
||||
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_14;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOB, &GPIO_InitStruct );
|
||||
}
|
||||
else if(UARTx == UART4)
|
||||
{
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_0;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOA, &GPIO_InitStruct );
|
||||
|
||||
GPIO_InitStruct.pin = FL_GPIO_PIN_1;
|
||||
GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
|
||||
GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.pull = FL_DISABLE;
|
||||
GPIO_InitStruct.remapPin = FL_DISABLE;
|
||||
|
||||
status = FL_GPIO_Init( GPIOA, &GPIO_InitStruct );
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLL_R, uint32_t PLL_DB, uint32_t PLL_O)
|
||||
{
|
||||
MODIFY_REG(RCC->PLLCR, RCC_PLLCR_DB_Msk | RCC_PLLCR_REFPRSC_Msk | RCC_PLLCR_OSEL_Msk | RCC_PLLCR_INSEL_Msk,
|
||||
(PLL_DB << RCC_PLLCR_DB_Pos) | PLL_R | PLL_O | Source);
|
||||
}
|
||||
|
||||
static void RCHFInit(uint32_t clock)
|
||||
{
|
||||
switch(clock)
|
||||
{
|
||||
case FL_RCC_RCHF_FREQUENCY_8MHZ:
|
||||
FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM);
|
||||
break;
|
||||
|
||||
case FL_RCC_RCHF_FREQUENCY_16MHZ:
|
||||
FL_RCC_RCHF_WriteTrimValue(RCHF16M_TRIM);
|
||||
break;
|
||||
|
||||
case FL_RCC_RCHF_FREQUENCY_24MHZ:
|
||||
FL_RCC_RCHF_WriteTrimValue(RCHF24M_TRIM);
|
||||
break;
|
||||
|
||||
default:
|
||||
FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM);
|
||||
break;
|
||||
}
|
||||
|
||||
FL_RCC_RCHF_SetFrequency(clock);
|
||||
}
|
||||
|
||||
void SelRCHFToPLL(uint32_t rchf, uint32_t clock)
|
||||
{
|
||||
uint32_t div = FL_RCC_PLL_PSC_DIV8;
|
||||
|
||||
if(clock > 64) { return; }
|
||||
|
||||
RCHFInit(rchf);
|
||||
|
||||
switch(rchf)
|
||||
{
|
||||
case FL_RCC_RCHF_FREQUENCY_16MHZ:
|
||||
div = FL_RCC_PLL_PSC_DIV16;
|
||||
break;
|
||||
|
||||
case FL_RCC_RCHF_FREQUENCY_24MHZ:
|
||||
div = FL_RCC_PLL_PSC_DIV24;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(clock <= 24)
|
||||
{
|
||||
FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_0CYCLE);
|
||||
}
|
||||
|
||||
else
|
||||
if((clock > 24) && (clock <= 48))
|
||||
{
|
||||
FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE);
|
||||
}
|
||||
|
||||
RCC_PLL_ConfigDomain_SYS(FL_RCC_PLL_CLK_SOURCE_RCHF, div, clock, FL_RCC_PLL_OUTPUT_X1);
|
||||
FL_RCC_PLL_Enable();
|
||||
|
||||
while(FL_RCC_IsActiveFlag_PLLReady() != FL_SET);
|
||||
|
||||
FL_RCC_SetAHBPrescaler(FL_RCC_AHBCLK_PSC_DIV1);
|
||||
FL_RCC_SetAPB1Prescaler(FL_RCC_APB1CLK_PSC_DIV1);
|
||||
FL_RCC_SetAPB2Prescaler(FL_RCC_APB2CLK_PSC_DIV1);
|
||||
FL_RCC_SetSystemClockSource(FL_RCC_SYSTEM_CLK_SOURCE_PLL);
|
||||
}
|
||||
|
||||
26
bsp/fm33lc0xx/board/board.h
Normal file
26
bsp/fm33lc0xx/board/board.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-5 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "fm33lc0xx_fl.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
1000
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cm0plus.h
Normal file
1000
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
664
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cmFunc.h
Normal file
664
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cmFunc.h
Normal file
File diff suppressed because it is too large
Load Diff
916
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cmInstr.h
Normal file
916
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/core_cmInstr.h
Normal file
File diff suppressed because it is too large
Load Diff
41
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33_assert.h
Normal file
41
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33_assert.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33_assert.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Assert function define
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
#ifndef __FM33_ASSERT_H
|
||||
#define __FM33_ASSERT_H
|
||||
#include "fm33xx.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
795
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33lc0xx.h
Normal file
795
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33lc0xx.h
Normal file
File diff suppressed because it is too large
Load Diff
1122
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33lg0xx.h
Normal file
1122
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33lg0xx.h
Normal file
File diff suppressed because it is too large
Load Diff
110
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33xx.h
Normal file
110
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/fm33xx.h
Normal file
@@ -0,0 +1,110 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33xx.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __FM33xx_H
|
||||
#define __FM33xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief FM33 Family
|
||||
*/
|
||||
#if !defined (FM33xx)
|
||||
#define FM33xx
|
||||
#endif /* FM33XX */
|
||||
/**
|
||||
* @brief CMSIS Device version number
|
||||
*/
|
||||
#define __FM33x0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __FM33x0xx_CMSIS_VERSION ((__FM33x0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__FM33x0xx_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
#if defined(FM33L0XX)
|
||||
#include "fm33l0xx.h"
|
||||
#elif defined(FM33LC0XX)
|
||||
#include "fm33lc0xx.h"
|
||||
#elif defined(FM33LG0XX)
|
||||
#include "fm33lg0xx.h"
|
||||
#else
|
||||
#error "Please select first the target FM33x0xx device used in your application (in FM33xxx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __FM33xx_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/
|
||||
155
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/system_fm33lc0xx.h
Normal file
155
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/system_fm33lc0xx.h
Normal file
@@ -0,0 +1,155 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_fm33lc0xx.h
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
|
||||
* Device FM33LC0XX
|
||||
* @version V2.00
|
||||
* @date 15. March 2021
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_FM33LC0XX_H
|
||||
#define SYSTEM_FM33LC0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "fm33lc0xx.h"
|
||||
|
||||
#define USE_LSCLK_CLOCK_SRC_XTLF
|
||||
|
||||
//#define SYSCLK_SRC_RC4M
|
||||
//#define SYSCLK_SRC_XTHF
|
||||
#define SYSCLK_SRC_RCHF
|
||||
//#define SYSCLK_SRC_PLL
|
||||
|
||||
|
||||
|
||||
//#define USE_PLL_CLOCK_SRC_RCHF
|
||||
//#define USE_PLL_CLOCK_SRC_XTHF
|
||||
|
||||
|
||||
#if ((!defined(SYSCLK_SRC_RC4M)) && (!defined(SYSCLK_SRC_XTHF))&&(!defined(SYSCLK_SRC_PLL))&&(!defined(SYSCLK_SRC_RCHF)))
|
||||
#error "Must select a clock source form the SYSCLK_SRC_RC4M or SYSCLK_SRC_XTHF or SYSCLK_SRC_PLL or SYSCLK_SRC_RCHF as the master clock."
|
||||
#elif (((defined(SYSCLK_SRC_RC4M)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_XTHF)) && ((defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_PLL)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_RCHF)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RC4M)))))
|
||||
#error "Only one clock source can be selected as the master clock."
|
||||
#endif
|
||||
|
||||
#if defined(SYSCLK_SRC_PLL) && !defined(USE_PLL_CLOCK_SRC_RCHF) && !defined(USE_PLL_CLOCK_SRC_XTHF)
|
||||
#error "You have chosen to enable the PLL, so you need to specify the clock source for the PLL.."
|
||||
#elif defined(SYSCLK_SRC_PLL) && (defined(USE_PLL_CLOCK_SRC_RCHF) && defined(USE_PLL_CLOCK_SRC_XTHF))
|
||||
#error "Please select one of the USE_PLL_CLOCK_SRC_RCHF and USE_PLL_CLOCK_SRC_XTHF in your application"
|
||||
#endif
|
||||
|
||||
#if !defined (XTHF_VALUE)
|
||||
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* XTHF_VALUE */
|
||||
|
||||
#if !defined (XTLF_VALUE)
|
||||
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* XTLF_VALUE */
|
||||
|
||||
|
||||
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
|
||||
((((_N_VALUE_ >> 16) & 0xffff) == \
|
||||
((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_)
|
||||
|
||||
#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值
|
||||
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值
|
||||
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值
|
||||
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值
|
||||
#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值
|
||||
|
||||
#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff)
|
||||
#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f)
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (8000000)
|
||||
|
||||
|
||||
/**
|
||||
* @brief FL NVIC Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 中断抢占优先级 */
|
||||
uint32_t preemptPriority;
|
||||
|
||||
}NVIC_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
void SystemCoreClockUpdate (void);
|
||||
/**
|
||||
* @brief NVIC_Init config NVIC
|
||||
*
|
||||
* @param NVIC_configStruct configParams
|
||||
*
|
||||
* @param IRQn Interrupt number
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_FM33LC0XX_H */
|
||||
101
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/system_fm33lg0xx.h
Normal file
101
bsp/fm33lc0xx/libraries/FM/FM33xx/Include/system_fm33lg0xx.h
Normal file
@@ -0,0 +1,101 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_FM33LG0XX.h
|
||||
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
|
||||
* Device FM33LG0XX
|
||||
* @version V1.02
|
||||
* @date 31-8-2018
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_FM33LG0XX_H
|
||||
#define SYSTEM_FM33LG0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "fm33lg0xx.h"
|
||||
|
||||
|
||||
#if !defined (XTHF_VALUE)
|
||||
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* XTHF_VALUE */
|
||||
|
||||
#if !defined (XTLF_VALUE)
|
||||
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* XTLF_VALUE */
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (8000000)
|
||||
#define DELAY_US (__SYSTEM_CLOCK/1000000)
|
||||
#define DELAY_MS (__SYSTEM_CLOCK/1000)
|
||||
|
||||
|
||||
#define Do_DelayStart() { \
|
||||
uint32_t LastTick = SysTick->VAL; do {
|
||||
|
||||
#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); \
|
||||
}
|
||||
|
||||
#define While_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); \
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_MVCM3_H */
|
||||
@@ -0,0 +1,233 @@
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD LFDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD IWDT_IRQHandler ; 6: IWDT
|
||||
DCD SPI1_IRQHandler ; 7: SPI1
|
||||
DCD SPI2_IRQHandler ; 8: SPI2
|
||||
DCD LCD_IRQHandler ; 9: LCD
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART4_IRQHandler ; 12: UART4
|
||||
DCD UART5_IRQHandler ; 13: UART5
|
||||
DCD HFDET_IRQHandler ; 14: HFDET
|
||||
DCD U7816_IRQHandler ; 15: U7816
|
||||
DCD LPUART1_IRQHandler ; 16: LPUART1
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD USB_IRQHandler ; 18: USB
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUP_IRQHandler ; 22: WKUP
|
||||
DCD OPAx_IRQHandler ; 23: OPAx
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_IRQHandler ; 26: GPTIM0
|
||||
DCD GPTIM1_IRQHandler ; 27: GPTIM1
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD LPUART0_IRQHandler ; 31: LPUART0
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT LPUART0_IRQHandler [WEAK]
|
||||
EXPORT GPIO_IRQHandler [WEAK]
|
||||
EXPORT VREF_IRQHandler [WEAK]
|
||||
EXPORT ATIM_IRQHandler [WEAK]
|
||||
EXPORT GPTIM1_IRQHandler [WEAK]
|
||||
EXPORT GPTIM0_IRQHandler [WEAK]
|
||||
EXPORT COMPx_IRQHandler [WEAK]
|
||||
EXPORT BSTIM_IRQHandler [WEAK]
|
||||
EXPORT OPAx_IRQHandler [WEAK]
|
||||
EXPORT WKUP_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT LPTIM_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT U7816_IRQHandler [WEAK]
|
||||
EXPORT HFDET_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT IWDT_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT LFDET_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT SVD_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
|
||||
LPUART0_IRQHandler
|
||||
GPIO_IRQHandler
|
||||
VREF_IRQHandler
|
||||
ATIM_IRQHandler
|
||||
GPTIM1_IRQHandler
|
||||
GPTIM0_IRQHandler
|
||||
COMPx_IRQHandler
|
||||
BSTIM_IRQHandler
|
||||
OPAx_IRQHandler
|
||||
WKUP_IRQHandler
|
||||
DMA_IRQHandler
|
||||
LPTIM_IRQHandler
|
||||
AES_IRQHandler
|
||||
USB_IRQHandler
|
||||
I2C_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
U7816_IRQHandler
|
||||
HFDET_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
LCD_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
IWDT_IRQHandler
|
||||
ADC_IRQHandler
|
||||
LFDET_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RTC_IRQHandler
|
||||
SVD_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
*****END OF FILE*****
|
||||
@@ -0,0 +1,233 @@
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000800
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD FDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD DAC_IRQHandler ; 6: DAC
|
||||
DCD SPI0_IRQHandler ; 7: SPI0
|
||||
DCD SPI1_IRQHandler ; 8: SPI1
|
||||
DCD SPI2_IRQHandler ; 9: SPI2
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART3_IRQHandler ; 12: UART3
|
||||
DCD UART4_IRQHandler ; 13: UART4
|
||||
DCD UART5_IRQHandler ; 14: UART5
|
||||
DCD U7816_IRQHandler ; 15: U7816
|
||||
DCD LPUARTx_IRQHandler ; 16: LPUART
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD CCL_IRQHandler ; 18: CCL
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUPx_IRQHandler ; 22: WKUP
|
||||
DCD LUT_IRQHandler ; 23: LUT
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1
|
||||
DCD GPTIM2_IRQHandler ; 27: GPTIM2
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD CAN_IRQHandler ; 31: CAN
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT GPIO_IRQHandler [WEAK]
|
||||
EXPORT VREF_IRQHandler [WEAK]
|
||||
EXPORT ATIM_IRQHandler [WEAK]
|
||||
EXPORT GPTIM2_IRQHandler [WEAK]
|
||||
EXPORT GPTIM0_1_IRQHandler [WEAK]
|
||||
EXPORT COMPx_IRQHandler [WEAK]
|
||||
EXPORT BSTIM_IRQHandler [WEAK]
|
||||
EXPORT LUT_IRQHandler [WEAK]
|
||||
EXPORT WKUPx_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT LPTIM_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT CCL_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT LPUARTx_IRQHandler [WEAK]
|
||||
EXPORT U7816_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT FDET_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT SVD_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
|
||||
CAN_IRQHandler
|
||||
GPIO_IRQHandler
|
||||
VREF_IRQHandler
|
||||
ATIM_IRQHandler
|
||||
GPTIM2_IRQHandler
|
||||
GPTIM0_1_IRQHandler
|
||||
COMPx_IRQHandler
|
||||
BSTIM_IRQHandler
|
||||
LUT_IRQHandler
|
||||
WKUPx_IRQHandler
|
||||
DMA_IRQHandler
|
||||
LPTIM_IRQHandler
|
||||
AES_IRQHandler
|
||||
CCL_IRQHandler
|
||||
I2C_IRQHandler
|
||||
LPUARTx_IRQHandler
|
||||
U7816_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
DAC_IRQHandler
|
||||
ADC_IRQHandler
|
||||
FDET_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RTC_IRQHandler
|
||||
SVD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
*****END OF FILE*****
|
||||
@@ -0,0 +1,131 @@
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20006000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Stack_Size = 0x400; /* amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
|
||||
/* system stack */
|
||||
PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/
|
||||
ASSERT ((_stack_base > end), "Error: No room left for the stack")
|
||||
/* _estack is top of stack*/
|
||||
|
||||
/* left ram for heap */
|
||||
PROVIDE (heap_start = _end);
|
||||
PROVIDE (heap_end = _stack_base);
|
||||
PROVIDE (heap_len = heap_end - heap_start);
|
||||
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,131 @@
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20006000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Stack_Size = 0x400; /* amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
|
||||
/* system stack */
|
||||
PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/
|
||||
ASSERT ((_stack_base > end), "Error: No room left for the stack")
|
||||
/* _estack is top of stack*/
|
||||
|
||||
/* left ram for heap */
|
||||
PROVIDE (heap_start = _end);
|
||||
PROVIDE (heap_end = _stack_base);
|
||||
PROVIDE (heap_len = heap_end - heap_start);
|
||||
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,131 @@
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20006000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Stack_Size = 0x400; /* amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
|
||||
/* system stack */
|
||||
PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/
|
||||
ASSERT ((_stack_base > end), "Error: No room left for the stack")
|
||||
/* _estack is top of stack*/
|
||||
|
||||
/* left ram for heap */
|
||||
PROVIDE (heap_start = _end);
|
||||
PROVIDE (heap_end = _stack_base);
|
||||
PROVIDE (heap_len = heap_end - heap_start);
|
||||
ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap")
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,250 @@
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
// bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.global g_pfnVectors
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word WWDT_IRQHandler /* 0: WWDT */
|
||||
.word SVD_IRQHandler /* 1: SVD */
|
||||
.word RTC_IRQHandler /* 2: RTC */
|
||||
.word FLASH_IRQHandler /* 3: FLASH */
|
||||
.word LFDET_IRQHandler /* 4: LFDET */
|
||||
.word ADC_IRQHandler /* 5: ADC */
|
||||
.word IWDT_IRQHandler /* 6: IWDT */
|
||||
.word SPI1_IRQHandler /* 7: SPI1 */
|
||||
.word SPI2_IRQHandler /* 8: SPI2 */
|
||||
.word LCD_IRQHandler /* 9: LCD */
|
||||
.word UART0_IRQHandler /* 10: UART0 */
|
||||
.word UART1_IRQHandler /* 11: UART1 */
|
||||
.word UART4_IRQHandler /* 12: UART4 */
|
||||
.word UART5_IRQHandler /* 13: UART5 */
|
||||
.word HFDET_IRQHandler /* 14: HFDET */
|
||||
.word U7816_IRQHandler /* 15: U7816 */
|
||||
.word LPUART1_IRQHandler /* 16: LPUART1 */
|
||||
.word I2C_IRQHandler /* 17: I2C */
|
||||
.word USB_IRQHandler /* 18: USB */
|
||||
.word AES_IRQHandler /* 19: AES */
|
||||
.word LPTIM_IRQHandler /* 20: LPTIM */
|
||||
.word DMA_IRQHandler /* 21: DMA */
|
||||
.word WKUP_IRQHandler /* 22: WKUP */
|
||||
.word OPAx_IRQHandler /* 23: OPAx */
|
||||
.word BSTIM_IRQHandler /* 24: BSTIM */
|
||||
.word COMPx_IRQHandler /* 25: COMPx */
|
||||
.word GPTIM0_IRQHandler /* 26: GPTIM0 */
|
||||
.word GPTIM1_IRQHandler /* 27: GPTIM1 */
|
||||
.word ATIM_IRQHandler /* 28: ATIM */
|
||||
.word VREF_IRQHandler /* 39: VREF */
|
||||
.word GPIO_IRQHandler /* 30: GPIO */
|
||||
.word LPUART0_IRQHandler /* 31: LPUART0 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDT_IRQHandler
|
||||
.thumb_set WWDT_IRQHandler,Default_Handler
|
||||
|
||||
.weak SVD_IRQHandler
|
||||
.thumb_set SVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak LFDET_IRQHandler
|
||||
.thumb_set LFDET_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDT_IRQHandler
|
||||
.thumb_set IWDT_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART0_IRQHandler
|
||||
.thumb_set UART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART1_IRQHandler
|
||||
.thumb_set UART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HFDET_IRQHandler
|
||||
.thumb_set HFDET_IRQHandler,Default_Handler
|
||||
|
||||
.weak U7816_IRQHandler
|
||||
.thumb_set U7816_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C_IRQHandler
|
||||
.thumb_set I2C_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_IRQHandler
|
||||
.thumb_set USB_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM_IRQHandler
|
||||
.thumb_set LPTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_IRQHandler
|
||||
.thumb_set DMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak WKUP_IRQHandler
|
||||
.thumb_set WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OPAx_IRQHandler
|
||||
.thumb_set OPAx_IRQHandler,Default_Handler
|
||||
|
||||
.weak BSTIM_IRQHandler
|
||||
.thumb_set BSTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMPx_IRQHandler
|
||||
.thumb_set COMPx_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPTIM0_IRQHandler
|
||||
.thumb_set GPTIM0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPTIM1_IRQHandler
|
||||
.thumb_set GPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ATIM_IRQHandler
|
||||
.thumb_set ATIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak VREF_IRQHandler
|
||||
.thumb_set VREF_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPIO_IRQHandler
|
||||
.thumb_set GPIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART0_IRQHandler
|
||||
.thumb_set LPUART0_IRQHandler,Default_Handler
|
||||
|
||||
@@ -0,0 +1,313 @@
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD LFDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD IWDT_IRQHandler ; 6: IWDT
|
||||
DCD SPI1_IRQHandler ; 7: SPI1
|
||||
DCD SPI2_IRQHandler ; 8: SPI2
|
||||
DCD LCD_IRQHandler ; 9: LCD
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART4_IRQHandler ; 12: UART4
|
||||
DCD UART5_IRQHandler ; 13: UART5
|
||||
DCD HFDET_IRQHandler ; 14: HFDET
|
||||
DCD U7816_IRQHandler ; 15: U7816
|
||||
DCD LPUART1_IRQHandler ; 16: LPUART1
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD USB_IRQHandler ; 18: USB
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUP_IRQHandler ; 22: WKUP
|
||||
DCD OPAx_IRQHandler ; 23: OPAx
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_IRQHandler ; 26: GPTIM0
|
||||
DCD GPTIM1_IRQHandler ; 27: GPTIM1
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD LPUART0_IRQHandler ; 31: LPUART0
|
||||
__Vectors_End
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
|
||||
PUBWEAK WWDT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDT_IRQHandler
|
||||
B WWDT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVD_IRQHandler
|
||||
B SVD_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LFDET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LFDET_IRQHandler
|
||||
B LFDET_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK IWDT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDT_IRQHandler
|
||||
B IWDT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK HFDET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HFDET_IRQHandler
|
||||
B HFDET_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK U7816_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
U7816_IRQHandler
|
||||
B U7816_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK I2C_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C_IRQHandler
|
||||
B I2C_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM_IRQHandler
|
||||
B LPTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WKUP_IRQHandler
|
||||
B WKUP_IRQHandler
|
||||
|
||||
PUBWEAK OPAx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OPAx_IRQHandler
|
||||
B OPAx_IRQHandler
|
||||
|
||||
|
||||
|
||||
PUBWEAK OPA1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OPA1_IRQHandler
|
||||
B OPA1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK BSTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BSTIM_IRQHandler
|
||||
B BSTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK COMPx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMPx_IRQHandler
|
||||
B COMPx_IRQHandler
|
||||
|
||||
|
||||
|
||||
PUBWEAK OPA2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OPA2_IRQHandler
|
||||
B OPA2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM0_IRQHandler
|
||||
B GPTIM0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM1_IRQHandler
|
||||
B GPTIM1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ATIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ATIM_IRQHandler
|
||||
B ATIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK VREF_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
VREF_IRQHandler
|
||||
B VREF_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPUART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART0_IRQHandler
|
||||
B LPUART0_IRQHandler
|
||||
END
|
||||
@@ -0,0 +1,299 @@
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: WWDT
|
||||
DCD SVD_IRQHandler ; 1: SVD
|
||||
DCD RTC_IRQHandler ; 2: RTC
|
||||
DCD FLASH_IRQHandler ; 3: FLASH
|
||||
DCD FDET_IRQHandler ; 4: LFDET
|
||||
DCD ADC_IRQHandler ; 5: ADC
|
||||
DCD DAC_IRQHandler ; 6: DAC
|
||||
DCD SPI0_IRQHandler ; 7: SPI0
|
||||
DCD SPI1_IRQHandler ; 8: SPI1
|
||||
DCD SPI2_IRQHandler ; 9: SPI2
|
||||
DCD UART0_IRQHandler ; 10: UART0
|
||||
DCD UART1_IRQHandler ; 11: UART1
|
||||
DCD UART3_IRQHandler ; 12: UART3
|
||||
DCD UART4_IRQHandler ; 13: UART4
|
||||
DCD UART5_IRQHandler ; 14: UART5
|
||||
DCD U7816_IRQHandler ; 15: U7816
|
||||
DCD LPUARTx_IRQHandler ; 16: LPUART
|
||||
DCD I2C_IRQHandler ; 17: I2C
|
||||
DCD CCL_IRQHandler ; 18: CCL
|
||||
DCD AES_IRQHandler ; 19: AES
|
||||
DCD LPTIM_IRQHandler ; 20: LPTIM
|
||||
DCD DMA_IRQHandler ; 21: DMA
|
||||
DCD WKUPx_IRQHandler ; 22: WKUP
|
||||
DCD LUT_IRQHandler ; 23: LUT
|
||||
DCD BSTIM_IRQHandler ; 24: BSTIM
|
||||
DCD COMPx_IRQHandler ; 25: COMPx
|
||||
DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1
|
||||
DCD GPTIM2_IRQHandler ; 27: GPTIM2
|
||||
DCD ATIM_IRQHandler ; 28: ATIM
|
||||
DCD VREF_IRQHandler ; 29: VREF
|
||||
DCD GPIO_IRQHandler ; 30: GPIO
|
||||
DCD CAN_IRQHandler ; 31: CAN
|
||||
__Vectors_End
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WDT_IRQHandler
|
||||
B WDT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVD_IRQHandler
|
||||
B SVD_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK FDET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDET_IRQHandler
|
||||
B FDET_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK U7816_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
U7816_IRQHandler
|
||||
B U7816_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPUARTx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUARTx_IRQHandler
|
||||
B LPUARTx_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK I2C_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C_IRQHandler
|
||||
B I2C_IRQHandler
|
||||
|
||||
PUBWEAK CCL_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CCL_IRQHandler
|
||||
B CCL_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK LPTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM_IRQHandler
|
||||
B LPTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK WKUPx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WKUPx_IRQHandler
|
||||
B WKUPx_IRQHandler
|
||||
|
||||
PUBWEAK LUT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LUT_IRQHandler
|
||||
B LUT_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK BSTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BSTIM_IRQHandler
|
||||
B BSTIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK COMPx_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMPx_IRQHandler
|
||||
B COMPx_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM0_1_IRQHandler
|
||||
B GPTIM0_1_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPTIM2_IRQHandler
|
||||
B GPTIM2_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK ATIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ATIM_IRQHandler
|
||||
B ATIM_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK VREF_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
VREF_IRQHandler
|
||||
B VREF_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33_assert.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Assert function define
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
#ifndef __FM33_ASSERT_H
|
||||
#define __FM33_ASSERT_H
|
||||
#include "fm33xx.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0)
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file fm33xx.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Module
|
||||
****************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
****************************************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __FM33xx_H
|
||||
#define __FM33xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief FM33 Family
|
||||
*/
|
||||
#if !defined (FM33xx)
|
||||
#define FM33xx
|
||||
#endif /* FM33XX */
|
||||
/**
|
||||
* @brief CMSIS Device version number
|
||||
*/
|
||||
#define __FM33x0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __FM33x0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __FM33x0xx_CMSIS_VERSION ((__FM33x0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__FM33x0xx_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
#if defined(FM33L0XX)
|
||||
#include "fm33l0xx.h"
|
||||
#elif defined(FM33LC0XX)
|
||||
#include "fm33lc0xx.h"
|
||||
#elif defined(FM33LG0XX)
|
||||
#include "fm33lg0xx.h"
|
||||
#else
|
||||
#error "Please select first the target FM33x0xx device used in your application (in FM33xxx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __FM33xx_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,155 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_fm33lc0xx.h
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
|
||||
* Device FM33LC0XX
|
||||
* @version V2.00
|
||||
* @date 15. March 2021
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_FM33LC0XX_H
|
||||
#define SYSTEM_FM33LC0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "fm33lc0xx.h"
|
||||
|
||||
#define USE_LSCLK_CLOCK_SRC_XTLF
|
||||
|
||||
//#define SYSCLK_SRC_RC4M
|
||||
//#define SYSCLK_SRC_XTHF
|
||||
#define SYSCLK_SRC_RCHF
|
||||
//#define SYSCLK_SRC_PLL
|
||||
|
||||
|
||||
|
||||
//#define USE_PLL_CLOCK_SRC_RCHF
|
||||
//#define USE_PLL_CLOCK_SRC_XTHF
|
||||
|
||||
|
||||
#if ((!defined(SYSCLK_SRC_RC4M)) && (!defined(SYSCLK_SRC_XTHF))&&(!defined(SYSCLK_SRC_PLL))&&(!defined(SYSCLK_SRC_RCHF)))
|
||||
#error "Must select a clock source form the SYSCLK_SRC_RC4M or SYSCLK_SRC_XTHF or SYSCLK_SRC_PLL or SYSCLK_SRC_RCHF as the master clock."
|
||||
#elif (((defined(SYSCLK_SRC_RC4M)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_XTHF)) && ((defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_PLL)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_RCHF))))||\
|
||||
((defined(SYSCLK_SRC_RCHF)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RC4M)))))
|
||||
#error "Only one clock source can be selected as the master clock."
|
||||
#endif
|
||||
|
||||
#if defined(SYSCLK_SRC_PLL) && !defined(USE_PLL_CLOCK_SRC_RCHF) && !defined(USE_PLL_CLOCK_SRC_XTHF)
|
||||
#error "You have chosen to enable the PLL, so you need to specify the clock source for the PLL.."
|
||||
#elif defined(SYSCLK_SRC_PLL) && (defined(USE_PLL_CLOCK_SRC_RCHF) && defined(USE_PLL_CLOCK_SRC_XTHF))
|
||||
#error "Please select one of the USE_PLL_CLOCK_SRC_RCHF and USE_PLL_CLOCK_SRC_XTHF in your application"
|
||||
#endif
|
||||
|
||||
#if !defined (XTHF_VALUE)
|
||||
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* XTHF_VALUE */
|
||||
|
||||
#if !defined (XTLF_VALUE)
|
||||
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* XTLF_VALUE */
|
||||
|
||||
|
||||
#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \
|
||||
((((_N_VALUE_ >> 16) & 0xffff) == \
|
||||
((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_)
|
||||
|
||||
#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值
|
||||
#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值
|
||||
#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值
|
||||
#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值
|
||||
#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值
|
||||
|
||||
#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff)
|
||||
#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f)
|
||||
#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f)
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (8000000)
|
||||
|
||||
|
||||
/**
|
||||
* @brief FL NVIC Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* 中断抢占优先级 */
|
||||
uint32_t preemptPriority;
|
||||
|
||||
}NVIC_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
void SystemCoreClockUpdate (void);
|
||||
/**
|
||||
* @brief NVIC_Init config NVIC
|
||||
*
|
||||
* @param NVIC_configStruct configParams
|
||||
*
|
||||
* @param IRQn Interrupt number
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_FM33LC0XX_H */
|
||||
@@ -0,0 +1,101 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_FM33LG0XX.h
|
||||
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
|
||||
* Device FM33LG0XX
|
||||
* @version V1.02
|
||||
* @date 31-8-2018
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_FM33LG0XX_H
|
||||
#define SYSTEM_FM33LG0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "fm33lg0xx.h"
|
||||
|
||||
|
||||
#if !defined (XTHF_VALUE)
|
||||
#define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* XTHF_VALUE */
|
||||
|
||||
#if !defined (XTLF_VALUE)
|
||||
#define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* XTLF_VALUE */
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (8000000)
|
||||
#define DELAY_US (__SYSTEM_CLOCK/1000000)
|
||||
#define DELAY_MS (__SYSTEM_CLOCK/1000)
|
||||
|
||||
|
||||
#define Do_DelayStart() { \
|
||||
uint32_t LastTick = SysTick->VAL; do {
|
||||
|
||||
#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); \
|
||||
}
|
||||
|
||||
#define While_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); \
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_MVCM3_H */
|
||||
@@ -0,0 +1,286 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_fm33lc0xx.c
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
|
||||
* Device FM33LC0XX
|
||||
* @version V2.00
|
||||
* @date 15. March 2021
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "system_fm33lc0xx.h"
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* ToDo: add here your necessary defines for device initialization
|
||||
following is an example for different system frequencies */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
|
||||
achieved after system intitialization.
|
||||
This means system core clock frequency after call to SystemInit() */
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
static uint32_t SystemPLLClockUpdate(void)
|
||||
{
|
||||
uint32_t clock = 0;
|
||||
|
||||
// 时钟源
|
||||
switch ((RCC->PLLCR >> 1) & 0x1)
|
||||
{
|
||||
case 0:
|
||||
switch ((RCC->RCHFCR >> 16) & 0xf)
|
||||
{
|
||||
case 1: // 16M
|
||||
clock = 16000000;
|
||||
break;
|
||||
|
||||
case 2: // 24M
|
||||
clock = 24000000;
|
||||
break;
|
||||
|
||||
case 0: // 8M
|
||||
default:
|
||||
clock = 8000000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
clock = XTHF_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
// 分频
|
||||
switch ((RCC->PLLCR >> 0x4) & 0x7)
|
||||
{
|
||||
case 0: // 不分频
|
||||
clock /= 1;
|
||||
break;
|
||||
|
||||
case 1: // 2分频
|
||||
clock /= 2;
|
||||
break;
|
||||
|
||||
case 2: // 4分频
|
||||
clock /= 4;
|
||||
break;
|
||||
|
||||
case 3: // 8分频
|
||||
clock /= 8;
|
||||
break;
|
||||
|
||||
case 4: // 12分频
|
||||
clock /= 12;
|
||||
break;
|
||||
|
||||
case 5: // 16分频
|
||||
clock /= 16;
|
||||
break;
|
||||
|
||||
case 6: // 24分频
|
||||
clock /= 24;
|
||||
break;
|
||||
|
||||
case 7: // 32分频
|
||||
clock /= 32;
|
||||
break;
|
||||
}
|
||||
|
||||
// 倍频比
|
||||
clock = clock * (((RCC->PLLCR >> 16) & 0x7f) + 1);
|
||||
|
||||
// 输出选择
|
||||
if ((RCC->PLLCR >> 3) & 0x1)
|
||||
{
|
||||
clock *= 2;
|
||||
}
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
switch ((RCC->SYSCLKCR >> 0) & 0x7)
|
||||
{
|
||||
case 1: // XTHF
|
||||
SystemCoreClock = XTHF_VALUE;
|
||||
break;
|
||||
|
||||
case 2: // PLL
|
||||
SystemCoreClock = SystemPLLClockUpdate();
|
||||
break;
|
||||
|
||||
case 4: // RCMF
|
||||
switch ((RCC->RCMFCR >> 16) & 0x3)
|
||||
{
|
||||
case 0: // 不分频
|
||||
SystemCoreClock = 4000000;
|
||||
break;
|
||||
|
||||
case 1: // 4分频
|
||||
SystemCoreClock = 1000000;
|
||||
break;
|
||||
|
||||
case 2: // 8分频
|
||||
SystemCoreClock = 500000;
|
||||
break;
|
||||
|
||||
case 3: // 16分频
|
||||
SystemCoreClock = 250000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 5: // LSCLK
|
||||
case 6: // LPOSC
|
||||
SystemCoreClock = 32768;
|
||||
break;
|
||||
|
||||
case 7: // USBBCK
|
||||
switch ((RCC->SYSCLKCR >> 3) & 0x1)
|
||||
{
|
||||
case 0: // USBBCK 48M
|
||||
SystemCoreClock = 48000000;
|
||||
break;
|
||||
|
||||
case 1: // USBBCK 120M 2分频
|
||||
SystemCoreClock = 60000000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
switch ((RCC->RCHFCR >> 16) & 0xf)
|
||||
{
|
||||
case 1: // 16M
|
||||
SystemCoreClock = 16000000;
|
||||
break;
|
||||
|
||||
case 2: // 24M
|
||||
SystemCoreClock = 24000000;
|
||||
break;
|
||||
|
||||
case 0: // 8M
|
||||
default:
|
||||
SystemCoreClock = 8000000;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief NVIC_Init config NVIC
|
||||
*
|
||||
* @param NVIC_configStruct configParams
|
||||
*
|
||||
* @param IRQn Interrupt number
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn)
|
||||
{
|
||||
/* Params Check */
|
||||
if(NVIC_configStruct->preemptPriority>3)
|
||||
{
|
||||
NVIC_configStruct->preemptPriority = 3;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
NVIC_SetPriority(IRQn,NVIC_configStruct->preemptPriority);
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* */
|
||||
RCC->PLLCR = (uint32_t)0x00000000U;
|
||||
RCC->SYSCLKCR = (uint32_t)0x0A000000U;
|
||||
/* PAD RCC*/
|
||||
RCC->PCLKCR1 |= (0x1U << 7U);
|
||||
#ifdef USE_LSCLK_CLOCK_SRC_XTLF
|
||||
GPIOD->FCR |= 0x3C0000;
|
||||
/* XTLF*/
|
||||
RCC->XTLFCR = (uint32_t)(0x00000000U);
|
||||
/* XTLF*/
|
||||
RCC->XTLFCR |= (uint32_t)(0x00000005U<<8);
|
||||
for(temp = 2000;temp>0;temp--);
|
||||
/* LSCLKXTLF*/
|
||||
RCC->LSCLKSEL = 0xAA;
|
||||
/* LSCXTLF*/
|
||||
RCC->SYSCLKCR |= 0x8000000U;
|
||||
#else
|
||||
RCC->SYSCLKCR &= 0x7FFFFFFU;
|
||||
RCC->LSCLKSEL = 0x55;
|
||||
#endif
|
||||
/*PDR*/
|
||||
RMU->PDRCR |=0x01;
|
||||
/*BOR*/
|
||||
RMU->BORCR &=0xFE;
|
||||
|
||||
/* DEBUG IWDT WWDT */
|
||||
DBG->CR =0x03;
|
||||
|
||||
RCC->RCHFTR = RCHF24M_TRIM;
|
||||
RCC->RCMFTR = RCMF4M_TRIM;
|
||||
RCC->LPOSCTR = LPOSC_TRIM;
|
||||
|
||||
GPIOD->PUEN |= 0x3 << 7;
|
||||
|
||||
/* DMA Flash Channel: Flash->RAM */
|
||||
RCC->PCLKCR2 |= 0x1 << 4;
|
||||
DMA->CH7CR |= 0x1 << 10;
|
||||
RCC->PCLKCR2 &= ~(0x1 << 4);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_<Device>.c
|
||||
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for
|
||||
* Device <Device>
|
||||
* @version V3.10
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THES
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "fm33lg0xx.h"
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* ToDo: add here your necessary defines for device initialization
|
||||
following is an example for different system frequencies */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
|
||||
achieved after system intitialization.
|
||||
This means system core clock frequency after call to SystemInit() */
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
}
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
289
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h
Normal file
289
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h
Normal file
@@ -0,0 +1,289 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lc0xx_fl.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Header file of FL Driver Library
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------------------------------*/
|
||||
#ifndef __FM33LC0XX_FL_H
|
||||
#define __FM33LC0XX_FL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Select FM33LC0XX Device
|
||||
*/
|
||||
#if !defined (FM33LC0XX)
|
||||
#define FM33LC0XX
|
||||
#endif /* FM33LC0XX */
|
||||
|
||||
/* Defines -------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief List of drivers to be used.
|
||||
*
|
||||
* @note Uncomment following lines to disable specified driver.
|
||||
*/
|
||||
|
||||
#ifndef MFANG
|
||||
|
||||
#define FL_ADC_DRIVER_ENABLED
|
||||
#define FL_AES_DRIVER_ENABLED
|
||||
#define FL_ATIM_DRIVER_ENABLED
|
||||
#define FL_BSTIM32_DRIVER_ENABLED
|
||||
#define FL_COMP_DRIVER_ENABLED
|
||||
#define FL_CRC_DRIVER_ENABLED
|
||||
#define FL_DIVAS_DRIVER_ENABLED
|
||||
#define FL_DMA_DRIVER_ENABLED
|
||||
#define FL_EXTI_DRIVER_ENABLED
|
||||
#define FL_FLASH_DRIVER_ENABLED
|
||||
#define FL_GPIO_DRIVER_ENABLED
|
||||
#define FL_GPTIM_DRIVER_ENABLED
|
||||
#define FL_I2C_DRIVER_ENABLED
|
||||
#define FL_IWDT_DRIVER_ENABLED
|
||||
#define FL_LCD_DRIVER_ENABLED
|
||||
#define FL_LPTIM32_DRIVER_ENABLED
|
||||
#define FL_LPUART_DRIVER_ENABLED
|
||||
#define FL_OPA_DRIVER_ENABLED
|
||||
#define FL_PMU_DRIVER_ENABLED
|
||||
#define FL_RCC_DRIVER_ENABLED
|
||||
#define FL_RMU_DRIVER_ENABLED
|
||||
#define FL_RNG_DRIVER_ENABLED
|
||||
#define FL_RTC_DRIVER_ENABLED
|
||||
#define FL_SPI_DRIVER_ENABLED
|
||||
#define FL_SVD_DRIVER_ENABLED
|
||||
#define FL_U7816_DRIVER_ENABLED
|
||||
#define FL_UART_DRIVER_ENABLED
|
||||
#define FL_VREF_DRIVER_ENABLED
|
||||
#define FL_WWDT_DRIVER_ENABLED
|
||||
|
||||
#endif
|
||||
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33xx.h"
|
||||
#include "fm33_assert.h"
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Macros ---------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_Private_Macros FL Driver Library Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FM33LC0xx FL Driver Library version number
|
||||
*/
|
||||
#define __FM33LC0xx_FL_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __FM33LC0xx_FL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __FM33LC0xx_FL_VERSION_SUB2 (0x01) /*!< [15:0] sub2 version */
|
||||
#define __FM33LC0xx_FL_VERSION ((__FM33LC0xx_FL_VERSION_MAIN << 24)\
|
||||
|(__FM33LC0xx_FL_VERSION_SUB1 << 16)\
|
||||
|(__FM33LC0xx_FL_VERSION_SUB2))
|
||||
|
||||
/**
|
||||
* @brief Macros used by delay support functions
|
||||
*/
|
||||
#define FL_DELAY_US (SystemCoreClock/1000000)
|
||||
#define FL_DELAY_MS (SystemCoreClock/1000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Types ----------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_ET_Return FL Exported Return Type Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_RESET = 0U,
|
||||
FL_SET = !FL_RESET
|
||||
} FL_FlagStatus, FL_ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_DISABLE = 0U,
|
||||
FL_ENABLE = !FL_DISABLE
|
||||
} FL_FunState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FL_DISABLE) || ((STATE) == FL_ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FL_FAIL = 0U,
|
||||
FL_PASS = !FL_FAIL
|
||||
} FL_ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported Functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup FL_EF_DELAY Exported FL Driver Library Delay Support Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FL_EF_INIT Exported FL Driver Library Init Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FL_Init(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Post Includes --------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include peripheral's header file
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_ASSERT)
|
||||
#include "fm33_assert.h"
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#if defined(FL_ADC_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_adc.h"
|
||||
#endif /* FL_ADC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_AES_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_aes.h"
|
||||
#endif /* FL_AES_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_ATIM_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_atim.h"
|
||||
#endif /* FL_ATIM_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_BSTIM32_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_bstim32.h"
|
||||
#endif /* FL_BSTIM32_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_COMP_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_comp.h"
|
||||
#endif /* FL_COMP_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_CRC_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_crc.h"
|
||||
#endif /* FL_CRC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_DIVAS_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_divas.h"
|
||||
#endif /* FL_DIVAS_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_DMA_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_dma.h"
|
||||
#endif /* FL_DMA_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_EXTI_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_exti.h"
|
||||
#endif /* FL_EXTI_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_FLASH_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_flash.h"
|
||||
#endif /* FL_FLASH_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_GPIO_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_gpio.h"
|
||||
#endif /* FL_GPIO_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_GPTIM_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_gptim.h"
|
||||
#endif /* FL_GPTIM_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_I2C_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_i2c.h"
|
||||
#endif /* FL_I2C_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_IWDT_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_iwdt.h"
|
||||
#endif /* FL_IWDT_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LCD_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_lcd.h"
|
||||
#endif /* FL_LCD_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LPTIM32_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_lptim32.h"
|
||||
#endif /* FL_LPTIM32_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_LPUART_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_lpuart.h"
|
||||
#endif /* FL_LPUART_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_OPA_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_opa.h"
|
||||
#endif /* FL_OPA_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_PMU_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_pmu.h"
|
||||
#endif /* FL_PMU_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RCC_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_rcc.h"
|
||||
#endif /* FL_RCC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RMU_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_rmu.h"
|
||||
#endif /* FL_RMU_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RNG_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_rng.h"
|
||||
#endif /* FL_RNG_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_RTC_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_rtc.h"
|
||||
#endif /* FL_RTC_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_SPI_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_spi.h"
|
||||
#endif /* FL_SPI_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_SVD_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_svd.h"
|
||||
#endif /* FL_SVD_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_U7816_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_u7816.h"
|
||||
#endif /* FL_U7816_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_UART_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_uart.h"
|
||||
#endif /* FL_UART_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_VREF_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_vref.h"
|
||||
#endif /* FL_VREF_DRIVER_ENABLED */
|
||||
|
||||
#if defined(FL_WWDT_DRIVER_ENABLED)
|
||||
#include "fm33lc0xx_fl_wwdt.h"
|
||||
#endif /* FL_WWDT_DRIVER_ENABLED */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LC0XX_FL_H */
|
||||
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1655
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h
Normal file
1655
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3790
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h
Normal file
3790
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,483 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lc0xx_fl_bstim32.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of BSTIM32 FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LC0XX_FL_BSTIM32_H
|
||||
#define __FM33LC0XX_FL_BSTIM32_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lc0xx_fl.h"
|
||||
/** @addtogroup FM33LC0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM32 BSTIM32
|
||||
* @brief BSTIM32 FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_ES_INIT BSTIM32 Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief BSTIM32 Init Sturcture Definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* 预分频系数 */
|
||||
uint32_t prescaler;
|
||||
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReload;
|
||||
|
||||
/* 自动重装载值 */
|
||||
uint32_t autoReloadState;
|
||||
|
||||
/* 时钟源 */
|
||||
uint32_t clockSource;
|
||||
|
||||
} FL_BSTIM32_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_Exported_Constants BSTIM32 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BSTIM32_CR1_ARPE_Pos (7U)
|
||||
#define BSTIM32_CR1_ARPE_Msk (0x1U << BSTIM32_CR1_ARPE_Pos)
|
||||
#define BSTIM32_CR1_ARPE BSTIM32_CR1_ARPE_Msk
|
||||
|
||||
#define BSTIM32_CR1_OPM_Pos (3U)
|
||||
#define BSTIM32_CR1_OPM_Msk (0x1U << BSTIM32_CR1_OPM_Pos)
|
||||
#define BSTIM32_CR1_OPM BSTIM32_CR1_OPM_Msk
|
||||
|
||||
#define BSTIM32_CR1_URS_Pos (2U)
|
||||
#define BSTIM32_CR1_URS_Msk (0x1U << BSTIM32_CR1_URS_Pos)
|
||||
#define BSTIM32_CR1_URS BSTIM32_CR1_URS_Msk
|
||||
|
||||
#define BSTIM32_CR1_UDIS_Pos (1U)
|
||||
#define BSTIM32_CR1_UDIS_Msk (0x1U << BSTIM32_CR1_UDIS_Pos)
|
||||
#define BSTIM32_CR1_UDIS BSTIM32_CR1_UDIS_Msk
|
||||
|
||||
#define BSTIM32_CR1_CEN_Pos (0U)
|
||||
#define BSTIM32_CR1_CEN_Msk (0x1U << BSTIM32_CR1_CEN_Pos)
|
||||
#define BSTIM32_CR1_CEN BSTIM32_CR1_CEN_Msk
|
||||
|
||||
#define BSTIM32_CR2_MMS_Pos (4U)
|
||||
#define BSTIM32_CR2_MMS_Msk (0x7U << BSTIM32_CR2_MMS_Pos)
|
||||
#define BSTIM32_CR2_MMS BSTIM32_CR2_MMS_Msk
|
||||
|
||||
#define BSTIM32_IER_UIE_Pos (0U)
|
||||
#define BSTIM32_IER_UIE_Msk (0x1U << BSTIM32_IER_UIE_Pos)
|
||||
#define BSTIM32_IER_UIE BSTIM32_IER_UIE_Msk
|
||||
|
||||
#define BSTIM32_ISR_UIF_Pos (0U)
|
||||
#define BSTIM32_ISR_UIF_Msk (0x1U << BSTIM32_ISR_UIF_Pos)
|
||||
#define BSTIM32_ISR_UIF BSTIM32_ISR_UIF_Msk
|
||||
|
||||
#define BSTIM32_EGR_UG_Pos (0U)
|
||||
#define BSTIM32_EGR_UG_Msk (0x1U << BSTIM32_EGR_UG_Pos)
|
||||
#define BSTIM32_EGR_UG BSTIM32_EGR_UG_Msk
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS (0x0U << BSTIM32_CR1_OPM_Pos)
|
||||
#define FL_BSTIM32_ONE_PULSE_MODE_SINGLE (0x1U << BSTIM32_CR1_OPM_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM32_UPDATE_SOURCE_REGULAR (0x0U << BSTIM32_CR1_URS_Pos)
|
||||
#define FL_BSTIM32_UPDATE_SOURCE_COUNTER (0x1U << BSTIM32_CR1_URS_Pos)
|
||||
|
||||
|
||||
#define FL_BSTIM32_TRGO_UG (0x0U << BSTIM32_CR2_MMS_Pos)
|
||||
#define FL_BSTIM32_TRGO_ENABLE (0x1U << BSTIM32_CR2_MMS_Pos)
|
||||
#define FL_BSTIM32_TRGO_UPDATE (0x2U << BSTIM32_CR2_MMS_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup BSTIM32_FL_Exported_Functions BSTIM32 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload enable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_EnableARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload preload enable status
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_IsEnabledARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk) == BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Auto-Reload preload disable
|
||||
* @rmtoll CR1 ARPE FL_BSTIM32_DisableARRPreload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableARRPreload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM32_SetOnePulseMode
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetOnePulseMode(BSTIM32_Type *BSTIM32x, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get one pulse mode
|
||||
* @rmtoll CR1 OPM FL_BSTIM32_GetOnePulseMode
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS
|
||||
* @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetOnePulseMode(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set update request
|
||||
* @rmtoll CR1 URS FL_BSTIM32_SetUpdateSource
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param source This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetUpdateSource(BSTIM32_Type *BSTIM32x, uint32_t source)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk, source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update request status
|
||||
* @rmtoll CR1 URS FL_BSTIM32_GetUpdateSource
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR
|
||||
* @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetUpdateSource(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event enable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_EnableUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event disable status
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_IsEnabledUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)!(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk) == BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event disable
|
||||
* @rmtoll CR1 UDIS FL_BSTIM32_DisableUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter enable
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_Enable
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_Enable(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter enable status
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_IsEnabled
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabled(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk) == BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Counter disable
|
||||
* @rmtoll CR1 CEN FL_BSTIM32_Disable
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_Disable(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set master mode
|
||||
* @rmtoll CR2 MMS FL_BSTIM32_SetTriggerOutput
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param triggerOutput This parameter can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_TRGO_UG
|
||||
* @arg @ref FL_BSTIM32_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM32_TRGO_UPDATE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_SetTriggerOutput(BSTIM32_Type *BSTIM32x, uint32_t triggerOutput)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk, triggerOutput);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get master mode status
|
||||
* @rmtoll CR2 MMS FL_BSTIM32_GetTriggerOutput
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_BSTIM32_TRGO_UG
|
||||
* @arg @ref FL_BSTIM32_TRGO_ENABLE
|
||||
* @arg @ref FL_BSTIM32_TRGO_UPDATE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_GetTriggerOutput(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt disable
|
||||
* @rmtoll IER UIE FL_BSTIM32_DisableIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_DisableIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
CLEAR_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update event interrupt enable
|
||||
* @rmtoll IER UIE FL_BSTIM32_EnableIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_EnableIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt enable status
|
||||
* @rmtoll IER UIE FL_BSTIM32_IsEnabledIT_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledIT_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk) == BSTIM32_IER_UIE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM32_IsActiveFlag_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_IsActiveFlag_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk) == (BSTIM32_ISR_UIF_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear update event interrupt flag
|
||||
* @rmtoll ISR UIF FL_BSTIM32_ClearFlag_Update
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_ClearFlag_Update(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
WRITE_REG(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software update event enable
|
||||
* @rmtoll EGR UG FL_BSTIM32_GenerateUpdateEvent
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_GenerateUpdateEvent(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
SET_BIT(BSTIM32x->EGR, BSTIM32_EGR_UG_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter value
|
||||
* @rmtoll CNT FL_BSTIM32_WriteCounter
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param cnt
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WriteCounter(BSTIM32_Type *BSTIM32x, uint32_t cnt)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->CNT, (0xffffffffU << 0U), (cnt << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter value
|
||||
* @rmtoll CNT FL_BSTIM32_ReadCounter
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadCounter(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->CNT, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM32_WritePrescaler
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param psc
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WritePrescaler(BSTIM32_Type *BSTIM32x, uint32_t psc)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->PSC, (0xffffffffU << 0U), (psc << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter Clock prescaler value
|
||||
* @rmtoll PSC FL_BSTIM32_ReadPrescaler
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadPrescaler(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->PSC, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM32_WriteAutoReload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @param value
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_BSTIM32_WriteAutoReload(BSTIM32_Type *BSTIM32x, uint32_t value)
|
||||
{
|
||||
MODIFY_REG(BSTIM32x->ARR, (0xffffffffU << 0U), (value << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Auto-Reload register value
|
||||
* @rmtoll ARR FL_BSTIM32_ReadAutoReload
|
||||
* @param BSTIM32x BSTIM32 instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_BSTIM32_ReadAutoReload(BSTIM32_Type *BSTIM32x)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(BSTIM32x->ARR, 0xffffffffU) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BSTIM32_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_BSTIM32_DeInit(BSTIM32_Type *BSTIM32x);
|
||||
FL_ErrorStatus FL_BSTIM32_Init(BSTIM32_Type *BSTIM32x, FL_BSTIM32_InitTypeDef *initStruct);
|
||||
void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *initStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LC0XX_FL_BSTIM32_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,474 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lc0xx_fl_crc.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of CRC FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LC0XX_FL_CRC_H
|
||||
#define __FM33LC0XX_FL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lc0xx_fl.h"
|
||||
/** @addtogroup FM33LC0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_ES_INIT CRC Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL CRC Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/** CRC初值 */
|
||||
uint32_t initVal;
|
||||
|
||||
/** 计算数据宽度 */
|
||||
uint32_t dataWidth;
|
||||
|
||||
/** 输入数据翻转 */
|
||||
uint32_t reflectIn;
|
||||
|
||||
/** 输出数据翻转 */
|
||||
uint32_t reflectOut;
|
||||
|
||||
/** 输出结果异或寄存器 */
|
||||
uint32_t xorReg;
|
||||
|
||||
/** 输出结果异或使能 */
|
||||
uint32_t xorRegState;
|
||||
|
||||
/** CRC多项式宽 */
|
||||
uint32_t polynomialWidth;
|
||||
|
||||
/** CRC多项式 */
|
||||
uint32_t polynomial;
|
||||
|
||||
/** 计算模式串行或并行 */
|
||||
uint32_t calculatMode;
|
||||
|
||||
} FL_CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRC_CR_OPWD_Pos (9U)
|
||||
#define CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos)
|
||||
#define CRC_CR_OPWD CRC_CR_OPWD_Msk
|
||||
|
||||
#define CRC_CR_PARA_Pos (8U)
|
||||
#define CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos)
|
||||
#define CRC_CR_PARA CRC_CR_PARA_Msk
|
||||
|
||||
#define CRC_CR_RFLTIN_Pos (6U)
|
||||
#define CRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos)
|
||||
#define CRC_CR_RFLTIN CRC_CR_RFLTIN_Msk
|
||||
|
||||
#define CRC_CR_RFLTO_Pos (5U)
|
||||
#define CRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos)
|
||||
#define CRC_CR_RFLTO CRC_CR_RFLTO_Msk
|
||||
|
||||
#define CRC_CR_RES_Pos (4U)
|
||||
#define CRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos)
|
||||
#define CRC_CR_RES CRC_CR_RES_Msk
|
||||
|
||||
#define CRC_CR_BUSY_Pos (3U)
|
||||
#define CRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos)
|
||||
#define CRC_CR_BUSY CRC_CR_BUSY_Msk
|
||||
|
||||
#define CRC_CR_XOR_Pos (2U)
|
||||
#define CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos)
|
||||
#define CRC_CR_XOR CRC_CR_XOR_Msk
|
||||
|
||||
#define CRC_CR_SEL_Pos (0U)
|
||||
#define CRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos)
|
||||
#define CRC_CR_SEL CRC_CR_SEL_Msk
|
||||
|
||||
|
||||
#define FL_CRC_DATA_WIDTH_8B (0x0U << CRC_CR_OPWD_Pos)
|
||||
#define FL_CRC_DATA_WIDTH_32B (0x1U << CRC_CR_OPWD_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_CALCULATE_SERIAL (0x0U << CRC_CR_PARA_Pos)
|
||||
#define FL_CRC_CALCULATE_PARALLEL (0x1U << CRC_CR_PARA_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_INPUT_INVERT_NONE (0x0U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_HALF_WORD (0x2U << CRC_CR_RFLTIN_Pos)
|
||||
#define FL_CRC_INPUT_INVERT_WORD (0x3U << CRC_CR_RFLTIN_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_OUPUT_INVERT_NONE (0x0U << CRC_CR_RFLTO_Pos)
|
||||
#define FL_CRC_OUPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTO_Pos)
|
||||
|
||||
|
||||
#define FL_CRC_POLYNOMIAL_32B (0x0U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_16B (0x1U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_8B (0x2U << CRC_CR_SEL_Pos)
|
||||
#define FL_CRC_POLYNOMIAL_7B (0x3U << CRC_CR_SEL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup CRC_FL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC data register
|
||||
* @rmtoll DR FL_CRC_WriteData
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteData(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->DR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC data register value
|
||||
* @rmtoll DR FL_CRC_ReadData
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadData(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->DR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC calculate operation width
|
||||
* @rmtoll CR OPWD FL_CRC_SetDataWidth
|
||||
* @param CRCx CRC instance
|
||||
* @param dataWidth This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_8B
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_32B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetDataWidth(CRC_Type *CRCx, uint32_t dataWidth)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_OPWD_Msk, dataWidth);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC calculate operation width
|
||||
* @rmtoll CR OPWD FL_CRC_GetDataWidth
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_8B
|
||||
* @arg @ref FL_CRC_DATA_WIDTH_32B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetDataWidth(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_OPWD_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC parallel calculation mode
|
||||
* @rmtoll CR PARA FL_CRC_SetCalculateMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_CALCULATE_SERIAL
|
||||
* @arg @ref FL_CRC_CALCULATE_PARALLEL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetCalculateMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_PARA_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC parallel calculation mode
|
||||
* @rmtoll CR PARA FL_CRC_GetCalculateMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_CALCULATE_SERIAL
|
||||
* @arg @ref FL_CRC_CALCULATE_PARALLEL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetCalculateMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_PARA_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC reflected input
|
||||
* @rmtoll CR RFLTIN FL_CRC_SetInputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_BYTE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_WORD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetInputInvertMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_RFLTIN_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC reflected input status
|
||||
* @rmtoll CR RFLTIN FL_CRC_GetInputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_BYTE
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD
|
||||
* @arg @ref FL_CRC_INPUT_INVERT_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetInputInvertMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTIN_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC reflected output
|
||||
* @rmtoll CR RFLTO FL_CRC_SetOutputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @param mode This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_BYTE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetOutputInvertMode(CRC_Type *CRCx, uint32_t mode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_RFLTO_Msk, mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC feflected output status
|
||||
* @rmtoll CR RFLTO FL_CRC_GetOutputInvertMode
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_NONE
|
||||
* @arg @ref FL_CRC_OUPUT_INVERT_BYTE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetOutputInvertMode(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTO_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result flag
|
||||
* @rmtoll CR RES FL_CRC_IsActiveFlag_Zero
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Zero(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RES_Msk) == (CRC_CR_RES_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC operational flag
|
||||
* @rmtoll CR BUSY FL_CRC_IsActiveFlag_Busy
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Busy(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_BUSY_Msk) == (CRC_CR_BUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Output XORed with CRC_XOR register enable
|
||||
* @rmtoll CR XOR FL_CRC_EnableOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_EnableOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get output XORed with CRC_XOR register enable status
|
||||
* @rmtoll CR XOR FL_CRC_IsEnabledOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_IsEnabledOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_XOR_Msk) == CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Output XORed with CRC_XOR register disable
|
||||
* @rmtoll CR XOR FL_CRC_DisableOutputXOR
|
||||
* @param CRCx CRC instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_DisableOutputXOR(CRC_Type *CRCx)
|
||||
{
|
||||
CLEAR_BIT(CRCx->CR, CRC_CR_XOR_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polynomial width selection
|
||||
* @rmtoll CR SEL FL_CRC_SetPolynomialWidth
|
||||
* @param CRCx CRC instance
|
||||
* @param width This parameter can be one of the following values:
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_32B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_16B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_8B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_7B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_SetPolynomialWidth(CRC_Type *CRCx, uint32_t width)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_SEL_Msk, width);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Polynomial width Selection status
|
||||
* @rmtoll CR SEL FL_CRC_GetPolynomialWidth
|
||||
* @param CRCx CRC instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_32B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_16B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_8B
|
||||
* @arg @ref FL_CRC_POLYNOMIAL_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_GetPolynomialWidth(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_SEL_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set linear feedback shift register
|
||||
* @rmtoll LFSR FL_CRC_WriteInitialValue
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteInitialValue(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->LFSR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get linear feedback shift register value
|
||||
* @rmtoll LFSR FL_CRC_ReadInitialValue
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadInitialValue(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->LFSR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set eXclusive XOR register
|
||||
* @rmtoll XOR FL_CRC_WriteXORValue
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WriteXORValue(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->XOR, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get eXclusive XOR register value
|
||||
* @rmtoll XOR FL_CRC_ReadXORValue
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadXORValue(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->XOR, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC Polynominals
|
||||
* @rmtoll POLY FL_CRC_WritePolynominalParam
|
||||
* @param CRCx CRC instance
|
||||
* @param data
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_CRC_WritePolynominalParam(CRC_Type *CRCx, uint32_t data)
|
||||
{
|
||||
MODIFY_REG(CRCx->POLY, (0xffffffffU << 0U), (data << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC Polynominals
|
||||
* @rmtoll POLY FL_CRC_ReadPolynominalParam
|
||||
* @param CRCx CRC instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_CRC_ReadPolynominalParam(CRC_Type *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->POLY, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
FL_ErrorStatus FL_CRC_DeInit(CRC_Type *CRCx);
|
||||
void FL_CRC_StructInit(FL_CRC_InitTypeDef *CRC_InitStruct);
|
||||
FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LC0XX_FL_CRC_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
@@ -0,0 +1,206 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lc0xx_fl_divas.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of DIVAS FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LC0XX_FL_DIVAS_H
|
||||
#define __FM33LC0XX_FL_DIVAS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lc0xx_fl.h"
|
||||
/** @addtogroup FM33LC0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DIVAS DIVAS
|
||||
* @brief DIVAS FL driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_ES_INIT DIVAS Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_Exported_Constants DIVAS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DIV_SR_DIVBYZERO_Pos (1U)
|
||||
#define DIV_SR_DIVBYZERO_Msk (0x1U << DIV_SR_DIVBYZERO_Pos)
|
||||
#define DIV_SR_DIVBYZERO DIV_SR_DIVBYZERO_Msk
|
||||
|
||||
#define DIV_SR_BUSY_Pos (0U)
|
||||
#define DIV_SR_BUSY_Msk (0x1U << DIV_SR_BUSY_Pos)
|
||||
#define DIV_SR_BUSY DIV_SR_BUSY_Msk
|
||||
|
||||
|
||||
|
||||
#define FL_DIVAS_SR_BUSY_TIMEOUT 0xFFFU
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup DIVAS_FL_Exported_Functions DIVAS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write Dividend Register
|
||||
* @rmtoll OPRD FL_DIV_WriteDividend_S32
|
||||
* @param DIVx DIV instance
|
||||
* @param number
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DIV_WriteDividend_S32(DIV_Type *DIVx, int32_t number)
|
||||
{
|
||||
MODIFY_REG(DIVx->END, (0xffffffffU << 0U), (number << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read Dividend Register
|
||||
* @rmtoll OPRD FL_DIV_ReadDividend_S32
|
||||
* @param DIVx DIV instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIV_ReadDividend_S32(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->END, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write 16bit Signed Divisor
|
||||
* @rmtoll DIVSOR FL_DIV_WriteDivisor_S16
|
||||
* @param DIVx DIV instance
|
||||
* @param number
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FL_DIV_WriteDivisor_S16(DIV_Type *DIVx, int16_t number)
|
||||
{
|
||||
MODIFY_REG(DIVx->SOR, (0xffffU << 0U), (number << 0U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 16bit Signed Divisor
|
||||
* @rmtoll DIVSOR FL_DIV_ReadDivisor_S16
|
||||
* @param DIVx DIV instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIV_ReadDivisor_S16(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->SOR, (0xffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 32bit Signed QUTO
|
||||
* @rmtoll QUOT FL_DIV_ReadQuotient_S32
|
||||
* @param DIVx DIV instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIV_ReadQuotient_S32(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->QUOT, (0xffffffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read 16bit Signed Reminder
|
||||
* @rmtoll REMD FL_DIV_ReadResidue_S16
|
||||
* @param DIVx DIV instance
|
||||
* @retval
|
||||
*/
|
||||
__STATIC_INLINE int32_t FL_DIV_ReadResidue_S16(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->REMD, (0xffffU << 0U)) >> 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get divided by 0 flag
|
||||
* @rmtoll SR DIVBYZERO FL_DIV_IsActiveFlag_DividedZero
|
||||
* @param DIVx DIV instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DIV_IsActiveFlag_DividedZero(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->SR, DIV_SR_DIVBYZERO_Msk) == (DIV_SR_DIVBYZERO_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Busy flag
|
||||
* @rmtoll SR BUSY FL_DIV_IsActiveFlag_Busy
|
||||
* @param DIVx DIV instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FL_DIV_IsActiveFlag_Busy(DIV_Type *DIVx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DIVx->SR, DIV_SR_BUSY_Msk) == (DIV_SR_BUSY_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DIVAS_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_DIVAS_DeInit(DIV_Type *DIVx);
|
||||
FL_ErrorStatus FL_DIVAS_Init(DIV_Type *DIVx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DIVAS_FL_EF_Operation Opeartion functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t FL_DIVAS_Hdiv_Calculation(DIV_Type *DIVx, int32_t DivisorEnd, int16_t Divisor, int32_t *Quotient, int16_t *Residue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LC0XX_FL_DIVAS_H*/
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
1287
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h
Normal file
1287
bsp/fm33lc0xx/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,123 @@
|
||||
/**
|
||||
*******************************************************************************************************
|
||||
* @file fm33lc0xx_fl_exti.h
|
||||
* @author FMSH Application Team
|
||||
* @brief Head file of EXTI FL Module
|
||||
*******************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) [2019] [Fudan Microelectronics]
|
||||
* THIS SOFTWARE is licensed under the Mulan PSL v1.
|
||||
* can use this software according to the terms and conditions of the Mulan PSL v1.
|
||||
* You may obtain a copy of Mulan PSL v1 at:
|
||||
* http://license.coscl.org.cn/MulanPSL
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
|
||||
* PURPOSE.
|
||||
* See the Mulan PSL v1 for more details.
|
||||
*
|
||||
*******************************************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion---------------------------------------------------------------*/
|
||||
#ifndef __FM33LC0XX_FL_EXTI_H
|
||||
#define __FM33LC0XX_FL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes -------------------------------------------------------------------------------------------*/
|
||||
#include "fm33lc0xx_fl.h"
|
||||
/** @addtogroup FM33LC0XX_FL_Driver
|
||||
* @{
|
||||
*/
|
||||
/* Exported types -------------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_ES_INIT EXTI Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FL EXTI Common Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! EXTI时钟源配置 */
|
||||
uint32_t clockSource;
|
||||
|
||||
} FL_EXTI_CommonInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FL EXTI Init Sturcture definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*! EXTI输入配置 */
|
||||
uint32_t input;
|
||||
|
||||
/*! EXTI触发边沿配置 */
|
||||
uint32_t triggerEdge;
|
||||
|
||||
/*! EXTI数字滤波配置 */
|
||||
uint32_t filter;
|
||||
|
||||
} FL_EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP0 (0x0U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP1 (0x1U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP2 (0x2U << 0U)
|
||||
#define FL_GPIO_EXTI_INPUT_GROUP3 (0x3U << 0U)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ---------------------------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_FL_Exported_Functions EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_FL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
FL_ErrorStatus FL_EXTI_CommonInit(FL_EXTI_CommonInitTypeDef *init);
|
||||
FL_ErrorStatus FL_EXTI_CommonDeinit(void);
|
||||
void FL_EXTI_CommonStructInit(FL_EXTI_CommonInitTypeDef *init);
|
||||
|
||||
FL_ErrorStatus FL_EXTI_Init(uint32_t extiLineX, FL_EXTI_InitTypeDef *init);
|
||||
FL_ErrorStatus FL_EXTI_DeInit(uint32_t extiLineX);
|
||||
void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *init);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FM33LC0XX_FL_EXTI_H */
|
||||
|
||||
/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2021-03-16*************************/
|
||||
/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user