mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-05-21 18:11:51 +08:00
add Freescale k64F bsp. FRDM-K64 based
This commit is contained in:
geniusgogo
@@ -0,0 +1,164 @@
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/*
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* K64F ARM GCC linker script file
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||||
*/
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||||
|
||||
MEMORY
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||||
{
|
||||
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
|
||||
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410
|
||||
RAM (rwx) : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
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||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
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||||
* with other linker script that defines memory regions FLASH and RAM.
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||||
* It references following symbols, which must be defined in code:
|
||||
* _reset_init : Entry of reset handler
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||||
*
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||||
* It defines following symbols, which code can use without definition:
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||||
* __exidx_start
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||||
* __exidx_end
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||||
* __etext
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||||
* __data_start__
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||||
* __preinit_array_start
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||||
* __preinit_array_end
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||||
* __init_array_start
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||||
* __init_array_end
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||||
* __fini_array_start
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||||
* __fini_array_end
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||||
* __data_end__
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||||
* __bss_start__
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||||
* __bss_end__
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||||
* __end__
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||||
* end
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||||
* __HeapLimit
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||||
* __StackLimit
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* __StackTop
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* __stack
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*/
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||||
ENTRY(Reset_Handler)
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||||
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||||
SECTIONS
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{
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||||
.isr_vector :
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{
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||||
__vector_table = .;
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KEEP(*(.vector_table))
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||||
*(.text.Reset_Handler)
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||||
*(.text.System_Init)
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||||
. = ALIGN(4);
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||||
} > VECTORS
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||||
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||||
.flash_protect :
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||||
{
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KEEP(*(.kinetis_flash_config_field))
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||||
. = ALIGN(4);
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||||
} > FLASH_PROTECTION
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||||
|
||||
.text :
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||||
{
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||||
*(.text*)
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||||
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KEEP(*(.init))
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KEEP(*(.fini))
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||||
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||||
/* .ctors */
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||||
*crtbegin.o(.ctors)
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||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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||||
*(SORT(.ctors.*))
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||||
*(.ctors)
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||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
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||||
*crtbegin?.o(.dtors)
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||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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||||
*(SORT(.dtors.*))
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*(.dtors)
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||||
|
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > FLASH
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||||
|
||||
.ARM.extab :
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||||
{
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||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
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||||
} > FLASH
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||||
__exidx_start = .;
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||||
.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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||||
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__etext = .;
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.data : AT (__etext)
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{
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__data_start__ = .;
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||||
*(vtable)
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||||
*(.data*)
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||||
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. = ALIGN(4);
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||||
/* preinit data */
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||||
PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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||||
PROVIDE_HIDDEN (__preinit_array_end = .);
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||||
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||||
. = ALIGN(4);
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||||
/* init data */
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||||
PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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||||
PROVIDE_HIDDEN (__init_array_end = .);
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||||
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||||
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. = ALIGN(4);
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||||
/* finit data */
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||||
PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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||||
PROVIDE_HIDDEN (__fini_array_end = .);
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||||
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. = ALIGN(4);
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||||
/* All data end */
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||||
__data_end__ = .;
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||||
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} > RAM
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.bss :
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||||
{
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||||
__bss_start__ = .;
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||||
*(.bss*)
|
||||
*(COMMON)
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||||
__bss_end__ = .;
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||||
} > RAM
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||||
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||||
.heap :
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||||
{
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||||
__end__ = .;
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||||
end = __end__;
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||||
*(.heap*)
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||||
__HeapLimit = .;
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||||
} > RAM
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||||
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||||
/* .stack_dummy section doesn't contains any symbols. It is only
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||||
* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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||||
.stack_dummy :
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||||
{
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||||
*(.stack)
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||||
} > RAM
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||||
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||||
/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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||||
/* Check if data + heap + stack exceeds RAM limit */
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||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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@@ -0,0 +1,14 @@
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LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
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ER_IROM1 0x00000000 0x100000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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||||
.ANY (+RO)
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||||
}
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||||
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
|
||||
; 0x40000 - 0x198 = 0x3FE68
|
||||
RW_IRAM1 0x1FFF0198 0x3FE68 {
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||||
.ANY (+RW +ZI)
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||||
}
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||||
}
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@@ -0,0 +1,14 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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cwd = str(Dir('#'))
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,37 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-k64f.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# build program
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env.Program(TARGET, objs)
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# end building
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EndBuilding(TARGET)
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@@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,118 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
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||||
* Change Logs:
|
||||
* Date Author Notes
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||||
*
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||||
*/
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||||
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||||
/**
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||||
* @addtogroup k64
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*/
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/*@{*/
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#include <stdio.h>
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#include "MK64F12.h"
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#include <board.h>
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#include <rtthread.h>
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#include "led.h"
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#ifdef RT_USING_LWIP
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#include <lwip/sys.h>
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#include <lwip/api.h>
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#include <netif/ethernetif.h>
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#include "stm32_eth.h"
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#endif
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||||
void rt_init_thread_entry(void* parameter)
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{
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/* LwIP Initialization */
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#ifdef RT_USING_LWIP
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||||
{
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extern void lwip_sys_init(void);
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/* register ethernetif device */
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eth_system_device_init();
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rt_hw_stm32_eth_init();
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/* re-init device driver */
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rt_device_init_all();
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/* init lwip system */
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lwip_sys_init();
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rt_kprintf("TCP/IP initialized!\n");
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}
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#endif
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//FS
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//GUI
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}
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||||
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||||
float f_var1;
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float f_var2;
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float f_var3;
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float f_var4;
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||||
ALIGN(RT_ALIGN_SIZE)
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||||
static char thread_led1_stack[1024];
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||||
struct rt_thread thread_led1;
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||||
static void rt_thread_entry_led1(void* parameter)
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||||
{
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||||
int n = 0;
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||||
rt_hw_led_init();
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||||
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||||
while (1)
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||||
{
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//rt_kprintf("LED\t%d\tis shining\r\n",n);
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||||
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||||
rt_hw_led_on(n);
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||||
rt_thread_delay(RT_TICK_PER_SECOND/2);
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||||
rt_hw_led_off(n);
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||||
rt_thread_delay(RT_TICK_PER_SECOND/2);
|
||||
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||||
n++;
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||||
|
||||
if (n == LED_MAX)
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||||
n = 0;
|
||||
}
|
||||
}
|
||||
|
||||
int rt_application_init()
|
||||
{
|
||||
rt_thread_t init_thread;
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||||
|
||||
#if (RT_THREAD_PRIORITY_MAX == 32)
|
||||
init_thread = rt_thread_create("init",
|
||||
rt_init_thread_entry, RT_NULL,
|
||||
2048, 8, 20);
|
||||
#else
|
||||
init_thread = rt_thread_create("init",
|
||||
rt_init_thread_entry, RT_NULL,
|
||||
2048, 80, 20);
|
||||
#endif
|
||||
|
||||
if (init_thread != RT_NULL)
|
||||
rt_thread_startup(init_thread);
|
||||
|
||||
//------- init led1 thread
|
||||
rt_thread_init(&thread_led1,
|
||||
"led_demo",
|
||||
rt_thread_entry_led1,
|
||||
RT_NULL,
|
||||
&thread_led1_stack[0],
|
||||
sizeof(thread_led1_stack),11,5);
|
||||
rt_thread_startup(&thread_led1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* File : startup.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <MK64F12.H>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @addtogroup k64
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
extern int rt_application_init(void);
|
||||
#ifdef RT_USING_FINSH
|
||||
extern void finsh_system_init(void);
|
||||
extern void finsh_set_device(const char* device);
|
||||
#endif
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define K64_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define K64_SRAM_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define K64_SRAM_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : assert_failed
|
||||
* Description : Reports the name of the source file and the source line number
|
||||
* where the assert error has occurred.
|
||||
* Input : - file: pointer to the source file name
|
||||
* - line: assert error line source number
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void assert_failed(rt_uint8_t* file, rt_uint32_t line)
|
||||
{
|
||||
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
|
||||
rt_kprintf(" file %s\r\n", file);
|
||||
rt_kprintf(" line %d\r\n", line);
|
||||
|
||||
while (1) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will startup RT-Thread RTOS.
|
||||
*/
|
||||
void rtthread_startup(void)
|
||||
{
|
||||
/* init board */
|
||||
rt_hw_board_init();
|
||||
|
||||
/* show version */
|
||||
rt_show_version();
|
||||
|
||||
/* init tick */
|
||||
rt_system_tick_init();
|
||||
|
||||
/* init kernel object */
|
||||
rt_system_object_init();
|
||||
|
||||
/* init timer system */
|
||||
rt_system_timer_init();
|
||||
|
||||
rt_system_heap_init((void*)K64_SRAM_BEGIN, (void*)K64_SRAM_END);
|
||||
|
||||
/* init scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
/* init all device */
|
||||
rt_device_init_all();
|
||||
|
||||
/* init application */
|
||||
rt_application_init();
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
/* init finsh */
|
||||
finsh_system_init();
|
||||
finsh_set_device( FINSH_DEVICE_NAME );
|
||||
#endif
|
||||
|
||||
/* init timer thread */
|
||||
rt_system_timer_thread_init();
|
||||
|
||||
/* init idle thread */
|
||||
rt_thread_idle_init();
|
||||
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
|
||||
/* never reach here */
|
||||
return ;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* disable interrupt first */
|
||||
rt_hw_interrupt_disable();
|
||||
|
||||
/* startup RT-Thread RTOS */
|
||||
rtthread_startup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,12 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'board')
|
||||
src = Glob('*.c')
|
||||
src += Glob('*.s')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <MK64F12.H>
|
||||
#include "board.h"
|
||||
|
||||
#include "drv_uart.h"
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup K60
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_Configuration
|
||||
* Description : Configures Vector Table base location.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
SystemCoreClockUpdate(); /* Update Core Clock Frequency */
|
||||
SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); /* Generate interrupt each 1 ms */
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial Tower board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
NVIC_Configuration();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
rt_hw_uart_init();
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(CONSOLE_DEVICE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* File : board.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <MK64F12.H>
|
||||
|
||||
|
||||
/* board configuration */
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <8-64>
|
||||
// <i>Default: 64
|
||||
#define K64_SRAM_SIZE 256
|
||||
#define K64_SRAM_END (0x1FFF0000 + (K64_SRAM_SIZE * 1024))
|
||||
|
||||
//#define RT_USING_UART1
|
||||
#define RT_USING_UART5
|
||||
//#define RT_USING_UART3
|
||||
|
||||
// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
|
||||
// <i>Default: 1
|
||||
#define K64_CONSOLE_USART 0
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#if K64_CONSOLE_USART == 0
|
||||
#define CONSOLE_DEVICE "uart0"
|
||||
#elif K64_CONSOLE_USART == 1
|
||||
#define CONSOLE_DEVICE "uart1"
|
||||
#elif K64_CONSOLE_USART == 2
|
||||
#define CONSOLE_DEVICE "uart2"
|
||||
#elif K64_CONSOLE_USART == 3
|
||||
#define CONSOLE_DEVICE "uart3"
|
||||
#elif K64_CONSOLE_USART == 4
|
||||
#define CONSOLE_DEVICE "uart4"
|
||||
#elif K64_CONSOLE_USART == 5
|
||||
#define CONSOLE_DEVICE "uart5"
|
||||
#endif
|
||||
|
||||
#define FINSH_DEVICE_NAME CONSOLE_DEVICE
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
@@ -0,0 +1,269 @@
|
||||
/*
|
||||
* File : drv_uart.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include "drv_uart.h"
|
||||
|
||||
static struct rt_serial_device _k64_serial; //abstracted serial for RTT
|
||||
static struct serial_ringbuffer _k64_int_rx; //UART send buffer area
|
||||
|
||||
struct k64_serial_device
|
||||
{
|
||||
/* UART base address */
|
||||
UART_Type *baseAddress;
|
||||
|
||||
/* UART IRQ Number */
|
||||
int irq_num;
|
||||
|
||||
/* device config */
|
||||
struct serial_configure config;
|
||||
};
|
||||
|
||||
//hardware abstract device
|
||||
static struct k64_serial_device _k64_node =
|
||||
{
|
||||
(UART_Type *)UART0,
|
||||
UART0_RX_TX_IRQn,
|
||||
};
|
||||
|
||||
static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2 = 0,reg_BRFA=0;
|
||||
unsigned int cal_SBR = 0;
|
||||
UART_Type *uart_reg;
|
||||
|
||||
/* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
|
||||
* calculate baud_rate
|
||||
*/
|
||||
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
|
||||
/*
|
||||
* set bit order
|
||||
*/
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
|
||||
|
||||
/*
|
||||
* set data_bits
|
||||
*/
|
||||
if (cfg->data_bits == DATA_BITS_8)
|
||||
reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
|
||||
else if (cfg->data_bits == DATA_BITS_9)
|
||||
reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
|
||||
|
||||
/*
|
||||
* set parity
|
||||
*/
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
{
|
||||
reg_C1 &= ~(UART_C1_PE_MASK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* first ,set parity enable bit */
|
||||
reg_C1 |= (UART_C1_PE_MASK);
|
||||
|
||||
/* second ,determine parity odd or even*/
|
||||
if (cfg->parity == PARITY_ODD)
|
||||
reg_C1 |= UART_C1_PT_MASK;
|
||||
if (cfg->parity == PARITY_EVEN)
|
||||
reg_C1 &= ~(UART_C1_PT_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
* set NZR mode
|
||||
* not tested
|
||||
*/
|
||||
if (cfg->invert != NRZ_NORMAL)
|
||||
{
|
||||
/* not in normal mode ,set inverted polarity */
|
||||
reg_C3 |= UART_C3_TXINV_MASK;
|
||||
}
|
||||
|
||||
switch ((unsigned int)uart_reg)
|
||||
{
|
||||
/*
|
||||
* if you're using other board
|
||||
* set clock and pin map for UARTx
|
||||
*/
|
||||
case UART0_BASE:
|
||||
/* calc SBR */
|
||||
cal_SBR = SystemCoreClock / (16 * cfg->baud_rate);
|
||||
|
||||
/* check to see if sbr is out of range of register bits */
|
||||
if ((cal_SBR > 0x1FFF) || (cal_SBR < 1))
|
||||
{
|
||||
/* unsupported baud rate for given source clock input*/
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
/* calc baud_rate */
|
||||
reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
|
||||
reg_BDL = cal_SBR & 0x00FF;
|
||||
|
||||
/* fractional divider */
|
||||
reg_BRFA = ((SystemCoreClock * 32) / (cfg->baud_rate * 16)) - (cal_SBR * 32);
|
||||
|
||||
reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
|
||||
|
||||
SIM_SOPT5 &= ~ SIM_SOPT5_UART0RXSRC(0);
|
||||
SIM_SOPT5 |= SIM_SOPT5_UART0RXSRC(0);
|
||||
SIM_SOPT5 &= ~ SIM_SOPT5_UART0TXSRC(0);
|
||||
SIM_SOPT5 |= SIM_SOPT5_UART0TXSRC(0);
|
||||
|
||||
// set UART0 clock
|
||||
// Enable UART gate clocking
|
||||
// Enable PORTE gate clocking
|
||||
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
|
||||
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
|
||||
|
||||
// set UART0 pin
|
||||
PORTB->PCR[16] &= ~(3UL << 8);
|
||||
PORTB->PCR[16] |= (3UL << 8); // Pin mux configured as ALT3
|
||||
|
||||
PORTB->PCR[17] &= ~(3UL << 8);
|
||||
PORTB->PCR[17] |= (3UL << 8); // Pin mux configured as ALT3
|
||||
break;
|
||||
|
||||
default:
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
uart_reg->BDH = reg_BDH;
|
||||
uart_reg->BDL = reg_BDL;
|
||||
uart_reg->C1 = reg_C1;
|
||||
uart_reg->C4 = reg_C4;
|
||||
uart_reg->S2 = reg_S2;
|
||||
|
||||
uart_reg->S2 = 0;
|
||||
uart_reg->C3 = 0;
|
||||
|
||||
uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
|
||||
uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
|
||||
|
||||
uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK; //Transmitter enable
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
int uart_irq_num = 0;
|
||||
|
||||
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
uart_irq_num = ((struct k64_serial_device *)serial->parent.user_data)->irq_num;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
uart_reg->C2 &= ~UART_C2_RIE_MASK;
|
||||
//disable NVIC
|
||||
NVIC->ICER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
uart_reg->C2 |= UART_C2_RIE_MASK;
|
||||
//enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
|
||||
NVIC->ICPR[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
|
||||
NVIC->ISER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SUSPEND:
|
||||
/* suspend device */
|
||||
uart_reg->C2 &= ~(UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK); //Transmitter enable
|
||||
break;
|
||||
case RT_DEVICE_CTRL_RESUME:
|
||||
/* resume device */
|
||||
uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK; //Transmitter enable
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int _putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
|
||||
while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
|
||||
uart_reg->D = (c & 0xFF);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int _getc(struct rt_serial_device *serial)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
uart_reg = ((struct k64_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
|
||||
if (uart_reg->S1 & UART_S1_RDRF_MASK)
|
||||
return (uart_reg->D);
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _k64_ops =
|
||||
{
|
||||
_configure,
|
||||
_control,
|
||||
_putc,
|
||||
_getc,
|
||||
};
|
||||
|
||||
|
||||
void UART0_RX_TX_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
rt_hw_serial_isr((struct rt_serial_device*)&_k64_serial);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config;
|
||||
|
||||
/* fake configuration */
|
||||
config.baud_rate = BAUD_RATE_115200;
|
||||
config.bit_order = BIT_ORDER_LSB;
|
||||
config.data_bits = DATA_BITS_8;
|
||||
config.parity = PARITY_NONE;
|
||||
config.stop_bits = STOP_BITS_1;
|
||||
config.invert = NRZ_NORMAL;
|
||||
|
||||
_k64_serial.ops = &_k64_ops;
|
||||
_k64_serial.int_rx = &_k64_int_rx;
|
||||
_k64_serial.config = config;
|
||||
|
||||
rt_hw_serial_register(&_k64_serial, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
(void*)&_k64_node);
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while(*str != '\0')
|
||||
{
|
||||
if (*str == '\n')
|
||||
_putc(&_k64_serial,'\r');
|
||||
_putc(&_k64_serial,*str);
|
||||
str++;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* File : drv_uart.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H
|
||||
#define DRV_UART_H
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <MK64F12.H>
|
||||
|
||||
#include <drivers/serial.h>
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
//for kernel debug when console not registered
|
||||
void rt_hw_console_output(const char *str);
|
||||
|
||||
#endif /* end of include guard: DRV_UART_H */
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* File : led.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#include <MK64F12.H>
|
||||
#include "led.h"
|
||||
|
||||
const rt_uint32_t led_mask[] = {1 << 21, 1 << 22, 1 << 26};
|
||||
|
||||
void rt_hw_led_init(void)
|
||||
{
|
||||
SIM_SCGC5 |= (1 << SIM_SCGC5_PORTB_SHIFT);
|
||||
SIM_SCGC5 |= (1 << SIM_SCGC5_PORTE_SHIFT);
|
||||
|
||||
PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
|
||||
PORTB->PCR[21] |= PORT_PCR_MUX(1); //PTB21 is GPIO pin
|
||||
|
||||
PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
|
||||
PORTB->PCR[22] |= PORT_PCR_MUX(1); //PTB22 is GPIO pin
|
||||
|
||||
PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
|
||||
PORTE->PCR[26] |= PORT_PCR_MUX(1); //PTE26 is GPIO pin
|
||||
|
||||
/* Switch LEDs off and enable output*/
|
||||
PTB->PDDR |= GPIO_PDDR_PDD(led_mask[1] | led_mask[0]);
|
||||
PTE->PDDR |= GPIO_PDDR_PDD(led_mask[2]);
|
||||
|
||||
rt_hw_led_off(LED_RED);
|
||||
rt_hw_led_off(LED_GREEN);
|
||||
rt_hw_led_off(LED_BLUE);
|
||||
}
|
||||
|
||||
void rt_hw_led_uninit(void)
|
||||
{
|
||||
PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
|
||||
|
||||
PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
|
||||
|
||||
PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
|
||||
}
|
||||
|
||||
void rt_hw_led_on(rt_uint32_t n)
|
||||
{
|
||||
if (n != LED_GREEN)
|
||||
{
|
||||
PTB->PCOR |= led_mask[n];
|
||||
}
|
||||
else
|
||||
{
|
||||
PTE->PCOR |= led_mask[n];
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_led_off(rt_uint32_t n)
|
||||
{
|
||||
if (n != LED_GREEN)
|
||||
{
|
||||
PTB->PSOR |= led_mask[n];
|
||||
}
|
||||
else
|
||||
{
|
||||
PTE->PSOR |= led_mask[n];
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* File : led.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LED_H__
|
||||
#define __LED_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
enum LED_NUM
|
||||
{
|
||||
LED_BLUE,
|
||||
LED_RED,
|
||||
LED_GREEN,
|
||||
LED_MAX
|
||||
};
|
||||
|
||||
void rt_hw_led_init(void);
|
||||
void rt_hw_led_uninit(void);
|
||||
void rt_hw_led_on(rt_uint32_t n);
|
||||
void rt_hw_led_off(rt_uint32_t n);
|
||||
|
||||
#endif /* end of __LED_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_DMAMUX_REGISTERS_H__
|
||||
#define __HW_DMAMUX_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
/*
|
||||
* MK64F12 DMAMUX
|
||||
*
|
||||
* DMA channel multiplexor
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_DMAMUX_CHCFGn - Channel Configuration register
|
||||
*
|
||||
* - hw_dmamux_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_DMAMUX_BASE
|
||||
#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
|
||||
#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
|
||||
#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
|
||||
|
||||
//! @brief Table of base addresses for DMAMUX instances.
|
||||
static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
|
||||
REGS_DMAMUX0_BASE,
|
||||
};
|
||||
|
||||
//! @brief Get the base address of DMAMUX by instance number.
|
||||
//! @param x DMAMUX instance number, from 0 through 0.
|
||||
#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
|
||||
|
||||
//! @brief Get the instance number given a base address.
|
||||
//! @param b Base address for an instance of DMAMUX.
|
||||
#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_DMAMUX_CHCFGn - Channel Configuration register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* Each of the DMA channels can be independently enabled/disabled and associated
|
||||
* with one of the DMA slots (peripheral slots or always-on slots) in the
|
||||
* system. Setting multiple CHCFG registers with the same source value will result in
|
||||
* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
|
||||
* Before changing the trigger or source settings, a DMA channel must be disabled
|
||||
* via CHCFGn[ENBL].
|
||||
*/
|
||||
typedef union _hw_dmamux_chcfgn
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_dmamux_chcfgn_bitfields
|
||||
{
|
||||
uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
|
||||
uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
|
||||
uint8_t ENBL : 1; //!< [7] DMA Channel Enable
|
||||
} B;
|
||||
} hw_dmamux_chcfgn_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire DMAMUX_CHCFGn register
|
||||
*/
|
||||
//@{
|
||||
#define HW_DMAMUX_CHCFGn_COUNT (16U)
|
||||
|
||||
#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
|
||||
#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
|
||||
#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
|
||||
#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
|
||||
#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
|
||||
#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual DMAMUX_CHCFGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
|
||||
*
|
||||
* Specifies which DMA source, if any, is routed to a particular DMA channel.
|
||||
* See your device's chip configuration details for information about the
|
||||
* peripherals and their slot numbers.
|
||||
*/
|
||||
//@{
|
||||
#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
|
||||
#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
|
||||
#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
|
||||
#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
|
||||
#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SOURCE field to a new value.
|
||||
#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
|
||||
*
|
||||
* Enables the periodic trigger capability for the triggered DMA channel.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
|
||||
* DMA Channel will simply route the specified source to the DMA channel.
|
||||
* (Normal mode)
|
||||
* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
|
||||
* DMAMUX is in Periodic Trigger mode.
|
||||
*/
|
||||
//@{
|
||||
#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
|
||||
#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
|
||||
#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
|
||||
#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
|
||||
#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the TRIG field to a new value.
|
||||
#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
|
||||
*
|
||||
* Enables the DMA channel.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - DMA channel is disabled. This mode is primarily used during
|
||||
* configuration of the DMAMux. The DMA has separate channel enables/disables, which
|
||||
* should be used to disable or reconfigure a DMA channel.
|
||||
* - 1 - DMA channel is enabled
|
||||
*/
|
||||
//@{
|
||||
#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
|
||||
#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
|
||||
#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
|
||||
#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
|
||||
#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the ENBL field to a new value.
|
||||
#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_dmamux_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All DMAMUX module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_dmamux
|
||||
{
|
||||
__IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
|
||||
} hw_dmamux_t;
|
||||
#pragma pack()
|
||||
|
||||
//! @brief Macro to access all DMAMUX registers.
|
||||
//! @param x DMAMUX instance number.
|
||||
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
|
||||
#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
|
||||
#endif
|
||||
|
||||
#endif // __HW_DMAMUX_REGISTERS_H__
|
||||
// v22/130726/0.9
|
||||
// EOF
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,430 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_EWM_REGISTERS_H__
|
||||
#define __HW_EWM_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
/*
|
||||
* MK64F12 EWM
|
||||
*
|
||||
* External Watchdog Monitor
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_EWM_CTRL - Control Register
|
||||
* - HW_EWM_SERV - Service Register
|
||||
* - HW_EWM_CMPL - Compare Low Register
|
||||
* - HW_EWM_CMPH - Compare High Register
|
||||
*
|
||||
* - hw_ewm_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_EWM_BASE
|
||||
#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
|
||||
#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_EWM_CTRL - Control Register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_EWM_CTRL - Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
|
||||
* written once after a CPU reset. Modifying these bits more than once, generates
|
||||
* a bus transfer error.
|
||||
*/
|
||||
typedef union _hw_ewm_ctrl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_ctrl_bitfields
|
||||
{
|
||||
uint8_t EWMEN : 1; //!< [0] EWM enable.
|
||||
uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
|
||||
uint8_t INEN : 1; //!< [2] Input Enable.
|
||||
uint8_t INTEN : 1; //!< [3] Interrupt Enable.
|
||||
uint8_t RESERVED0 : 4; //!< [7:4]
|
||||
} B;
|
||||
} hw_ewm_ctrl_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CTRL register
|
||||
*/
|
||||
//@{
|
||||
#define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
|
||||
#define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
|
||||
#define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
|
||||
#define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
|
||||
#define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
|
||||
#define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CTRL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field EWMEN[0] (RW)
|
||||
*
|
||||
* This bit when set, enables the EWM module. This resets the EWM counter to
|
||||
* zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
|
||||
* therefore it cannot be enabled until a reset occurs, due to the write-once
|
||||
* nature of this bit.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
|
||||
#define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
|
||||
#define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CTRL_EWMEN field.
|
||||
#define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CTRL_EWMEN.
|
||||
#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the EWMEN field to a new value.
|
||||
#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field ASSIN[1] (RW)
|
||||
*
|
||||
* Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
|
||||
* inverts the assert state to a logic one.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
|
||||
#define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
|
||||
#define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CTRL_ASSIN field.
|
||||
#define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CTRL_ASSIN.
|
||||
#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the ASSIN field to a new value.
|
||||
#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field INEN[2] (RW)
|
||||
*
|
||||
* This bit when set, enables the EWM_in port.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
|
||||
#define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
|
||||
#define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CTRL_INEN field.
|
||||
#define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CTRL_INEN.
|
||||
#define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the INEN field to a new value.
|
||||
#define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CTRL, field INTEN[3] (RW)
|
||||
*
|
||||
* This bit when set and EWM_out is asserted, an interrupt request is generated.
|
||||
* To de-assert interrupt request, user should clear this bit by writing 0.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
|
||||
#define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
|
||||
#define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CTRL_INTEN field.
|
||||
#define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CTRL_INTEN.
|
||||
#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the INTEN field to a new value.
|
||||
#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_EWM_SERV - Service Register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_EWM_SERV - Service Register (WORZ)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The SERV register provides the interface from the CPU to the EWM module. It
|
||||
* is write-only and reads of this register return zero.
|
||||
*/
|
||||
typedef union _hw_ewm_serv
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_serv_bitfields
|
||||
{
|
||||
uint8_t SERVICE : 8; //!< [7:0]
|
||||
} B;
|
||||
} hw_ewm_serv_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_SERV register
|
||||
*/
|
||||
//@{
|
||||
#define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
|
||||
#define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
|
||||
#define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_SERV bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
|
||||
*
|
||||
* The EWM service mechanism requires the CPU to write two values to the SERV
|
||||
* register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
|
||||
* EWM service is illegal if either of the following conditions is true. The
|
||||
* first or second data byte is not written correctly. The second data byte is not
|
||||
* written within a fixed number of peripheral bus cycles of the first data byte.
|
||||
* This fixed number of cycles is called EWM_service_time.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
|
||||
#define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
|
||||
#define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
|
||||
|
||||
//! @brief Format value for bitfield EWM_SERV_SERVICE.
|
||||
#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SERVICE field to a new value.
|
||||
#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_EWM_CMPL - Compare Low Register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_EWM_CMPL - Compare Low Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* The CMPL register is reset to zero after a CPU reset. This provides no
|
||||
* minimum time for the CPU to service the EWM counter. This register can be written
|
||||
* only once after a CPU reset. Writing this register more than once generates a
|
||||
* bus transfer error.
|
||||
*/
|
||||
typedef union _hw_ewm_cmpl
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_cmpl_bitfields
|
||||
{
|
||||
uint8_t COMPAREL : 8; //!< [7:0]
|
||||
} B;
|
||||
} hw_ewm_cmpl_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CMPL register
|
||||
*/
|
||||
//@{
|
||||
#define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
|
||||
#define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
|
||||
#define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
|
||||
#define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
|
||||
#define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
|
||||
#define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CMPL bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
|
||||
*
|
||||
* To prevent runaway code from changing this field, software should write to
|
||||
* this field after a CPU reset even if the (default) minimum service time is
|
||||
* required.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
|
||||
#define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
|
||||
#define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CMPL_COMPAREL field.
|
||||
#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
|
||||
#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the COMPAREL field to a new value.
|
||||
#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_EWM_CMPH - Compare High Register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_EWM_CMPH - Compare High Register (RW)
|
||||
*
|
||||
* Reset value: 0xFFU
|
||||
*
|
||||
* The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
|
||||
* of 256 clocks time, for the CPU to service the EWM counter. This register can
|
||||
* be written only once after a CPU reset. Writing this register more than once
|
||||
* generates a bus transfer error. The valid values for CMPH are up to 0xFE
|
||||
* because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
|
||||
* if EWM counter is greater than CMPH.
|
||||
*/
|
||||
typedef union _hw_ewm_cmph
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_ewm_cmph_bitfields
|
||||
{
|
||||
uint8_t COMPAREH : 8; //!< [7:0]
|
||||
} B;
|
||||
} hw_ewm_cmph_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire EWM_CMPH register
|
||||
*/
|
||||
//@{
|
||||
#define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
|
||||
#define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
|
||||
#define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
|
||||
#define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
|
||||
#define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
|
||||
#define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual EWM_CMPH bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
|
||||
*
|
||||
* To prevent runaway code from changing this field, software should write to
|
||||
* this field after a CPU reset even if the (default) maximum service time is
|
||||
* required.
|
||||
*/
|
||||
//@{
|
||||
#define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
|
||||
#define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
|
||||
#define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the EWM_CMPH_COMPAREH field.
|
||||
#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
|
||||
#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the COMPAREH field to a new value.
|
||||
#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_ewm_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All EWM module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_ewm
|
||||
{
|
||||
__IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
|
||||
__O hw_ewm_serv_t SERV; //!< [0x1] Service Register
|
||||
__IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
|
||||
__IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
|
||||
} hw_ewm_t;
|
||||
#pragma pack()
|
||||
|
||||
//! @brief Macro to access all EWM registers.
|
||||
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
//! use the '&' operator, like <code>&HW_EWM</code>.
|
||||
#define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
|
||||
#endif
|
||||
|
||||
#endif // __HW_EWM_REGISTERS_H__
|
||||
// v22/130726/0.9
|
||||
// EOF
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,302 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_OSC_REGISTERS_H__
|
||||
#define __HW_OSC_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
/*
|
||||
* MK64F12 OSC
|
||||
*
|
||||
* Oscillator
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_OSC_CR - OSC Control Register
|
||||
*
|
||||
* - hw_osc_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_OSC_BASE
|
||||
#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
|
||||
#define HW_OSC0 (0U) //!< Instance number for OSC.
|
||||
#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
|
||||
|
||||
//! @brief Table of base addresses for OSC instances.
|
||||
static const uint32_t __g_regs_OSC_base_addresses[] = {
|
||||
REGS_OSC0_BASE,
|
||||
};
|
||||
|
||||
//! @brief Get the base address of OSC by instance number.
|
||||
//! @param x OSC instance number, from 0 through 0.
|
||||
#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
|
||||
|
||||
//! @brief Get the instance number given a base address.
|
||||
//! @param b Base address for an instance of OSC.
|
||||
#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_OSC_CR - OSC Control Register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_OSC_CR - OSC Control Register (RW)
|
||||
*
|
||||
* Reset value: 0x00U
|
||||
*
|
||||
* After OSC is enabled and starts generating the clocks, the configurations
|
||||
* such as low power and frequency range, must not be changed.
|
||||
*/
|
||||
typedef union _hw_osc_cr
|
||||
{
|
||||
uint8_t U;
|
||||
struct _hw_osc_cr_bitfields
|
||||
{
|
||||
uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
|
||||
uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
|
||||
uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
|
||||
uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
|
||||
uint8_t RESERVED0 : 1; //!< [4]
|
||||
uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
|
||||
uint8_t RESERVED1 : 1; //!< [6]
|
||||
uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
|
||||
} B;
|
||||
} hw_osc_cr_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire OSC_CR register
|
||||
*/
|
||||
//@{
|
||||
#define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
|
||||
#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
|
||||
#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
|
||||
#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
|
||||
#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
|
||||
#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual OSC_CR bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC16P[0] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 16 pF capacitor to the oscillator load.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
|
||||
#define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
|
||||
#define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_SC16P field.
|
||||
#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_SC16P.
|
||||
#define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SC16P field to a new value.
|
||||
#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC8P[1] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 8 pF capacitor to the oscillator load.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
|
||||
#define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
|
||||
#define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_SC8P field.
|
||||
#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_SC8P.
|
||||
#define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SC8P field to a new value.
|
||||
#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC4P[2] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 4 pF capacitor to the oscillator load.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
|
||||
#define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
|
||||
#define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_SC4P field.
|
||||
#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_SC4P.
|
||||
#define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SC4P field to a new value.
|
||||
#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field SC2P[3] (RW)
|
||||
*
|
||||
* Configures the oscillator load.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - Disable the selection.
|
||||
* - 1 - Add 2 pF capacitor to the oscillator load.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
|
||||
#define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
|
||||
#define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_SC2P field.
|
||||
#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_SC2P.
|
||||
#define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the SC2P field to a new value.
|
||||
#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field EREFSTEN[5] (RW)
|
||||
*
|
||||
* Controls whether or not the external reference clock (OSCERCLK) remains
|
||||
* enabled when MCU enters Stop mode.
|
||||
*
|
||||
* Values:
|
||||
* - 0 - External reference clock is disabled in Stop mode.
|
||||
* - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
|
||||
* before entering Stop mode.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
|
||||
#define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
|
||||
#define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_EREFSTEN field.
|
||||
#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_EREFSTEN.
|
||||
#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the EREFSTEN field to a new value.
|
||||
#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register OSC_CR, field ERCLKEN[7] (RW)
|
||||
*
|
||||
* Enables external reference clock (OSCERCLK).
|
||||
*
|
||||
* Values:
|
||||
* - 0 - External reference clock is inactive.
|
||||
* - 1 - External reference clock is enabled.
|
||||
*/
|
||||
//@{
|
||||
#define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
|
||||
#define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
|
||||
#define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the OSC_CR_ERCLKEN field.
|
||||
#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield OSC_CR_ERCLKEN.
|
||||
#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the ERCLKEN field to a new value.
|
||||
#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_osc_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All OSC module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_osc
|
||||
{
|
||||
__IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
|
||||
} hw_osc_t;
|
||||
#pragma pack()
|
||||
|
||||
//! @brief Macro to access all OSC registers.
|
||||
//! @param x OSC instance number.
|
||||
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
//! use the '&' operator, like <code>&HW_OSC(0)</code>.
|
||||
#define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
|
||||
#endif
|
||||
|
||||
#endif // __HW_OSC_REGISTERS_H__
|
||||
// v22/130726/0.9
|
||||
// EOF
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_RFSYS_REGISTERS_H__
|
||||
#define __HW_RFSYS_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
/*
|
||||
* MK64F12 RFSYS
|
||||
*
|
||||
* System register file
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_RFSYS_REGn - Register file register
|
||||
*
|
||||
* - hw_rfsys_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_RFSYS_BASE
|
||||
#define HW_RFSYS_INSTANCE_COUNT (1U) //!< Number of instances of the RFSYS module.
|
||||
#define REGS_RFSYS_BASE (0x40041000U) //!< Base address for RFSYS.
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_RFSYS_REGn - Register file register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_RFSYS_REGn - Register file register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Each register can be accessed as 8-, 16-, or 32-bits.
|
||||
*/
|
||||
typedef union _hw_rfsys_regn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_rfsys_regn_bitfields
|
||||
{
|
||||
uint32_t LL : 8; //!< [7:0]
|
||||
uint32_t LH : 8; //!< [15:8]
|
||||
uint32_t HL : 8; //!< [23:16]
|
||||
uint32_t HH : 8; //!< [31:24]
|
||||
} B;
|
||||
} hw_rfsys_regn_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire RFSYS_REGn register
|
||||
*/
|
||||
//@{
|
||||
#define HW_RFSYS_REGn_COUNT (8U)
|
||||
|
||||
#define HW_RFSYS_REGn_ADDR(n) (REGS_RFSYS_BASE + 0x0U + (0x4U * n))
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_RFSYS_REGn(n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(n))
|
||||
#define HW_RFSYS_REGn_RD(n) (HW_RFSYS_REGn(n).U)
|
||||
#define HW_RFSYS_REGn_WR(n, v) (HW_RFSYS_REGn(n).U = (v))
|
||||
#define HW_RFSYS_REGn_SET(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) | (v)))
|
||||
#define HW_RFSYS_REGn_CLR(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) & ~(v)))
|
||||
#define HW_RFSYS_REGn_TOG(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual RFSYS_REGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field LL[7:0] (RW)
|
||||
*
|
||||
* Low lower byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFSYS_REGn_LL (0U) //!< Bit position for RFSYS_REGn_LL.
|
||||
#define BM_RFSYS_REGn_LL (0x000000FFU) //!< Bit mask for RFSYS_REGn_LL.
|
||||
#define BS_RFSYS_REGn_LL (8U) //!< Bit field size in bits for RFSYS_REGn_LL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFSYS_REGn_LL field.
|
||||
#define BR_RFSYS_REGn_LL(n) (HW_RFSYS_REGn(n).B.LL)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFSYS_REGn_LL.
|
||||
#define BF_RFSYS_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LL), uint32_t) & BM_RFSYS_REGn_LL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the LL field to a new value.
|
||||
#define BW_RFSYS_REGn_LL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field LH[15:8] (RW)
|
||||
*
|
||||
* Low higher byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFSYS_REGn_LH (8U) //!< Bit position for RFSYS_REGn_LH.
|
||||
#define BM_RFSYS_REGn_LH (0x0000FF00U) //!< Bit mask for RFSYS_REGn_LH.
|
||||
#define BS_RFSYS_REGn_LH (8U) //!< Bit field size in bits for RFSYS_REGn_LH.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFSYS_REGn_LH field.
|
||||
#define BR_RFSYS_REGn_LH(n) (HW_RFSYS_REGn(n).B.LH)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFSYS_REGn_LH.
|
||||
#define BF_RFSYS_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LH), uint32_t) & BM_RFSYS_REGn_LH)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the LH field to a new value.
|
||||
#define BW_RFSYS_REGn_LH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field HL[23:16] (RW)
|
||||
*
|
||||
* High lower byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFSYS_REGn_HL (16U) //!< Bit position for RFSYS_REGn_HL.
|
||||
#define BM_RFSYS_REGn_HL (0x00FF0000U) //!< Bit mask for RFSYS_REGn_HL.
|
||||
#define BS_RFSYS_REGn_HL (8U) //!< Bit field size in bits for RFSYS_REGn_HL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFSYS_REGn_HL field.
|
||||
#define BR_RFSYS_REGn_HL(n) (HW_RFSYS_REGn(n).B.HL)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFSYS_REGn_HL.
|
||||
#define BF_RFSYS_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HL), uint32_t) & BM_RFSYS_REGn_HL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the HL field to a new value.
|
||||
#define BW_RFSYS_REGn_HL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFSYS_REGn, field HH[31:24] (RW)
|
||||
*
|
||||
* High higher byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFSYS_REGn_HH (24U) //!< Bit position for RFSYS_REGn_HH.
|
||||
#define BM_RFSYS_REGn_HH (0xFF000000U) //!< Bit mask for RFSYS_REGn_HH.
|
||||
#define BS_RFSYS_REGn_HH (8U) //!< Bit field size in bits for RFSYS_REGn_HH.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFSYS_REGn_HH field.
|
||||
#define BR_RFSYS_REGn_HH(n) (HW_RFSYS_REGn(n).B.HH)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFSYS_REGn_HH.
|
||||
#define BF_RFSYS_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HH), uint32_t) & BM_RFSYS_REGn_HH)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the HH field to a new value.
|
||||
#define BW_RFSYS_REGn_HH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_rfsys_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All RFSYS module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_rfsys
|
||||
{
|
||||
__IO hw_rfsys_regn_t REGn[8]; //!< [0x0] Register file register
|
||||
} hw_rfsys_t;
|
||||
#pragma pack()
|
||||
|
||||
//! @brief Macro to access all RFSYS registers.
|
||||
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
//! use the '&' operator, like <code>&HW_RFSYS</code>.
|
||||
#define HW_RFSYS (*(hw_rfsys_t *) REGS_RFSYS_BASE)
|
||||
#endif
|
||||
|
||||
#endif // __HW_RFSYS_REGISTERS_H__
|
||||
// v22/130726/0.9
|
||||
// EOF
|
||||
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||
*
|
||||
* This file was generated automatically and any changes may be lost.
|
||||
*/
|
||||
#ifndef __HW_RFVBAT_REGISTERS_H__
|
||||
#define __HW_RFVBAT_REGISTERS_H__
|
||||
|
||||
#include "regs.h"
|
||||
|
||||
/*
|
||||
* MK64F12 RFVBAT
|
||||
*
|
||||
* VBAT register file
|
||||
*
|
||||
* Registers defined in this header file:
|
||||
* - HW_RFVBAT_REGn - VBAT register file register
|
||||
*
|
||||
* - hw_rfvbat_t - Struct containing all module registers.
|
||||
*/
|
||||
|
||||
//! @name Module base addresses
|
||||
//@{
|
||||
#ifndef REGS_RFVBAT_BASE
|
||||
#define HW_RFVBAT_INSTANCE_COUNT (1U) //!< Number of instances of the RFVBAT module.
|
||||
#define REGS_RFVBAT_BASE (0x4003E000U) //!< Base address for RFVBAT.
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// HW_RFVBAT_REGn - VBAT register file register
|
||||
//-------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
/*!
|
||||
* @brief HW_RFVBAT_REGn - VBAT register file register (RW)
|
||||
*
|
||||
* Reset value: 0x00000000U
|
||||
*
|
||||
* Each register can be accessed as 8-, 16-, or 32-bits.
|
||||
*/
|
||||
typedef union _hw_rfvbat_regn
|
||||
{
|
||||
uint32_t U;
|
||||
struct _hw_rfvbat_regn_bitfields
|
||||
{
|
||||
uint32_t LL : 8; //!< [7:0]
|
||||
uint32_t LH : 8; //!< [15:8]
|
||||
uint32_t HL : 8; //!< [23:16]
|
||||
uint32_t HH : 8; //!< [31:24]
|
||||
} B;
|
||||
} hw_rfvbat_regn_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Constants and macros for entire RFVBAT_REGn register
|
||||
*/
|
||||
//@{
|
||||
#define HW_RFVBAT_REGn_COUNT (8U)
|
||||
|
||||
#define HW_RFVBAT_REGn_ADDR(n) (REGS_RFVBAT_BASE + 0x0U + (0x4U * n))
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#define HW_RFVBAT_REGn(n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(n))
|
||||
#define HW_RFVBAT_REGn_RD(n) (HW_RFVBAT_REGn(n).U)
|
||||
#define HW_RFVBAT_REGn_WR(n, v) (HW_RFVBAT_REGn(n).U = (v))
|
||||
#define HW_RFVBAT_REGn_SET(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) | (v)))
|
||||
#define HW_RFVBAT_REGn_CLR(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) & ~(v)))
|
||||
#define HW_RFVBAT_REGn_TOG(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) ^ (v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*
|
||||
* Constants & macros for individual RFVBAT_REGn bitfields
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field LL[7:0] (RW)
|
||||
*
|
||||
* Low lower byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFVBAT_REGn_LL (0U) //!< Bit position for RFVBAT_REGn_LL.
|
||||
#define BM_RFVBAT_REGn_LL (0x000000FFU) //!< Bit mask for RFVBAT_REGn_LL.
|
||||
#define BS_RFVBAT_REGn_LL (8U) //!< Bit field size in bits for RFVBAT_REGn_LL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFVBAT_REGn_LL field.
|
||||
#define BR_RFVBAT_REGn_LL(n) (HW_RFVBAT_REGn(n).B.LL)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFVBAT_REGn_LL.
|
||||
#define BF_RFVBAT_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LL), uint32_t) & BM_RFVBAT_REGn_LL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the LL field to a new value.
|
||||
#define BW_RFVBAT_REGn_LL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field LH[15:8] (RW)
|
||||
*
|
||||
* Low higher byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFVBAT_REGn_LH (8U) //!< Bit position for RFVBAT_REGn_LH.
|
||||
#define BM_RFVBAT_REGn_LH (0x0000FF00U) //!< Bit mask for RFVBAT_REGn_LH.
|
||||
#define BS_RFVBAT_REGn_LH (8U) //!< Bit field size in bits for RFVBAT_REGn_LH.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFVBAT_REGn_LH field.
|
||||
#define BR_RFVBAT_REGn_LH(n) (HW_RFVBAT_REGn(n).B.LH)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFVBAT_REGn_LH.
|
||||
#define BF_RFVBAT_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LH), uint32_t) & BM_RFVBAT_REGn_LH)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the LH field to a new value.
|
||||
#define BW_RFVBAT_REGn_LH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field HL[23:16] (RW)
|
||||
*
|
||||
* High lower byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFVBAT_REGn_HL (16U) //!< Bit position for RFVBAT_REGn_HL.
|
||||
#define BM_RFVBAT_REGn_HL (0x00FF0000U) //!< Bit mask for RFVBAT_REGn_HL.
|
||||
#define BS_RFVBAT_REGn_HL (8U) //!< Bit field size in bits for RFVBAT_REGn_HL.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFVBAT_REGn_HL field.
|
||||
#define BR_RFVBAT_REGn_HL(n) (HW_RFVBAT_REGn(n).B.HL)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFVBAT_REGn_HL.
|
||||
#define BF_RFVBAT_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HL), uint32_t) & BM_RFVBAT_REGn_HL)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the HL field to a new value.
|
||||
#define BW_RFVBAT_REGn_HL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
/*!
|
||||
* @name Register RFVBAT_REGn, field HH[31:24] (RW)
|
||||
*
|
||||
* High higher byte
|
||||
*/
|
||||
//@{
|
||||
#define BP_RFVBAT_REGn_HH (24U) //!< Bit position for RFVBAT_REGn_HH.
|
||||
#define BM_RFVBAT_REGn_HH (0xFF000000U) //!< Bit mask for RFVBAT_REGn_HH.
|
||||
#define BS_RFVBAT_REGn_HH (8U) //!< Bit field size in bits for RFVBAT_REGn_HH.
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Read current value of the RFVBAT_REGn_HH field.
|
||||
#define BR_RFVBAT_REGn_HH(n) (HW_RFVBAT_REGn(n).B.HH)
|
||||
#endif
|
||||
|
||||
//! @brief Format value for bitfield RFVBAT_REGn_HH.
|
||||
#define BF_RFVBAT_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HH), uint32_t) & BM_RFVBAT_REGn_HH)
|
||||
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
//! @brief Set the HH field to a new value.
|
||||
#define BW_RFVBAT_REGn_HH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
|
||||
#endif
|
||||
//@}
|
||||
|
||||
//-------------------------------------------------------------------------------------------
|
||||
// hw_rfvbat_t - module struct
|
||||
//-------------------------------------------------------------------------------------------
|
||||
/*!
|
||||
* @brief All RFVBAT module registers.
|
||||
*/
|
||||
#ifndef __LANGUAGE_ASM__
|
||||
#pragma pack(1)
|
||||
typedef struct _hw_rfvbat
|
||||
{
|
||||
__IO hw_rfvbat_regn_t REGn[8]; //!< [0x0] VBAT register file register
|
||||
} hw_rfvbat_t;
|
||||
#pragma pack()
|
||||
|
||||
//! @brief Macro to access all RFVBAT registers.
|
||||
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||
//! use the '&' operator, like <code>&HW_RFVBAT</code>.
|
||||
#define HW_RFVBAT (*(hw_rfvbat_t *) REGS_RFVBAT_BASE)
|
||||
#endif
|
||||
|
||||
#endif // __HW_RFVBAT_REGISTERS_H__
|
||||
// v22/130726/0.9
|
||||
// EOF
|
||||
File diff suppressed because it is too large
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