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Update nuvoton porting.

Browse Source 
1. Make up sources and bugfix.
2. Add nu_gpio_pin_get.
3. Add PM operator in USB host driver.
4. Support NUC980 stage 1 and add nk-980iot board.
This commit is contained in:
Wayne Lin
2020-12-21 14:57:09 +08:00
parent c924330469
commit 8d90cfadf0
158 changed files with 47829 additions and 363 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/nuvoton/README.md
+3 -2
View File
@@ -3,5 +3,6 @@ Current supported BSP shown in below table:
| **BSP folder** | **Board name** |
|:------------------------- |:-------------------------- |
| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-m487 |
| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-m487 |
| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
| [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
bsp/nuvoton/libraries/m480/StdDriver/src/nu_can.c
+2 -2
View File
@@ -1148,11 +1148,11 @@ int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType,
int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
{
int32_t rev = (int32_t)TRUE;
uint32_t i = 0ul;
uint32_t i;
uint32_t u32TimeOutCount;
uint32_t u32EOB_Flag = 0ul;
for(i = 1ul; i < u32MsgCount; i++)
for(i = 1ul; i <= u32MsgCount; i++)
{
u32TimeOutCount = 0ul;
bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h
+1 -1
View File
@@ -141,7 +141,7 @@ typedef int (UAC_CB_FUNC)(struct uac_dev_t *dev, uint8_t *data, int len); /*!
/* */
/*------------------------------------------------------------------*/
extern void usbh_core_init(void);
extern int usbh_pooling_root_hubs(void);
extern int usbh_polling_root_hubs(void);
extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
extern void usbh_suspend(void);
extern void usbh_resume(void);
bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c
+1 -1
View File
@@ -80,7 +80,7 @@ void usbh_core_init()
* @retval 0 No any hub port status changes found.
* @retval 1 There's hub port status changes.
*/
int usbh_pooling_root_hubs(void)
int usbh_polling_root_hubs(void)
{
int ret, change = 0;
bsp/nuvoton/libraries/m480/rtt_port/Kconfig
+7
View File
@@ -941,6 +941,13 @@ config SOC_SERIES_M480
select RT_USING_USB_HOST
select RT_USBH_MSTORAGE
if BSP_USING_USBH || BSP_USING_HSUSBH
config NU_USBHOST_HUB_POLLING_INTERVAL
int "USB Root Hub Polling Interval(in Mili-seconds)"
range 100 2000
default 100
endif
config BSP_USING_HSOTG
bool "Enable High-Speed USB On-The-Go(HSOTG)"
select BSP_USING_HSUSBH
bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
+4 -2
View File
@@ -12,6 +12,7 @@
#include <rtconfig.h>
#if defined(BSP_USING_BPWM_CAPTURE)
#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
@@ -211,7 +212,7 @@ static rt_err_t nu_bpwm_init(nu_capture_t *nu_capture)
/* Enable BPWM0 clock */
SYS_UnlockReg();
CLK_EnableModuleClock(BPWM0_MODULE);
CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PLL, (uint32_t)NULL);
CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PLL, 0);
SYS_LockReg();
bpwm_config(nu_capture);
bBPWM0Inited = RT_TRUE;
@@ -225,7 +226,7 @@ static rt_err_t nu_bpwm_init(nu_capture_t *nu_capture)
/* Enable BPWM1 clock */
SYS_UnlockReg();
CLK_EnableModuleClock(BPWM1_MODULE);
CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PLL, (uint32_t)NULL);
CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PLL, 0);
SYS_LockReg();
bpwm_config(nu_capture);
bBPWM1Inited = RT_TRUE;
@@ -330,4 +331,5 @@ static int nu_bpwm_capture_device_init(void)
}
INIT_DEVICE_EXPORT(nu_bpwm_capture_device_init);
#endif //#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
#endif //#if defined(BSP_USING_BPWM_CAPTURE)
bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
+5 -4
View File
@@ -369,7 +369,7 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
/*set the filter message object*/
if (filter_cfg->items[i].mode == 1)
{
if (CAN_SetRxMsgObjAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
if (CAN_SetRxMsgObjAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
{
return -(RT_ERROR);
}
@@ -378,7 +378,7 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
/*set the filter message object*/
if (CAN_SetRxMsgAndMsk(can_base, MSG(i + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
if (CAN_SetRxMsgAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
{
return -(RT_ERROR);
}
@@ -439,7 +439,7 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
}
break;
default:
return -(RT_EINVAL);
return -(RT_EINVAL);
}
@@ -507,7 +507,8 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
#ifdef RT_CAN_USING_HDR
/* Hardware filter messages are valid */
can->hdr->connected = 1;
pmsg->hdr = boxno - RX_MSG_ID_INDEX;
can->hdr[pmsg->hdr].connected = 1;
#endif
/* Standard ID (11 bits)*/
bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
+21 -41
View File
@@ -89,64 +89,44 @@ static struct rt_pm_ops ops =
struct rt_device pm;
/* Sleep and power-down mapping */
const static uint32_t g_au32SleepingMode[PM_SLEEP_MODE_MAX] =
{
0,
0,
CONFIG_MODE_LIGHT,
CONFIG_MODE_DEEP,
CONFIG_MODE_STANDBY,
CONFIG_MODE_SHUTDOWN
};
/* pm sleep() entry */
static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode)
{
SYS_UnlockReg();
RT_ASSERT(mode < PM_SLEEP_MODE_MAX);
if ((mode == PM_SLEEP_MODE_NONE) || (mode == PM_SLEEP_MODE_IDLE))
return;
switch (mode)
{
/* wake-up source: */
/* PM_SLEEP_MODE_LIGHT : TIMERn */
/* PM_SLEEP_MODE_DEEP : TIMERn */
/* PM_SLEEP_MODE_STANDBY : wake-up timer (optional) */
/* PM_SLEEP_MODE_SHUTDOWN : wake-up timer (optional) */
case PM_SLEEP_MODE_NONE:
case PM_SLEEP_MODE_IDLE:
break;
case PM_SLEEP_MODE_LIGHT:
CLK_SetPowerDownMode(CONFIG_MODE_LIGHT);
CLK_PowerDown();
break;
case PM_SLEEP_MODE_DEEP:
CLK_SetPowerDownMode(CONFIG_MODE_DEEP);
CLK_PowerDown();
break;
case PM_SLEEP_MODE_STANDBY:
SYS_UnlockReg();
#if defined (NU_CLK_INVOKE_WKTMR)
if ((mode == PM_SLEEP_MODE_SHUTDOWN) || (mode == PM_SLEEP_MODE_STANDBY))
{
/* Enable wake-up timer with pre-defined interval if it is invoked */
CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL);
CLK_ENABLE_WKTMR();
#endif
CLK_SetPowerDownMode(CONFIG_MODE_STANDBY);
CLK_PowerDown();
break;
case PM_SLEEP_MODE_SHUTDOWN:
#if defined (NU_CLK_INVOKE_WKTMR)
/* Enable wake-up timer with pre-defined interval if it is invoked */
CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL);
CLK_ENABLE_WKTMR();
#endif
CLK_SetPowerDownMode(CONFIG_MODE_SHUTDOWN);
CLK_PowerDown();
break;
default:
RT_ASSERT(0);
break;
}
#endif
CLK_SetPowerDownMode(g_au32SleepingMode[mode]);
CLK_PowerDown();
SYS_LockReg();
}
bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
+13 -10
View File
@@ -25,6 +25,11 @@
/* Private define ---------------------------------------------------------------*/
#define NU_CRYPTO_CRC_NAME "nu_CRC"
#define CRC_32_POLY 0x04C11DB7
#define CRC_CCITT_POLY 0x00001021
#define CRC_16_POLY 0x00008005
#define CRC_8_POLY 0x00000007
/* Private variables ------------------------------------------------------------*/
static struct rt_mutex s_CRC_mutex;
@@ -85,7 +90,6 @@ static rt_uint32_t nu_crc_run(
return u32CalChecksum;
}
rt_err_t nu_crc_init(void)
{
SYS_ResetModule(CRC_RST);
@@ -103,30 +107,29 @@ rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_siz
//select CRC operation mode
switch (ctx->crc_cfg.poly)
{
case 0x04C11DB7:
case CRC_32_POLY:
u32OpMode = CRC_32;
break;
case 0x00001021:
case CRC_CCITT_POLY:
u32OpMode = CRC_CCITT;
break;
case 0x00008005:
case CRC_16_POLY:
u32OpMode = CRC_16;
break;
case 0x00000007:
case CRC_8_POLY:
u32OpMode = CRC_8;
break;
default:
return 0;
}
u32CRCAttr |= (ctx->crc_cfg.flags & CRC_FLAG_REFOUT) ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse
u32CRCAttr |= (ctx->crc_cfg.flags & CRC_FLAG_REFIN) ? CRC_WDATA_RVS : 0; //CRC Write Data Reverse
u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFOUT ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse
u32CRCAttr |= ctx->crc_cfg.flags & CRC_FLAG_REFIN ? CRC_WDATA_RVS : 0; //CRC Write Data Reverse
//Calcluate CRC checksum, using config's last value as CRC seed
//Calculate CRC checksum, using config's last value as CRC seed
crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length);
//update CRC result to config's last vaule
//update CRC result to config's last value
ctx->crc_cfg.last_val = crc_result;
return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout;
}
bsp/nuvoton/libraries/m480/rtt_port/drv_crc.h
-1
View File
@@ -17,5 +17,4 @@ rt_err_t nu_crc_init(void);
rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length);
#endif
bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
+239 -60
View File
File diff suppressed because it is too large Load Diff
bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
+5 -4
View File
@@ -12,6 +12,7 @@
#include <rtconfig.h>
#if defined(BSP_USING_ECAP)
#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
@@ -262,7 +263,7 @@ static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputca
else /* Overrun case */
fTempCnt = nu_capture->u32CurrentCnt + ((0x1000000 - nu_capture->u32LastCnt) + 1);
*pulsewidth_us =(int)(fTempCnt * nu_capture->ecap_dev->fUsPerTick);
*pulsewidth_us = (int)(fTempCnt * nu_capture->ecap_dev->fUsPerTick);
nu_capture->u32LastCnt = nu_capture->u32CurrentCnt;
@@ -430,7 +431,7 @@ static int nu_ecap_capture_device_init(void)
#if (BSP_USING_ECAP0_CHMSK!=0)
if (BSP_USING_ECAP0_CHMSK & (0x1 << i))
{
nu_ecap0_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t));
nu_ecap0_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
ecap_init(nu_ecap0_capture[i], i, &nu_ecap0_dev, nu_ecap0_device_name[i]);
}
#endif //#if (BSP_USING_ECAP0_CHMSK!=0)
@@ -438,7 +439,7 @@ static int nu_ecap_capture_device_init(void)
#if (BSP_USING_ECAP1_CHMSK!=0)
if (BSP_USING_ECAP1_CHMSK & (0x1 << i))
{
nu_ecap1_capture[i] = (nu_capture_t*)rt_malloc(sizeof(nu_capture_t));
nu_ecap1_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
ecap_init(nu_ecap1_capture[i], i, &nu_ecap1_dev, nu_ecap1_device_name[i]);
}
#endif //#if (BSP_USING_ECAP1_CHMSK!=0)
@@ -447,5 +448,5 @@ static int nu_ecap_capture_device_init(void)
return 0;
}
INIT_DEVICE_EXPORT(nu_ecap_capture_device_init);
#endif //#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
#endif //#if defined(BSP_USING_ECAP)
bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
+8 -7
View File
@@ -12,6 +12,7 @@
#include <rtconfig.h>
#if defined(BSP_USING_EPWM_CAPTURE)
#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
@@ -73,7 +74,7 @@ static rt_err_t CalPulseWidth(nu_capture_t *nu_capture)
bWrapAroundFlag = RT_TRUE;
}
/* Read the capture counter value if falling/risning edge */
/* Read the capture counter value if falling/rising edge */
if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 1)//Rising edge
{
EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH);
@@ -294,7 +295,7 @@ void EPWM1P1_IRQHandler(void)
void EPWM1P2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter()
rt_interrupt_enter();
/* Avoid excessive iteration by monitoring enabled channels */
#if (BSP_USING_EPWM1_CAPTURE_CHMSK&(0x1<<EPWM_CH4CH5_POS))
@@ -366,7 +367,7 @@ static rt_err_t nu_epwm_init(nu_capture_t *nu_capture)
/* Enable EPWM0 clock */
SYS_UnlockReg();
CLK_EnableModuleClock(EPWM0_MODULE);
CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PLL, (uint32_t)NULL);
CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PLL, 0);
SYS_LockReg();
bEPWM0Inited = RT_TRUE;
}
@@ -379,7 +380,7 @@ static rt_err_t nu_epwm_init(nu_capture_t *nu_capture)
/* Enable EPWM1 clock */
SYS_UnlockReg();
CLK_EnableModuleClock(EPWM1_MODULE);
CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PLL, (uint32_t)NULL);
CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PLL, 0);
SYS_LockReg();
bEPWM1Inited = RT_TRUE;
}
@@ -416,7 +417,7 @@ static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
nu_capture = (nu_capture_t *) inputcapture;
/* Set capture time as 1000 nano second */
/* Set capture time as 1000 nanosecond */
EPWM_ConfigCaptureChannel(nu_capture->epwm, nu_capture->u8Channel, 1000, 0);
/* Enable capture rising/falling edge interrupt */
@@ -500,10 +501,10 @@ int nu_epwm_capture_device_init(void)
rt_device_inputcapture_register(&nu_epwm1_capture[i].parent, nu_epwm1_device_name[i], &nu_epwm1_capture[i]);
}
}
#endif //#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
#endif //#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
return 0;
}
INIT_DEVICE_EXPORT(nu_epwm_capture_device_init);
#endif //#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
#endif //#if defined(BSP_USING_EPWM_CAPTURE)
bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c
+6 -1
View File
@@ -159,7 +159,7 @@ int nu_fmc_erase(long addr, size_t size)
uint32_t addr_end = addr + size;
#if defined(NU_SUPPORT_NONALIGN)
uint8_t *page_sdtemp = RT_NULL;
uint8_t *page_sdtemp = RT_NULL;
uint8_t *page_edtemp = RT_NULL;
@@ -316,6 +316,11 @@ static int nu_fmc_init(void)
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
/* PKG_USING_FAL */
#if defined(PKG_USING_FAL)
fal_init();
#endif
return (int)RT_EOK;
}
INIT_APP_EXPORT(nu_fmc_init);
bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
+28 -1
View File
@@ -19,6 +19,7 @@
#include <NuMicro.h>
#include <nu_bitutil.h>
#include <drv_gpio.h>
#include <stdlib.h>
/* Private define ---------------------------------------------------------------*/
@@ -34,6 +35,7 @@ static int nu_gpio_read(struct rt_device *device, rt_base_t pin);
static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args);
static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin);
static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled);
static rt_base_t nu_gpio_pin_get(const char *name);
/* Private variables ------------------------------------------------------------*/
static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM];
@@ -45,7 +47,7 @@ static struct rt_pin_ops nu_gpio_ops =
nu_gpio_attach_irq,
nu_gpio_detach_irq,
nu_gpio_irq_enable,
RT_NULL,
nu_gpio_pin_get,
};
static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn};
@@ -102,6 +104,31 @@ static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index)
}
}
static rt_base_t nu_gpio_pin_get(const char *name)
{
/* Get pin number by name,such as PA.0, PF12 */
if ((name[2] == '\0') || ((name[2] == '.') && (name[3] == '\0')))
return -(RT_EINVAL);
long number;
if ((name[2] == '.'))
number = atol(&name[3]);
else
number = atol(&name[2]);
if (number > 15)
return -(RT_EINVAL);
if (name[1] >= 'A' && name[1] <= 'H')
return ((name[1] - 'A') * 0x10) + number;
if (name[1] >= 'a' && name[1] <= 'h')
return ((name[1] - 'a') * 0x10) + number;
return -(RT_EINVAL);
}
static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
GPIO_T *PORT;
bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
+3 -3
View File
@@ -202,9 +202,9 @@ static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c,
if (ret != RT_EOK) /* for timeout condition */
return -RT_EIO;
if ( (I2C_GET_STATUS(nu_i2c->I2C)
!= ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK))
&& !ignore_nack)
if ((I2C_GET_STATUS(nu_i2c->I2C)
!= ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK))
&& !ignore_nack)
{
LOG_E("sending address failed\n");
return -RT_EIO;
bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c
+81 -38
View File
@@ -54,7 +54,6 @@ struct nu_pdma_memfun_actor
{
int m_i32ChannID;
uint32_t m_u32Result;
uint32_t m_u32TrigTransferCnt;
rt_sem_t m_psSemMemFun;
} ;
typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t;
@@ -553,6 +552,8 @@ rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u3
goto exit_nu_pdma_desc_setup;
else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8)))
goto exit_nu_pdma_desc_setup;
else if ( i32TransferCnt > NU_PDMA_MAX_TXCNT )
goto exit_nu_pdma_desc_setup;
psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
@@ -701,9 +702,10 @@ static rt_err_t nu_pdma_sgtbls_valid(nu_pdma_desc_t head)
node = (nu_pdma_desc_t)(node->NEXT + PDMA->SCATBA);
} while (((uint32_t)node != PDMA->SCATBA) && (node != head));
}
while (((uint32_t)node != PDMA->SCATBA) && (node != head));
return RT_EOK;
return RT_EOK;
}
static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
@@ -718,7 +720,7 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
PDMA_SetTransferMode(PDMA,
i32ChannID,
u32Peripheral,
(head != NULL) ? 1 : 0,
(head->NEXT != 0) ? 1 : 0,
(uint32_t)head);
/* If peripheral is M2M, trigger it. */
@@ -747,7 +749,7 @@ rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32Add
if (ret != RT_EOK)
goto exit_nu_pdma_transfer;
_nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, NULL, u32IdleTimeout_us);
_nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, &PDMA->DSCT[i32ChannID], u32IdleTimeout_us);
ret = RT_EOK;
@@ -765,7 +767,7 @@ rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32Id
goto exit_nu_pdma_sg_transfer;
else if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
goto exit_nu_pdma_sg_transfer;
else if ( (ret=nu_pdma_sgtbls_valid(head)) != RT_EOK ) /* Check SG-tbls. */
else if ((ret = nu_pdma_sgtbls_valid(head)) != RT_EOK) /* Check SG-tbls. */
goto exit_nu_pdma_sg_transfer;
psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
@@ -912,11 +914,14 @@ static int nu_pdma_memfun_employ(void)
return idx;
}
static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl)
static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl)
{
nu_pdma_memfun_actor_t psMemFunActor = NULL;
int idx;
rt_size_t ret = 0;
rt_uint32_t u32Offset = 0;
rt_uint32_t u32TxCnt = 0;
while (1)
{
/* Employ actor */
@@ -925,37 +930,51 @@ static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, un
psMemFunActor = &nu_pdma_memfun_actor_arr[idx];
psMemFunActor->m_u32TrigTransferCnt = count;
/* Set PDMA memory control to eMemCtl. */
nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl);
/* Register ISR callback function */
nu_pdma_callback_register(psMemFunActor->m_i32ChannID, nu_pdma_memfun_cb, (void *)psMemFunActor, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE);
psMemFunActor->m_u32Result = 0;
/* Trigger it */
nu_pdma_transfer(psMemFunActor->m_i32ChannID, u32DataWidth, (uint32_t)src, (uint32_t)dest, count, 0);
/* Wait it done. */
rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER);
/* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/
if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE)
do
{
ret = psMemFunActor->m_u32TrigTransferCnt;
}
else
{
ret = psMemFunActor->m_u32TrigTransferCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID);
}
/* Terminate it if get ABORT event */
if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT)
{
nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID);
u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt;
/* Set PDMA memory control to eMemCtl. */
nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl);
/* Register ISR callback function */
nu_pdma_callback_register(psMemFunActor->m_i32ChannID, nu_pdma_memfun_cb, (void *)psMemFunActor, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE);
psMemFunActor->m_u32Result = 0;
/* Trigger it */
nu_pdma_transfer(psMemFunActor->m_i32ChannID,
u32DataWidth,
(eMemCtl & 0x2ul) ? (uint32_t)src + u32Offset : (uint32_t)src, /* Src address is Inc or not. */
(eMemCtl & 0x1ul) ? (uint32_t)dest + u32Offset : (uint32_t)dest, /* Dst address is Inc or not. */
u32TxCnt,
0);
/* Wait it done. */
rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER);
/* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/
if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE)
{
ret += u32TxCnt;
}
else
{
ret += (u32TxCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID));
}
/* Terminate it if get ABORT event */
if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT)
{
nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID);
break;
}
u32TransferCnt -= u32TxCnt;
u32Offset += u32TxCnt;
}
while (u32TransferCnt > 0);
rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER);
nu_pdma_memfun_actor_mask &= ~(1 << idx);
@@ -979,10 +998,34 @@ rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned i
void *nu_pdma_memcpy(void *dest, void *src, unsigned int count)
{
if (count == nu_pdma_memfun(dest, src, 8, count, eMemCtl_SrcInc_DstInc))
int i = 0;
uint32_t u32Offset = 0;
uint32_t u32Remaining = count;
for (i = 4; (i > 0) && (u32Remaining > 0) ; i >>= 1)
{
uint32_t u32src = (uint32_t)src + u32Offset;
uint32_t u32dest = (uint32_t)dest + u32Offset;
if (((u32src % i) == (u32dest % i)) &&
((u32src % i) == 0) &&
(RT_ALIGN_DOWN(u32Remaining, i) >= i))
{
uint32_t u32TXCnt = u32Remaining / i;
if (u32TXCnt != nu_pdma_memfun((void *)u32dest, (void *)u32src, i * 8, u32TXCnt, eMemCtl_SrcInc_DstInc))
goto exit_nu_pdma_memcpy;
u32Offset += (u32TXCnt * i);
u32Remaining -= (u32TXCnt * i);
}
}
if (count == u32Offset)
return dest;
else
return NULL;
exit_nu_pdma_memcpy:
return NULL;
}
/**
bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
+1
View File
@@ -31,6 +31,7 @@
#define NU_PDMA_UNUSED (-1)
#define NU_PDMA_SG_LIMITED_DISTANCE ((PDMA_DSCT_NEXT_NEXT_Msk>>PDMA_DSCT_NEXT_NEXT_Pos)+1)
#define NU_PDMA_MAX_TXCNT ((PDMA_DSCT_CTL_TXCNT_Msk>>PDMA_DSCT_CTL_TXCNT_Pos) + 1)
typedef enum
{
bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
+5 -5
View File
@@ -52,21 +52,21 @@
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args);
#if defined (NU_RTC_SUPPORT_IO_RW)
static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
#endif
static rt_err_t nu_rtc_is_date_valid(const time_t *const t);
static void nu_rtc_init(void);
#if defined(RT_USING_ALARM)
static void nu_rtc_alarm_reset(void);
static void nu_rtc_alarm_reset(void);
#endif
/* Public functions -------------------------------------------------------------*/
#if defined (NU_RTC_SUPPORT_MSH_CMD)
extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day);
extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second);
extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day);
extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second);
#endif
/* Private variables ------------------------------------------------------------*/
bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c
+24 -11
View File
@@ -342,25 +342,38 @@ exit_nu_pdma_spi_tx_config:
static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
{
rt_err_t result = RT_EOK;
rt_uint32_t u32Offset = 0;
rt_uint32_t u32TransferCnt = length / bytes_per_word;
rt_uint32_t u32TxCnt = 0;
/* Get base address of spi register */
SPI_T *spi_base = spi_bus->spi_base;
result = nu_pdma_spi_rx_config(spi_bus, recv_addr, length, bytes_per_word);
RT_ASSERT(result == RT_EOK);
result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word);
RT_ASSERT(result == RT_EOK);
do
{
u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt;
result = nu_pdma_spi_rx_config(spi_bus, (recv_addr == RT_NULL) ? recv_addr : &recv_addr[u32Offset], (u32TxCnt * bytes_per_word), bytes_per_word);
RT_ASSERT(result == RT_EOK);
/* Trigger TX/RX PDMA transfer. */
SPI_TRIGGER_TX_RX_PDMA(spi_base);
result = nu_pdma_spi_tx_config(spi_bus, (send_addr == RT_NULL) ? send_addr : &send_addr[u32Offset], (u32TxCnt * bytes_per_word), bytes_per_word);
RT_ASSERT(result == RT_EOK);
/* Wait RX-PDMA transfer done */
rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER);
/* Trigger TX/RX PDMA transfer. */
SPI_TRIGGER_TX_RX_PDMA(spi_base);
/* Stop TX/RX DMA transfer. */
SPI_DISABLE_TX_RX_PDMA(spi_base);
/* Wait RX-PDMA transfer done */
rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER);
return result;
/* Stop TX/RX DMA transfer. */
SPI_DISABLE_TX_RX_PDMA(spi_base);
u32TransferCnt -= u32TxCnt;
u32Offset += u32TxCnt;
}
while (u32TransferCnt > 0);
return length;
}
rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus)
bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c
+15 -11
View File
@@ -13,6 +13,10 @@
#include <rtconfig.h>
#if defined(BSP_USING_TIMER_CAPTURE)
#if defined(BSP_USING_TIMER0_CAPTURE)|| \
defined(BSP_USING_TIMER1_CAPTURE)|| \
defined(BSP_USING_TIMER2_CAPTURE)|| \
defined(BSP_USING_TIMER3_CAPTURE)
#include <rtdevice.h>
#include <NuMicro.h>
@@ -150,8 +154,6 @@ static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputca
static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
{
rt_err_t ret = RT_ERROR;
SYS_UnlockReg();
#if defined(BSP_USING_TIMER0_CAPTURE)
@@ -160,8 +162,6 @@ static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
/* Enable TIMER0 clock */
CLK_EnableModuleClock(TMR0_MODULE);
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0);
ret = RT_EOK;
goto exit_nu_timer_init;
}
#endif
@@ -171,8 +171,6 @@ static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
/* Enable TIMER1 clock */
CLK_EnableModuleClock(TMR1_MODULE);
CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0);
ret = RT_EOK;
goto exit_nu_timer_init;
}
#endif
@@ -182,8 +180,6 @@ static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
/* Enable TIMER2 clock */
CLK_EnableModuleClock(TMR2_MODULE);
CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, 0);
ret = RT_EOK;
goto exit_nu_timer_init;
}
#endif
@@ -193,12 +189,17 @@ static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
/* Enable TIMER3 clock */
CLK_EnableModuleClock(TMR3_MODULE);
CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_PCLK1, 0);
goto exit_nu_timer_init;
}
#endif
exit_nu_timer_init:
SYS_LockReg();
return -(ret);
return -(RT_ERROR);
exit_nu_timer_init:
SYS_LockReg();
return RT_EOK;
}
static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
@@ -241,6 +242,9 @@ static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
/* Enable Timer NVIC */
NVIC_EnableIRQ(nu_capture->irq);
/* Reset counter before openning. */
TIMER_ResetCounter(nu_capture->timer);
TIMER_Open(nu_capture->timer, TIMER_CONTINUOUS_MODE, 1);
TIMER_SET_PRESCALE_VALUE(nu_capture->timer, cal_time_prescale(nu_capture));
TIMER_SET_CMP_VALUE(nu_capture->timer, 0xFFFFFF);
@@ -318,5 +322,5 @@ static int nu_timer_capture_device_init(void)
return 0;
}
INIT_DEVICE_EXPORT(nu_timer_capture_device_init);
#endif //#if defined(BSP_USING_TIMER*_CAPTURE)
#endif //#if defined(BSP_USING_TIMER_CAPTURE)
bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c
+1 -1
View File
@@ -15,8 +15,8 @@
#if (defined(BSP_USING_TRNG) && defined(RT_HWCRYPTO_USING_RNG))
#include <rtdevice.h>
#include <stdlib.h>
#include "NuMicro.h"
#include <stdlib.h>
#define NU_CRYPTO_TRNG_NAME "nu_TRNG"
bsp/nuvoton/libraries/m480/rtt_port/drv_trng.h
-1
View File
@@ -18,4 +18,3 @@ void nu_trng_open(void);
rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx);
#endif
bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
+2 -2
View File
@@ -546,7 +546,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
nu_pdma_uart_rx_cb,
(void *)serial,
NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
if ( result != RT_EOK )
if (result != RT_EOK)
{
goto exit_nu_pdma_uart_rx_config;
}
@@ -557,7 +557,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
(uint32_t)pu8Buf,
i32TriggerLen,
1000); //Idle-timeout, 1ms
if ( result != RT_EOK )
if (result != RT_EOK)
{
goto exit_nu_pdma_uart_rx_config;
}
bsp/nuvoton/libraries/m480/rtt_port/drv_usbd.c
+1 -1
View File
@@ -364,7 +364,7 @@ __STATIC_INLINE void _USBD_IRQHandler(void)
/* Clear event flag */
USBD_CLR_INT_FLAG(USBD_INTSTS_EP0);
if ( (USBD_GET_ADDR() == 0)
if ((USBD_GET_ADDR() == 0)
&& (nu_usbd.address_tmp)
)
{
bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
+72 -32
View File
@@ -22,6 +22,10 @@
#include "usb.h"
#include "usbh_lib.h"
#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL)
#define NU_USBHOST_HUB_POLLING_INTERVAL (100)
#endif
#define NU_MAX_USBH_PORT 2 //USB1.1 + USB2.0 port
#define NU_MAX_USBH_PIPE 16
#define NU_USBH_THREAD_STACK_SIZE 2048
@@ -51,6 +55,7 @@ typedef struct nu_port_ctrl
struct nu_usbh_dev
{
uhcd_t uhcd;
rt_thread_t polling_thread;
S_NU_RH_PORT_CTRL asPortCtrl[NU_MAX_USBH_PORT];
};
@@ -290,7 +295,6 @@ static rt_err_t nu_open_pipe(upipe_t pipe)
static rt_err_t nu_close_pipe(upipe_t pipe)
{
int i;
S_NU_RH_PORT_CTRL *psPortCtrl;
S_NU_PORT_DEV *psPortDev;
@@ -309,6 +313,7 @@ static rt_err_t nu_close_pipe(upipe_t pipe)
{
if (psPortDev->pUDev)
{
int i;
for (i = 0; i < NU_MAX_USBH_PIPE; i++)
{
if (psPortDev->apsEPInfo[i] != NULL)
@@ -320,7 +325,6 @@ static rt_err_t nu_close_pipe(upipe_t pipe)
free_device(psPortDev->pUDev);
psPortDev->pUDev = NULL;
}
psPortDev->port_num = 0;
}
}
@@ -615,8 +619,8 @@ static void nu_usbh_rh_thread_entry(void *parameter)
{
while (1)
{
usbh_pooling_root_hubs();
rt_thread_delay(10);
usbh_polling_root_hubs();
rt_thread_mdelay(NU_USBHOST_HUB_POLLING_INTERVAL);
}
}
@@ -674,6 +678,8 @@ static void nu_hcd_disconnect_callback(
return;
}
port_index = i + 1;
for (i = 0; i < NU_MAX_USBH_PIPE; i++)
{
if (psPortCtrl->sRHPortDev.apsEPInfo[i] != NULL)
@@ -682,10 +688,9 @@ static void nu_hcd_disconnect_callback(
}
}
port_index = i + 1;
psPortCtrl->sRHPortDev.pUDev = NULL;
RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n"));
RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnect\n"));
rt_usbh_root_hub_disconnect_handler(s_sUSBHDev.uhcd, port_index);
}
@@ -701,22 +706,21 @@ static struct uhcd_ops nu_uhcd_ops =
static rt_err_t nu_hcd_init(rt_device_t device)
{
rt_thread_t thread;
struct nu_usbh_dev * pNuUSBHDev = (struct nu_usbh_dev *)device;
usbh_core_init();
//install connect/disconnect callback
usbh_install_conn_callback(nu_hcd_connect_callback, nu_hcd_disconnect_callback);
usbh_pooling_root_hubs();
usbh_polling_root_hubs();
//create thread for polling usbh port status
/* create usb hub thread */
thread = rt_thread_create("usbh_drv", nu_usbh_rh_thread_entry, RT_NULL,
pNuUSBHDev->polling_thread = rt_thread_create("usbh_drv", nu_usbh_rh_thread_entry, RT_NULL,
NU_USBH_THREAD_STACK_SIZE, 8, 20);
if (thread != RT_NULL)
if ( pNuUSBHDev->polling_thread != RT_NULL)
{
/* startup usb host thread */
rt_thread_startup(thread);
rt_thread_startup( pNuUSBHDev->polling_thread );
}
else
{
@@ -742,6 +746,54 @@ uint32_t usbh_tick_from_millisecond(uint32_t msec)
return rt_tick_from_millisecond(msec);
}
#if defined(RT_USING_PM)
/* device pm suspend() entry. */
static int usbhost_pm_suspend(const struct rt_device *device, rt_uint8_t mode)
{
struct nu_usbh_dev * pNuUSBHDev = (struct nu_usbh_dev *)device;
RT_ASSERT(pNuUSBHDev!=RT_NULL);
switch (mode)
{
case PM_SLEEP_MODE_LIGHT:
case PM_SLEEP_MODE_DEEP:
pNuUSBHDev->polling_thread->stat = RT_THREAD_READY;
rt_thread_suspend(pNuUSBHDev->polling_thread);
break;
default:
break;
}
return (int)RT_EOK;
}
/* device pm resume() entry. */
static void usbhost_pm_resume(const struct rt_device *device, rt_uint8_t mode)
{
struct nu_usbh_dev * pNuUSBHDev = (struct nu_usbh_dev *)device;
RT_ASSERT(pNuUSBHDev!=RT_NULL);
switch (mode)
{
case PM_SLEEP_MODE_LIGHT:
case PM_SLEEP_MODE_DEEP:
rt_thread_resume(pNuUSBHDev->polling_thread);
break;
default:
break;
}
}
static struct rt_device_pm_ops device_pm_ops =
{
.suspend = usbhost_pm_suspend,
.resume = usbhost_pm_resume,
.frequency_change = RT_NULL
};
#endif
int nu_usbh_register(void)
{
@@ -760,9 +812,6 @@ int nu_usbh_register(void)
#endif
#if defined(BSP_USING_USBH)
/* Enable USBD and OTG clock */
CLK_EnableModuleClock(USBD_MODULE);
CLK_EnableModuleClock(OTG_MODULE);
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ;
@@ -775,11 +824,7 @@ int nu_usbh_register(void)
rt_memset(&s_sUSBHDev, 0x0, sizeof(struct nu_usbh_dev));
uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd));
if (uhcd == RT_NULL)
{
rt_kprintf("uhcd malloc failed\r\n");
return -RT_ERROR;
}
RT_ASSERT(res != RT_NULL);
rt_memset((void *)uhcd, 0, sizeof(struct uhcd));
@@ -792,23 +837,18 @@ int nu_usbh_register(void)
s_sUSBHDev.uhcd = uhcd;
res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE);
if (res != RT_EOK)
{
rt_kprintf("register usb host failed res = %d\r\n", res);
return -RT_ERROR;
}
RT_ASSERT(res == RT_EOK);
/*initialize the usb host functin */
/*initialize the usb host function */
res = rt_usb_host_init();
RT_ASSERT(res == RT_EOK);
#if defined(RT_USING_PM)
rt_pm_device_register(&uhcd->parent, &device_pm_ops);
#endif
return RT_EOK;
}
INIT_DEVICE_EXPORT(nu_usbh_register);
#endif
bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c
+1 -1
View File
@@ -493,7 +493,7 @@ static void nu_uspi_transfer(struct nu_uspi *uspi_bus, uint8_t *tx, uint8_t *rx,
/* DMA transfer constrains */
if ((uspi_bus->pdma_chanid_rx >= 0) &&
!((uint32_t)tx % bytes_per_word) &&
!((uint32_t)rx % bytes_per_word) )
!((uint32_t)rx % bytes_per_word))
nu_uspi_pdma_transmit(uspi_bus, tx, rx, length, bytes_per_word);
else
nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word);
bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c
+12 -11
View File
@@ -91,16 +91,17 @@ typedef volatile struct soft_time_handle soft_time_handle_t;
/* Private functions ------------------------------------------------------------*/
static rt_err_t wdt_init(rt_watchdog_t *dev);
static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args);
static uint32_t wdt_get_module_clock(void);
static uint32_t wdt_get_working_hz(void);
static void soft_time_init(soft_time_handle_t *const soft_time);
static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time);
static void soft_time_feed_dog(soft_time_handle_t *const soft_time);
#if defined(RT_USING_PM)
static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode);
static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode);
static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode);
static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time);
static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode);
static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode);
static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode);
static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time);
#endif
/* Public functions -------------------------------------------------------------*/
@@ -118,7 +119,6 @@ static struct rt_watchdog_ops ops_wdt =
static struct rt_device_pm_ops device_pm_ops =
{
.suspend = wdt_pm_suspend,
.resume = wdt_pm_resume,
.frequency_change = wdt_pm_frequency_change
@@ -180,12 +180,6 @@ static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode)
}
static uint32_t wdt_get_module_clock(void)
{
return (CLK_GetModuleClockSource(WDT_MODULE) << CLK_CLKSEL1_WDTSEL_Pos);
}
/* device pm frequency_change() entry. */
static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode)
{
@@ -288,6 +282,12 @@ static rt_err_t wdt_init(rt_watchdog_t *dev)
}
static uint32_t wdt_get_module_clock(void)
{
return (CLK_GetModuleClockSource(WDT_MODULE) << CLK_CLKSEL1_WDTSEL_Pos);
}
static uint32_t wdt_get_working_hz(void)
{
uint32_t clk, hz = 0;
@@ -408,6 +408,7 @@ static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args)
case RT_DEVICE_CTRL_WDT_START:
WDT_RESET_COUNTER();
WDT_Open(MIN_TOUTSEL, WDT_RESET_DELAY_1026CLK, TRUE, TRUE);
WDT_EnableInt();
break;
bsp/nuvoton/libraries/nu_packages/Demo/SConscript
+1
View File
@@ -5,6 +5,7 @@ group = []
if GetDepend('NU_PKG_USING_DEMO'):
src = Split("""
usbd_hid_dance_mouse.c
slcd_show_tick.c
""")
CPPPATH = [cwd]
group = DefineGroup('nu_pkgs_demo', src, depend = [''], CPPPATH = CPPPATH)
bsp/nuvoton/libraries/nu_packages/Demo/usbd_hid_dance_mouse.c
+13 -14
View File
@@ -23,13 +23,12 @@
static struct rt_thread usb_thread;
ALIGN(RT_ALIGN_SIZE)
static char usb_thread_stack[512];
static char usb_thread_stack[1024];
static struct rt_semaphore tx_sem_complete;
static rt_err_t event_hid_in(rt_device_t dev, void *buffer)
{
rt_sem_release(&tx_sem_complete);
return RT_EOK;
return rt_sem_release(&tx_sem_complete);
}
static void usb_thread_entry(void *parameter)
@@ -38,6 +37,7 @@ static void usb_thread_entry(void *parameter)
uint8_t u8MouseIdx = 0;
uint8_t u8MoveLen=0, u8MouseMode = 1;
uint8_t pu8Buf[4];
rt_err_t result = RT_EOK;
rt_device_t device = (rt_device_t)parameter;
@@ -78,7 +78,8 @@ static void usb_thread_entry(void *parameter)
else
{
/* Wait it done. */
rt_sem_take(&tx_sem_complete, RT_WAITING_FOREVER);
result = rt_sem_take(&tx_sem_complete, RT_WAITING_FOREVER);
RT_ASSERT( result== RT_EOK );
}
} // while(1)
@@ -86,29 +87,27 @@ static void usb_thread_entry(void *parameter)
static int dance_mouse_init(void)
{
int err = 0;
rt_err_t ret = RT_EOK;
rt_device_t device = rt_device_find("hidd");
RT_ASSERT(device != RT_NULL);
err = rt_device_open(device, RT_DEVICE_FLAG_WRONLY);
ret = rt_device_open(device, RT_DEVICE_FLAG_WRONLY);
RT_ASSERT(ret == RT_EOK);
if (err != RT_EOK)
{
LOG_E("open dev failed!\n");
return -1;
}
rt_thread_init(&usb_thread,
ret = rt_thread_init(&usb_thread,
"hidd",
usb_thread_entry, device,
usb_thread_stack, sizeof(usb_thread_stack),
10, 20);
RT_ASSERT(ret == RT_EOK);
rt_thread_startup(&usb_thread);
ret = rt_thread_startup(&usb_thread);
RT_ASSERT(ret == RT_EOK);
return 0;
}
INIT_APP_EXPORT(dance_mouse_init);
#endif /* #if defined(RT_USB_DEVICE_HID) && (defined(BSP_USING_USBD) || defined(BSP_USING_HSUSBD)) */
bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_ebi.c
+9
View File
@@ -42,6 +42,15 @@ void ili9341_send_pixel_data(rt_uint16_t color)
ili9341_write_data(color);
}
void ili9341_send_pixels(rt_uint16_t *pixels, int len)
{
int i = 0;
int size = len / sizeof(rt_uint16_t);
while (i < size)
ili9341_write_data(pixels[i]);
}
void ili9341_set_column(uint16_t StartCol, uint16_t EndCol)
{
ili9341_send_cmd(0x2A);
bsp/nuvoton/libraries/nu_packages/ILI9341/ili9341_spi.c
+8 -2
View File
@@ -54,9 +54,15 @@ static void ili9341_write_data_16bit(uint16_t data)
rt_spi_transfer(&ili9341_spi_device, (const void *)&data, NULL, 2);
}
void ili9341_send_pixel_data(rt_uint16_t color)
void ili9341_send_pixel_data(rt_uint16_t pixel)
{
ili9341_write_data_16bit(color);
ili9341_write_data_16bit(pixel);
}
void ili9341_send_pixels(rt_uint16_t *pixels, int len)
{
ili9341_change_datawidth(16);
rt_spi_transfer(&ili9341_spi_device, (const void *)pixels, NULL, len);
}
static rt_err_t ili9341_spi_send_then_recv(struct rt_spi_device *device,
bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c
+52 -10
View File
@@ -17,6 +17,15 @@
#include <rtdevice.h>
#include <lcd_ili9341.h>
static struct rt_device_graphic_info g_Ili9341Info =
{
.bits_per_pixel = 16,
.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565,
.framebuffer = RT_NULL,
.width = XSIZE_PHYS,
.height = YSIZE_PHYS
};
static void ili9341_delay_ms(rt_uint32_t nms)
{
rt_thread_mdelay(nms);
@@ -92,7 +101,11 @@ static rt_err_t ili9341_lcd_init(rt_device_t dev)
ili9341_send_cmd_parameter(0x86);
ili9341_send_cmd(0x36);
ili9341_send_cmd_parameter(0x48); // for 240x320
if (g_Ili9341Info.width == 240)
ili9341_send_cmd_parameter(0x48); // for 240x320
else
ili9341_send_cmd_parameter(0xE8); // for 320x240
ili9341_send_cmd(0x3A);
ili9341_send_cmd_parameter(0x55);
@@ -157,14 +170,37 @@ static rt_err_t ili9341_lcd_init(rt_device_t dev)
return RT_EOK;
}
static void ili9341_fillscreen(uint16_t color)
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
static void ili9341_fillrect(uint16_t *pixels, struct rt_device_rect_info *pRectInfo)
{
ili9341_set_column(pRectInfo->x, pRectInfo->x + pRectInfo->width);
ili9341_set_page(pRectInfo->y, pRectInfo->y + pRectInfo->height);
ili9341_send_cmd(0x2c);
ili9341_send_pixels(pixels, pRectInfo->height * pRectInfo->width * 2);
}
#endif
static void ili9341_fillscreen(rt_uint16_t color)
{
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
struct rt_device_rect_info rectinfo = { 0, 0, XSIZE_PHYS, YSIZE_PHYS };
int pixel_count = XSIZE_PHYS * YSIZE_PHYS;
rt_uint16_t *pu16ShadowBuf = (rt_uint16_t *)g_Ili9341Info.framebuffer;
while (pixel_count--)
{
*pu16ShadowBuf++ = color;
}
ili9341_fillrect((uint16_t *)g_Ili9341Info.framebuffer, &rectinfo);
#else
ili9341_set_column(0, (XSIZE_PHYS - 1));
ili9341_set_page(0, (YSIZE_PHYS - 1));
ili9341_send_cmd(0x2c);
for (int i = 0; i < (XSIZE_PHYS * YSIZE_PHYS); i++)
ili9341_send_pixel_data(color);
#endif
}
static void ili9341_lcd_set_pixel(const char *color, int x, int y)
@@ -227,19 +263,20 @@ static rt_err_t ili9341_lcd_control(rt_device_t dev, int cmd, void *args)
info = (struct rt_device_graphic_info *) args;
RT_ASSERT(info != RT_NULL);
info->bits_per_pixel = 16;
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
info->framebuffer = RT_NULL;
info->width = XSIZE_PHYS;
info->height = YSIZE_PHYS;
rt_memcpy(args, (void *)&g_Ili9341Info, sizeof(struct rt_device_graphic_info));
}
break;
case RTGRAPHIC_CTRL_RECT_UPDATE:
{
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
RT_ASSERT(args != RT_NULL);
ili9341_fillrect((uint16_t *)g_Ili9341Info.framebuffer, (struct rt_device_rect_info *) args);
#else
/* nothong to be done */
break;
#endif
}
break;
default:
break;
}
@@ -272,6 +309,11 @@ int rt_hw_lcd_ili9341_init(void)
lcd_device.user_data = &ili9341_ops;
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
g_Ili9341Info.framebuffer = rt_malloc_align(g_Ili9341Info.bits_per_pixel / 2 * g_Ili9341Info.height * g_Ili9341Info.width, 32);
RT_ASSERT(g_Ili9341Info.framebuffer != RT_NULL);
#endif
/* register graphic device driver */
rt_device_register(&lcd_device, "lcd", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.h
+8 -2
View File
@@ -28,8 +28,13 @@
//
// Physical display size
//
#define XSIZE_PHYS 240
#define YSIZE_PHYS 320
#if defined(NU_PKG_ILI9341_HORIZONTAL)
#define XSIZE_PHYS 320
#define YSIZE_PHYS 240
#else
#define XSIZE_PHYS 240
#define YSIZE_PHYS 320
#endif
int rt_hw_lcd_ili9341_init(void);
void ili9341_send_cmd(rt_uint8_t cmd);
@@ -38,6 +43,7 @@ void ili9341_set_column(rt_uint16_t StartCol, rt_uint16_t EndCol);
void ili9341_set_page(rt_uint16_t StartPage, rt_uint16_t EndPage);
void ili9341_send_pixel_data(rt_uint16_t color);
void ili9341_lcd_get_pixel(char *color, int x, int y);
void ili9341_send_pixels(rt_uint16_t *pixels, int len);
#if defined(NU_PKG_USING_ILI9341_SPI)
rt_err_t rt_hw_lcd_ili9341_spi_init(const char *spibusname);
bsp/nuvoton/libraries/nu_packages/Kconfig
+8
View File
@@ -47,6 +47,14 @@ menu "Nuvoton Packages Config"
Choose this option if you the ili9341 device is with EBI interface.
endchoice
config NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER
bool "Create an offscreen framebuffer."
default n
config NU_PKG_ILI9341_HORIZONTAL
bool "Set horizontal view. (320x240)"
default n
endif
endmenu
bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h
+4 -2
View File
@@ -43,7 +43,7 @@ extern "C" {
*/
__STATIC_INLINE int nu_clz(uint32_t x)
{
return __CLZ(x);
return x ? __CLZ(x):32;
}
/* Count Leading Ones in word - Find Highest Zero
@@ -65,7 +65,9 @@ __STATIC_INLINE int nu_clo(uint32_t x)
*/
__STATIC_INLINE int nu_ctz(uint32_t x)
{
int c = __CLZ(x & -x);
int c = 32;
if (x)
c = __CLZ(x & -x);
return x ? 31 - c : c;
}
bsp/nuvoton/libraries/nuc980/Driver/Include/NuMicro.h
+47
View File
@@ -0,0 +1,47 @@
/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "nuc980.h"
#include "nu_adc.h"
#include "nu_uart.h"
#include "nu_spi.h"
#include "nu_qspi.h"
#include "nu_i2c.h"
#include "nu_pdma.h"
#include "nu_etimer.h"
#include "nu_emac.h"
#include "nu_sdh.h"
#include "nu_gpio.h"
#include "nu_rtc.h"
#include "nu_wdt.h"
#include "nu_ebi.h"
#include "nu_scuart.h"
#include "nu_pwm.h"
#include "nu_crypto.h"
#include "nu_can.h"
#include "nu_sys.h"
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __CLZ
#if defined(__CC_ARM)
#define __CLZ __clz
#else
#define __CLZ __builtin_clz
#endif
#endif
#endif /* __NUMICRO_H__ */
bsp/nuvoton/libraries/nuc980/Driver/Include/emac_reg.h
+2063
View File
File diff suppressed because it is too large Load Diff
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_adc.h
+110
View File
@@ -0,0 +1,110 @@
/**************************************************************************//**
* @file adc.h
* @version V1.00
* $Revision: 6 $
* $Date: 15/10/05 7:00p $
* @brief NUC980 ADC driver header file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_ADC_H__
#define __NU_ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ADC_Driver ADC Driver
@{
*/
/** @addtogroup ADC_EXPORTED_CONSTANTS ADC Exported Constants
@{
*/
#define ADC_ERR_ARGS 1 /*!< The arguments is wrong */
#define ADC_ERR_CMD 2 /*!< The command is wrong */
/// @cond HIDDEN_SYMBOLS
typedef INT32(*ADC_CALLBACK)(UINT32 status, UINT32 userData);
/// @endcond HIDDEN_SYMBOLS
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_CTL_ADEN 0x00000001 /*!< ADC Power Control */
#define ADC_CTL_VBGEN 0x00000002 /*!< ADC Internal Bandgap Power Control */
#define ADC_CTL_MST 0x00000100 /*!< Menu Start Conversion */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_CONF constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_CONF_NACEN 0x00000004 /*!< Normal AD Conversion Enable */
#define ADC_CONF_SELFTEN 0x00000400 /*!< Selft Test Enable */
#define ADC_CONF_HSPEED (1<<22) /*!< High Speed Enable */
#define ADC_CONF_CHSEL_Pos 12 /*!< Channel Selection Position */
#define ADC_CONF_CHSEL_Msk (0xF<<ADC_CONF_CHSEL_Pos) /*!< Channel Selection Mask */
#define ADC_CONF_REFSEL_Pos 6 /*!< Reference Selection Position */
#define ADC_CONF_REFSEL_Msk (3<<6) /*!< Reference Selection Mask */
#define ADC_CONF_REFSEL_VREF (0<<6) /*!< ADC reference select VREF input */
#define ADC_CONF_REFSEL_AVDD33 (3<<6) /*!< ADC reference select AGND33 vs AVDD33 */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_IER constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_IER_MIEN 0x00000001 /*!< Menu Interrupt Enable */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_ISR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_ISR_MF 0x00000001 /*!< Menu Complete Flag */
#define ADC_ISR_NACF 0x00000400 /*!< Normal AD Conversion Finish */
/** \brief Structure type of ADC_CMD
*/
typedef enum
{
START_MST, /*!<Menu Start Conversion */
VBPOWER_ON, /*!<Enable ADC Internal Bandgap Power */
VBPOWER_OFF, /*!<Disable ADC Internal Bandgap Power */
NAC_ON, /*!<Enable Normal AD Conversion */
NAC_OFF, /*!<Disable Normal AD Conversion */
SWITCH_CH, /*!<Switch Channel */
} ADC_CMD;
/*@}*/ /* end of group ADC_EXPORTED_CONSTANTS */
/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
int adcOpen(void);
int adcOpen2(uint32_t freq);
int adcClose(void);
int adcReadXY(short *bufX, short *bufY, int dataCnt);
int adcReadZ(short *bufZ1, short *bufZ2, int dataCnt);
int adcIoctl(ADC_CMD cmd, int arg1, int arg2);
int adcChangeChannel(int channel);
/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ADC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_ADC_H__
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_can.h
+461
View File
@@ -0,0 +1,461 @@
/**************************************************************************//**
* @file can.h
* @version V2.00
* @brief NUC980 Series CAN Driver Header File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CAN_H__
#define __NU_CAN_H__
#include "nuc980.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CAN_Driver CAN Driver
@{
*/
/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CAN Test Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_NORMAL_MODE 0ul /*!< CAN select normal mode \hideinitializer */
#define CAN_BASIC_MODE 1ul /*!< CAN select basic mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Message ID Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_STD_ID 0ul /*!< CAN select standard ID \hideinitializer */
#define CAN_EXT_ID 1ul /*!< CAN select extended ID \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Message Frame Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_REMOTE_FRAME 0ul /*!< CAN frame select remote frame \hideinitializer */
#define CAN_DATA_FRAME 1ul /*!< CAN frame select data frame \hideinitializer */
/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
typedef struct
{
uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */
uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */
uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */
uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */
uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */
uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */
uint32_t MCON; /*!< [0x0038] IFn Message Control Register */
uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */
uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */
uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */
uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */
uint32_t RESERVE0[13];
} CAN_IF_T;
typedef struct
{
uint32_t CON; /*!< [0x0000] Control Register */
uint32_t STATUS; /*!< [0x0004] Status Register */
uint32_t ERR; /*!< [0x0008] Error Counter Register */
uint32_t BTIME; /*!< [0x000c] Bit Timing Register */
uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */
uint32_t TEST; /*!< [0x0014] Test Register */
uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */
uint32_t RESERVE0[1];
CAN_IF_T IF[2];
uint32_t RESERVE2[8];
uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */
uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */
uint32_t RESERVE3[6];
uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */
uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */
uint32_t RESERVE4[6];
uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */
uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */
uint32_t RESERVE5[6];
uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */
uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */
uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */
uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */
} CAN_T;
#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */
#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */
#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */
#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */
#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */
#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */
#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */
#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */
#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */
#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */
#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */
#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */
#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */
#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */
#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */
#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */
#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */
#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */
#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */
#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */
#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */
#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */
#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */
#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */
#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */
#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */
#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */
#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */
#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */
#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */
#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */
#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */
#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */
#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */
#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */
#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */
#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */
#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */
#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/
#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */
#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */
#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */
#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */
#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */
#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */
#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */
#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */
#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */
#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */
#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */
#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */
#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */
#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */
#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */
#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */
#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */
#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */
#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */
#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */
#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */
#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */
#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */
#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */
#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */
#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */
#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */
#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */
#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */
#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */
#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */
#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */
#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */
#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */
#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */
#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */
#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */
#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */
#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */
#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */
#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */
#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */
#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */
#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */
#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */
#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */
#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */
#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */
#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */
#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */
#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */
#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */
#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */
#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */
#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */
#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */
#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */
#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */
#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */
#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */
#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */
#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */
#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */
#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */
#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */
#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */
#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */
#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */
#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */
#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */
#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */
#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */
#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */
#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */
#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */
#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */
#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */
#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */
#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */
#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */
#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */
#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */
#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */
#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */
#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */
#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */
#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
#define CAN0 ((CAN_T *) CAN0_BA)
#define CAN1 ((CAN_T *) CAN1_BA)
#define CAN2 ((CAN_T *) CAN2_BA)
#define CAN3 ((CAN_T *) CAN3_BA)
/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
@{
*/
/**
* @details CAN message structure
*/
typedef struct
{
uint32_t IdType; /*!< ID type */
uint32_t FrameType; /*!< Frame type */
uint32_t Id; /*!< Message ID */
uint8_t DLC; /*!< Data length */
uint8_t Data[8]; /*!< Data */
} STR_CANMSG_T;
/**
* @details CAN mask message structure
*/
typedef struct
{
uint8_t u8Xtd; /*!< Extended ID */
uint8_t u8Dir; /*!< Direction */
uint32_t u32Id; /*!< Message ID */
uint8_t u8IdType; /*!< ID type*/
} STR_CANMASK_T;
/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */
/** @cond HIDDEN_SYMBOLS */
#define MSG(id) (id)
/** @endcond HIDDEN_SYMBOLS */
/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
@{
*/
/**
* @brief Get interrupt status.
*
* @param[in] can The base address of can module.
*
* @return CAN module status register value.
*
* @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
* EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
* \hideinitializer
*/
#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
/**
* @brief Get specified interrupt pending status.
*
* @param[in] can The base address of can module.
*
* @return The source of the interrupt.
*
* @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
* with the highest priority, disregarding their chronological order.
* \hideinitializer
*/
#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
/**
* @brief Disable wake-up function.
*
* @param[in] can The base address of can module.
*
* @return None
*
* @details The macro is used to disable wake-up function.
* \hideinitializer
*/
#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul)
/**
* @brief Enable wake-up function.
*
* @param[in] can The base address of can module.
*
* @return None
*
* @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
* \hideinitializer
*/
#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
/**
* @brief Get specified Message Object new data into bit value.
*
* @param[in] can The base address of can module.
* @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
*
* @return Specified Message Object new data into bit value.
*
* @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
* or by the Message Handler after reception of a Data Frame or after a successful transmission.
* \hideinitializer
*/
#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
/*---------------------------------------------------------------------------------------------------------*/
/* Define CAN functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
void CAN_Close(CAN_T *tCAN);
void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);
int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T *pCanMsg);
int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg);
int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T *pCanMsg);
void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
void CAN_LeaveTestMode(CAN_T *tCAN);
uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
void CAN_LeaveInitMode(CAN_T *tCAN);
int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
void CAN_WaitMsg(CAN_T *tCAN);
int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T *pCanMsg);
/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CAN_Driver */
/*@}*/ /* end of group Standard_Driver */
#endif /*__NU_CAN_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_cap.h
+471
View File
@@ -0,0 +1,471 @@
/**************************************************************************//**
* @file cap.h
* @brief Image Capture Driver Header File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CAP_H__
#define __NU_CAP_H__
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#ifdef __cplusplus
extern "C"
{
#endif
/*---------------------- Capture Engine -------------------------*/
/**
@addtogroup CAP Capture Engine(CAP)
Memory Mapped Structure for CAP Controller
@{ */
typedef struct
{
__IO uint32_t CTL;
__IO uint32_t PAR;
__IO uint32_t INT;
__IO uint32_t POSTERIZE;
__IO uint32_t MD;
__IO uint32_t MDADDR;
__IO uint32_t MDYADDR;
__IO uint32_t SEPIA;
__IO uint32_t CWSP;
__IO uint32_t CWS;
__IO uint32_t PKTSL;
__IO uint32_t PLNSL;
__IO uint32_t FRCTL;
__IO uint32_t STRIDE;
/// @cond HIDDEN_SYMBOLS
uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t FIFOTH;
__IO uint32_t CMPADDR;
/// @cond HIDDEN_SYMBOLS
uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PKTSM;
__IO uint32_t PLNSM;
__I uint32_t CURADDRP;
__I uint32_t CURADDRY;
__I uint32_t CURADDRU;
__I uint32_t CURVADDR;
__IO uint32_t PKTBA0;
__IO uint32_t PKTBA1;
/// @cond HIDDEN_SYMBOLS
uint32_t RESERVE2[6];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t YBA;
__IO uint32_t UBA;
__IO uint32_t VBA;
} CAP_T;
/**
@addtogroup CAP_CONST CAP Bit Field Definition
Constant Definitions for CAP Controller
@{ */
#define CAP_CTL_CAPEN_Pos (0) /*!< CAP_T::CTL: CAPEN Position */
#define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) /*!< CAP_T::CTL: CAPEN Mask */
#define CAP_CTL_ADDRSW_Pos (3) /*!< CAP_T::CTL: ADDRSW Position */
#define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) /*!< CAP_T::CTL: ADDRSW Mask */
#define CAP_CTL_PLNEN_Pos (5) /*!< CAP_T::CTL: PLNEN Position */
#define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) /*!< CAP_T::CTL: PLNEN Mask */
#define CAP_CTL_PKTEN_Pos (6) /*!< CAP_T::CTL: PKTEN Position */
#define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) /*!< CAP_T::CTL: PKTEN Mask */
#define CAP_CTL_SHUTTER_Pos (16) /*!< CAP_T::CTL: SHUTTER Position */
#define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) /*!< CAP_T::CTL: SHUTTER Mask */
#define CAP_CTL_UPDATE_Pos (20) /*!< CAP_T::CTL: UPDATE Position */
#define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) /*!< CAP_T::CTL: UPDATE Mask */
#define CAP_CTL_VPRST_Pos (24) /*!< CAP_T::CTL: VPRST Position */
#define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) /*!< CAP_T::CTL: VPRST Mask */
#define CAP_PAR_INFMT_Pos (0) /*!< CAP_T::PAR: INFMT Position */
#define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) /*!< CAP_T::PAR: INFMT Mask */
#define CAP_PAR_SENTYPE_Pos (1) /*!< CAP_T::PAR: SENTYPE Position */
#define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) /*!< CAP_T::PAR: SENTYPE Mask */
#define CAP_PAR_INDATORD_Pos (2) /*!< CAP_T::PAR: INDATORD Position */
#define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) /*!< CAP_T::PAR: INDATORD Mask */
#define CAP_PAR_OUTFMT_Pos (4) /*!< CAP_T::PAR: OUTFMT Position */
#define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) /*!< CAP_T::PAR: OUTFMT Mask */
#define CAP_PAR_RANGE_Pos (6) /*!< CAP_T::PAR: RANGE Position */
#define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) /*!< CAP_T::PAR: RANGE Mask */
#define CAP_PAR_PLNFMT_Pos (7) /*!< CAP_T::PAR: PLNFMT Position */
#define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) /*!< CAP_T::PAR: PLNFMT Mask */
#define CAP_PAR_PCLKP_Pos (8) /*!< CAP_T::PAR: PCLKP Position */
#define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) /*!< CAP_T::PAR: PCLKP Mask */
#define CAP_PAR_HSP_Pos (9) /*!< CAP_T::PAR: HSP Position */
#define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) /*!< CAP_T::PAR: HSP Mask */
#define CAP_PAR_VSP_Pos (10) /*!< CAP_T::PAR: VSP Position */
#define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) /*!< CAP_T::PAR: VSP Mask */
#define CAP_PAR_COLORCTL_Pos (11) /*!< CAP_T::PAR: COLORCTL Position */
#define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) /*!< CAP_T::PAR: COLORCTL Mask */
#define CAP_PAR_FBB_Pos (18) /*!< CAP_T::PAR: FBB Position */
#define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) /*!< CAP_T::PAR: FBB Mask */
#define CAP_INT_VINTF_Pos (0) /*!< CAP_T::INT: VINTF Position */
#define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) /*!< CAP_T::INT: VINTF Mask */
#define CAP_INT_MEINTF_Pos (1) /*!< CAP_T::INT: MEINTF Position */
#define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) /*!< CAP_T::INT: MEINTF Mask */
#define CAP_INT_ADDRMINTF_Pos (3) /*!< CAP_T::INT: ADDRMINTF Position */
#define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) /*!< CAP_T::INT: ADDRMINTF Mask */
#define CAP_INT_MDINTF_Pos (4) /*!< CAP_T::INT: MDINTF Position */
#define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) /*!< CAP_T::INT: MDINTF Mask */
#define CAP_INT_VIEN_Pos (16) /*!< CAP_T::INT: VIEN Position */
#define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) /*!< CAP_T::INT: VIEN Mask */
#define CAP_INT_MEIEN_Pos (17) /*!< CAP_T::INT: MEIEN Position */
#define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) /*!< CAP_T::INT: MEIEN Mask */
#define CAP_INT_ADDRMIEN_Pos (19) /*!< CAP_T::INT: ADDRMIEN Position */
#define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) /*!< CAP_T::INT: ADDRMIEN Mask */
#define CAP_INT_MDIEN_Pos (20) /*!< CAP_T::INT: MDIEN Position */
#define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) /*!< CAP_T::INT: MDIEN Mask */
#define CAP_POSTERIZE_VCOMP_Pos (0) /*!< CAP_T::POSTERIZE: VCOMP Position */
#define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) /*!< CAP_T::POSTERIZE: VCOMP Mask */
#define CAP_POSTERIZE_UCOMP_Pos (8) /*!< CAP_T::POSTERIZE: UCOMP Position */
#define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) /*!< CAP_T::POSTERIZE: UCOMP Mask */
#define CAP_POSTERIZE_YCOMP_Pos (16) /*!< CAP_T::POSTERIZE: YCOMP Position */
#define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) /*!< CAP_T::POSTERIZE: YCOMP Mask */
#define CAP_MD_MDEN_Pos (0) /*!< CAP_T::MD: MDEN Position */
#define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) /*!< CAP_T::MD: MDEN Mask */
#define CAP_MD_MDBS_Pos (8) /*!< CAP_T::MD: MDBS Position */
#define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) /*!< CAP_T::MD: MDBS Mask */
#define CAP_MD_MDSM_Pos (9) /*!< CAP_T::MD: MDSM Position */
#define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) /*!< CAP_T::MD: MDSM Mask */
#define CAP_MD_MDDF_Pos (10) /*!< CAP_T::MD: MDDF Position */
#define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) /*!< CAP_T::MD: MDDF Mask */
#define CAP_MD_MDTHR_Pos (16) /*!< CAP_T::MD: MDTHR Position */
#define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) /*!< CAP_T::MD: MDTHR Mask */
#define CAP_MDADDR_MDADDR_Pos (0) /*!< CAP_T::MDADDR: MDADDR Position */
#define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) /*!< CAP_T::MDADDR: MDADDR Mask */
#define CAP_MDYADDR_MDYADDR_Pos (0) /*!< CAP_T::MDYADDR: MDYADDR Position */
#define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) /*!< CAP_T::MDYADDR: MDYADDR Mask */
#define CAP_SEPIA_VCOMP_Pos (0) /*!< CAP_T::SEPIA: VCOMP Position */
#define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) /*!< CAP_T::SEPIA: VCOMP Mask */
#define CAP_SEPIA_UCOMP_Pos (8) /*!< CAP_T::SEPIA: UCOMP Position */
#define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) /*!< CAP_T::SEPIA: UCOMP Mask */
#define CAP_CWSP_CWSADDRH_Pos (0) /*!< CAP_T::CWSP: CWSADDRH Position */
#define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) /*!< CAP_T::CWSP: CWSADDRH Mask */
#define CAP_CWSP_CWSADDRV_Pos (16) /*!< CAP_T::CWSP: CWSADDRV Position */
#define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) /*!< CAP_T::CWSP: CWSADDRV Mask */
#define CAP_CWS_CWW_Pos (0) /*!< CAP_T::CWS: CWW Position */
#define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) /*!< CAP_T::CWS: CWW Mask */
#define CAP_CWS_CWH_Pos (16) /*!< CAP_T::CWS: CIWH Position */
#define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) /*!< CAP_T::CWS: CIWH Mask */
#define CAP_PKTSL_PKTSHML_Pos (0) /*!< CAP_T::PKTSL: PKTSHML Position */
#define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) /*!< CAP_T::PKTSL: PKTSHML Mask */
#define CAP_PKTSL_PKTSHNL_Pos (8) /*!< CAP_T::PKTSL: PKTSHNL Position */
#define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) /*!< CAP_T::PKTSL: PKTSHNL Mask */
#define CAP_PKTSL_PKTSVML_Pos (16) /*!< CAP_T::PKTSL: PKTSVML Position */
#define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) /*!< CAP_T::PKTSL: PKTSVML Mask */
#define CAP_PKTSL_PKTSVNL_Pos (24) /*!< CAP_T::PKTSL: PKTSVNL Position */
#define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) /*!< CAP_T::PKTSL: PKTSVNL Mask */
#define CAP_PLNSL_PLNSHML_Pos (0) /*!< CAP_T::PLNSL: PLNSHML Position */
#define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) /*!< CAP_T::PLNSL: PLNSHML Mask */
#define CAP_PLNSL_PLNSHNL_Pos (8) /*!< CAP_T::PLNSL: PLNSHNL Position */
#define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) /*!< CAP_T::PLNSL: PLNSHNL Mask */
#define CAP_PLNSL_PLNSVML_Pos (16) /*!< CAP_T::PLNSL: PLNSVML Position */
#define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) /*!< CAP_T::PLNSL: PLNSVML Mask */
#define CAP_PLNSL_PLNSVNL_Pos (24) /*!< CAP_T::PLNSL: PLNSVNL Position */
#define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) /*!< CAP_T::PLNSL: PLNSVNL Mask */
#define CAP_FRCTL_FRM_Pos (0) /*!< CAP_T::FRCTL: FRM Position */
#define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) /*!< CAP_T::FRCTL: FRM Mask */
#define CAP_FRCTL_FRN_Pos (8) /*!< CAP_T::FRCTL: FRN Position */
#define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) /*!< CAP_T::FRCTL: FRN Mask */
#define CAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CAP_T::STRIDE: PKTSTRIDE Position */
#define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) /*!< CAP_T::STRIDE: PKTSTRIDE Mask */
#define CAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CAP_T::STRIDE: PLNSTRIDE Position */
#define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) /*!< CAP_T::STRIDE: PLNSTRIDE Mask */
#define CAP_FIFOTH_PLNVFTH_Pos (0) /*!< CAP_T::FIFOTH: PLNVFTH Position */
#define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) /*!< CAP_T::FIFOTH: PLNVFTH Mask */
#define CAP_FIFOTH_PLNUFTH_Pos (8) /*!< CAP_T::FIFOTH: PLNUFTH Position */
#define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) /*!< CAP_T::FIFOTH: PLNUFTH Mask */
#define CAP_FIFOTH_PLNYFTH_Pos (16) /*!< CAP_T::FIFOTH: PLNYFTH Position */
#define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) /*!< CAP_T::FIFOTH: PLNYFTH Mask */
#define CAP_FIFOTH_PKTFTH_Pos (24) /*!< CAP_T::FIFOTH: PKTFTH Position */
#define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) /*!< CAP_T::FIFOTH: PKTFTH Mask */
#define CAP_FIFOTH_OVF_Pos (31) /*!< CAP_T::FIFOTH: OVF Position */
#define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) /*!< CAP_T::FIFOTH: OVF Mask */
#define CAP_CMPADDR_CMPADDR_Pos (0) /*!< CAP_T::CMPADDR: CMPADDR Position */
#define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) /*!< CAP_T::CMPADDR: CMPADDR Mask */
#define CAP_PKTSM_PKTSHMH_Pos (0) /*!< CAP_T::PKTSM: PKTSHMH Position */
#define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) /*!< CAP_T::PKTSM: PKTSHMH Mask */
#define CAP_PKTSM_PKTSHNH_Pos (8) /*!< CAP_T::PKTSM: PKTSHNH Position */
#define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) /*!< CAP_T::PKTSM: PKTSHNH Mask */
#define CAP_PKTSM_PKTSVMH_Pos (16) /*!< CAP_T::PKTSM: PKTSVMH Position */
#define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) /*!< CAP_T::PKTSM: PKTSVMH Mask */
#define CAP_PKTSM_PKTSVNH_Pos (24) /*!< CAP_T::PKTSM: PKTSVNH Position */
#define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) /*!< CAP_T::PKTSM: PKTSVNH Mask */
#define CAP_PLNSM_PLNSHMH_Pos (0) /*!< CAP_T::PLNSM: PLNSHMH Position */
#define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) /*!< CAP_T::PLNSM: PLNSHMH Mask */
#define CAP_PLNSM_PLNSHNH_Pos (8) /*!< CAP_T::PLNSM: PLNSHNH Position */
#define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) /*!< CAP_T::PLNSM: PLNSHNH Mask */
#define CAP_PLNSM_PLNSVMH_Pos (16) /*!< CAP_T::PLNSM: PLNSVMH Position */
#define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) /*!< CAP_T::PLNSM: PLNSVMH Mask */
#define CAP_PLNSM_PLNSVNH_Pos (24) /*!< CAP_T::PLNSM: PLNSVNH Position */
#define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) /*!< CAP_T::PLNSM: PLNSVNH Mask */
#define CAP_CURADDRP_CURADDR_Pos (0) /*!< CAP_T::CURADDRP: CURADDR Position */
#define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) /*!< CAP_T::CURADDRP: CURADDR Mask */
#define CAP_CURADDRY_CURADDR_Pos (0) /*!< CAP_T::CURADDRY: CURADDR Position */
#define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) /*!< CAP_T::CURADDRY: CURADDR Mask */
#define CAP_CURADDRU_CURADDR_Pos (0) /*!< CAP_T::CURADDRU: CURADDR Position */
#define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) /*!< CAP_T::CURADDRU: CURADDR Mask */
#define CAP_CURVADDR_CURADDR_Pos (0) /*!< CAP_T::CURVADDR: CURADDR Position */
#define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) /*!< CAP_T::CURVADDR: CURADDR Mask */
#define CAP_PKTBA0_BASEADDR_Pos (0) /*!< CAP_T::PKTBA0: BASEADDR Position */
#define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) /*!< CAP_T::PKTBA0: BASEADDR Mask */
#define CAP_PKTBA1_BASEADDR_Pos (0) /*!< CAP_T::PKTBA1: BASEADDR Position */
#define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) /*!< CAP_T::PKTBA1: BASEADDR Mask */
#define CAP_YBA_BASEADDR_Pos (0) /*!< CAP_T::YBA: BASEADDR Position */
#define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) /*!< CAP_T::YBA: BASEADDR Mask */
#define CAP_UBA_BASEADDR_Pos (0) /*!< CAP_T::UBA: BASEADDR Position */
#define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) /*!< CAP_T::UBA: BASEADDR Mask */
#define CAP_VBA_BASEADDR_Pos (0) /*!< CAP_T::VBA: BASEADDR Position */
#define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) /*!< CAP_T::VBA: BASEADDR Mask */
/**@}*/ /* CAP_CONST */
/**@}*/ /* end of CAP register group */
#define CAP0 ((CAP_T *) CAP0_BA)
#define CAP1 ((CAP_T *) CAP1_BA)
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CAP_Driver CAP Driver
@{
*/
/** @addtogroup CAP_EXPORTED_CONSTANTS CAP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* VINCTRL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAP_CTL_CAPEN (1ul<<CAP_CTL_CAPEN_Pos) /*!< CAP CTL setting for enabling capture engine mode \hideinitializer */
#define CAP_CTL_ADDRSW (1ul<<CAP_CTL_ADDRSW_Pos) /*!< CAP CTL setting for packet buffer address switch \hideinitializer */
#define CAP_CTL_PKTEN (1ul<<CAP_CTL_PKTEN_Pos) /*!< CAP CTL setting for enabling packet output mode \hideinitializer */
#define CAP_CTL_PLNEN (1ul<<CAP_CTL_PLNEN_Pos) /*!< CAP CTL setting for enabling planar output mode \hideinitializer */
#define CAP_CTL_SHUTTER (1ul<<CAP_CTL_SHUTTER_Pos) /*!< CAP CTL setting for enabling shutter mode \hideinitializer */
#define CAP_CTL_UPDATE (1ul<<CAP_CTL_UPDATE_Pos) /*!< CAP CTL setting for enabling update register at new frame \hideinitializer */
#define CAP_CTL_RESET (1ul<<CAP_CTL_VPRST_Pos) /*!< CAP CTL setting for capture reset \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CAPPAR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAP_PAR_INFMT_YUV422 (0ul<<CAP_PAR_INFMT_Pos) /*!< CAP PAR setting for Sensor Input Data YUV422 Format \hideinitializer */
#define CAP_PAR_INFMT_RGB565 (1ul<<CAP_PAR_INFMT_Pos) /*!< CAP PAR setting for Sensor Input Data RGB565 Format \hideinitializer */
#define CAP_PAR_SENTYPE_CCIR601 (0ul<<CAP_PAR_SENTYPE_Pos) /*!< CAP PAR setting for Sensor Input CCIR601 Type \hideinitializer */
#define CAP_PAR_SENTYPE_CCIR656 (1ul<<CAP_PAR_SENTYPE_Pos) /*!< CAP PAR setting for Sensor Input CCIR656 Type \hideinitializer */
#define CAP_PAR_INDATORD_YUYV (0x0ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, YUYV \hideinitializer */
#define CAP_PAR_INDATORD_YVYU (0x1ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, YVYU \hideinitializer */
#define CAP_PAR_INDATORD_UYVY (0x2ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, UYVY \hideinitializer */
#define CAP_PAR_INDATORD_VYUY (0x3ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, VYUY \hideinitializer */
#define CAP_PAR_INDATORD_RGGB (0x0ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: R[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CAP_PAR_INDATORD_BGGR (0x1ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: b[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CAP_PAR_INDATORD_GBRG (0x2ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CAP_PAR_INDATORD_GRBG (0x3ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CAP_PAR_OUTFMT_YUV422 (0x0ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data YUV422 Format Output to System Memory \hideinitializer */
#define CAP_PAR_OUTFMT_ONLY_Y (0x1ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data ONLY_Y Format Output to System Memory \hideinitializer */
#define CAP_PAR_OUTFMT_RGB555 (0x2ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data RGB555 Format Output to System Memory \hideinitializer */
#define CAP_PAR_OUTFMT_RGB565 (0x3ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data RGB565 Format Output to System Memory \hideinitializer */
#define CAP_PAR_PLNFMT_YUV422 (0x0ul<<CAP_PAR_PLNFMT_Pos) /*!< CAP PAR setting for Planar Output YUV422 Format \hideinitializer */
#define CAP_PAR_PLNFMT_YUV420 (0x1ul<<CAP_PAR_PLNFMT_Pos) /*!< CAP PAR setting for Planar Output YUV420 Format \hideinitializer */
#define CAP_PAR_VSP_LOW (0x0ul<<CAP_PAR_VSP_Pos) /*!< CAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CAP_PAR_VSP_HIGH (0x1ul<<CAP_PAR_VSP_Pos) /*!< CAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CAP_PAR_HSP_LOW (0x0ul<<CAP_PAR_HSP_Pos) /*!< CAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CAP_PAR_HSP_HIGH (0x1ul<<CAP_PAR_HSP_Pos) /*!< CAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CAP_PAR_PCLKP_LOW (0x0ul<<CAP_PAR_PCLKP_Pos) /*!< CAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
#define CAP_PAR_PCLKP_HIGH (0x1ul<<CAP_PAR_PCLKP_Pos) /*!< CAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* VININT constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAP_INT_VIEN_ENABLE (0x1ul<<CAP_INT_VIEN_Pos) /*!< VININT setting for Frame End Interrupt enable \hideinitializer */
#define CAP_INT_MEIEN_ENABLE (0x1ul<<CAP_INT_MEIEN_Pos) /*!< VININT setting for Bus Master Transfer Error Interrupt enable \hideinitializer */
#define CAP_INT_ADDRMIEN_ENABLE (0x1ul<<CAP_INT_ADDRMIEN_Pos) /*!< VININT setting for Memory Address Match Interrupt enable \hideinitializer */
#define CAP_INT_MDIEN_ENABLE (0x1ul<<CAP_INT_MDIEN_Pos) /*!< VININT setting for Motion Detection Output Finish Interrupt Enable enable \hideinitializer */
static uint32_t u32EscapeFrame = 0;
/*---------------------------------------------------------------------------------------------------------*/
/* Define Error Code */
/*---------------------------------------------------------------------------------------------------------*/
#define CAP_INVALID_INT ((int32_t)(0xFFFFFFFF-1))
#define CAP_INVALID_BUF ((int32_t)(0xFFFFFFFF-2))
#define CAP_INVALID_PIPE ((int32_t)(0xFFFFFFFF-3))
/*@}*/ /* end of group CAP_EXPORTED_CONSTANTS */
/** @addtogroup CAP_EXPORTED_FUNCTIONS CAP Exported Functions
@{
*/
/**
* @brief Is CAP module Enable
*
* @param[in] VCAP: The pointer of the specified CAP module
*
* @return FALSE(Enable) or TRUE(Disable)
*
* @details Check Image Capture Interface module Enable or Disable
* \hideinitializer
*/
#define CAP_IS_STOPPED(VCAP) ((VCAP->CTL & CAP_CTL_CAPEN_Msk)?0:1)
/**
* @brief Clear CAP flag
*
* @param[in] VCAP: The pointer of the specified CAP module
*
* @param[in] u32IntMask interrupt flags settings. It could be
* - \ref CAP_INT_VINTF_Msk
* - \ref CAP_INT_MEINTF_Msk
* - \ref CAP_INT_ADDRMINTF_Msk
* - \ref CAP_INT_MDINTF_Msk
*
* @return TRUE(Enable) or FALSE(Disable)
*
* @details Clear Image Capture Interface interrupt flag
* \hideinitializer
*/
#define CAP_CLR_INT_FLAG(VCAP,u32IntMask) (VCAP->INT |=u32IntMask)
/**
* @brief Get CAP Interrupt status
*
* @param[in] VCAP: The pointer of the specified CAP module
*
* @return TRUE(Enable) or FALSE(Disable)
*
* @details Get Image Capture Interface interrupt status.
* \hideinitializer
*/
#define CAP_GET_INT_STS(VCAP) (VCAP->INT)
void CAP_Open(CAP_T *VCAP, uint32_t u32InFormat, uint32_t u32OutFormet);
void CAP_SetCroppingWindow(CAP_T *VCAP, uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width);
void CAP_SetPacketBuf(CAP_T *VCAP, uint32_t u32Address);
void CAP_SetPlanarBuf(CAP_T *VCAP, uint32_t u32YAddr, uint32_t u32UAddr, uint32_t u32VAddr);
void CAP_Close(CAP_T *VCAP);
void CAP_EnableInt(CAP_T *VCAP, uint32_t u32IntMask);
void CAP_DisableInt(CAP_T *VCAP, uint32_t u32IntMask);
void CAP_Start(CAP_T *VCAP);
void CAP_Stop(CAP_T *VCAP, uint32_t u32FrameComplete);
void CAP_SetPacketScaling(CAP_T *VCAP, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CAP_SetPlanarScaling(CAP_T *VCAP, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CAP_SetPacketStride(CAP_T *VCAP, uint32_t u32Stride);
void CAP_SetPlanarStride(CAP_T *VCAP, uint32_t u32Stride);
void CAP_EnableMotionDet(CAP_T *VCAP, uint32_t u32Freq, uint32_t u32BlockSize, uint32_t u32Format, uint32_t u32Threshold, uint32_t u32YDetAddr, uint32_t u32DetAddr);
void CAP_DisableMotionDet(CAP_T *VCAP);
/*@}*/ /* end of group CAP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CAP_Driver */
/*@}*/ /* end of group Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__CAP_H__
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_crypto.h
+1456
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bsp/nuvoton/libraries/nuc980/Driver/Include/nu_ebi.h
+418
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@@ -0,0 +1,418 @@
/**************************************************************************//**
* @file ebi.h
* @brief EBI driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_EBI_H__
#define __NU_EBI_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include "nuc980.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EBI_Driver EBI Driver
@{
*/
/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
@{
*/
#define EBI ((EBI_T *) EBI_BA)
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{ */
typedef struct
{
__IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /* Offset: 0x20 External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL2; /* Offset: 0x24 External Bus Interface Bank1 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position \hideinitializer */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask \hideinitializer */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position \hideinitializer */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask \hideinitializer */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position \hideinitializer */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask \hideinitializer */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI EBICON: CS_PINV Position \hideinitializer */
#define EBI_CTL_CACCESS_Msk (1ul << EBI_CTL_CACCESS_Pos) /*!< EBI EBICON: CS_PINV Mask \hideinitializer */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position \hideinitializer */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask \hideinitializer */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position \hideinitializer */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask \hideinitializer */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position \hideinitializer */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask \hideinitializer */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position \hideinitializer */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask \hideinitializer */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position \hideinitializer */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask \hideinitializer */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position \hideinitializer */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask \hideinitializer */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position \hideinitializer */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask \hideinitializer */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position \hideinitializer */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask \hideinitializer */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/*---------------------------------------------------------------------------------------------------------*/
/* Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */
#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */
#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */
#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI bank number */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */
#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */
#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI data bus width */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */
#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI CS Active Level */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */
#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI MCLK divider and Timing */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */
#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */
#define EBI_OPMODE_CACCESS (0x1UL << 4) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Read 8-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Enable EBI Write Buffer
*
* @return None
*
* @details This macro is used to improve EBI write operation for EBI all banks.
* \hideinitializer
*/
#define EBI_ENABLE_WRITE_BUFFER() outpw(REG_EBI_CTL0, inpw(REG_EBI_CTL0) | (0x1UL << 24))
/**
* @brief Disable EBI Write Buffer
*
* @return None
*
* @details This macro is used to disable EBI write buffer function.
* \hideinitializer
*/
#define EBI_DISABLE_WRITE_BUFFER() outpw(REG_EBI_CTL0, (inpw(REG_EBI_CTL0) & ~(0x1UL << 24)) | (0x1UL << 24))
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
void EBI_Close(uint32_t u32Bank);
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EBI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_EBI_H__
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_emac.h
+396
View File
@@ -0,0 +1,396 @@
/**************************************************************************//**
* @file nu_emac.h
* @version V1.00
* @brief EMAC driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_EMAC_H__
#define __NU_EMAC_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include "emac_reg.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EMAC_Driver EMAC Driver
@{
*/
/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
@{
*/
#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */
#define EMAC_RX_DESC_SIZE 64UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_TX_DESC_SIZE 32UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_CAMENTRY_NB 16UL /*!< Number of CAM \hideinitializer */
#define EMAC_MAX_PKT_SIZE 1536UL /*!< Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */
#define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */
#define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */
#define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */
#define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */
#define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */
/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
/** Tx/Rx buffer descriptor structure */
typedef struct
{
uint32_t u32Status1; /*!< Status word 1 */
uint32_t u32Data; /*!< Pointer to data buffer */
uint32_t u32Status2; /*!< Status word 2 */
uint32_t u32Next; /*!< Pointer to next descriptor */
uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */
uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */
} EMAC_DESCRIPTOR_T;
/** Tx/Rx buffer structure */
typedef struct
{
uint8_t au8Buf[EMAC_MAX_PKT_SIZE];
} EMAC_FRAME_T;
typedef struct
{
EMAC_T *psEmac;
uint32_t u32TxDescSize;
uint32_t u32RxDescSize;
EMAC_DESCRIPTOR_T *psRXDescs;
EMAC_FRAME_T *psRXFrames;
EMAC_DESCRIPTOR_T *psTXDescs;
EMAC_FRAME_T *psTXFrames;
EMAC_DESCRIPTOR_T *psCurrentTxDesc;
EMAC_DESCRIPTOR_T *psNextTxDesc;
EMAC_DESCRIPTOR_T *psCurrentRxDesc;
} EMAC_MEMMGR_T;
/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
@{
*/
/**
* @brief Enable EMAC Tx function
* @param None
* @return None
* \hideinitializer
*/
#define EMAC_ENABLE_TX(EMAC) (EMAC->CTL |= EMAC_CTL_TXON_Msk)
/**
* @brief Enable EMAC Rx function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_ENABLE_RX(EMAC) do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
/**
* @brief Disable EMAC Tx function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_DISABLE_TX(EMAC) (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
/**
* @brief Disable EMAC Rx function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_DISABLE_RX(EMAC) (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
/**
* @brief Enable EMAC Magic Packet Wakeup function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_ENABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
/**
* @brief Disable EMAC Magic Packet Wakeup function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_DISABLE_MAGIC_PKT_WAKEUP(EMAC) (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
/**
* @brief Enable EMAC to receive broadcast packets
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_ENABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
/**
* @brief Disable EMAC to receive broadcast packets
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_DISABLE_RECV_BCASTPKT(EMAC) (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
/**
* @brief Enable EMAC to receive multicast packets
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_ENABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
/**
* @brief Disable EMAC Magic Packet Wakeup function
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_DISABLE_RECV_MCASTPKT(EMAC) (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
/**
* @brief Check if EMAC time stamp alarm interrupt occurred or not
* @param The pointer of the specified EMAC module
* @return If time stamp alarm interrupt occurred or not
* @retval 0 Alarm interrupt does not occur
* @retval 1 Alarm interrupt occurred
* \hideinitializer
*/
#define EMAC_GET_ALARM_FLAG(EMAC) (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
/**
* @brief Clear EMAC time stamp alarm interrupt flag
* @param The pointer of the specified EMAC module
* @return None
* \hideinitializer
*/
#define EMAC_CLR_ALARM_FLAG(EMAC) (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
/**
* @brief Trigger EMAC Rx function
* @param The pointer of the specified EMAC module
* @return None
*/
#define EMAC_TRIGGER_RX(EMAC) do{EMAC->RXST = 0UL;}while(0)
/**
* @brief Trigger EMAC Tx function
* @param The pointer of the specified EMAC module
* @return None
*/
#define EMAC_TRIGGER_TX(EMAC) do{EMAC->TXST = 0UL;}while(0)
/**
* @brief Enable specified EMAC interrupt
*
* @param[in] EMAC The pointer of the specified EMAC module
* @param[in] u32eIntSel Interrupt type select
* - \ref EMAC_INTEN_RXIEN_Msk : Receive
* - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error
* - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow
* - \ref EMAC_INTEN_LPIEN_Msk : Long Packet
* - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good
* - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error
* - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet
* - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
* - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed
* - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification
* - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable
* - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error
* - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive
* - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt
* - \ref EMAC_INTEN_TXIEN_Msk : Transmit
* - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow
* - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion
* - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
* - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense
* - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
* - \ref EMAC_INTEN_LCIEN_Msk : Late Collision
* - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable
* - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error
* - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
*
* @return None
*
* @details This macro enable specified EMAC interrupt.
* \hideinitializer
*/
#define EMAC_ENABLE_INT(EMAC, u32eIntSel) ((EMAC)->INTEN |= (u32eIntSel))
/**
* @brief Disable specified EMAC interrupt
*
* @param[in] emac The pointer of the specified EMAC module
* @param[in] u32eIntSel Interrupt type select
* - \ref EMAC_INTEN_RXIEN_Msk : Receive
* - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error
* - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow
* - \ref EMAC_INTEN_LPIEN_Msk : Long Packet
* - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good
* - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error
* - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet
* - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun
* - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed
* - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification
* - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable
* - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error
* - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive
* - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt
* - \ref EMAC_INTEN_TXIEN_Msk : Transmit
* - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow
* - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion
* - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed
* - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense
* - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort
* - \ref EMAC_INTEN_LCIEN_Msk : Late Collision
* - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable
* - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error
* - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm
*
* @return None
*
* @details This macro disable specified EMAC interrupt.
* \hideinitializer
*/
#define EMAC_DISABLE_INT(EMAC, u32eIntSel) ((EMAC)->INTEN &= ~ (u32eIntSel))
/**
* @brief Get specified interrupt flag/status
*
* @param[in] emac The pointer of the specified EMAC module
* @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
* - \ref EMAC_INTSTS_RXIF_Msk : Receive
* - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
* - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
* - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
* - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
* - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
* - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
* - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
* - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
* - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
* - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
* - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
* - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
* - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
* - \ref EMAC_INTSTS_TXIF_Msk : Transmit
* - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
* - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
* - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
* - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
* - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
* - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
* - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
* - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
* - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
*
* @return None
*
* @details This macro get specified interrupt flag or interrupt indicator status.
* \hideinitializer
*/
#define EMAC_GET_INT_FLAG(EMAC, u32eIntTypeFlag) (((EMAC)->INTSTS & (u32eIntTypeFlag))?1:0)
/**
* @brief Clear specified interrupt flag/status
*
* @param[in] emac The pointer of the specified EMAC module
* @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
* - \ref EMAC_INTSTS_RXIF_Msk : Receive
* - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error
* - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow
* - \ref EMAC_INTSTS_LPIF_Msk : Long Packet
* - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good
* - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error
* - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet
* - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter
* - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed
* - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification
* - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable
* - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error
* - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive
* - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN
* - \ref EMAC_INTSTS_TXIF_Msk : Transmit
* - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow
* - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion
* - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed
* - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense
* - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort
* - \ref EMAC_INTSTS_LCIF_Msk : Late Collision
* - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable
* - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error
* - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm
*
* @retval 0 The specified interrupt is not happened.
* 1 The specified interrupt is happened.
*
* @details This macro clear specified interrupt flag or interrupt indicator status.
* \hideinitializer
*/
#define EMAC_CLEAR_INT_FLAG(EMAC, u32eIntTypeFlag) ((EMAC)->INTSTS |= (u32eIntTypeFlag))
#define EMAC_CLEAR_ALL_INT_FLAG(EMAC) ((EMAC)->INTSTS |= (EMAC)->INTSTS)
void EMAC_Open(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8MacAddr);
void EMAC_Close(EMAC_T *EMAC);
void EMAC_SetMacAddr(EMAC_T *EMAC, uint8_t *pu8MacAddr);
void EMAC_EnableCamEntry(EMAC_T *EMAC, uint32_t u32Entry, uint8_t pu8MacAddr[]);
void EMAC_DisableCamEntry(EMAC_T *EMAC, uint32_t u32Entry);
uint32_t EMAC_RecvPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size);
uint32_t EMAC_RecvPktTS(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
void EMAC_RecvPktDone(EMAC_MEMMGR_T *psMemMgr);
uint32_t EMAC_SendPkt(EMAC_MEMMGR_T *psMemMgr, uint8_t *pu8Data, uint32_t u32Size);
uint32_t EMAC_SendPktDone(EMAC_MEMMGR_T *psMemMgr);
uint32_t EMAC_SendPktDoneTS(EMAC_MEMMGR_T *psMemMgr, uint32_t *pu32Sec, uint32_t *pu32Nsec);
void EMAC_EnableTS(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
void EMAC_DisableTS(EMAC_T *EMAC);
void EMAC_GetTime(EMAC_T *EMAC, uint32_t *pu32Sec, uint32_t *pu32Nsec);
void EMAC_SetTime(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
void EMAC_UpdateTime(EMAC_T *EMAC, uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
void EMAC_EnableAlarm(EMAC_T *EMAC, uint32_t u32Sec, uint32_t u32Nsec);
void EMAC_DisableAlarm(EMAC_T *EMAC);
uint32_t EMAC_CheckLinkStatus(EMAC_T *EMAC);
void EMAC_Reset(EMAC_T *EMAC);
void EMAC_PhyInit(EMAC_T *EMAC);
int32_t EMAC_FillCamEntry(EMAC_T *EMAC, uint8_t pu8MacAddr[]);
uint8_t *EMAC_ClaimFreeTXBuf(EMAC_MEMMGR_T *psMemMgr);
uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf);
uint32_t EMAC_SendPktWoCopy(EMAC_MEMMGR_T *psMemMgr, uint32_t u32Size);
void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr);
/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EMAC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_EMAC_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_etimer.h
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bsp/nuvoton/libraries/nuc980/Driver/Include/nu_gpio.h
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bsp/nuvoton/libraries/nuc980/Driver/Include/nu_i2c.h
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bsp/nuvoton/libraries/nuc980/Driver/Include/nu_i2s.h
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/**************************************************************************//**
* @file i2s.h
* @version V1.00
* $Revision: 2 $
* $Date: 18/08/05 2:12p $
* @brief I2S driver header file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_I2S_H__
#define __NU_I2S_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup I2S_Driver I2S Driver
@{
*/
/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
@{
*/
#define I2S_ERR_BUSY -1 /*!< Interface is busy */
#define I2S_ERR_IO -2 /*!< IO contril error */
#define I2S_DISABLE 0 /*!< Enable I2S */
#define I2S_ENABLE 1 /*!< Disable I2S */
#define I2S_PLAY 0 /*!< Play I2S audio */
#define I2S_REC 1 /*!< Reocrd I2S audio */
#define PCM_PLAY 0 /*!< Play PCM audio */
#define PCM_REC 1 /*!< Record PCM audio */
#define I2S_SET_PLAY 0 /*!< Start or stop to play */
#define I2S_START_PLAY 0 /*!< Start to play */
#define I2S_STOP_PLAY 1 /*!< Stop to play */
#define I2S_SET_RECORD 1 /*!< Start or stop to record */
#define I2S_START_REC 0 /*!< Start to record */
#define I2S_STOP_REC 1 /*!< Stop to record */
#define I2S_SELECT_BLOCK 2 /*!< Select block function */
#define I2S_BLOCK_I2S 0 /*!< Select I2S function */
#define I2S_BLOCK_PCM 1 /*!< Select PCM function */
#define I2S_SELECT_BIT 3 /*!< Select data bit width */
#define I2S_BIT_WIDTH_8 0 /*!< 8-bit */
#define I2S_BIT_WIDTH_16 1 /*!< 16-bit */
#define I2S_BIT_WIDTH_24 2 /*!< 24-bit */
#define I2S_SET_PLAY_DMA_INT_SEL 4 /*!< Select play DMA interrupt request */
#define I2S_SET_REC_DMA_INT_SEL 5 /*!< Select record DMA interrupt request */
#define I2S_DMA_INT_END 0 /*!< End of buffer */
#define I2S_DMA_INT_HALF 1 /*!< Half of buffer */
#define I2S_DMA_INT_QUARTER 2 /*!< Quarter of buffer */
#define I2S_DMA_INT_EIGHTH 3 /*!< Eighth of buffer */
#define I2S_SET_ZEROCROSS 6 /*!< Enable or disable zero cross function */
#define I2S_SET_DMACOUNTER 7 /*!< Enable or disable DMA counter function */
#define I2S_SET_CHANNEL 8 /*!< Set channel number */
#define I2S_CHANNEL_P_I2S_ONE 2 /*!< I2S one channel */
#define I2S_CHANNEL_P_I2S_TWO 3 /*!< I2S two channels */
#define I2S_CHANNEL_P_PCM_TWO 3 /*!< PCM two slots */
#define I2S_CHANNEL_P_PCM_TWO_SLOT1 0 /*!< PCM two slots with all slot1 data */
#define I2S_CHANNEL_P_PCM_TWO_SLOT0 1 /*!< PCM two slots with all slot0 data */
#define I2S_CHANNEL_P_PCM_ONE_SLOT0 2 /*!< PCM one slot with all slot0 data */
#define I2S_CHANNEL_R_I2S_LEFT_PCM_SLOT0 1 /*!< I2S left channel or PCM slot0 */
#define I2S_CHANNEL_R_I2S_RIGHT_PCM_SLOT1 2 /*!< I2S right channel or PCM slot1 */
#define I2S_CHANNEL_R_I2S_TWO 3 /*!< I2S two channels */
#define I2S_SET_MODE 9 /*!< Select master or slave mode */
#define I2S_MODE_MASTER 0 /*!< master mode */
#define I2S_MODE_SLAVE 1 /*!< slave mode */
#define I2S_SET_SPLITDATA 10 /*!< Enable or disable split data function */
#define I2S_SET_DMA_ADDRESS 11 /*!< Set DMA address */
#define I2S_SET_DMA_LENGTH 12 /*!< Set DMA length */
#define I2S_GET_DMA_CUR_ADDRESS 13 /*!< Get current DMA address */
#define I2S_SET_I2S_FORMAT 14 /*!< Select I2S format */
#define I2S_FORMAT_I2S 0 /*!< I2S format */
#define I2S_FORMAT_MSB 1 /*!< MSB foramt */
#define I2S_SET_I2S_CALLBACKFUN 15 /*!< Install play or record call-back function */
#define I2S_SET_PCMSLOT 16 /*!< Set PCM interface start position of slot */
#define PCM_SLOT1_IN 0 /*!< Slot-1 in position */
#define PCM_SLOT1_OUT 1 /*!< Slot-1 out position */
#define PCM_SLOT2_IN 2 /*!< Slot-2 in position */
#define PCM_SLOT2_OUT 3 /*!< Slot-2 out position */
#define I2S_SET_PCM_FS_PERIOD 17 /*!< Set PCM FS pulse period */
/*@}*/ /* end of group ARM9_I2S_EXPORTED_CONSTANTS */
/** @addtogroup ARM9_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
@{
*/
int32_t i2sOpen(void);
void i2sInit(void);
int32_t i2sIoctl(uint32_t cmd, uint32_t arg0, uint32_t arg1);
void i2sSetSampleRate(uint32_t u32SourceClockRate, uint32_t u32SampleRate, uint32_t u32DataBit, uint32_t u32Channel);
void i2sSetMCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32SampleRate);
void i2sSetPCMBCLKFrequency(uint32_t u32SourceClockRate, uint32_t u32Rate);
/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group I2S_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_I2S_H__
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_pdma.h
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bsp/nuvoton/libraries/nuc980/Driver/Include/nu_pwm.h
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/**************************************************************************//**
* @file pwm.h
* @version V1.00
* $Revision: 3 $
* $Date: 15/05/19 10:16a $
* @brief NUC980 series PWM driver header file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_PWM_H__
#define __NU_PWM_H__
#include "nuc980.h"
#include "nu_sys.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup PWM_Driver PWM Driver
@{
*/
/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
@{
*/
#define PWM_OFFSET 0xc ///< each channel has 3 control registers which occupies 12 bytes
// Timer channel identity information
#define PWM_TIMER_NUM 8 ///< Total PWM channel count
#define PWM_TIMER_MIN 0 ///< Min PWM channel number
#define PWM_TIMER_MAX 7 ///< Max PWM channel number
#define PWM0_TIMER0 0 ///< PWM0 channel 0
#define PWM0_TIMER1 1 ///< PWM0 channel 1
#define PWM0_TIMER2 2 ///< PWM0 channel 2
#define PWM0_TIMER3 3 ///< PWM0 channel 3
#define PWM1_TIMER0 4 ///< PWM1 channel 0
#define PWM1_TIMER1 5 ///< PWM1 channel 1
#define PWM1_TIMER2 6 ///< PWM1 channel 2
#define PWM1_TIMER3 7 ///< PWM1 channel 3
//ioctl command
#define START_PWMTIMER 0 ///< Start PWM ioctl command
#define STOP_PWMTIMER 1 ///< Stop PWM ioctl command
#define SET_CSR 2 ///< Set CSR ioctl command
#define SET_CP 3 ///< Set CP ioctl command
#define SET_DZI 4 ///< Set dead zone ioctl command
#define SET_INVERTER 5 ///< Set inverter ioctl command
#define SET_MODE 6 ///< Set OP mode ioctl command
#define ENABLE_DZ_GENERATOR 7 ///< Enable dead zone ioctl command
#define DISABLE_DZ_GENERATOR 8 ///< Disable dead zone ioctl command
#define ENABLE_PWMGPIOOUTPUT 9 ///< Enable PWM output ioctl command
#define PWM_STOP_METHOD1 1 ///< PWM stop method 1
#define PWM_STOP_METHOD2 2 ///< PWM stop method 2
//#define PWM_STOP_METHOD3 3 not recommended
//Timer default value
#define DEFAULT_CSR CSRD16 ///< Default CSR value
#define DEFAULT_CP 255 ///< Default CP value
#define DEFAULT_DZI 50 ///< Default DZI value
#define DEFAULT_CNR 19531 ///< Default CNR value
#define DEFAULT_CMR (19531/4) ///< Default CMR value
#define DEFAULT_MODE PWM_TOGGLE ///< Default OP mode
// for PWM_PPR
#define DZI_MIN 0 ///< Min DZI value
#define DZI_MAX 255 ///< Max DZI value
#define CP_MIN 0 ///< Min CP value
#define CP_MAX 255 ///< Max CP value
// for PWM_CSR
#define CSR_MIN 0 ///< Min CSR value
#define CSR_MAX 4 ///< Mac SCR value
#define CSRD2 0x0 ///< Div by 2
#define CSRD4 0x1 ///< Div by 4
#define CSRD8 0x2 ///< Div by 8
#define CSRD16 0x3 ///< Div by 16
#define CSRD1 0x4 ///< Div by 1
// for PWM_PCR
#define PWMDZG_ENABLE 1 ///< Enable PWM dead zone
#define PWMDZG_DISABLE 0 ///< Disable PWM dead zone
#define PWM_ENABLE 1 ///< Enable PWM channel
#define PWM_DISABLE 0 ///< Disable PWM channel
#define PWM_TOGGLE 1 ///< PWM toggle mode
#define PWM_ONESHOT 0 ///< PWM one-shot mode
#define PWM_INVON 1 ///< Enable PWM inverter
#define PWM_INVOFF 0 ///< Disable PWM inverter
// for PWM_CNR
#define CNR_MIN 0 ///< Min CNR value
#define CNR_MAX 65535 ///< Mac CNR value
// for PWM_CMR
#define CMR_MIN 0 ///< Min CMR value
#define CMR_MAX 65535 ///< Max CMR value
// for pin control
#define PWM00_GPF5 0 ///< PWM00 output on GPF5
#define PWM01_GPF6 1 ///< PWM01 output on GPF6
#define PWM02_GPF7 2 ///< PWM02 output on GPF7
#define PWM03_GPF8 3 ///< PWM03 output on GPF8
#define PWM00_GPG0 4 ///< PWM00 output on GPG0
#define PWM01_GPG1 5 ///< PWM01 output on GPG1
#define PWM02_GPG2 6 ///< PWM02 output on GPG2
#define PWM03_GPG3 7 ///< PWM03 output on GPG3
#define PWM00_GPD12 8 ///< PWM00 output on GPD12
#define PWM01_GPD13 9 ///< PWM01 output on GPD13
#define PWM02_GPD14 10 ///< PWM02 output on GPD14
#define PWM03_GPD15 11 ///< PWM03 output on GPD15
#define PWM00_GPG10 12 ///< PWM00 output on GPG10
#define PWM01_GPA15 13 ///< PWM01 output on GPA15
#define PWM02_GPA14 14 ///< PWM02 output on GPA14
#define PWM03_GPA13 15 ///< PWM03 output on GPA13
#define PWM02_GPB13 16 ///< PWM02 output on GPB13
#define PWM10_GPB12 17 ///< PWM10 output on GPB12
#define PWM11_GPB11 18 ///< PWM11 output on GPB11
#define PWM12_GPB10 19 ///< PWM12 output on GPB10
#define PWM13_GPB9 20 ///< PWM13 output on GPB9
#define PWM10_GPG6 21 ///< PWM10 output on GPG6
#define PWM11_GPG7 22 ///< PWM11 output on GPG7
#define PWM12_GPG8 23 ///< PWM12 output on GPG8
#define PWM13_GPG9 24 ///< PWM13 output on GPG9
#define PWM10_GPG11 25 ///< PWM10 output on GPG11
#define PWM11_GPG12 26 ///< PWM11 output on GPG12
#define PWM12_GPG13 27 ///< PWM12 output on GPG13
#define PWM13_GPG14 28 ///< PWM13 output on GPG14
#define PWM10_GPF9 29 ///< PWM10 output on GPF9
#define PWM11_GPF10 30 ///< PWM11 output on GPF10
#define PWM12_GPE10 31 ///< PWM12 output on GPE10
#define PWM13_GPE12 32 ///< PWM13 output on GPE12
#define PWM_ERR_ID 0xFFFF1300 ///< PWM library ID
//PWM Error code
#define pwmInvalidTimerChannel (PWM_ERR_ID|1) ///< Invalid channel number
#define pwmInvalidStructLength (PWM_ERR_ID|2) ///< Invalid structure length
#define pwmInvalidIoctlCommand (PWM_ERR_ID|3) ///< Invalid ioctl command
#define pwmInvalidStopMethod (PWM_ERR_ID|4) ///< Invalid stop mode
#define pwmInvalidCPValue (PWM_ERR_ID|5) ///< Invalid CP value
#define pwmInvalidDZIValue (PWM_ERR_ID|6) ///< Invalid DZI value
#define pwmInvalidCSRValue (PWM_ERR_ID|7) ///< Invalid CSR value
#define pwmInvalidDZGStatus (PWM_ERR_ID|8) ///< Invalid DZ status
#define pwmInvalidTimerStatus (PWM_ERR_ID|9) ///< Invalid timer status
#define pwmInvalidInverterValue (PWM_ERR_ID|10) ///< Invalid inverter value
#define pwmInvalidModeStatus (PWM_ERR_ID|11) ///< Invalid OP mode
#define pwmInvalidCNRValue (PWM_ERR_ID|12) ///< Invalid CNR value
#define pwmInvalidCMRValue (PWM_ERR_ID|13) ///< Invalid CMR value
#define pwmTimerNotOpen (PWM_ERR_ID|14) ///< PWM channel not stop
#define pwmTimerBusy (PWM_ERR_ID|15) ///< PWM channel is busy
#define pwmInvalidPin (PWM_ERR_ID|16) ///< Invalid PWM output pin
/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
/// @cond HIDDEN_SYMBOLS
/** @addtogroup PWM_EXPORTED_STRUCTS PWM Exported Structs
@{
*/
typedef union
{
UINT value;
struct
{
UINT cp0: 8, cp1: 8, dzi0: 8, dzi1: 8;
} field;
} typePPR;
typedef union
{
UINT value;
struct
{
UINT csr0: 3, _reserved3: 1,
csr1: 3, _reserved7: 1,
csr2: 3, _reserved11: 1,
csr3: 3, _reserved15: 1,
_reserved16_31: 16;
} field;
} typeCSR;
typedef union
{
UINT value;
struct
{
UINT ch0_en: 1, _reserved1: 1, ch0_inverter: 1, ch0_mode: 1,
grpup0_dzen: 1, grpup1_dzen: 1,
_reserved6_7: 2,
ch1_en: 1, _reserved9: 1, ch1_inverter: 1, ch1_mode: 1,
ch2_en: 1, _reserved13: 1, ch2_inverter: 1, ch2_mode: 1,
ch3_en: 1, _reserved17: 1, ch3_inverter: 1, ch3_mode: 1,
_reserved20_31: 12;
} field;
} typePCR;
typedef union
{
UINT value;
struct
{
UINT cnr: 16, _reserved16_31: 16;
} field;
} typeCNR;
typedef union
{
UINT value;
struct
{
UINT cmr: 16, _reserved16_31: 16;
} field;
} typeCMR;
// for write operation
typedef union
{
UINT value;
struct
{
UINT cnr: 16, cmr: 16;
} field;
} typePWMVALUE;
// for read operation
typedef struct
{
UINT volatile PDR;
BOOL volatile InterruptFlag;
BOOL _reversed0;
BOOL _reversed1;
BOOL _reversed2;
} typePWMSTATUS;
/*@}*/ /* end of group PWM_EXPORTED_STRUCTS */
/// @endcond /* HIDDEN_SYMBOLS */
/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
@{
*/
// function definition
INT pwmInit(const INT nTimerIdentity);
INT pwmExit(void);
INT pwmOpen(const INT nTimerIdentity);
INT pwmClose(const INT nTimerIdentity);
INT pwmRead(const INT nTimerIdentity, PUCHAR pucStatusValue, const UINT uLength);
INT pwmWrite(const INT nTimerIdentity, PUCHAR pucCNRCMRValue, const UINT uLength);
INT pwmIoctl(const INT nTimerIdentity, const UINT uCommand, const UINT uIndication, UINT uValue);
/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group PWM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_PWM_H__
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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