mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-20 17:44:20 +08:00
update stm32f10x project directory structure.
This commit is contained in:
aozima
+10
-29
@@ -1,33 +1,14 @@
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import rtconfig
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c']
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src_drv = ['rtc.c', 'usart.c', 'serial.c', 'led.c']
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cwd = str(Dir('#'))
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objs = []
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list = os.listdir(cwd)
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if GetDepend('RT_USING_DFS'):
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if rtconfig.STM32_TYPE == 'STM32F10X_HD':
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src_drv += ['sdcard.c']
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else:
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src_drv += ['msd.c']
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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if GetDepend('RT_USING_LWIP'):
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src_drv += ['enc28j60.c'] + ['dm9000a.c']
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if GetDepend('RT_USING_RTGUI'):
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src_drv += ['touch.c']
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if GetDepend('RT_USING_RTGUI'):
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if rtconfig.RT_USING_LCD_TYPE == 'FMT0371':
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src_drv += ['lcd_a70.c']
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elif rtconfig.RT_USING_LCD_TYPE == 'ILI932X':
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src_drv += ['ili_lcd_general.c']
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elif rtconfig.RT_USING_LCD_TYPE == 'SSD1289':
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src_drv += ['ssd1289.c']
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src = src_bsp + src_drv
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CPPPATH = [ GetCurrentDir() ]
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CPPDEFINES = []
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group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
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Return('group')
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Return('objs')
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@@ -28,10 +28,8 @@ Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# STM32 firemare library building script
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objs = objs + SConscript( GetCurrentDir() + '/Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,40 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'drivers')
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# add the general drvers.
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src = Split("""
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board.c
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led.c
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serial.c
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usart.c
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""")
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# add Ethernet drvers.
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if GetDepend('RT_USING_LWIP'):
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src += ['dm9000a.c']
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# add Ethernet drvers.
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if GetDepend('RT_USING_DFS'):
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src += ['sdcard.c']
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# add Ethernet drvers.
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if GetDepend('RT_USING_RTC'):
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src += ['rtc.c']
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# add Ethernet drvers.
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if GetDepend('RT_USING_RTGUI'):
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src += ['touch.c']
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if rtconfig.RT_USING_LCD_TYPE == 'ILI932X':
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src += ['ili_lcd_general.c']
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elif rtconfig.RT_USING_LCD_TYPE == 'SSD1289':
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src += ['ssd1289.c']
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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File diff suppressed because it is too large
Load Diff
@@ -1,315 +0,0 @@
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/*
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* File : enc28j60.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard the first version
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*/
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#ifndef __ENC28J60_H__
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#define __ENC28J60_H__
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#include <rtthread.h>
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// ENC28J60 Control Registers
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// Control register definitions are a combination of address,
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// bank number, and Ethernet/MAC/PHY indicator bits.
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// - Register address (bits 0-4)
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// - Bank number (bits 5-6)
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// - MAC/PHY indicator (bit 7)
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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// All-bank registers
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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// Bank 0 registers
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#define ERDPTL (0x00|0x00)
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#define ERDPTH (0x01|0x00)
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#define EWRPTL (0x02|0x00)
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#define EWRPTH (0x03|0x00)
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#define ETXSTL (0x04|0x00)
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#define ETXSTH (0x05|0x00)
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#define ETXNDL (0x06|0x00)
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#define ETXNDH (0x07|0x00)
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#define ERXSTL (0x08|0x00)
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#define ERXSTH (0x09|0x00)
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#define ERXNDL (0x0A|0x00)
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#define ERXNDH (0x0B|0x00)
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#define ERXRDPTL (0x0C|0x00)
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#define ERXRDPTH (0x0D|0x00)
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#define ERXWRPTL (0x0E|0x00)
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#define ERXWRPTH (0x0F|0x00)
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#define EDMASTL (0x10|0x00)
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#define EDMASTH (0x11|0x00)
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#define EDMANDL (0x12|0x00)
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#define EDMANDH (0x13|0x00)
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#define EDMADSTL (0x14|0x00)
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#define EDMADSTH (0x15|0x00)
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#define EDMACSL (0x16|0x00)
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#define EDMACSH (0x17|0x00)
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// Bank 1 registers
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCSL (0x10|0x20)
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#define EPMCSH (0x11|0x20)
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#define EPMOL (0x14|0x20)
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#define EPMOH (0x15|0x20)
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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// Bank 2 registers
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#define MACON1 (0x00|0x40|0x80)
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#define MACON2 (0x01|0x40|0x80)
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#define MACON3 (0x02|0x40|0x80)
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#define MACON4 (0x03|0x40|0x80)
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#define MABBIPG (0x04|0x40|0x80)
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#define MAIPGL (0x06|0x40|0x80)
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#define MAIPGH (0x07|0x40|0x80)
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#define MACLCON1 (0x08|0x40|0x80)
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#define MACLCON2 (0x09|0x40|0x80)
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#define MAMXFLL (0x0A|0x40|0x80)
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#define MAMXFLH (0x0B|0x40|0x80)
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#define MAPHSUP (0x0D|0x40|0x80)
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#define MICON (0x11|0x40|0x80)
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#define MICMD (0x12|0x40|0x80)
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#define MIREGADR (0x14|0x40|0x80)
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#define MIWRL (0x16|0x40|0x80)
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#define MIWRH (0x17|0x40|0x80)
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#define MIRDL (0x18|0x40|0x80)
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#define MIRDH (0x19|0x40|0x80)
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// Bank 3 registers
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#define MAADR1 (0x00|0x60|0x80)
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#define MAADR0 (0x01|0x60|0x80)
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#define MAADR3 (0x02|0x60|0x80)
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#define MAADR2 (0x03|0x60|0x80)
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#define MAADR5 (0x04|0x60|0x80)
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#define MAADR4 (0x05|0x60|0x80)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCSL (0x08|0x60)
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#define EBSTCSH (0x09|0x60)
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#define MISTAT (0x0A|0x60|0x80)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUSL (0x18|0x60)
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#define EPAUSH (0x19|0x60)
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// PHY registers
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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// ENC28J60 ERXFCON Register Bit Definitions
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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// ENC28J60 EIE Register Bit Definitions
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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#define EIE_WOLIE 0x04
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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// ENC28J60 EIR Register Bit Definitions
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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#define EIR_WOLIF 0x04
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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// ENC28J60 ESTAT Register Bit Definitions
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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// ENC28J60 ECON2 Register Bit Definitions
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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// ENC28J60 ECON1 Register Bit Definitions
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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// ENC28J60 MACON1 Register Bit Definitions
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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// ENC28J60 MACON2 Register Bit Definitions
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#define MACON2_MARST 0x80
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#define MACON2_RNDRST 0x40
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#define MACON2_MARXRST 0x08
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#define MACON2_RFUNRST 0x04
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#define MACON2_MATXRST 0x02
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#define MACON2_TFUNRST 0x01
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// ENC28J60 MACON3 Register Bit Definitions
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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// ENC28J60 MACON4 Register Bit Definitions
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#define MACON4_DEFER (1<<6)
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#define MACON4_BPEN (1<<5)
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#define MACON4_NOBKOFF (1<<4)
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// ENC28J60 MICMD Register Bit Definitions
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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// ENC28J60 MISTAT Register Bit Definitions
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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// ENC28J60 PHY PHCON1 Register Bit Definitions
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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// ENC28J60 PHY PHSTAT1 Register Bit Definitions
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
|
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#define PHSTAT1_JBSTAT 0x0002
|
||||
/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
|
||||
#define PHSTAT2_TXSTAT (1 << 13)
|
||||
#define PHSTAT2_RXSTAT (1 << 12)
|
||||
#define PHSTAT2_COLSTAT (1 << 11)
|
||||
#define PHSTAT2_LSTAT (1 << 10)
|
||||
#define PHSTAT2_DPXSTAT (1 << 9)
|
||||
#define PHSTAT2_PLRITY (1 << 5)
|
||||
// ENC28J60 PHY PHCON2 Register Bit Definitions
|
||||
#define PHCON2_FRCLINK 0x4000
|
||||
#define PHCON2_TXDIS 0x2000
|
||||
#define PHCON2_JABBER 0x0400
|
||||
#define PHCON2_HDLDIS 0x0100
|
||||
|
||||
// ENC28J60 Packet Control Byte Bit Definitions
|
||||
#define PKTCTRL_PHUGEEN 0x08
|
||||
#define PKTCTRL_PPADEN 0x04
|
||||
#define PKTCTRL_PCRCEN 0x02
|
||||
#define PKTCTRL_POVERRIDE 0x01
|
||||
|
||||
/* ENC28J60 Transmit Status Vector */
|
||||
#define TSV_TXBYTECNT 0
|
||||
#define TSV_TXCOLLISIONCNT 16
|
||||
#define TSV_TXCRCERROR 20
|
||||
#define TSV_TXLENCHKERROR 21
|
||||
#define TSV_TXLENOUTOFRANGE 22
|
||||
#define TSV_TXDONE 23
|
||||
#define TSV_TXMULTICAST 24
|
||||
#define TSV_TXBROADCAST 25
|
||||
#define TSV_TXPACKETDEFER 26
|
||||
#define TSV_TXEXDEFER 27
|
||||
#define TSV_TXEXCOLLISION 28
|
||||
#define TSV_TXLATECOLLISION 29
|
||||
#define TSV_TXGIANT 30
|
||||
#define TSV_TXUNDERRUN 31
|
||||
#define TSV_TOTBYTETXONWIRE 32
|
||||
#define TSV_TXCONTROLFRAME 48
|
||||
#define TSV_TXPAUSEFRAME 49
|
||||
#define TSV_BACKPRESSUREAPP 50
|
||||
#define TSV_TXVLANTAGFRAME 51
|
||||
|
||||
#define TSV_SIZE 7
|
||||
#define TSV_BYTEOF(x) ((x) / 8)
|
||||
#define TSV_BITMASK(x) (1 << ((x) % 8))
|
||||
#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
|
||||
|
||||
/* ENC28J60 Receive Status Vector */
|
||||
#define RSV_RXLONGEVDROPEV 16
|
||||
#define RSV_CARRIEREV 18
|
||||
#define RSV_CRCERROR 20
|
||||
#define RSV_LENCHECKERR 21
|
||||
#define RSV_LENOUTOFRANGE 22
|
||||
#define RSV_RXOK 23
|
||||
#define RSV_RXMULTICAST 24
|
||||
#define RSV_RXBROADCAST 25
|
||||
#define RSV_DRIBBLENIBBLE 26
|
||||
#define RSV_RXCONTROLFRAME 27
|
||||
#define RSV_RXPAUSEFRAME 28
|
||||
#define RSV_RXUNKNOWNOPCODE 29
|
||||
#define RSV_RXTYPEVLAN 30
|
||||
|
||||
#define RSV_SIZE 6
|
||||
#define RSV_BITMASK(x) (1 << ((x) - 16))
|
||||
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
|
||||
|
||||
// SPI operation codes
|
||||
#define ENC28J60_READ_CTRL_REG 0x00
|
||||
#define ENC28J60_READ_BUF_MEM 0x3A
|
||||
#define ENC28J60_WRITE_CTRL_REG 0x40
|
||||
#define ENC28J60_WRITE_BUF_MEM 0x7A
|
||||
#define ENC28J60_BIT_FIELD_SET 0x80
|
||||
#define ENC28J60_BIT_FIELD_CLR 0xA0
|
||||
#define ENC28J60_SOFT_RESET 0xFF
|
||||
|
||||
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
|
||||
// buffer boundaries applied to internal 8K ram
|
||||
// the entire available packet buffer space is allocated
|
||||
//
|
||||
|
||||
// start with recbuf at 0/
|
||||
#define RXSTART_INIT 0x0
|
||||
// receive buffer end
|
||||
#define RXSTOP_INIT (0x1FFF-0x0600) - 1
|
||||
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
|
||||
|
||||
#define TXSTART_INIT (0x1FFF-0x0600)
|
||||
// stp TX buffer at end of mem
|
||||
#define TXSTOP_INIT 0x1FFF
|
||||
|
||||
// max frame length which the conroller will accept:
|
||||
#define MAX_FRAMELEN 1518
|
||||
|
||||
void rt_hw_enc28j60_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,173 +0,0 @@
|
||||
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
|
||||
* File Name : msd.h
|
||||
* Author : MCD Application Team
|
||||
* Version : V2.1
|
||||
* Date : 05/30/2008
|
||||
* Description : Header for msd.c file.
|
||||
********************************************************************************
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
|
||||
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MSD_H
|
||||
#define __MSD_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stm32f10x.h>
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Block Size */
|
||||
#define BLOCK_SIZE 512
|
||||
|
||||
/* Dummy byte */
|
||||
#define DUMMY 0xFF
|
||||
|
||||
/* Start Data tokens */
|
||||
/* Tokens (necessary because at nop/idle (and CS active) only 0xff is on the data/command line) */
|
||||
#define MSD_START_DATA_SINGLE_BLOCK_READ 0xFE /* Data token start byte, Start Single Block Read */
|
||||
#define MSD_START_DATA_MULTIPLE_BLOCK_READ 0xFE /* Data token start byte, Start Multiple Block Read */
|
||||
#define MSD_START_DATA_SINGLE_BLOCK_WRITE 0xFE /* Data token start byte, Start Single Block Write */
|
||||
#define MSD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD /* Data token start byte, Start Multiple Block Write */
|
||||
#define MSD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD /* Data toke stop byte, Stop Multiple Block Write */
|
||||
|
||||
/* MSD functions return */
|
||||
#define MSD_SUCCESS 0x00
|
||||
#define MSD_FAIL 0xFF
|
||||
|
||||
/* MSD reponses and error flags */
|
||||
#define MSD_RESPONSE_NO_ERROR 0x00
|
||||
#define MSD_IN_IDLE_STATE 0x01
|
||||
#define MSD_ERASE_RESET 0x02
|
||||
#define MSD_ILLEGAL_COMMAND 0x04
|
||||
#define MSD_COM_CRC_ERROR 0x08
|
||||
#define MSD_ERASE_SEQUENCE_ERROR 0x10
|
||||
#define MSD_ADDRESS_ERROR 0x20
|
||||
#define MSD_PARAMETER_ERROR 0x40
|
||||
#define MSD_RESPONSE_FAILURE 0xFF
|
||||
|
||||
/* Data response error */
|
||||
#define MSD_DATA_OK 0x05
|
||||
#define MSD_DATA_CRC_ERROR 0x0B
|
||||
#define MSD_DATA_WRITE_ERROR 0x0D
|
||||
#define MSD_DATA_OTHER_ERROR 0xFF
|
||||
|
||||
/* Commands: CMDxx = CMD-number | 0x40 */
|
||||
#define MSD_GO_IDLE_STATE 0 /* CMD0=0x40 */
|
||||
#define MSD_SEND_OP_COND 1 /* CMD1=0x41 */
|
||||
#define MSD_SEND_CSD 9 /* CMD9=0x49 */
|
||||
#define MSD_SEND_CID 10 /* CMD10=0x4A */
|
||||
#define MSD_STOP_TRANSMISSION 12 /* CMD12=0x4C */
|
||||
#define MSD_SEND_STATUS 13 /* CMD13=0x4D */
|
||||
#define MSD_SET_BLOCKLEN 16 /* CMD16=0x50 */
|
||||
#define MSD_READ_SINGLE_BLOCK 17 /* CMD17=0x51 */
|
||||
#define MSD_READ_MULTIPLE_BLOCK 18 /* CMD18=0x52 */
|
||||
#define MSD_SET_BLOCK_COUNT 23 /* CMD23=0x57 */
|
||||
#define MSD_WRITE_BLOCK 24 /* CMD24=0x58 */
|
||||
#define MSD_WRITE_MULTIPLE_BLOCK 25 /* CMD25=0x59 */
|
||||
#define MSD_PROGRAM_CSD 27 /* CMD27=0x5B */
|
||||
#define MSD_SET_WRITE_PROT 28 /* CMD28=0x5C */
|
||||
#define MSD_CLR_WRITE_PROT 29 /* CMD29=0x5D */
|
||||
#define MSD_SEND_WRITE_PROT 30 /* CMD30=0x5E */
|
||||
#define MSD_TAG_SECTOR_START 32 /* CMD32=0x60 */
|
||||
#define MSD_TAG_SECTOR_END 33 /* CMD33=0x61 */
|
||||
#define MSD_UNTAG_SECTOR 34 /* CMD34=0x62 */
|
||||
#define MSD_TAG_ERASE_GROUP_START 35 /* CMD35=0x63 */
|
||||
#define MSD_TAG_ERASE_GROUP_END 36 /* CMD36=0x64 */
|
||||
#define MSD_UNTAG_ERASE_GROUP 37 /* CMD37=0x65 */
|
||||
#define MSD_ERASE 38 /* CMD38=0x66 */
|
||||
#define MSD_READ_OCR 39 /* CMD39=0x67 */
|
||||
#define MSD_CRC_ON_OFF 40 /* CMD40=0x68 */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
typedef struct _MSD_CSD /*Card Specific Data*/
|
||||
{
|
||||
vu8 CSDStruct; /* CSD structure */
|
||||
vu8 SysSpecVersion; /* System specification version */
|
||||
vu8 Reserved1; /* Reserved */
|
||||
vu8 TAAC; /* Data read access-time 1 */
|
||||
vu8 NSAC; /* Data read access-time 2 in CLK cycles */
|
||||
vu8 MaxBusClkFrec; /* Max. bus clock frequency */
|
||||
vu16 CardComdClasses; /* Card command classes */
|
||||
vu8 RdBlockLen; /* Max. read data block length */
|
||||
vu8 PartBlockRead; /* Partial blocks for read allowed */
|
||||
vu8 WrBlockMisalign; /* Write block misalignment */
|
||||
vu8 RdBlockMisalign; /* Read block misalignment */
|
||||
vu8 DSRImpl; /* DSR implemented */
|
||||
vu8 Reserved2; /* Reserved */
|
||||
vu16 DeviceSize; /* Device Size */
|
||||
vu8 MaxRdCurrentVDDMin; /* Max. read current @ VDD min */
|
||||
vu8 MaxRdCurrentVDDMax; /* Max. read current @ VDD max */
|
||||
vu8 MaxWrCurrentVDDMin; /* Max. write current @ VDD min */
|
||||
vu8 MaxWrCurrentVDDMax; /* Max. write current @ VDD max */
|
||||
vu8 DeviceSizeMul; /* Device size multiplier */
|
||||
vu8 EraseGrSize; /* Erase group size */
|
||||
vu8 EraseGrMul; /* Erase group size multiplier */
|
||||
vu8 WrProtectGrSize; /* Write protect group size */
|
||||
vu8 WrProtectGrEnable; /* Write protect group enable */
|
||||
vu8 ManDeflECC; /* Manufacturer default ECC */
|
||||
vu8 WrSpeedFact; /* Write speed factor */
|
||||
vu8 MaxWrBlockLen; /* Max. write data block length */
|
||||
vu8 WriteBlockPaPartial; /* Partial blocks for write allowed */
|
||||
vu8 Reserved3; /* Reserded */
|
||||
vu8 ContentProtectAppli; /* Content protection application */
|
||||
vu8 FileFormatGrouop; /* File format group */
|
||||
vu8 CopyFlag; /* Copy flag (OTP) */
|
||||
vu8 PermWrProtect; /* Permanent write protection */
|
||||
vu8 TempWrProtect; /* Temporary write protection */
|
||||
vu8 FileFormat; /* File Format */
|
||||
vu8 ECC; /* ECC code */
|
||||
vu8 msd_CRC; /* CRC */
|
||||
vu8 Reserved4; /* always 1*/
|
||||
}
|
||||
sMSD_CSD;
|
||||
|
||||
typedef struct _MSD_CID /*Card Identification Data*/
|
||||
{
|
||||
vu8 ManufacturerID; /* ManufacturerID */
|
||||
vu16 OEM_AppliID; /* OEM/Application ID */
|
||||
vu32 ProdName1; /* Product Name part1 */
|
||||
vu8 ProdName2; /* Product Name part2*/
|
||||
vu8 ProdRev; /* Product Revision */
|
||||
vu32 ProdSN; /* Product Serial Number */
|
||||
vu8 Reserved1; /* Reserved1 */
|
||||
vu16 ManufactDate; /* Manufacturing Date */
|
||||
vu8 msd_CRC; /* CRC */
|
||||
vu8 Reserved2; /* always 1*/
|
||||
}
|
||||
sMSD_CID;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/*----- High layer function -----*/
|
||||
u8 MSD_Init(void);
|
||||
u8 MSD_WriteBlock(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
|
||||
u8 MSD_ReadBlock(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);
|
||||
u8 MSD_WriteBuffer(u8* pBuffer, u32 WriteAddr, u32 NumByteToWrite);
|
||||
u8 MSD_ReadBuffer(u8* pBuffer, u32 ReadAddr, u32 NumByteToRead);
|
||||
u8 MSD_GetCSDRegister(sMSD_CSD* MSD_csd);
|
||||
u8 MSD_GetCIDRegister(sMSD_CID* MSD_cid);
|
||||
|
||||
/*----- Medium layer function -----*/
|
||||
void MSD_SendCmd(u8 Cmd, u32 Arg, u8 Crc);
|
||||
u8 MSD_GetResponse(u8 Response);
|
||||
u8 MSD_GetDataResponse(void);
|
||||
u8 MSD_GoIdleState(void);
|
||||
u16 MSD_GetStatus(void);
|
||||
|
||||
/*----- Low layer function -----*/
|
||||
void MSD_WriteByte(u8 byte);
|
||||
u8 MSD_ReadByte(void);
|
||||
|
||||
#endif /* __MSD_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user