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add Vango V85xx first version

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This commit is contained in:
FuChao
2021-09-07 20:08:26 +08:00
parent d71e2ac582
commit 8b250bc9ff
80 changed files with 25092 additions and 0 deletions
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109
bsp/Vango_V85xx/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_GD32F1
bool
default y
config SOC_GD32103C
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_GD32F1
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu

40
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h Normal file
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/**
******************************************************************************
* @brief Configuration file.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CONF_H
#define __GD32F10X_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "lib_ana.h"
#include "lib_adc.h"
#include "lib_adc_tiny.h"
#include "lib_clk.h"
#include "lib_comp.h"
#include "lib_crypt.h"
#include "lib_dma.h"
#include "lib_flash.h"
#include "lib_gpio.h"
#include "lib_i2c.h"
#include "lib_iso7816.h"
#include "lib_lcd.h"
#include "lib_misc.h"
#include "lib_pmu.h"
#include "lib_pwm.h"
#include "lib_rtc.h"
#include "lib_spi.h"
#include "lib_tmr.h"
#include "lib_u32k.h"
#include "lib_uart.h"
#include "lib_version.h"
#include "lib_wdt.h"
#include "lib_LoadNVR.h"
#include "lib_CodeRAM.h"
#include "lib_cortex.h"
#endif /* __GD32F10X_CONF_H */

46
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h Normal file
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/**
******************************************************************************
* @file lib_CodeRAM.h
* @author Application Team
* @version V4.4.0
* @date 2019-01-18
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CODERAM_H
#define __LIB_CODERAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#ifndef __GNUC__
#ifdef __ICCARM__ /* EWARM */
#define __RAM_FUNC __ramfunc
#endif
#ifdef __CC_ARM /* MDK-ARM */
#define __RAM_FUNC __attribute__((used))
#endif
/* Exported Functions ------------------------------------------------------- */
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CODERAM_H */
/*********************************** END OF FILE ******************************/

231
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h Normal file
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/**
******************************************************************************
* @file lib_LoadNVR.h
* @author Application Team
* @version V4.7.0
* @date 2019-12-12
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LOADNVR_H
#define __LIB_LOADNVR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
/* BAT measure result */
typedef struct
{
float BATRESResult; // BAT Resistor division Measure Result
float BATCAPResult; // BATRTC Cap division Measure Result
} NVR_BATMEARES;
/* Power Measure Result */
typedef struct
{
uint32_t AVCCMEAResult; // LDO33 Measure Result
uint32_t DVCCMEAResult; // LDO15 Measure Result
uint32_t BGPMEAResult; // BGP Measure Result
uint32_t RCLMEAResult; // RCL Measure Result
uint32_t RCHMEAResult; // RCH Measure Result
} NVR_MISCGain;
/* Chip ID */
typedef struct
{
uint32_t ChipID0; // ID word 0
uint32_t ChipID1; // ID word 1
} NVR_CHIPID;
/* Temperature information */
typedef struct
{
float TempOffset;
} NVR_TEMPINFO;
/* LCD information */
typedef struct
{
uint32_t MEALCDLDO; // Measure LCD LDO pre trim value
uint32_t MEALCDVol; // VLCD setting
} NVR_LCDINFO;
/* RTC(temp) information */
typedef struct
{
int16_t RTCTempP0; //P0
int16_t RTCTempP1; //P1
int32_t RTCTempP2; //P2
int16_t RTCTempP4; //P4
int16_t RTCTempP5; //P5
int16_t RTCTempP6; //P6
int16_t RTCTempP7; //P7
int16_t RTCTempK1; //K1
int16_t RTCTempK2; //K2
int16_t RTCTempK3; //K3
int16_t RTCTempK4; //K4
int16_t RTCTempK5; //K5
int16_t RTCACTI; //Center temperature
uint32_t RTCACKTemp; //section X temperature
int16_t RTCTempDelta; //Temperature delta
uint32_t RTCACF200; //RTC_ACF200
uint32_t APBClock; //APB clock
} NVR_RTCINFO;
/* ADC Voltage Parameters */
typedef struct
{
float aParameter;
float bParameter;
} NVR_ADCVOLPARA;
//Mode
#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define NVR_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive
#define NVR_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define NVR_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive
#define NVR_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive
#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define NVR_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive
#define NVR_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define NVR_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive
#define NVR_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive
#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_3V_VDD_RESDIV) ||\
((__MODE__) == NVR_3V_VDD_CAPDIV) ||\
((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_3V_BATRTC_CAPDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_5V_VDD_RESDIV) ||\
((__MODE__) == NVR_5V_VDD_CAPDIV) ||\
((__MODE__) == NVR_5V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_5V_BATRTC_CAPDIV))
/********** NVR Address **********/
//ADC Voltage Parameters
#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x40400)
#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x40440)
#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x40480)
#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x404C0)
//RTC DATA
//P4
#define NVR_RTC1_P4 (__IO uint32_t *)(0x40800)
#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x40804)
#define NVR_RTC2_P4 (__IO uint32_t *)(0x40808)
#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x4080C)
//ACK1~ACK5
#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x40810)
#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x40814)
#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x40818)
#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x4081C)
#define NVR_RTC1_ACK5 (__IO uint32_t *)(0x40820)
#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x40824)
#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x40828)
#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x4082C)
#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x40830)
#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x40834)
#define NVR_RTC2_ACK5 (__IO uint32_t *)(0x40838)
#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x4083C)
//ACTI
#define NVR_RTC1_ACTI (__IO uint32_t *)(0x40840)
#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x40844)
#define NVR_RTC2_ACTI (__IO uint32_t *)(0x40848)
#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x4084C)
//ACKTEMP
#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x40850)
#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x40854)
#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x40858)
#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x4085C)
//Analog trim data
#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x40DC0)
#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x40DC4)
#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x40DC8)
#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x40DCC)
#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x40DD0)
#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x40DD4)
#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x40DD8)
#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x40DDC)
//BAT Measure Result
#define NVR_BAT_R1 (__IO uint32_t *)(0x40CE0)
#define NVR_BAT_C1 (__IO uint32_t *)(0x40CE4)
#define NVR_BATMEA_CHECHSUM1 (__IO uint32_t *)(0x40CE8)
#define NVR_BAT_R2 (__IO uint32_t *)(0x40CF0)
#define NVR_BAT_C2 (__IO uint32_t *)(0x40CF4)
#define NVR_BATMEA_CHECHSUM2 (__IO uint32_t *)(0x40CF8)
//RTC AutoCal Px pramameters
#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x40D00)
#define NVR_RTC1_P2 (__IO uint32_t *)(0x40D04)
#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x40D08)
#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x40D0C)
#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x40D10)
#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x40D14)
#define NVR_RTC2_P2 (__IO uint32_t *)(0x40D18)
#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x40D1C)
#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x40D20)
#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x40D24)
//Power Measure Result
#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x40D28)
#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x40D2C)
#define NVR_BGP_MEA1 (__IO uint32_t *)(0x40D30)
#define NVR_RCL_MEA1 (__IO uint32_t *)(0x40D34)
#define NVR_RCH_MEA1 (__IO uint32_t *)(0x40D38)
#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x40D3C)
#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x40D40)
#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x40D44)
#define NVR_BGP_MEA2 (__IO uint32_t *)(0x40D48)
#define NVR_RCL_MEA2 (__IO uint32_t *)(0x40D4C)
#define NVR_RCH_MEA2 (__IO uint32_t *)(0x40D50)
#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x40D54)
//Chip ID
#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x40D58)
#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x40D5C)
#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x40D60)
#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x40D64)
#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x40D68)
#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x40D6C)
//Temperature information
#define NVR_REALTEMP1 (__IO uint32_t *)(0x40D70)
#define NVR_MEATEMP1 (__IO uint32_t *)(0x40D74)
#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x40D78)
#define NVR_REALTEMP2 (__IO uint32_t *)(0x40D7C)
#define NVR_MEATEMP2 (__IO uint32_t *)(0x40D80)
#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x40D84)
//LCD Information
#define NVR_LCD_LDO1 (__IO uint32_t *)(0x40D90)
#define NVR_LCD_VOL1 (__IO uint32_t *)(0x40D94)
#define NVR_LCD_CHECKSUM1 (__IO uint32_t *)(0x40D98)
#define NVR_LCD_LDO2 (__IO uint32_t *)(0x40D9C)
#define NVR_LCD_VOL2 (__IO uint32_t *)(0x40DA0)
#define NVR_LCD_CHECKSUM2 (__IO uint32_t *)(0x40DA4)
uint32_t NVR_LoadANADataManual(void);
uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult);
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData);
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LOADNVR_H */
/*********************************** END OF FILE ******************************/

62
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h Normal file
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/**
******************************************************************************
* @file lib_conf.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Dirver configuration.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CONF_H
#define __LIB_CONF_H
/* ########################## Assert Selection ############################## */
//#define ASSERT_NDEBUG 1
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#include "lib_ana.h"
#include "lib_adc.h"
#include "lib_adc_tiny.h"
#include "lib_clk.h"
#include "lib_comp.h"
#include "lib_crypt.h"
#include "lib_dma.h"
#include "lib_flash.h"
#include "lib_gpio.h"
#include "lib_i2c.h"
#include "lib_iso7816.h"
#include "lib_lcd.h"
#include "lib_misc.h"
#include "lib_pmu.h"
#include "lib_pwm.h"
#include "lib_rtc.h"
#include "lib_spi.h"
#include "lib_tmr.h"
#include "lib_u32k.h"
#include "lib_uart.h"
#include "lib_version.h"
#include "lib_wdt.h"
#include "lib_LoadNVR.h"
#include "lib_CodeRAM.h"
#include "lib_cortex.h"
/* Exported macro ------------------------------------------------------------*/
#ifndef ASSERT_NDEBUG
#define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_errhandler(uint8_t* file, uint32_t line);
#else
#define assert_parameters(expr) ((void)0U)
#endif /* ASSERT_NDEBUG */
#endif
/*********************************** END OF FILE ******************************/

48
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h Normal file
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/**
******************************************************************************
* @file lib_Cortex.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CORTEX_H
#define __LIB_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
/* Exported Functions ------------------------------------------------------- */
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_SystemReset(void);
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CORTEX_H */
/*********************************** END OF FILE ******************************/

41
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h Normal file
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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __SYSTEM_TARGET_H
#define __SYSTEM_TARGET_H
#ifdef __cplusplus
extern "C" {
#endif
#include "type_def.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/* ########################### System Configuration ######################### */
extern void SystemInit(void);
extern void SystemUpdate(void);
#ifdef USE_TARGET_DRIVER
#include "lib_conf.h"
#endif /* USE_TARGET_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_TARGET_H */
/*********************************** END OF FILE ******************************/

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bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h Normal file
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bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h Normal file
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/**
******************************************************************************
* @file type_def.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Typedef file
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __TYPE_DEF_H
#define __TYPE_DEF_H
#define ENABLE 1
#define DISABLE 0
#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#endif /* __TYPE_DEF_H */
/*********************************** END OF FILE ******************************/

478
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S Normal file
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;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.equ __CHIPINITIAL, 1
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/*************************************************************************
* Chip init.
* 1. Load flash configuration
* 2. Load ANA_REG(B/C/D/E) information
* 3. Load ANA_REG10 information
**************************************************************************/
.if (__CHIPINITIAL != 0)
.section .chipinit_section.__CHIP_INIT
__CHIP_INIT:
CONFIG1_START:
/*-------------------------------*/
/* 1. Load flash configuration */
/* Unlock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
/* Load configure word 0 to 7
Compare bit[7:0] */
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1:
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1:
/* Load configure word 8 to 11
Compare bit 31,24,23:16,8,7:0 */
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2:
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2:
/* Lock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
/*-------------------------------*/
/* 2. Load ANA_REG(B/C/D/E) information */
CONFIG2_START:
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR:
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR:
B ANADAT_CHECKSUM2_ERR
/*-------------------------------*/
/* 3. Load ANA_REG10 information */
CONFIG3_START:
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR:
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR:
B ANADAT10_CHECKSUM2_ERR
.size __CHIP_INIT, .-__CHIP_INIT
.endif
.if (__CHIPINITIAL != 0)
.global __CHIP_INIT
.section .chipinit_section.Reset_Handler
.else
.section .text.Reset_Handler
.endif
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.if (__CHIPINITIAL != 0)
/* Chip Initiliazation */
bl __CHIP_INIT
/* System Initiliazation */
bl SystemInit
.endif
/* set stack pointer */
ldr r0, =_estack
mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word PMU_IRQHandler /* 0: PMU */
.word RTC_IRQHandler /* 1: RTC */
.word U32K0_IRQHandler /* 2: U32K0 */
.word U32K1_IRQHandler /* 3: U32K1 */
.word I2C_IRQHandler /* 4: I2C */
.word SPI1_IRQHandler /* 5: SPI1 */
.word UART0_IRQHandler /* 6: UART0 */
.word UART1_IRQHandler /* 7: UART1 */
.word UART2_IRQHandler /* 8: UART2 */
.word UART3_IRQHandler /* 9: UART3 */
.word UART4_IRQHandler /* 10: UART4 */
.word UART5_IRQHandler /* 11: UART5 */
.word ISO78160_IRQHandler /* 12: ISO78160 */
.word ISO78161_IRQHandler /* 13: ISO78161 */
.word TMR0_IRQHandler /* 14: TMR0 */
.word TMR1_IRQHandler /* 15: TMR1 */
.word TMR2_IRQHandler /* 16: TMR2 */
.word TMR3_IRQHandler /* 17: TMR3 */
.word PWM0_IRQHandler /* 18: PWM0 */
.word PWM1_IRQHandler /* 19: PWM1 */
.word PWM2_IRQHandler /* 20: PWM2 */
.word PWM3_IRQHandler /* 21: PWM3 */
.word DMA_IRQHandler /* 22: DMA */
.word FLASH_IRQHandler /* 23: FLASH */
.word ANA_IRQHandler /* 24: ANA */
.word 0 /* 25: Reserved */
.word 0 /* 26: Reserved */
.word SPI2_IRQHandler /* 27: SPI2 */
.word SPI3_IRQHandler /* 28: SPI3 */
.word 0 /* 29: Reserved */
.word 0 /* 30: Reserved */
.word 0 /* 31: Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak PMU_IRQHandler
.thumb_set PMU_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak U32K0_IRQHandler
.thumb_set U32K0_IRQHandler,Default_Handler
.weak U32K1_IRQHandler
.thumb_set U32K1_IRQHandler,Default_Handler
.weak I2C_IRQHandler
.thumb_set I2C_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak ISO78160_IRQHandler
.thumb_set ISO78160_IRQHandler,Default_Handler
.weak ISO78161_IRQHandler
.thumb_set ISO78161_IRQHandler,Default_Handler
.weak TMR0_IRQHandler
.thumb_set TMR0_IRQHandler,Default_Handler
.weak TMR1_IRQHandler
.thumb_set TMR1_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Default_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Default_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Default_Handler
.weak PWM3_IRQHandler
.thumb_set PWM3_IRQHandler,Default_Handler
.weak DMA_IRQHandler
.thumb_set DMA_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak ANA_IRQHandler
.thumb_set ANA_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler

81
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c Normal file
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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "target.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/**
* @brief Setup the microcontroller system
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
uint32_t i,nCount,nValue,nAddress,nChecksum;
nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1;
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4))
{
nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET);
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4))
{
while(1);
}
}
for(i=0; i<nCount; i++)
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+16+i*12))
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+16+i*12))
{
while(1);
}
}
if((nAddress>=0x40014800) && (nAddress<=0x40015000))
{
RTC_WriteRegisters(nAddress, &nValue, 1);
}
else
{
*(__IO uint32_t *)(nAddress) = nValue;
}
}
}
/**
* @brief Initializes registers.
* @param None
* @retval None
*/
void SystemUpdate(void)
{
}
/*********************************** END OF FILE ******************************/

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bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h Normal file
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
path = [
cwd + '/CMSIS/Vango/V85xx/Include',
cwd + '/CMSIS',
cwd + '/VangoV85xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER']
group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/**
******************************************************************************
* @file lib_adc.h
* @author Application Team
* @version V4.6.0
* @date 2019-06-18
* @brief ADC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_H
#define __LIB_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t TrigMode;
uint32_t ConvMode;
uint32_t ClockSource;
uint32_t ClockDivider;
uint32_t Channel;
} ADCInitType;
//TrigMode
#define ADC_TRIGMODE_AUTO 0
#define ADC_TRIGMODE_MANUAL ANA_ADCCTRL_MTRIG
#define IS_ADC_TRIGMODE(__TRIGMODE__) (((__TRIGMODE__) == ADC_TRIGMODE_AUTO) ||\
((__TRIGMODE__) == ADC_TRIGMODE_MANUAL))
//ConvMode
#define ADC_CONVMODE_SINGLECHANNEL 0
#define ADC_CONVMODE_MULTICHANNEL 1
#define IS_ADC_CONVMODE(__CONVMODE__) (((__CONVMODE__) == ADC_CONVMODE_SINGLECHANNEL) ||\
((__CONVMODE__) == ADC_CONVMODE_MULTICHANNEL))
//ClockSource
#define ADC_CLKSRC_RCH 0
#define ADC_CLKSRC_PLLL ANA_ADCCTRL_CLKSEL
#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\
((__CLKSRC__) == ADC_CLKSRC_PLLL))
//TrigSource
#define ADC_TRIGSOURCE_OFF ANA_ADCCTRL_AEN_OFF
#define ADC_TRIGSOURCE_TIM0 ANA_ADCCTRL_AEN_TMR0
#define ADC_TRIGSOURCE_TIM1 ANA_ADCCTRL_AEN_TMR1
#define ADC_TRIGSOURCE_TIM2 ANA_ADCCTRL_AEN_TMR2
#define ADC_TRIGSOURCE_TIM3 ANA_ADCCTRL_AEN_TMR3
#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM0) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM1) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM2) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM3))
//ClockDivider
#define ADC_CLKDIV_1 ANA_ADCCTRL_CLKDIV_1
#define ADC_CLKDIV_2 ANA_ADCCTRL_CLKDIV_2
#define ADC_CLKDIV_3 ANA_ADCCTRL_CLKDIV_3
#define ADC_CLKDIV_4 ANA_ADCCTRL_CLKDIV_4
#define ADC_CLKDIV_5 ANA_ADCCTRL_CLKDIV_5
#define ADC_CLKDIV_6 ANA_ADCCTRL_CLKDIV_6
#define ADC_CLKDIV_7 ANA_ADCCTRL_CLKDIV_7
#define ADC_CLKDIV_8 ANA_ADCCTRL_CLKDIV_8
#define ADC_CLKDIV_9 ANA_ADCCTRL_CLKDIV_9
#define ADC_CLKDIV_10 ANA_ADCCTRL_CLKDIV_10
#define ADC_CLKDIV_11 ANA_ADCCTRL_CLKDIV_11
#define ADC_CLKDIV_12 ANA_ADCCTRL_CLKDIV_12
#define ADC_CLKDIV_13 ANA_ADCCTRL_CLKDIV_13
#define ADC_CLKDIV_14 ANA_ADCCTRL_CLKDIV_14
#define ADC_CLKDIV_15 ANA_ADCCTRL_CLKDIV_15
#define ADC_CLKDIV_16 ANA_ADCCTRL_CLKDIV_16
#define IS_ADC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == ADC_CLKDIV_1) ||\
((__CLKDIV__) == ADC_CLKDIV_2) ||\
((__CLKDIV__) == ADC_CLKDIV_3) ||\
((__CLKDIV__) == ADC_CLKDIV_4) ||\
((__CLKDIV__) == ADC_CLKDIV_5) ||\
((__CLKDIV__) == ADC_CLKDIV_6) ||\
((__CLKDIV__) == ADC_CLKDIV_7) ||\
((__CLKDIV__) == ADC_CLKDIV_8) ||\
((__CLKDIV__) == ADC_CLKDIV_9) ||\
((__CLKDIV__) == ADC_CLKDIV_10) ||\
((__CLKDIV__) == ADC_CLKDIV_11) ||\
((__CLKDIV__) == ADC_CLKDIV_12) ||\
((__CLKDIV__) == ADC_CLKDIV_13) ||\
((__CLKDIV__) == ADC_CLKDIV_14) ||\
((__CLKDIV__) == ADC_CLKDIV_15) ||\
((__CLKDIV__) == ADC_CLKDIV_16))
//Channel
#define ADC_CHANNEL0 0
#define ADC_CHANNEL1 1
#define ADC_CHANNEL2 2
#define ADC_CHANNEL3 3
#define ADC_CHANNEL4 4
#define ADC_CHANNEL5 5
#define ADC_CHANNEL6 6
#define ADC_CHANNEL7 7
#define ADC_CHANNEL8 8
#define ADC_CHANNEL9 9
#define ADC_CHANNEL10 10
#define ADC_CHANNEL11 11
#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL0) ||\
((__CHANNEL__) == ADC_CHANNEL1) ||\
((__CHANNEL__) == ADC_CHANNEL2) ||\
((__CHANNEL__) == ADC_CHANNEL3) ||\
((__CHANNEL__) == ADC_CHANNEL4) ||\
((__CHANNEL__) == ADC_CHANNEL5) ||\
((__CHANNEL__) == ADC_CHANNEL6) ||\
((__CHANNEL__) == ADC_CHANNEL7) ||\
((__CHANNEL__) == ADC_CHANNEL8) ||\
((__CHANNEL__) == ADC_CHANNEL9) ||\
((__CHANNEL__) == ADC_CHANNEL10) ||\
((__CHANNEL__) == ADC_CHANNEL11))
//INTMask
#define ADC_INT_AUTODONE ANA_INTEN_INTEN1
#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0
#define ADC_INT_Msk (ADC_INT_AUTODONE | ADC_INT_MANUALDONE)
#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0U) &&\
(((__INT__) & ~ADC_INT_Msk) == 0U))
//ScaleDown
#define ADC_SCA_NONE 0
#define ADC_SCA_DIV2 ANA_ADCCTRL_CICSCA
#define IS_ADC_SCA(__SCA__) (((__SCA__) == ADC_SCA_NONE) || ((__SCA__) == ADC_SCA_DIV2))
//Skip
#define ADC_SKIP_4 ANA_ADCCTRL_CICSKIP_4
#define ADC_SKIP_5 ANA_ADCCTRL_CICSKIP_5
#define ADC_SKIP_6 ANA_ADCCTRL_CICSKIP_6
#define ADC_SKIP_7 ANA_ADCCTRL_CICSKIP_7
#define ADC_SKIP_0 ANA_ADCCTRL_CICSKIP_0
#define ADC_SKIP_1 ANA_ADCCTRL_CICSKIP_1
#define ADC_SKIP_2 ANA_ADCCTRL_CICSKIP_2
#define ADC_SKIP_3 ANA_ADCCTRL_CICSKIP_3
#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_4) ||\
((__SKIP__) == ADC_SKIP_5) ||\
((__SKIP__) == ADC_SKIP_6) ||\
((__SKIP__) == ADC_SKIP_7) ||\
((__SKIP__) == ADC_SKIP_0) ||\
((__SKIP__) == ADC_SKIP_1) ||\
((__SKIP__) == ADC_SKIP_2) ||\
((__SKIP__) == ADC_SKIP_3))
//DSRSelection
#define ADC_SDRSEL_DIV512 ANA_ADCCTRL_DSRSEL_512
#define ADC_SDRSEL_DIV256 ANA_ADCCTRL_DSRSEL_256
#define ADC_SDRSEL_DIV128 ANA_ADCCTRL_DSRSEL_128
#define ADC_SDRSEL_DIV64 ANA_ADCCTRL_DSRSEL_64
#define IS_ADC_SDR(__SDR__) (((__SDR__) == ADC_SDRSEL_DIV512) ||\
((__SDR__) == ADC_SDRSEL_DIV256) ||\
((__SDR__) == ADC_SDRSEL_DIV128) ||\
((__SDR__) == ADC_SDRSEL_DIV64))
typedef struct
{
float VDDVoltage;
float BATRTCVoltage;
float Temperature;
} ADC_CalResType;
//Division
#define ADC_BAT_CAPDIV (ANA_REG1_GDE4)
#define ADC_BAT_RESDIV (ANA_REG1_RESDIV)
#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\
((__BATDIV__) == ADC_BAT_RESDIV))
/* ADC_GetVoltage */
//Mode
#define ADC_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define ADC_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define ADC_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive
#define ADC_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define ADC_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive
#define ADC_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive
#define ADC_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define ADC_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define ADC_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive
#define ADC_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define ADC_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive
#define ADC_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive
#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_EXTERNAL_NODIV) ||\
((__MODE__) == ADC_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == ADC_3V_EXTERNAL_CAPDIV) ||\
((__MODE__) == ADC_3V_VDD_RESDIV) ||\
((__MODE__) == ADC_3V_VDD_CAPDIV) ||\
((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_3V_BATRTC_CAPDIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_NODIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_CAPDIV) ||\
((__MODE__) == ADC_5V_VDD_RESDIV) ||\
((__MODE__) == ADC_5V_VDD_CAPDIV) ||\
((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_5V_BATRTC_CAPDIV))
/* Exported Functions ------------------------------------------------------- */
/* ADC Exported Functions Group1:
(De)Initialization -------------------------*/
void ADC_DeInit(void);
void ADC_StructInit(ADCInitType* ADC_InitStruct);
void ADC_Init(ADCInitType* ADC_InitStruct);
/* ADC Exported Functions Group2:
Get NVR Info, Calculate datas --------------*/
uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage);
uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetTemperature(ADC_CalResType *CalResults);
/* ADC Exported Functions Group3:
Interrupt (flag) ---------------------------*/
int16_t ADC_GetADCConversionValue(uint32_t Channel);
void ADC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t ADC_GetAutoDoneFlag(void);
uint8_t ADC_GetManualDoneFlag(void);
void ADC_ClearAutoDoneFlag(void);
void ADC_ClearManualDoneFlag(void);
/* ADC Exported Functions Group4:
MISC Configuration -------------------------*/
uint32_t ADC_Cmd(uint32_t NewState);
void ADC_StartManual(void);
void ADC_WaitForManual(void);
void ADC_TrigSourceConfig(uint32_t TrigSource);
void ADC_RESDivisionCmd(uint32_t NewState);
void ADC_CAPDivisionCmd(uint32_t NewState);
//CIC Control
void ADC_CICAlwaysOnCmd(uint32_t NewState);
void ADC_CICINVCmd(uint32_t NewState);
void ADC_CICScaleDownConfig(uint32_t ScaleDown);
void ADC_CICSkipConfig(uint32_t Skip);
void ADC_CICDownSamRateConfig(uint32_t DSRSelection);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc_tiny.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_TINY_H
#define __LIB_ADC_TINY_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SignalSel;
uint32_t ADTREF1;
uint32_t ADTREF2;
uint32_t ADTREF3;
} TADCInitType;
//SelADT
#define ADCTINY_SIGNALSEL_IOE6 0
#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_SELADT
#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
//ADTREF1
#define ADCTINY_REF1_0_9 0
#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL
#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
((__ADTREF1__) == ADCTINY_REF1_0_7))
//ADTREF2
#define ADCTINY_REF2_1_8 0
#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL
#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
((__ADTREF2__) == ADCTINY_REF2_1_6))
//ADTREF3
#define ADCTINY_REF3_2_7 0
#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL
#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
((__ADTREF3__) == ADCTINY_REF3_2_5))
//THSel
#define ADCTINY_THSEL_0 ANA_MISC_TADCTH_0
#define ADCTINY_THSEL_1 ANA_MISC_TADCTH_1
#define ADCTINY_THSEL_2 ANA_MISC_TADCTH_2
#define ADCTINY_THSEL_3 ANA_MISC_TADCTH_3
#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\
((__THSEL__) == ADCTINY_THSEL_1) ||\
((__THSEL__) == ADCTINY_THSEL_2) ||\
((__THSEL__) == ADCTINY_THSEL_3))
/* Exported Functions ------------------------------------------------------- */
void TADC_DeInit(void);
void TADC_StructInit(TADCInitType* TADC_InitStruct);
void TADC_Init(TADCInitType* TADC_InitStruct);
void TADC_Cmd(uint32_t NewState);
uint8_t TADC_GetOutput(void);
void TADC_IntTHConfig(uint32_t THSel);
void TADC_INTConfig(uint32_t NewState);
uint8_t TADC_GetINTStatus(void);
void TADC_ClearINTStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_TINY_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
#ifndef __LIB_ANA_H
#define __LIB_ANA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/***** StatusMask (ANA_GetStatus) *****/
#define ANA_STATUS_AVCCLV ANA_COMPOUT_AVCCLV
#define ANA_STATUS_VDCINDROP ANA_COMPOUT_VDCINDROP
#define ANA_STATUS_VDDALARM ANA_COMPOUT_VDDALARM
#define ANA_STATUS_COMP2 ANA_COMPOUT_COMP2
#define ANA_STATUS_COMP1 ANA_COMPOUT_COMP1
#define ANA_STATUS_LOCKL ANA_COMPOUT_LOCKL
#define ANA_STATUS_LOCKH ANA_COMPOUT_LOCKH
/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/
#define ANA_INT_TADC_OVER ANA_INTSTS_INTSTS13
#define ANA_INT_REGERR ANA_INTSTS_INTSTS12
#define ANA_INT_SME ANA_INTSTS_INTSTS11
#define ANA_INT_AVCCLV ANA_INTSTS_INTSTS10
#define ANA_INT_VDCINDROP ANA_INTSTS_INTSTS8
#define ANA_INT_VDDALARM ANA_INTSTS_INTSTS7
#define ANA_INT_COMP2 ANA_INTSTS_INTSTS3
#define ANA_INT_COMP1 ANA_INTSTS_INTSTS2
#define ANA_INT_ADCA ANA_INTSTS_INTSTS1
#define ANA_INT_ADCM ANA_INTSTS_INTSTS0
#define ANA_INT_Msk (0x3DEFUL)
/* Private macros ------------------------------------------------------------*/
#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\
((__STATUS__) == ANA_STATUS_VDCINDROP) ||\
((__STATUS__) == ANA_STATUS_VDDALARM) ||\
((__STATUS__) == ANA_STATUS_COMP2) ||\
((__STATUS__) == ANA_STATUS_COMP1) ||\
((__STATUS__) == ANA_STATUS_LOCKL) ||\
((__STATUS__) == ANA_STATUS_LOCKH))
#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_TADC_OVER) ||\
((__INTSTSR__) == ANA_INT_REGERR) ||\
((__INTSTSR__) == ANA_INT_SME) ||\
((__INTSTSR__) == ANA_INT_AVCCLV) ||\
((__INTSTSR__) == ANA_INT_VDCINDROP) ||\
((__INTSTSR__) == ANA_INT_VDDALARM) ||\
((__INTSTSR__) == ANA_INT_COMP2) ||\
((__INTSTSR__) == ANA_INT_COMP1) ||\
((__INTSTSR__) == ANA_INT_ADCA) ||\
((__INTSTSR__) == ANA_INT_ADCM))
#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\
(((__INTSTSC__) & ~ANA_INT_Msk) == 0U))
#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__)
/* Exported Functions ------------------------------------------------------- */
uint8_t ANA_GetStatus(uint32_t StatusMask);
uint8_t ANA_GetINTStatus(uint32_t IntMask);
void ANA_ClearINTStatus(uint32_t IntMask);
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ANA_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_clk.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Clock library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CLK_H
#define __LIB_CLK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* PLLL Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLL_ConfTypeDef;
/* PLLH Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLH_ConfTypeDef;
/* RCH Configure */
typedef struct
{
uint32_t State;
} RCH_ConfTypeDef;
/* XTALH Configure */
typedef struct
{
uint32_t State;
} XTALH_ConfTypeDef;
/* RTCCLK Configure */
typedef struct
{
uint32_t Source;
uint32_t Divider;
} RTCCLK_ConfTypeDef;
/* HCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} HCLK_ConfTypeDef;
/* PCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} PCLK_ConfTypeDef;
/* Clock Configure */
typedef struct
{
uint32_t ClockType; /* The clock to be configured */
uint32_t AHBSource;
PLLL_ConfTypeDef PLLL;
PLLH_ConfTypeDef PLLH;
XTALH_ConfTypeDef XTALH;
RTCCLK_ConfTypeDef RTCCLK;
HCLK_ConfTypeDef HCLK;
PCLK_ConfTypeDef PCLK;
} CLK_InitTypeDef;
/***** ClockType *****/
#define CLK_TYPE_Msk (0xFFUL)
#define CLK_TYPE_ALL CLK_TYPE_Msk
#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */
#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */
#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */
#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */
#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */
#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */
#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */
/***** AHBSource *****/
#define CLK_AHBSEL_6_5MRC MISC2_CLKSEL_CLKSEL_RCOH
#define CLK_AHBSEL_6_5MXTAL MISC2_CLKSEL_CLKSEL_XOH
#define CLK_AHBSEL_HSPLL MISC2_CLKSEL_CLKSEL_PLLH
#define CLK_AHBSEL_RTCCLK MISC2_CLKSEL_CLKSEL_RTCCLK
#define CLK_AHBSEL_LSPLL MISC2_CLKSEL_CLKSEL_PLLL
/***** PLLL_ConfTypeDef PLLL *****/
/* PLLL.Source */
#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL
#define CLK_PLLLSRC_XTALL (0)
/* PLLL.State */
#define CLK_PLLL_ON ANA_REG3_PLLLPDN
#define CLK_PLLL_OFF (0)
/* PLLL.Frequency */
#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M
#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M
#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M
#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M
#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K
#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K
#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K
/***** PLLH_ConfTypeDef PLLH *****/
/* PLLH.Source */
#define CLK_PLLHSRC_RCH (0)
#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL
/* PLLH.State */
#define CLK_PLLH_ON ANA_REG3_PLLHPDN
#define CLK_PLLH_OFF (0)
/* PLLH.Frequency */
#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2
#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5
#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3
#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5
#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4
#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5
#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5
#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6
#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5
#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7
#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5
/* XTALH_ConfTypeDef XTALH */
/* XTALH.State */
#define CLK_XTALH_ON ANA_REG3_XOHPDN
#define CLK_XTALH_OFF (0)
/* RTCCLK Configure */
/* RTCCLK.Source */
#define CLK_RTCCLKSRC_XTALL (0)
#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCLK_SEL)
/* RTCCLK.Divider */
#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0)
#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1)
//AHB Periphral
#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA
#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO
#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD
#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT
#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_LCD \
|MISC2_HCLKEN_CRYPT)
//APB Periphral
#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA
#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C
#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1
#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0
#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1
#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2
#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3
#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4
#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5
#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160
#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161
#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER
#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC
#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2
#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU
#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC
#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA
#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0
#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1
#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2
#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160 \
|MISC2_PCLKEN_ISO78161 \
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC \
|MISC2_PCLKEN_MISC2 \
|MISC2_PCLKEN_PMU \
|MISC2_PCLKEN_RTC \
|MISC2_PCLKEN_ANA \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2)
/***** PLLStatus (CLK_GetPLLLockStatus) *****/
#define CLK_STATUS_LOCKL ANA_COMPOUT_LOCKL
#define CLK_STATUS_LOCKH ANA_COMPOUT_LOCKH
/* Private macros ------------------------------------------------------------*/
#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_Msk) != 0UL) &&\
(((__TYPE__) & ~CLK_TYPE_Msk) == 0UL))
#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\
((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\
((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\
((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\
((__AHBSRC__) == CLK_AHBSEL_LSPLL))
#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\
((__PLLLSRC__) == CLK_PLLLSRC_XTALL))
#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\
((__PLLLSTA__) == CLK_PLLL_OFF))
#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_2048MHz))
#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\
((__PLLHSRC__) == CLK_PLLHSRC_XTALH))
#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\
((__PLLHSTA__) == CLK_PLLH_OFF))
#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\
((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\
((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\
((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\
((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\
((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\
((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\
((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\
((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\
((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\
((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\
((__PLLHSRC__) == CLK_PLLH_49_152MHz))
#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\
((__XTALHSTA__) == CLK_XTALH_OFF))
#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\
((__RTCSRC__) == CLK_RTCCLKSRC_RCL))
#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\
((__RTCDIV__) == CLK_RTCCLKDIV_4))
#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\
((__HCLKDIV__) < 257UL))
#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\
((__PCLKDIV__) < 257UL))
#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\
(((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\
(((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_COMPOUT_LOCKL) ||\
((__PLLLOCK__) == ANA_COMPOUT_LOCKH))
/* Exported Functions ------------------------------------------------------- */
/* CLK Exported Functions Group1:
Initialization and functions ---------------*/
void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
/* CLK Exported Functions Group2:
Peripheral Control -------------------------*/
void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
/* CLK Exported Functions Group3:
Get clock/configuration information --------*/
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetPCLKFreq(void);
void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
uint8_t CLK_GetXTALHStatus(void);
uint8_t CLK_GetXTALLStatus(void);
uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CLK_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_comp.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief COMP library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_COMP_H
#define __LIB_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* Macros --------------------------------------------------------------------*/
/***** COMP_DEBConfig *****/
//COMPx
#define COMP_1 (0x00U)
#define COMP_2 (0x02U)
#define IS_COMP(__COMP__) (((__COMP__) == COMP_1) || ((__COMP__) == COMP_2))
//Debounce
#define COMP_DEB_0 ANA_CTRL_CMP1DEB_0
#define COMP_DEB_1 ANA_CTRL_CMP1DEB_1
#define COMP_DEB_2 ANA_CTRL_CMP1DEB_2
#define COMP_DEB_3 ANA_CTRL_CMP1DEB_3
#define IS_COMP_DEB(__DEB__) (((__DEB__) == COMP_DEB_0) ||\
((__DEB__) == COMP_DEB_1) ||\
((__DEB__) == COMP_DEB_2) ||\
((__DEB__) == COMP_DEB_3))
/***** Mode (COMP_ModeConfig) *****/
#define COMP_MODE_OFF ANA_CTRL_COMP1_SEL_0
#define COMP_MODE_RISING ANA_CTRL_COMP1_SEL_1
#define COMP_MODE_FALLING ANA_CTRL_COMP1_SEL_2
#define COMP_MODE_BOTH ANA_CTRL_COMP1_SEL_3
#define IS_COMP_MODE(__MODE__) (((__MODE__) == COMP_MODE_OFF) ||\
((__MODE__) == COMP_MODE_RISING) ||\
((__MODE__) == COMP_MODE_FALLING) ||\
((__MODE__) == COMP_MODE_BOTH))
/***** SourceSelect (COMP_ConfigSignalSource) *****/
#define COMP_SIGNALSRC_P_TO_REF ANA_REG2_CMP1_SEL_0
#define COMP_SIGNALSRC_N_TO_REF ANA_REG2_CMP1_SEL_1
#define COMP_SIGNALSRC_P_TO_N ANA_REG2_CMP1_SEL_2
#define IS_COMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_REF) ||\
((__SIGNALSRC__) == COMP_SIGNALSRC_N_TO_REF) ||\
((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_N))
/***** REFSelect (COMP_ConfigREF) *****/
#define COMP_REF_VREF (0)
#define COMP_REF_BGPREF ANA_REG2_REFSEL_CMP1
#define IS_COMP_REF(__REF__) (((__REF__) == COMP_REF_VREF) ||\
((__REF__) == COMP_REF_BGPREF))
/***** BiasSel (COMP_BiasConfig) *****/
#define COMP_BIAS_20nA ANA_REG5_IT_CMP1_0
#define COMP_BIAS_100nA ANA_REG5_IT_CMP1_1
#define COMP_BIAS_500nA ANA_REG5_IT_CMP1_2
#define IS_COMP_BIAS(__BIAS__) (((__BIAS__) == COMP_BIAS_20nA) ||\
((__BIAS__) == COMP_BIAS_100nA)||\
((__BIAS__) == COMP_BIAS_500nA))
/* Exported Functions ------------------------------------------------------- */
void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce);
void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode);
void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect);
void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect);
void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel);
void COMP_INTConfig(uint32_t COMPx, uint32_t NewState);
uint8_t COMP_GetINTStatus(uint32_t COMPx);
void COMP_ClearINTStatus(uint32_t COMPx);
void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState);
void COMP_Cmd(uint32_t COMPx, uint32_t NewState);
uint32_t COMP_GetCNTValue(uint32_t COMPx);
void COMP_ClearCNTValue(uint32_t COMPx);
uint8_t COMP1_GetOutputLevel(void);
uint8_t COMP2_GetOutputLevel(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_COMP_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_crypt.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief CRYPT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CRYPT_H
#define __LIB_CRYPT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//Length
#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32
#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64
#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96
#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128
#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160
#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192
#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224
#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256
#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288
#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320
#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352
#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384
#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416
#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448
#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480
#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512
//Nostop
#define CRYPT_STOPCPU (0)
#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP
/* Private macros ------------------------------------------------------------*/
#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) < 0x8000) &&\
(((__ADDR__) & 0x3U) == 0U))
#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_64) ||\
((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_96) ||\
((__LENGTH__) == CRYPT_LENGTH_128) ||\
((__LENGTH__) == CRYPT_LENGTH_160) ||\
((__LENGTH__) == CRYPT_LENGTH_192) ||\
((__LENGTH__) == CRYPT_LENGTH_224) ||\
((__LENGTH__) == CRYPT_LENGTH_256) ||\
((__LENGTH__) == CRYPT_LENGTH_288) ||\
((__LENGTH__) == CRYPT_LENGTH_320) ||\
((__LENGTH__) == CRYPT_LENGTH_352) ||\
((__LENGTH__) == CRYPT_LENGTH_384) ||\
((__LENGTH__) == CRYPT_LENGTH_416) ||\
((__LENGTH__) == CRYPT_LENGTH_448) ||\
((__LENGTH__) == CRYPT_LENGTH_480) ||\
((__LENGTH__) == CRYPT_LENGTH_512))
#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU))
/* Exported Functions ------------------------------------------------------- */
void CRYPT_AddressAConfig(uint16_t AddrA);
void CRYPT_AddressBConfig(uint16_t AddrB);
void CRYPT_AddressOConfig(uint16_t AddrO);
uint8_t CRYPT_GetCarryBorrowBit(void);
void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop);
void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop);
void CRYPT_StartSub(uint32_t Length, uint32_t Nostop);
void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop);
void CRYPT_WaitForLastOperation(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CRYPT_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_dma.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief DMA library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_DMA_H
#define __LIB_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//Channel
#define DMA_CHANNEL_0 0
#define DMA_CHANNEL_1 1
#define DMA_CHANNEL_2 2
#define DMA_CHANNEL_3 3
typedef struct
{
uint32_t DestAddr; /* destination address */
uint32_t SrcAddr; /* source address */
uint8_t FrameLen; /* Frame length */
uint8_t PackLen; /* Package length */
uint32_t ContMode; /* Continuous mode */
uint32_t TransMode; /* Transfer mode */
uint32_t ReqSrc; /* DMA request source */
uint32_t DestAddrMode; /* Destination address mode */
uint32_t SrcAddrMode; /* Source address mode */
uint32_t TransSize; /* Transfer size mode */
} DMA_InitType;
//ContMode
#define DMA_CONTMODE_ENABLE DMA_CTL_CONT
#define DMA_CONTMODE_DISABLE 0
//TransMode
#define DMA_TRANSMODE_SINGLE 0
#define DMA_TRANSMODE_PACK DMA_CTL_TMODE
//ReqSrc
#define DMA_REQSRC_SOFT DMA_CTL_DMASEL_SOFT
#define DMA_REQSRC_UART0TX DMA_CTL_DMASEL_UART0TX
#define DMA_REQSRC_UART0RX DMA_CTL_DMASEL_UART0RX
#define DMA_REQSRC_UART1TX DMA_CTL_DMASEL_UART1TX
#define DMA_REQSRC_UART1RX DMA_CTL_DMASEL_UART1RX
#define DMA_REQSRC_UART2TX DMA_CTL_DMASEL_UART2TX
#define DMA_REQSRC_UART2RX DMA_CTL_DMASEL_UART2RX
#define DMA_REQSRC_UART3TX DMA_CTL_DMASEL_UART3TX
#define DMA_REQSRC_UART3RX DMA_CTL_DMASEL_UART3RX
#define DMA_REQSRC_UART4TX DMA_CTL_DMASEL_UART4TX
#define DMA_REQSRC_UART4RX DMA_CTL_DMASEL_UART4RX
#define DMA_REQSRC_UART5TX DMA_CTL_DMASEL_UART5TX
#define DMA_REQSRC_UART5RX DMA_CTL_DMASEL_UART5RX
#define DMA_REQSRC_ISO78160TX DMA_CTL_DMASEL_ISO78160TX
#define DMA_REQSRC_ISO78160RX DMA_CTL_DMASEL_ISO78160RX
#define DMA_REQSRC_ISO78161TX DMA_CTL_DMASEL_ISO78161TX
#define DMA_REQSRC_ISO78161RX DMA_CTL_DMASEL_ISO78161RX
#define DMA_REQSRC_TIMER0 DMA_CTL_DMASEL_TIMER0
#define DMA_REQSRC_TIMER1 DMA_CTL_DMASEL_TIMER1
#define DMA_REQSRC_TIMER2 DMA_CTL_DMASEL_TIMER2
#define DMA_REQSRC_TIMER3 DMA_CTL_DMASEL_TIMER3
#define DMA_REQSRC_SPI1TX DMA_CTL_DMASEL_SPI1TX
#define DMA_REQSRC_SPI1RX DMA_CTL_DMASEL_SPI1RX
#define DMA_REQSRC_U32K0 DMA_CTL_DMASEL_U32K0
#define DMA_REQSRC_U32K1 DMA_CTL_DMASEL_U32K1
#define DMA_REQSRC_CMP1 DMA_CTL_DMASEL_CMP1
#define DMA_REQSRC_CMP2 DMA_CTL_DMASEL_CMP2
#define DMA_REQSRC_SPI2TX DMA_CTL_DMASEL_SPI2TX
#define DMA_REQSRC_SPI2RX DMA_CTL_DMASEL_SPI2RX
//DestAddrMode
#define DMA_DESTADDRMODE_FIX DMA_CxCTL_DMODE_FIX
#define DMA_DESTADDRMODE_PEND DMA_CxCTL_DMODE_PEND
#define DMA_DESTADDRMODE_FEND DMA_CxCTL_DMODE_FEND
//SrcAddrMode
#define DMA_SRCADDRMODE_FIX DMA_CxCTL_SMODE_FIX
#define DMA_SRCADDRMODE_PEND DMA_CxCTL_SMODE_PEND
#define DMA_SRCADDRMODE_FEND DMA_CxCTL_SMODE_FEND
//TransSize
#define DMA_TRANSSIZE_BYTE DMA_CxCTL_SIZE_BYTE
#define DMA_TRANSSIZE_HWORD DMA_CxCTL_SIZE_HWORD
#define DMA_TRANSSIZE_WORD DMA_CxCTL_SIZE_WORD
typedef struct
{
uint32_t Mode; /* AES mode */
uint32_t Direction; /* Direction */
uint32_t *KeyStr; /* AES key */
} DMA_AESInitType;
//AES MODE
#define DMA_AESMODE_128 DMA_AESCTL_MODE_AES128
#define DMA_AESMODE_192 DMA_AESCTL_MODE_AES192
#define DMA_AESMODE_256 DMA_AESCTL_MODE_AES256
//AES Direction
#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC
#define DMA_AESDIRECTION_DECODE 0
//INT
#define DMA_INT_C3DA DMA_IE_C3DAIE
#define DMA_INT_C2DA DMA_IE_C2DAIE
#define DMA_INT_C1DA DMA_IE_C1DAIE
#define DMA_INT_C0DA DMA_IE_C0DAIE
#define DMA_INT_C3FE DMA_IE_C3FEIE
#define DMA_INT_C2FE DMA_IE_C2FEIE
#define DMA_INT_C1FE DMA_IE_C1FEIE
#define DMA_INT_C0FE DMA_IE_C0FEIE
#define DMA_INT_C3PE DMA_IE_C3PEIE
#define DMA_INT_C2PE DMA_IE_C2PEIE
#define DMA_INT_C1PE DMA_IE_C1PEIE
#define DMA_INT_C0PE DMA_IE_C0PEIE
#define DMA_INT_Msk (0xFFFUL)
//INTSTS
#define DMA_INTSTS_C3DA DMA_STS_C3DA
#define DMA_INTSTS_C2DA DMA_STS_C2DA
#define DMA_INTSTS_C1DA DMA_STS_C1DA
#define DMA_INTSTS_C0DA DMA_STS_C0DA
#define DMA_INTSTS_C3FE DMA_STS_C3FE
#define DMA_INTSTS_C2FE DMA_STS_C2FE
#define DMA_INTSTS_C1FE DMA_STS_C1FE
#define DMA_INTSTS_C0FE DMA_STS_C0FE
#define DMA_INTSTS_C3PE DMA_STS_C3PE
#define DMA_INTSTS_C2PE DMA_STS_C2PE
#define DMA_INTSTS_C1PE DMA_STS_C1PE
#define DMA_INTSTS_C0PE DMA_STS_C0PE
#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY
#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY
#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY
#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY
#define DMA_INTSTS_Msk (0xFFF0UL)
/* Private macros ------------------------------------------------------------*/
#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\
((__CH__) == DMA_CHANNEL_1) ||\
((__CH__) == DMA_CHANNEL_2) ||\
((__CH__) == DMA_CHANNEL_3))
#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U)
#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U)
#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\
((__CONTMOD__) == DMA_CONTMODE_DISABLE))
#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\
((__TRANSMOD__) == DMA_TRANSMODE_PACK))
#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\
((__REQSRC__) == DMA_REQSRC_UART0TX) ||\
((__REQSRC__) == DMA_REQSRC_UART0RX) ||\
((__REQSRC__) == DMA_REQSRC_UART1TX) ||\
((__REQSRC__) == DMA_REQSRC_UART1RX) ||\
((__REQSRC__) == DMA_REQSRC_UART2TX) ||\
((__REQSRC__) == DMA_REQSRC_UART2RX) ||\
((__REQSRC__) == DMA_REQSRC_UART3TX) ||\
((__REQSRC__) == DMA_REQSRC_UART3RX) ||\
((__REQSRC__) == DMA_REQSRC_UART4TX) ||\
((__REQSRC__) == DMA_REQSRC_UART4RX) ||\
((__REQSRC__) == DMA_REQSRC_UART5TX) ||\
((__REQSRC__) == DMA_REQSRC_UART5RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\
((__REQSRC__) == DMA_REQSRC_TIMER0) ||\
((__REQSRC__) == DMA_REQSRC_TIMER1) ||\
((__REQSRC__) == DMA_REQSRC_TIMER2) ||\
((__REQSRC__) == DMA_REQSRC_TIMER3) ||\
((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\
((__REQSRC__) == DMA_REQSRC_U32K0) ||\
((__REQSRC__) == DMA_REQSRC_U32K1) ||\
((__REQSRC__) == DMA_REQSRC_CMP1) ||\
((__REQSRC__) == DMA_REQSRC_CMP2) ||\
((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI2RX))
#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\
((__DAM__) == DMA_DESTADDRMODE_PEND) ||\
((__DAM__) == DMA_DESTADDRMODE_FEND))
#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\
((__SAM__) == DMA_SRCADDRMODE_PEND) ||\
((__SAM__) == DMA_SRCADDRMODE_FEND))
#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\
((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\
((__TSIZE__) == DMA_TRANSSIZE_WORD))
#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\
((__AESMOD__) == DMA_AESMODE_192) ||\
((__AESMOD__) == DMA_AESMODE_256))
#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\
((__AESDIR__) == DMA_AESDIRECTION_DECODE))
#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\
(((__INT__) & ~DMA_INT_Msk) == 0U))
#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C0BUSY))
#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
/* DMA Exported Functions Group1:
(De)Initialization ------------------------*/
void DMA_DeInit(uint32_t Channel);
void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel);
void DMA_AESDeInit(void);
void DMA_AESInit(DMA_AESInitType *InitStruct);
/* DMA Exported Functions Group2:
Interrupt (flag) --------------------------*/
void DMA_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t DMA_GetINTStatus(uint32_t INTMask);
void DMA_ClearINTStatus(uint32_t INTMask);
/* DMA Exported Functions Group3:
MISC Configuration ------------------------*/
void DMA_Cmd(uint32_t Channel, uint32_t NewState);
void DMA_AESCmd(uint32_t NewState);
void DMA_StopTransmit(uint32_t Channel, uint32_t NewState);
uint8_t DMA_GetFrameLenTransferred(uint32_t Channel);
uint8_t DMA_GetPackLenTransferred(uint32_t Channel);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_DMA_H */
/*********************************** END OF FILE ******************************/

74
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/**
******************************************************************************
* @file lib_flash.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief FLASH library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_FLASH_H
#define __LIB_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//CSMode
#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE
#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON
#define FLASH_CSMODE_TIM2OF FLASH_CTRL_CSMODE_TIM2OV
#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC
#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\
((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\
((__CSMODE__) == FLASH_CSMODE_TIM2OF) ||\
((__CSMODE__) == FLASH_CSMODE_RTC))
//INT
#define FLASH_INT_CS FLASH_CTRL_CSINTEN
#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS)
//WriteStatus
#define FLASH_WSTA_BUSY 0
#define FLASH_WRITE_FINISH 1
#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH
#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x40000UL)
#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x40000UL) &&\
(((__ADDRW__) & 0x3U) == 0U))
#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x40000UL) &&\
(((__ADDRHW__) & 0x1U) == 0U))
#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x40000) && ((__ADDRESS2__) < 0x40000) && ((__ADDRESS1__) < (__ADDRESS2__)))
/* Exported Functions ------------------------------------------------------- */
void FLASH_Init(uint32_t CSMode);
void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState);
void FLASH_CycleInit(void);
void FLASH_SectorErase(uint32_t SectorAddr);
void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length);
void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length);
void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length);
uint32_t FLASH_GetWriteStatus(void);
void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd);
void FLASH_SetCheckSumCompValue(uint32_t Checksum);
uint32_t FLASH_GetCheckSum(void);
uint8_t FLASH_GetINTStatus(uint32_t IntMask);
void FLASH_ClearINTStatus(uint32_t IntMask);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_FLASH_H */
/*********************************** END OF FILE ******************************/

175
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/**
******************************************************************************
* @file lib_gpio.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief GPIO library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_GPIO_H
#define __LIB_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t GPIO_Pin;
uint32_t GPIO_Mode;
} GPIO_InitType;
/**
* @brief Bit_State_enumeration
*/
typedef enum {
Bit_RESET = 0,
Bit_SET
} BitState;
//GPIO_Pin
#define GPIO_Pin_0 ((uint16_t)0x0001)
#define GPIO_Pin_1 ((uint16_t)0x0002)
#define GPIO_Pin_2 ((uint16_t)0x0004)
#define GPIO_Pin_3 ((uint16_t)0x0008)
#define GPIO_Pin_4 ((uint16_t)0x0010)
#define GPIO_Pin_5 ((uint16_t)0x0020)
#define GPIO_Pin_6 ((uint16_t)0x0040)
#define GPIO_Pin_7 ((uint16_t)0x0080)
#define GPIO_Pin_8 ((uint16_t)0x0100)
#define GPIO_Pin_9 ((uint16_t)0x0200)
#define GPIO_Pin_10 ((uint16_t)0x0400)
#define GPIO_Pin_11 ((uint16_t)0x0800)
#define GPIO_Pin_12 ((uint16_t)0x1000)
#define GPIO_Pin_13 ((uint16_t)0x2000)
#define GPIO_Pin_14 ((uint16_t)0x4000)
#define GPIO_Pin_15 ((uint16_t)0x8000)
#define GPIO_Pin_All ((uint16_t)0xFFFF)
//GPIO_Mode
#define GPIO_Mode_INPUT (0xCU)
#define GPIO_Mode_OUTPUT_CMOS (0x2U)
#define GPIO_Mode_OUTPUT_OD (0x3U)
#define GPIO_Mode_INOUT_OD (0xBU)
#define GPIO_Mode_INOUT_CMOS (0xAU)
#define GPIO_Mode_FORBIDDEN (0x4U)
//GPIO AF
#define GPIOB_AF_PLLHDIV IOB_SEL_SEL1
#define GPIOB_AF_OSC IOB_SEL_SEL6
#define GPIOB_AF_PLLLOUT IOB_SEL_SEL2
#define GPIOE_AF_CMP1O IOE_SEL_SEL7
//PMUIO AF
#define PMUIO7_AF_PLLDIV PMU_IOASEL_SEL7
#define PMUIO_AF_CMP2O PMU_IOASEL_SEL6
#define PMUIO3_AF_PLLDIV PMU_IOASEL_SEL3
#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO_AF_CMP2O | PMUIO3_AF_PLLDIV)
//GPIO pin remap
#define GPIO_REMAP_I2C IO_MISC_I2CIOC
//PLLDIV
#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1
#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2
#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4
#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8
#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16
/* Private macros ------------------------------------------------------------*/
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\
(((__PIN__) & ~GPIO_Pin_All) == 0UL))
#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\
((__PINR__) == GPIO_Pin_1) ||\
((__PINR__) == GPIO_Pin_2) ||\
((__PINR__) == GPIO_Pin_3) ||\
((__PINR__) == GPIO_Pin_4) ||\
((__PINR__) == GPIO_Pin_5) ||\
((__PINR__) == GPIO_Pin_6) ||\
((__PINR__) == GPIO_Pin_7) ||\
((__PINR__) == GPIO_Pin_8) ||\
((__PINR__) == GPIO_Pin_9) ||\
((__PINR__) == GPIO_Pin_10) ||\
((__PINR__) == GPIO_Pin_11) ||\
((__PINR__) == GPIO_Pin_12) ||\
((__PINR__) == GPIO_Pin_13) ||\
((__PINR__) == GPIO_Pin_14) ||\
((__PINR__) == GPIO_Pin_15))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_INPUT) ||\
((__MODE__) == GPIO_Mode_OUTPUT_CMOS) ||\
((__MODE__) == GPIO_Mode_OUTPUT_OD) ||\
((__MODE__) == GPIO_Mode_INOUT_OD) ||\
((__MODE__) == GPIO_Mode_INOUT_CMOS) ||\
((__MODE__) == GPIO_Mode_FORBIDDEN))
#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U))
#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
((__GPIOAF__) == GPIOB_AF_OSC) ||\
((__GPIOAF__) == GPIOE_AF_CMP1O) ||\
((__GPIOAF__) == GPIOB_AF_PLLLOUT))
#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\
(((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U))
#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
((__PLLDIV__) == GPIO_PLLDIV_2) ||\
((__PLLDIV__) == GPIO_PLLDIV_4) ||\
((__PLLDIV__) == GPIO_PLLDIV_8) ||\
((__PLLDIV__) == GPIO_PLLDIV_16))
/* Exported Functions ------------------------------------------------------- */
/* GPIO Exported Functions Group1:
Initialization and functions --------------*/
void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct);
void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct);
/* GPIO Exported Functions Group2:
Read input data ---------------------------*/
uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx);
uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx);
/* GPIO Exported Functions Group3:
Read output data --------------------------*/
uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx);
uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx);
/* GPIO Exported Functions Group4:
Write output data -------------------------*/
void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val);
void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val);
/* GPIO Exported Functions Group5:
IO AF configure ---------------------------*/
void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState);
void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState);
/* GPIO Exported Functions Group6:
IO Remap configure ------------------------*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState);
/* GPIO Exported Functions Group7:
Others ------------------------------------*/
void GPIO_PLLDIV_Config(uint32_t Divider);
void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_GPIO_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_i2c.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief IIC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_I2C_H
#define __LIB_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SlaveAddr;
uint32_t GeneralCallAck;
uint32_t AssertAcknowledge;
uint32_t ClockSource;
} I2C_InitType;
//GeneralCallAck
#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC
#define I2C_GENERALCALLACK_DISABLE 0
//AssertAcknowledge
#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA
#define I2C_ASSERTACKNOWLEDGE_DISABLE 0
//ClockSource
#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0
#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1
#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2
#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3
#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4
#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5
#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6
#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7
typedef struct
{
uint16_t SlaveAddr;
uint8_t SubAddrType;
uint32_t PageRange;
uint32_t SubAddress;
uint8_t *pBuffer;
uint32_t Length;
} I2C_WRType;
//SubAddrType
#define I2C_SUBADDR_1BYTE 1
#define I2C_SUBADDR_2BYTE 2
#define I2C_SUBADDR_OTHER 3
//remap
#define I2C_REMAP_ENABLE 1
#define I2C_REMAP_DISABLE 0
/* Private macros ------------------------------------------------------------*/
#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\
((__GC__) == I2C_GENERALCALLACK_DISABLE))
#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\
((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE))
#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8))
#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\
((__TYPE__) == I2C_SUBADDR_2BYTE) ||\
((__TYPE__) == I2C_SUBADDR_OTHER))
/* Exported Functions ------------------------------------------------------- */
/* I2C Exported Functions Group1:
(De)Initialization ------------------------*/
void I2C_DeInit(uint32_t remap);
void I2C_StructInit(I2C_InitType *InitStruct);
void I2C_Init(I2C_InitType *InitStruct);
/* I2C Exported Functions Group2:
Interrupt ---------------------------------*/
void I2C_INTConfig(uint32_t NewState);
uint8_t I2C_GetINTStatus(void);
void I2C_ClearINTStatus(void);
/* I2C Exported Functions Group3:
Transfer datas ----------------------------*/
uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct);
uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct);
/* I2C Exported Functions Group4:
MISC Configuration ------------------------*/
void I2C_Cmd(uint32_t NewState);
/* I2C Exported Functions Group5:
Others ------------------------------------*/
void I2C_AssertAcknowledgeConfig(uint32_t NewState);
uint8_t I2C_ReceiveData(void);
void I2C_SendData(uint8_t Dat);
void I2C_GenerateSTART(uint32_t NewState);
void I2C_GenerateSTOP(uint32_t NewState);
uint8_t I2C_GetStatusCode(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_I2C_H */
/*********************************** END OF FILE ******************************/

104
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/**
******************************************************************************
* @file lib_iso7816.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ISO7816 library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ISO7816_H
#define __LIB_ISO7816_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t FirstBit;
uint32_t ACKLen;
uint32_t Parity;
uint32_t Baudrate;
} ISO7816_InitType;
//FirstBit
#define ISO7816_FIRSTBIT_LSB ISO7816_INFO_LSB
#define ISO7816_FIRSTBIT_MSB 0
#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB) ||\
((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB))
//ACKLen
#define ISO7816_ACKLEN_1 0
#define ISO7816_ACKLEN_2 ISO7816_CFG_ACKLEN
#define IS_ISO7816_ACKLEN(__ACKLEN__) (((__ACKLEN__) == ISO7816_ACKLEN_1) ||\
((__ACKLEN__) == ISO7816_ACKLEN_2))
//Parity
#define ISO7816_PARITY_EVEN 0
#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP
#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) || ((__PARITY__) == ISO7816_PARITY_ODD))
#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) > 299UL)
#define IS_ISO7816_PRESCALER(__PRESCALER__) (((__PRESCALER__) <= 0x80) && ((__PRESCALER__) > 0U))
//interrupt
#define ISO7816_INT_RXOV ISO7816_CFG_OVIE
#define ISO7816_INT_TX ISO7816_CFG_SDIE
#define ISO7816_INT_RX ISO7816_CFG_RCIE
#define ISO7816_INT_Msk (ISO7816_INT_RXOV \
|ISO7816_INT_TX \
|ISO7816_INT_RX)
#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\
(((__INT__) & ~ISO7816_INT_Msk) == 0U))
//INTStatus
#define ISO7816_INTSTS_RXOV ISO7816_INFO_OVIF
#define ISO7816_INTSTS_TX ISO7816_INFO_SDIF
#define ISO7816_INTSTS_RX ISO7816_INFO_RCIF
#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_RXOV \
|ISO7816_INTSTS_TX \
|ISO7816_INTSTS_RX)
#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\
((__INTFLAG__) == ISO7816_INTSTS_TX) ||\
((__INTFLAG__) == ISO7816_INTSTS_RX))
#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\
(((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U))
//status
#define ISO7816_FLAG_SDERR ISO7816_INFO_SDERR
#define ISO7816_FLAG_RCERR ISO7816_INFO_RCERR
#define ISO7816_FLAG_Msk (ISO7816_FLAG_SDERR|ISO7816_FLAG_RCERR)
#define IS_ISO7816_FLAGR(__FLAG__) (((__FLAG__) == ISO7816_FLAG_SDERR) || ((__FLAG__) == ISO7816_FLAG_RCERR))
#define IS_ISO7816_FLAGC(__FLAG__) ((((__FLAG__) & ISO7816_FLAG_Msk) != 0U) &&\
(((__FLAG__) & (~ISO7816_FLAG_Msk)) == 0U))
/* Exported Functions ------------------------------------------------------- */
void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x);
void ISO7816_StructInit(ISO7816_InitType *InitStruct);
void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct);
void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState);
void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate);
void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler);
void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState);
void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch);
uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x);
void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState);
uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask);
void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask);
uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask);
void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask);
uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x);
uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ISO7816_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_lcd.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief LCD library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LCD_H
#define __LIB_LCD_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* LCD SEGx IO typedef */
typedef struct
{
__IO uint32_t *GPIO;
uint16_t Pin;
}LCD_SEGIO;
/* LCD COMx IO typedef */
typedef struct
{
__IO uint32_t *GPIO;
uint16_t Pin;
}LCD_COMIO;
typedef struct
{
uint32_t Type;
uint32_t Drv;
uint32_t FRQ;
uint32_t SWPR;
uint32_t FBMODE;
uint32_t BKFILL;
} LCD_InitType;
//Type
#define LCD_TYPE_4COM LCD_CTRL_TYPE_4COM
#define LCD_TYPE_6COM LCD_CTRL_TYPE_6COM
#define LCD_TYPE_8COM LCD_CTRL_TYPE_8COM
//DrivingRes
#define LCD_DRV_300 LCD_CTRL_DRV_300KOHM
#define LCD_DRV_600 LCD_CTRL_DRV_600KOHM
#define LCD_DRV_150 LCD_CTRL_DRV_150KOHM
#define LCD_DRV_200 LCD_CTRL_DRV_200KOHM
//ScanFRQ
#define LCD_FRQ_64H LCD_CTRL_FRQ_64HZ
#define LCD_FRQ_128H LCD_CTRL_FRQ_128HZ
#define LCD_FRQ_256H LCD_CTRL_FRQ_256HZ
#define LCD_FRQ_512H LCD_CTRL_FRQ_512HZ
//SwitchMode
#define LCD_FBMODE_BUFA LCD_CTRL2_FBMODE_BUFA
#define LCD_FBMODE_BUFAB LCD_CTRL2_FBMODE_BUFAANDBUFB
#define LCD_FBMODE_BUFABLANK LCD_CTRL2_FBMODE_BUFAANDBLANK
//BlankFill
#define LCD_BKFILL_1 LCD_CTRL2_BKFILL
#define LCD_BKFILL_0 0
//ComMode
#define LCD_COMMOD_4COM 1
#define LCD_COMMOD_6COM 3
#define LCD_COMMOD_8COM 7
//BiasSelection
#define LCD_BMODE_DIV3 0
#define LCD_BMODE_DIV4 ANA_REG6_LCD_BMODE
//VLCDSelection
#define LCD_VLCD_0 0
#define LCD_VLCD_INC60MV 1
#define LCD_VLCD_INC120MV 2
#define LCD_VLCD_INC180MV 3
#define LCD_VLCD_INC240MV 4
#define LCD_VLCD_INC300MV 5
#define LCD_VLCD_DEC60MV 6
#define LCD_VLCD_DEC120MV 7
#define LCD_VLCD_DEC180MV 8
#define LCD_VLCD_DEC240MV 9
#define LCD_VLCD_DEC300MV 10
#define LCD_VLCD_DEC360MV 11
#define LCD_VLCD_DEC420MV 12
#define LCD_VLCD_DEC480MV 13
#define LCD_VLCD_DEC540MV 14
#define LCD_VLCD_DEC600MV 15
/* Private macros ------------------------------------------------------------*/
#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\
((__TYPE__) == LCD_TYPE_6COM) ||\
((__TYPE__) == LCD_TYPE_8COM))
#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\
((__DRV__) == LCD_DRV_600) ||\
((__DRV__) == LCD_DRV_150) ||\
((__DRV__) == LCD_DRV_200))
#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\
((__FRQ__) == LCD_FRQ_128H) ||\
((__FRQ__) == LCD_FRQ_256H) ||\
((__FRQ__) == LCD_FRQ_512H))
#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL)
#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\
((__FBMODE__) == LCD_FBMODE_BUFAB) ||\
((__FBMODE__) == LCD_FBMODE_BUFABLANK))
#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0))
#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\
((__BMODE__) == LCD_BMODE_DIV4))
#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\
((__COMMOD__) == LCD_COMMOD_6COM) ||\
((__COMMOD__) == LCD_COMMOD_8COM))
#define IS_LCD_VLCD(__VLCD__) (((__VLCD__) == LCD_VLCD_0) ||\
((__VLCD__) == LCD_VLCD_INC60MV) ||\
((__VLCD__) == LCD_VLCD_INC120MV) ||\
((__VLCD__) == LCD_VLCD_INC180MV) ||\
((__VLCD__) == LCD_VLCD_INC240MV) ||\
((__VLCD__) == LCD_VLCD_INC300MV) ||\
((__VLCD__) == LCD_VLCD_DEC60MV) ||\
((__VLCD__) == LCD_VLCD_DEC120MV) ||\
((__VLCD__) == LCD_VLCD_DEC180MV) ||\
((__VLCD__) == LCD_VLCD_DEC240MV) ||\
((__VLCD__) == LCD_VLCD_DEC300MV) ||\
((__VLCD__) == LCD_VLCD_DEC360MV) ||\
((__VLCD__) == LCD_VLCD_DEC420MV) ||\
((__VLCD__) == LCD_VLCD_DEC480MV) ||\
((__VLCD__) == LCD_VLCD_DEC540MV) ||\
((__VLCD__) == LCD_VLCD_DEC600MV))
/* Exported Functions ------------------------------------------------------- */
/* LCD Exported Functions Group1:
(De)Initialization -------------------------*/
void LCD_DeInit(void);
void LCD_StructInit(LCD_InitType *LCD_InitStruct);
void LCD_Init(LCD_InitType *InitStruct);
/* LCD Exported Functions Group1:
MISC Configuration -------------------------*/
void LCD_Cmd(uint32_t NewState);
void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState);
void LCD_SetSEG(uint32_t SegCtrl0, uint32_t SegCtrl1, uint16_t SegCtrl2);
void LCD_BiasModeConfig(uint32_t BiasSelection);
uint32_t LCD_VoltageConfig(uint32_t VLCDSelection);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LCD_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_misc.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief MISC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_MISC_H
#define __LIB_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//FlagMask
#define MISC_FLAG_LOCKUP MISC_SRAMINT_LOCKUP
#define MISC_FLAG_PIAC MISC_SRAMINT_PIAC
#define MISC_FLAG_HIAC MISC_SRAMINT_HIAC
#define MISC_FLAG_PERR MISC_SRAMINT_PERR
#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR)
//MISC interrupt
#define MISC_INT_LOCK MISC_SRAMINIT_LOCKIE
#define MISC_INT_PIAC MISC_SRAMINIT_PIACIE
#define MISC_INT_HIAC MISC_SRAMINIT_HIACIE
#define MISC_INT_PERR MISC_SRAMINIT_PERRIE
#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR)
//IR
#define MISC_IREN_TX0 MISC_IREN_UART0
#define MISC_IREN_TX1 MISC_IREN_UART1
#define MISC_IREN_TX2 MISC_IREN_UART2
#define MISC_IREN_TX3 MISC_IREN_UART3
#define MISC_IREN_TX4 MISC_IREN_UART4
#define MISC_IREN_TX5 MISC_IREN_UART5
#define MISC_IREN_Msk (0x3FUL)
/* Private macros ------------------------------------------------------------*/
#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\
((__FLAGR__) == MISC_FLAG_PIAC) ||\
((__FLAGR__) == MISC_FLAG_HIAC) ||\
((__FLAGR__) == MISC_FLAG_PERR))
#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\
(((__FLAGC__) & ~MISC_FLAG_Msk) == 0U))
#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\
(((__INT__) &~MISC_INT_Msk) == 0U))
#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\
(((__IREN__) & ~MISC_IREN_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
uint8_t MISC_GetFlag(uint32_t FlagMask);
void MISC_ClearFlag(uint32_t FlagMask);
void MISC_INTConfig(uint32_t INTMask, uint32_t NewState);
void MISC_SRAMParityCmd(uint32_t NewState);
uint32_t MISC_GetSRAMPEAddr(void);
uint32_t MISC_GetAPBErrAddr(void);
uint32_t MISC_GetAHBErrAddr(void);
void MISC_IRCmd(uint32_t IRx, uint32_t NewState);
void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow);
void MISC_HardFaultCmd(uint32_t NewState);
void MISC_LockResetCmd(uint32_t NewState);
void MISC_IRQLATConfig(uint8_t Latency);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_MISC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pmu.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief PMU library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PMU_H
#define __LIB_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/**
* Deep-sleep low-power configuration
*/
typedef struct
{
uint32_t COMP1Power; /* Comparator 1 power control */
uint32_t COMP2Power; /* Comparator 2 power control */
uint32_t TADCPower; /* Tiny ADC power control */
uint32_t BGPPower; /* BGP power control */
uint32_t AVCCPower; /* AVCC power control */
uint32_t LCDPower; /* LCD controller power control */
uint32_t VDCINDetector; /* VDCIN detector control */
uint32_t VDDDetector; /* VDD detector control */
uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */
uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */
} PMU_LowPWRTypeDef;
/* COMP1Power */
#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN)
#define PMU_COMP1PWR_OFF (0)
#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\
((__COMP1PWR__) == PMU_COMP1PWR_OFF))
/* COMP2Power */
#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN)
#define PMU_COMP2PWR_OFF (0)
#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\
((__COMP2PWR__) == PMU_COMP2PWR_OFF))
/* TADCPower */
#define PMU_TADCPWR_ON (ANA_REGF_PDNADT)
#define PMU_TADCPWR_OFF (0)
#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\
((__TADCPWR__) == PMU_TADCPWR_OFF))
/* BGPPower */
#define PMU_BGPPWR_ON (0)
#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD)
#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\
((__BGPPWR__) == PMU_BGPPWR_OFF))
/* AVCCPower */
#define PMU_AVCCPWR_ON (0)
#define PMU_AVCCPWR_OFF (ANA_REG8_PD_AVCCLDO)
#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\
((__AVCCPWR__) == PMU_AVCCPWR_OFF))
/* LCDPower */
#define PMU_LCDPWER_ON (LCD_CTRL_EN)
#define PMU_LCDPWER_OFF (0)
#define IS_PMU_LCDPWER(__LCDPWER__) (((__LCDPWER__) == PMU_LCDPWER_ON) ||\
((__LCDPWER__) == PMU_LCDPWER_OFF))
/* VDCINDetector */
#define PMU_VDCINDET_ENABLE (0)
#define PMU_VDCINDET_DISABLE (ANA_REGA_PD_VDCINDET)
#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\
((__VDCINDET__) == PMU_VDCINDET_DISABLE))
/* VDDDetector */
#define PMU_VDDDET_ENABLE (0)
#define PMU_VDDDET_DISABLE (ANA_REG9_PDDET)
#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\
((__VDDDET__) == PMU_VDDDET_DISABLE))
/* APBPeriphralDisable */
#define PMU_APB_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160\
|MISC2_PCLKEN_ISO78161\
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2)
#define PMU_APB_DMA MISC2_PCLKEN_DMA
#define PMU_APB_I2C MISC2_PCLKEN_I2C
#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1
#define PMU_APB_UART0 MISC2_PCLKEN_UART0
#define PMU_APB_UART1 MISC2_PCLKEN_UART1
#define PMU_APB_UART2 MISC2_PCLKEN_UART2
#define PMU_APB_UART3 MISC2_PCLKEN_UART3
#define PMU_APB_UART4 MISC2_PCLKEN_UART4
#define PMU_APB_UART5 MISC2_PCLKEN_UART5
#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160
#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161
#define PMU_APB_TIMER MISC2_PCLKEN_TIMER
#define PMU_APB_MISC MISC2_PCLKEN_MISC
#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0
#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1
#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2
/* AHBPeriphralDisable */
#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_LCD \
|MISC2_HCLKEN_CRYPT)
#define PMU_AHB_DMA MISC2_HCLKEN_DMA
#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO
#define PMU_AHB_LCD MISC2_HCLKEN_LCD
#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT
//PMU interrupt
#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN
#define PMU_INT_32K PMU_CONTROL_INT_32K_EN
#define PMU_INT_6M PMU_CONTROL_INT_6M_EN
#define PMU_INT_Msk (PMU_INT_IOAEN \
|PMU_INT_32K \
|PMU_INT_6M)
#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0U) &&\
(((__INT__)&(~PMU_INT_Msk)) == 0U))
//INTStatus
#define PMU_INTSTS_32K PMU_STS_INT_32K
#define PMU_INTSTS_6M PMU_STS_INT_6M
#define PMU_INTSTS_EXTRST PMU_STS_EXTRST
#define PMU_INTSTS_PORST PMU_STS_PORST
#define PMU_INTSTS_DPORST PMU_STS_DPORST
#define PMU_INTSTS_Msk (PMU_INTSTS_32K \
|PMU_INTSTS_6M \
|PMU_INTSTS_EXTRST \
|PMU_INTSTS_PORST \
|PMU_INTSTS_DPORST)
#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\
((__INTFLAG__) == PMU_INTSTS_6M) ||\
((__INTFLAG__) == PMU_INTSTS_EXTRST) ||\
((__INTFLAG__) == PMU_INTSTS_PORST) ||\
((__INTFLAG__) == PMU_INTSTS_DPORST))
#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0U) &&\
(((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0U))
//Status
#define PMU_STS_32K PMU_STS_EXIST_32K
#define PMU_STS_6M PMU_STS_EXIST_6M
#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M))
//Wakeup_Event
#define IOA_DISABLE (0)
#define IOA_RISING (1)
#define IOA_FALLING (2)
#define IOA_HIGH (3)
#define IOA_LOW (4)
#define IOA_EDGEBOTH (5)
#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\
((__WAKEUP__) == IOA_RISING) ||\
((__WAKEUP__) == IOA_FALLING) ||\
((__WAKEUP__) == IOA_HIGH) ||\
((__WAKEUP__) == IOA_LOW) ||\
((__WAKEUP__) == IOA_EDGEBOTH))
/***** Wakeup_Event (PMU_SleepWKUSRC_Config_RTC) *****/
#define PMU_RTCEVT_ACDONE RTC_INTSTS_INTSTS7
#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6
#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5
#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4
#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3
#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2
#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1
#define PMU_RTCEVT_Msk (PMU_RTCEVT_ACDONE \
|PMU_RTCEVT_WKUCNT \
|PMU_RTCEVT_MIDNIGHT \
|PMU_RTCEVT_WKUHOUR \
|PMU_RTCEVT_WKUMIN \
|PMU_RTCEVT_WKUSEC \
|PMU_RTCEVT_TIMEILLE)
#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0U) &&\
(((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0U))
/***** BATDisc (PMU_BATDischargeConfig) *****/
#define PMU_BATRTC_DISC ANA_REG6_BATRTCDISC
#define IS_PMU_BATRTCDISC(__BATRTCDISC__) ((__BATRTCDISC__) == PMU_BATRTC_DISC)
/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/
#define PMU_PWTH_4_5 ANA_REG8_VDDPVDSEL_0
#define PMU_PWTH_4_2 ANA_REG8_VDDPVDSEL_1
#define PMU_PWTH_3_9 ANA_REG8_VDDPVDSEL_2
#define PMU_PWTH_3_6 ANA_REG8_VDDPVDSEL_3
#define PMU_PWTH_3_2 ANA_REG8_VDDPVDSEL_4
#define PMU_PWTH_2_9 ANA_REG8_VDDPVDSEL_5
#define PMU_PWTH_2_6 ANA_REG8_VDDPVDSEL_6
#define PMU_PWTH_2_3 ANA_REG8_VDDPVDSEL_7
#define IS_PMU_PWTH(__PWTH__) (((__PWTH__) == PMU_PWTH_4_5) ||\
((__PWTH__) == PMU_PWTH_4_2) ||\
((__PWTH__) == PMU_PWTH_3_9) ||\
((__PWTH__) == PMU_PWTH_3_6) ||\
((__PWTH__) == PMU_PWTH_3_2) ||\
((__PWTH__) == PMU_PWTH_2_9) ||\
((__PWTH__) == PMU_PWTH_2_6) ||\
((__PWTH__) == PMU_PWTH_2_3))
/***** RTCLDOSel (PMU_RTCLDOConfig) *****/
#define PMU_RTCLDO_1_5 (0)
#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL
/***** StatusMask (PMU_GetPowerStatus) *****/
#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV
#define PMU_PWRSTS_VDCINDROP ANA_COMPOUT_VDCINDROP
#define PMU_PWRSTS_VDDALARM ANA_COMPOUT_VDDALARM
/***** Debounce (PMU_PWRDropDEBConfig) *****/
#define PMU_PWRDROP_DEB_0 ANA_CTRL_PWRDROPDEB_0
#define PMU_PWRDROP_DEB_1 ANA_CTRL_PWRDROPDEB_1
#define PMU_PWRDROP_DEB_2 ANA_CTRL_PWRDROPDEB_2
#define PMU_PWRDROP_DEB_3 ANA_CTRL_PWRDROPDEB_3
#define IS_PMU_PWRDROP_DEB(__DEB__) (((__DEB__) == PMU_PWRDROP_DEB_0) ||\
((__DEB__) == PMU_PWRDROP_DEB_1) ||\
((__DEB__) == PMU_PWRDROP_DEB_2) ||\
((__DEB__) == PMU_PWRDROP_DEB_3))
/***** RSTSource (PMU_GetRSTSource) *****/
#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST
#define PMU_RSTSRC_PORST PMU_STS_PORST
#define PMU_RSTSRC_DPORST PMU_STS_DPORST
//#define PMU_RSTSRC_WDTRST PMU_WDTSTS_WDTSTS
#define IS_PMU_RSTSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\
((__RSTSRC__) == PMU_RSTSRC_PORST) ||\
((__RSTSRC__) == PMU_RSTSRC_DPORST) )
/***** PMU_PDNDSleepConfig *****/
//VDCIN_PDNS
#define PMU_VDCINPDNS_0 (0)
#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS)
#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\
((__VDCINPDNS__) == PMU_VDCINPDNS_1))
//VDD_PDNS
#define PMU_VDDPDNS_0 (0)
#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2)
#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\
((__VDDPDNS__) == PMU_VDDPDNS_1))
/* Exported Functions ------------------------------------------------------- */
uint32_t PMU_EnterDSleepMode(void);
void PMU_EnterIdleMode(void);
uint32_t PMU_EnterSleepMode(void);
void PMU_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t PMU_GetINTStatus(uint32_t INTMask);
void PMU_ClearINTStatus(uint32_t INTMask);
uint8_t PMU_GetStatus(uint32_t Mask);
uint16_t PMU_GetIOAAllINTStatus(void);
uint16_t PMU_GetIOAINTStatus(uint16_t INTMask);
void PMU_ClearIOAINTStatus(uint16_t INTMask);
void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event);
uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
#ifndef __GNUC__
void PMU_EnterIdle_LowPower(void);
#endif
void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority);
void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority);
void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event);
void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event);
void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS);
/***** BGP functions *****/
void PMU_BGP_Cmd(uint32_t NewState);
/***** VDD functions *****/
void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold);
uint8_t PMU_GetVDDALARMStatus(void);
void PMU_VDDDetectorCmd(uint32_t NewState);
/***** AVCC functions *****/
void PMU_AVCC_Cmd(uint32_t NewState);
void PMU_AVCCOutput_Cmd(uint32_t NewState);
void PMU_AVCCLVDetector_Cmd(uint32_t NewState);
uint8_t PMU_GetAVCCLVStatus(void);
/***** VDCIN functions *****/
void PMU_VDCINDetector_Cmd(uint32_t NewState);
uint8_t PMU_GetVDCINDropStatus(void);
/***** BAT functions *****/
void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState);
/***** Other functions *****/
uint8_t PMU_GetModeStatus(void);
uint8_t PMU_GetPowerStatus(uint32_t StatusMask);
void PMU_PWRDropDEBConfig(uint32_t Debounce);
uint8_t PMU_GetRSTSource(uint32_t RSTSource);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PMU_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pwm.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief PWM library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PWM_H
#define __LIB_PWM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t ClockDivision;
uint32_t Mode;
uint32_t ClockSource;
} PWM_BaseInitType;
//ClockDivision
#define PWM_CLKDIV_2 PWM_CTL_ID_DIV2
#define PWM_CLKDIV_4 PWM_CTL_ID_DIV4
#define PWM_CLKDIV_8 PWM_CTL_ID_DIV8
#define PWM_CLKDIV_16 PWM_CTL_ID_DIV16
//Mode
#define PWM_MODE_STOP PWM_CTL_MC_STOP
#define PWM_MODE_UPCOUNT PWM_CTL_MC_UP
#define PWM_MODE_CONTINUOUS PWM_CTL_MC_CONTINUE
#define PWM_MODE_UPDOWN PWM_CTL_MC_UPDOWN
//ClockSource
#define PWM_CLKSRC_APB PWM_CTL_TESL_APBDIV1
#define PWM_CLKSRC_APBD128 PWM_CTL_TESL_APBDIV128
typedef struct
{
uint32_t Period;
uint32_t OutMode;
} PWM_OCInitType;
//OUTMOD
#define PWM_OUTMOD_CONST PWM_CCTL_OUTMOD_CONST
#define PWM_OUTMOD_SET PWM_CCTL_OUTMOD_SET
#define PWM_OUTMOD_TOGGLE_RESET PWM_CCTL_OUTMOD_TOGGLE_RESET
#define PWM_OUTMOD_SET_RESET PWM_CCTL_OUTMOD_SET_RESET
#define PWM_OUTMOD_TOGGLE PWM_CCTL_OUTMOD_TOGGLE
#define PWM_OUTMOD_RESET PWM_CCTL_OUTMOD_RESET
#define PWM_OUTMOD_TOGGLE_SET PWM_CCTL_OUTMOD_TOGGLE_SET
#define PWM_OUTMOD_RESET_SET PWM_CCTL_OUTMOD_RESET_SET
//PWM CHANNEL
#define PWM_CHANNEL_0 0
#define PWM_CHANNEL_1 1
#define PWM_CHANNEL_2 2
#define PWM_OSEL0_T0O0 (0<<0)
#define PWM_OSEL0_T0O1 (1<<0)
#define PWM_OSEL0_T0O2 (2<<0)
#define PWM_OSEL0_T1O0 (4<<0)
#define PWM_OSEL0_T1O1 (5<<0)
#define PWM_OSEL0_T1O2 (6<<0)
#define PWM_OSEL0_T2O0 (8<<0)
#define PWM_OSEL0_T2O1 (9<<0)
#define PWM_OSEL0_T2O2 (10<<0)
#define PWM_OSEL0_T3O0 (12<<0)
#define PWM_OSEL0_T3O1 (13<<0)
#define PWM_OSEL0_T3O2 (14<<0)
//outline
#define PWM_OLINE_0 1
#define PWM_OLINE_1 2
#define PWM_OLINE_2 4
#define PWM_OLINE_3 8
#define PWM_OLINE_Msk 0xF
//PWM output selection
#define PWM0_OUT0 PWM_OSEL0_T0O0
#define PWM0_OUT1 PWM_OSEL0_T0O1
#define PWM0_OUT2 PWM_OSEL0_T0O2
#define PWM1_OUT0 PWM_OSEL0_T1O0
#define PWM1_OUT1 PWM_OSEL0_T1O1
#define PWM1_OUT2 PWM_OSEL0_T1O2
#define PWM2_OUT0 PWM_OSEL0_T2O0
#define PWM2_OUT1 PWM_OSEL0_T2O1
#define PWM2_OUT2 PWM_OSEL0_T2O2
#define PWM3_OUT0 PWM_OSEL0_T3O0
#define PWM3_OUT1 PWM_OSEL0_T3O1
#define PWM3_OUT2 PWM_OSEL0_T3O2
//Level
#define PWM_LEVEL_HIGH PWM_CCTL_OUT
#define PWM_LEVEL_LOW 0
/* Private macros ------------------------------------------------------------*/
#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\
((__CLKDIV__) == PWM_CLKDIV_4) ||\
((__CLKDIV__) == PWM_CLKDIV_8) ||\
((__CLKDIV__) == PWM_CLKDIV_16))
#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\
((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\
((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\
((__CNTMODE__) == PWM_MODE_UPDOWN))
#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\
((__CLKSRC__) == PWM_CLKSRC_APBD128))
#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\
((__OUTMODE__) == PWM_OUTMOD_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET_SET))
#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U)
#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\
((__CHANNEL__) == PWM_CHANNEL_1) ||\
((__CHANNEL__) == PWM_CHANNEL_2))
#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\
(((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U))
#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\
((__OUTSEL__) == PWM0_OUT1) ||\
((__OUTSEL__) == PWM0_OUT2) ||\
((__OUTSEL__) == PWM1_OUT0) ||\
((__OUTSEL__) == PWM1_OUT1) ||\
((__OUTSEL__) == PWM1_OUT2) ||\
((__OUTSEL__) == PWM2_OUT0) ||\
((__OUTSEL__) == PWM2_OUT1) ||\
((__OUTSEL__) == PWM2_OUT2) ||\
((__OUTSEL__) == PWM3_OUT0) ||\
((__OUTSEL__) == PWM3_OUT1) ||\
((__OUTSEL__) == PWM3_OUT2))
#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\
((__OUTLVL__) == PWM_LEVEL_LOW))
/* Exported Functions ------------------------------------------------------- */
/* PWM Exported Functions Group1:
Initialization ----------------------------*/
void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct);
void PWM_BaseStructInit(PWM_BaseInitType *InitStruct);
void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OCStructInit(PWM_OCInitType *OCInitType);
/* PWM Exported Functions Group2:
Interrupt ---------------------------------*/
void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState);
uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx);
void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx);
void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState);
uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel);
void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel);
/* PWM Exported Functions Group3:
MISC --------------------------------------*/
void PWM_ClearCounter(PWM_TypeDef *PWMx);
void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period);
//Compare output
void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine);
void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState);
void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PWM_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_rtc.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief RTC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_RTC_H
#define __LIB_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* RTC Time struct */
typedef struct
{
uint32_t Year;
uint32_t Month;
uint32_t Date;
uint32_t WeekDay;
uint32_t Hours;
uint32_t Minutes;
uint32_t Seconds;
} RTC_TimeTypeDef;
//INT
#define RTC_INT_CEILLE RTC_INTEN_INTEN8
#define RTC_INT_ACDONE RTC_INTEN_INTEN7
#define RTC_INT_WKUCNT RTC_INTEN_INTEN6
#define RTC_INT_MIDNIGHT RTC_INTEN_INTEN5
#define RTC_INT_WKUHOUR RTC_INTEN_INTEN4
#define RTC_INT_WKUMIN RTC_INTEN_INTEN3
#define RTC_INT_WKUSEC RTC_INTEN_INTEN2
#define RTC_INT_TIMEILLE RTC_INTEN_INTEN1
#define RTC_INT_Msk (0x1FEUL)
//INTSTS
#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8
#define RTC_INTSTS_ACDONE RTC_INTSTS_INTSTS7
#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6
#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5
#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4
#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3
#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2
#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1
#define RTC_INTSTS_Msk (0x1FEUL)
/* RTC AutoCal struct */
typedef struct
{
uint32_t Period;
uint32_t ATDelay;
uint32_t ATClockSource;
uint32_t ADCSource;
} RTC_AutCalType;
//ATDelay
#define RTC_ATDELAY_15MS RTC_ACCTRL_ACDEL_0
#define RTC_ATDELAY_31MS RTC_ACCTRL_ACDEL_1
#define RTC_ATDELAY_62MS RTC_ACCTRL_ACDEL_2
#define RTC_ATDELAY_125MS RTC_ACCTRL_ACDEL_3
//ATClockSource
#define RTC_ATCS_DISABLE RTC_ACCTRL_ACCLK_0
#define RTC_ATCS_SEC RTC_ACCTRL_ACCLK_1
#define RTC_ATCS_MIN RTC_ACCTRL_ACCLK_2
#define RTC_ATCS_HOUR RTC_ACCTRL_ACCLK_3
//ADCSource
#define RTC_ADCS_DATA (0)
#define RTC_ADCS_PORT RTC_ACCTRL_ADCSEL
//CNTCLK
#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0
#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1
#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2
#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3
//Prescaler
#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0
#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1
/* Private macros ------------------------------------------------------------*/
#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U)
/* Year 0 ~ 99 */
#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU)
/* Month 1 ~ 12 */
#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U))
/* Date 1 ~ 31 */
#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32))
/* Weekday 0 ~ 6 */
#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U)
/* Hours 0 ~ 23 */
#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24)
/* Minutes 0 ~ 59 */
#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5A)
/* Seconds 0 ~ 59 */
#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5A)
#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\
(((__INT__) & ~RTC_INT_Msk) == 0U))
#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\
((__INTFLAGR_) == RTC_INTSTS_ACDONE) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\
((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\
((__INTFLAGR_) == RTC_INTSTS_TIMEILLE))
#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U))
#define IS_RTC_AUTOCAL_RELOAD(__RELOAD__) (((__RELOAD__) == RTC_AUTORELOAD_DISABLE) ||\
((__RELOAD__) == RTC_AUTORELOAD_ENABLE))
#define IS_RTC_AUTOCAL_ATDLY(__ATDLY__) (((__ATDLY__) == RTC_ATDELAY_15MS) ||\
((__ATDLY__) == RTC_ATDELAY_31MS) ||\
((__ATDLY__) == RTC_ATDELAY_62MS) ||\
((__ATDLY__) == RTC_ATDELAY_125MS))
#define IS_RTC_AUTOCAL_ATCS(__ATCS__) (((__ATCS__) == RTC_ATCS_DISABLE) ||\
((__ATCS__) == RTC_ATCS_SEC) ||\
((__ATCS__) == RTC_ATCS_MIN) ||\
((__ATCS__) == RTC_ATCS_HOUR))
#define IS_RTC_AUTOCAL_ADCSRC(__ADCSRC__) (((__ADCSRC__) == RTC_ADCS_DATA) ||\
((__ADCSRC__) == RTC_ADCS_PORT))
#define IS_RTC_AUTOCAL_PERIOD(__PERIOD__) ((__PERIOD__) < 64U)
#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) (((__PERIOD__) < 0x21U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) (((__PERIOD__) < 0x1000001U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\
((__CNTSEL__) == RTC_WKUCNT_2048) ||\
((__CNTSEL__) == RTC_WKUCNT_512) ||\
((__CNTSEL__) == RTC_WKUCNT_128))
#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\
((__CLKDIV__) == RTC_CLKDIV_4))
/* Exported Functions ------------------------------------------------------- */
/* RTC Exported Functions Group1:
Time functions -----------------------------*/
void RTC_SetTime(RTC_TimeTypeDef *sTime);
void RTC_GetTime(RTC_TimeTypeDef *gTime);
/* RTC Exported Functions Group2:
Registers operation functions --------------*/
void RTC_WriteProtection(uint32_t NewState);
void RTC_WaitForSynchro(void);
void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len);
void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len);
/* RTC Exported Functions Group3:
Interrupt functions ------------------------*/
void RTC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t RTC_GetINTStatus(uint32_t FlagMask);
void RTC_ClearINTStatus(uint32_t FlagMask);
/* RTC Exported Functions Group4:
AutoCal functions --------------------------*/
void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct);
void RTC_AutoCalInit(RTC_AutCalType *InitStruct);
void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period);
uint32_t RTC_AutoCalCmd(uint32_t NewState);
void RTC_StartAutoCalManual(void);
void RTC_WaitForAutoCalManual(void);
uint8_t RTC_GetACBusyFlag(void);
/* RTC Exported Functions Group5:
Wake-up functions --------------------------*/
void RTC_WKUSecondsConfig(uint8_t nPeriod);
void RTC_WKUMinutesConfig(uint8_t nPeriod);
void RTC_WKUHoursConfig(uint8_t nPeriod);
void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK);
uint32_t RTC_GetWKUCounterValue(void);
/* RTC Exported Functions Group6:
MISC functions -----------------------------*/
void RTC_PrescalerConfig(uint32_t Prescaler);
void RTC_PLLDIVConfig(uint32_t nfrequency);
void RTC_PLLDIVOutputCmd(uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_RTC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_spi.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief SPI library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_SPI_H
#define __LIB_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Mode;
uint32_t SPH;
uint32_t SPO;
uint32_t ClockDivision;
uint32_t CSNSoft;
uint32_t SWAP;
} SPI_InitType;
//Mode
#define SPI_MODE_MASTER 0
#define SPI_MODE_SLAVE SPI_CTRL_MOD
//SPH
#define SPI_SPH_0 0
#define SPI_SPH_1 SPI_CTRL_SCKPHA
//SPO
#define SPI_SPO_0 0
#define SPI_SPO_1 SPI_CTRL_SCKPOL
//ClockDivision
#define SPI_CLKDIV_2 (0)
#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0)
#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2)
//CSNSoft
#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO
#define SPI_CSNSOFT_DISABLE 0
//SWAP
#define SPI_SWAP_ENABLE SPI_CTRL_SWAP
#define SPI_SWAP_DISABLE 0
//INT
#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN)
#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN)
//status
#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF)
#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY)
#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR)
#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF)
#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL)
#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV)
#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY)
#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF)
#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE)
#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF)
#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE)
//TXFLEV
#define SPI_TXFLEV_0 (0)
#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0)
#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
//RXFLEV
#define SPI_RXFLEV_0 (0)
#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2)
#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0)
/* Private macros ------------------------------------------------------------*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE))
#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1))
#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1))
#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\
((__CLKDIV__) == SPI_CLKDIV_4) ||\
((__CLKDIV__) == SPI_CLKDIV_8) ||\
((__CLKDIV__) == SPI_CLKDIV_16) ||\
((__CLKDIV__) == SPI_CLKDIV_32) ||\
((__CLKDIV__) == SPI_CLKDIV_64) ||\
((__CLKDIV__) == SPI_CLKDIV_128))
#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE))
#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE))
#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\
(((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U))
#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\
((__STSR__) == SPI_STS_TXEMPTY) ||\
((__STSR__) == SPI_STS_TXFUR) ||\
((__STSR__) == SPI_STS_RXFULL) ||\
((__STSR__) == SPI_STS_RXFOV) ||\
((__STSR__) == SPI_STS_BSY) ||\
((__STSR__) == SPI_STS_RFF) ||\
((__STSR__) == SPI_STS_RNE) ||\
((__STSR__) == SPI_STS_TNF) ||\
((__STSR__) == SPI_STS_TFE) ||\
((__STSR__) == SPI_STS_RXIF))
#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF)) != 0U) &&\
(((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF)) == 0U))
#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\
((__TXFLEV__) == SPI_TXFLEV_1) ||\
((__TXFLEV__) == SPI_TXFLEV_2) ||\
((__TXFLEV__) == SPI_TXFLEV_3) ||\
((__TXFLEV__) == SPI_TXFLEV_4) ||\
((__TXFLEV__) == SPI_TXFLEV_5) ||\
((__TXFLEV__) == SPI_TXFLEV_6) ||\
((__TXFLEV__) == SPI_TXFLEV_7))
#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\
((__RXFLEV__) == SPI_RXFLEV_1) ||\
((__RXFLEV__) == SPI_RXFLEV_2) ||\
((__RXFLEV__) == SPI_RXFLEV_3) ||\
((__RXFLEV__) == SPI_RXFLEV_4) ||\
((__RXFLEV__) == SPI_RXFLEV_5) ||\
((__RXFLEV__) == SPI_RXFLEV_6) ||\
((__RXFLEV__) == SPI_RXFLEV_7))
/* Exported Functions ------------------------------------------------------- */
/* SPI Exported Functions Group1:
(De)Initialization -------------------------*/
void SPI_DeviceInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct);
void SPI_StructInit(SPI_InitType *InitStruct);
/* SPI Exported Functions Group2:
Interrupt (flag) ---------------------------*/
void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState);
uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status);
void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status);
/* SPI Exported Functions Group3:
Transfer datas -----------------------------*/
void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch);
uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx);
/* SPI Exported Functions Group4:
MISC Configuration -------------------------*/
void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState);
void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel);
void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel);
uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx);
uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx);
void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState);
void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_SPI_H */
/*********************************** END OF FILE ******************************/

63
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/**
******************************************************************************
* @file lib_tmr.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Timer library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_TMR_H
#define __LIB_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Period;
uint32_t ClockSource;
uint32_t EXTGT;
} TMR_InitType;
//ClockSource
#define TMR_CLKSRC_INTERNAL 0
#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK
//ClockGate
#define TMR_EXTGT_DISABLE 0
#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN
/* Private macros ------------------------------------------------------------*/
#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL))
#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE))
/* Exported Functions ------------------------------------------------------- */
/* Timer Exported Functions Group1:
(De)Initialization ----------------------*/
void TMR_DeInit(TMR_TypeDef *TMRx);
void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct);
void TMR_StructInit(TMR_InitType *InitStruct);
/* Timer Exported Functions Group2:
Interrupt (flag) -------------------------*/
void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState);
uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx);
void TMR_ClearINTStatus(TMR_TypeDef *TMRx);
/* Timer Exported Functions Group3:
MISC Configuration -----------------------*/
void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState);
uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_TMR_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_u32k.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief UART 32K library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_U32K_H
#define __LIB_U32K_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Debsel;
uint32_t Parity;
uint32_t WordLen;
uint32_t FirstBit;
uint32_t AutoCal;
uint32_t Baudrate;
uint32_t LineSel;
} U32K_InitType;
//Debsel
#define U32K_DEBSEL_0 U32K_CTRL0_DEBSEL_0
#define U32K_DEBSEL_1 U32K_CTRL0_DEBSEL_1
#define U32K_DEBSEL_2 U32K_CTRL0_DEBSEL_2
#define U32K_DEBSEL_3 U32K_CTRL0_DEBSEL_3
//Parity
#define U32K_PARITY_EVEN U32K_CTRL0_PMODE_EVEN
#define U32K_PARITY_ODD U32K_CTRL0_PMODE_ODD
#define U32K_PARITY_0 U32K_CTRL0_PMODE_0
#define U32K_PARITY_1 U32K_CTRL0_PMODE_1
#define U32K_PARITY_NONE 0
//WordLen
#define U32K_WORDLEN_8B 0
#define U32K_WORDLEN_9B U32K_CTRL0_MODE
//FirstBit
#define U32K_FIRSTBIT_LSB 0
#define U32K_FIRSTBIT_MSB U32K_CTRL0_MSB
//AutoCal
#define U32K_AUTOCAL_ON 0
#define U32K_AUTOCAL_OFF U32K_CTRL0_ACOFF
//Line
#define U32K_LINE_RX0 U32K_CTRL1_RXSEL_RX0
#define U32K_LINE_RX1 U32K_CTRL1_RXSEL_RX1
#define U32K_LINE_RX2 U32K_CTRL1_RXSEL_RX2
#define U32K_LINE_RX3 U32K_CTRL1_RXSEL_RX3
//INT
#define U32K_INT_RXOV U32K_CTRL1_RXOVIE
#define U32K_INT_RXPE U32K_CTRL1_RXPEIE
#define U32K_INT_RX U32K_CTRL1_RXIE
#define U32K_INT_Msk (U32K_INT_RXOV \
|U32K_INT_RXPE \
|U32K_INT_RX)
//INT Status
#define U32K_INTSTS_RXOV U32K_STS_RXOV
#define U32K_INTSTS_RXPE U32K_STS_RXPE
#define U32K_INTSTS_RX U32K_STS_RXIF
#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \
|U32K_INTSTS_RXPE \
|U32K_INTSTS_RX)
//WKUMode
#define U32K_WKUMOD_RX 0 // Wake-up when receive data
#define U32K_WKUMOD_PC U32K_CTRL0_WKUMODE // Wake-up when receive data and parity/stop bit correct
/* Private macros ------------------------------------------------------------*/
#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\
((__DEBSEL__) == U32K_DEBSEL_1) ||\
((__DEBSEL__) == U32K_DEBSEL_2) ||\
((__DEBSEL__) == U32K_DEBSEL_3))
#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\
((__PARITY__) == U32K_PARITY_ODD) ||\
((__PARITY__) == U32K_PARITY_0) ||\
((__PARITY__) == U32K_PARITY_1) ||\
((__PARITY__) == U32K_PARITY_NONE))
#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B))
#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB))
#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF))
#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\
((__LINE__) == U32K_LINE_RX1) ||\
((__LINE__) == U32K_LINE_RX2) ||\
((__LINE__) == U32K_LINE_RX3))
#define IS_U32K_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9601UL)
#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\
(((__INT__) & ~U32K_INT_Msk) == 0U))
#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\
((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\
((__INTFLAGR__) == U32K_INTSTS_RX))
#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U))
#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC))
/* Exported Functions ------------------------------------------------------- */
/* U32K Exported Functions Group1:
(De)Initialization -----------------------*/
void U32K_DeInit(U32K_TypeDef *U32Kx);
void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct);
void U32K_StructInit(U32K_InitType *InitStruct);
/* U32K Exported Functions Group2:
Interrupt (flag) configure ---------------*/
void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState);
uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask);
void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask);
/* U32K Exported Functions Group3:
Receive datas -----------------------------*/
uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx);
/* U32K Exported Functions Group4:
MISC Configuration -------- ---------------*/
void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate);
void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState);
void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line);
void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_U32K_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_uart.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief UART library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_UART_H
#define __LIB_UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//UART Init struct
typedef struct
{
uint32_t Mode;
uint32_t Parity;
uint32_t WordLen;
uint32_t FirstBit;
uint32_t Baudrate;
} UART_InitType;
//Mode
#define UART_MODE_RX UART_CTRL_RXEN
#define UART_MODE_TX UART_CTRL_TXEN
#define UART_MODE_OFF 0
#define UART_MODE_Msk (UART_CTRL_RXEN | UART_CTRL_TXEN)
//Parity
#define UART_PARITY_EVEN UART_CTRL2_PMODE_EVEN
#define UART_PARITY_ODD UART_CTRL2_PMODE_ODD
#define UART_PARITY_0 UART_CTRL2_PMODE_0
#define UART_PARITY_1 UART_CTRL2_PMODE_1
#define UART_PARITY_NONE 0
//WordLen
#define UART_WORDLEN_8B 0
#define UART_WORDLEN_9B UART_CTRL2_MODE
//FirstBit
#define UART_FIRSTBIT_LSB 0
#define UART_FIRSTBIT_MSB UART_CTRL2_MSB
//UART Configration Information struct
typedef struct
{
uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable
uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable
uint32_t Baudrate; //The value of current budrate
uint8_t Parity; //0: parity bit=0; 1: parity bit=1; 2: Even parity; 3:Odd parity
uint8_t WordLen; //8: data bits=8; 9: data bits=9
uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first
} UART_ConfigINFOType;
//status
#define UART_FLAG_RXPARITY UART_STATE_RXPSTS
#define UART_FLAG_TXDONE UART_STATE_TXDONE
#define UART_FLAG_RXPE UART_STATE_RXPE
#define UART_FLAG_RXOV UART_STATE_RXOV
#define UART_FLAG_TXOV UART_STATE_TXOV
#define UART_FLAG_RXFULL UART_STATE_RXFULL
#define UART_FLAG_RCMsk (UART_FLAG_TXDONE \
|UART_FLAG_RXPE \
|UART_FLAG_RXOV \
|UART_STATE_RXFULL\
|UART_FLAG_TXOV)
//interrupt
#define UART_INT_TXDONE UART_CTRL_TXDONEIE
#define UART_INT_RXPE UART_CTRL_RXPEIE
#define UART_INT_RXOV UART_CTRL_RXOVIE
#define UART_INT_TXOV UART_CTRL_TXOVIE
#define UART_INT_RX UART_CTRL_RXIE
#define UART_INT_Msk (UART_INT_TXDONE \
|UART_INT_RXPE \
|UART_INT_RXOV \
|UART_INT_TXOV \
|UART_INT_RX)
//INTStatus
#define UART_INTSTS_TXDONE UART_INTSTS_TXDONEIF
#define UART_INTSTS_RXPE UART_INTSTS_RXPEIF
#define UART_INTSTS_RXOV UART_INTSTS_RXOVIF
#define UART_INTSTS_TXOV UART_INTSTS_TXOVIF
#define UART_INTSTS_RX UART_INTSTS_RXIF
#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \
|UART_INTSTS_RXPE \
|UART_INTSTS_RXOV \
|UART_INTSTS_TXOV \
|UART_INTSTS_RX)
/* Private macros ------------------------------------------------------------*/
#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)) ||\
((__MODE__) == UART_MODE_OFF))
#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\
((__PARITY__) == UART_PARITY_ODD) ||\
((__PARITY__) == UART_PARITY_0) ||\
((__PARITY__) == UART_PARITY_1) ||\
((__PARITY__) == UART_PARITY_NONE))
#define IS_UART_WORDLEN(__WORDLEN__) (((__WORDLEN__) == UART_WORDLEN_8B) ||\
((__WORDLEN__) == UART_WORDLEN_9B))
#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\
((__FIRSTBIT__) == UART_FIRSTBIT_MSB))
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 0x100000UL)
#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_RXPARITY) ||\
((__FLAGR__) == UART_FLAG_TXDONE) ||\
((__FLAGR__) == UART_FLAG_RXPE) ||\
((__FLAGR__) == UART_FLAG_RXOV) ||\
((__FLAGR__) == UART_FLAG_TXOV) ||\
((__FLAGR__) == UART_FLAG_RXFULL))
#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\
(((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U))
#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\
(((__INT__) & ~UART_INT_Msk) == 0U))
#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\
((__INTFLAGR__) == UART_INTSTS_RXPE) ||\
((__INTFLAGR__) == UART_INTSTS_RXOV) ||\
((__INTFLAGR__) == UART_INTSTS_TXOV) ||\
((__INTFLAGR__) == UART_INTSTS_RX))
#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
/* UART Exported Functions Group1:
Initialization and functions --------------*/
void UART_DeInit(UART_TypeDef *UARTx);
void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct);
void UART_StructInit(UART_InitType *InitStruct);
/* UART Exported Functions Group2:
(Interrupt) Flag --------------------------*/
uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask);
void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask);
void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState);
uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask);
void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask);
/* UART Exported Functions Group3:
Transfer datas ----------------------------*/
void UART_SendData(UART_TypeDef *UARTx, uint8_t ch);
uint8_t UART_ReceiveData(UART_TypeDef *UARTx);
/* UART Exported Functions Group4:
MISC Configuration ------------------------*/
void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate);
void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState);
void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_UART_H */
/*********************************** END OF FILE ******************************/

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/**
*******************************************************************************
* @file lib_version.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief Version library.
*******************************************************************************/
#ifndef __LIB_VERSION_H
#define __LIB_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
/* Exported Functions ------------------------------------------------------- */
/**
* @brief Read receive data register.
* @param None
* @retval Version value
*/
uint16_t Target_GetDriveVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_VERSION_H */
/*********************************** END OF FILE ******************************/

46
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/**
******************************************************************************
* @file lib_wdt.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief WDT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_WDT_H
#define __LIB_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define WDT_2_SECS PMU_WDTEN_WDTSEL_0
#define WDT_1_SECS PMU_WDTEN_WDTSEL_1
#define WDT_0_5_SECS PMU_WDTEN_WDTSEL_2
#define WDT_0_25_SECS PMU_WDTEN_WDTSEL_3
/* Private macros ------------------------------------------------------------*/
#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\
((__PERIOD__) == WDT_1_SECS) ||\
((__PERIOD__) == WDT_0_5_SECS) ||\
((__PERIOD__) == WDT_0_25_SECS))
/* Exported Functions ------------------------------------------------------- */
void WDT_Enable(void);
void WDT_Disable(void);
void WDT_Clear(void);
void WDT_SetPeriod(uint32_t period);
uint16_t WDT_GetCounterValue(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_WDT_H */
/*********************************** END OF FILE ******************************/

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bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c Normal file
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/**
******************************************************************************
* @file lib_adc_tiny.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_adc_tiny.h"
#define ANA_REGF_RSTValue (0U)
/**
* @brief Initializes the Tiny ADC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void TADC_DeInit(void)
{
ANA->REGF = ANA_REGF_RSTValue;
ANA->INTSTS = ANA_INTSTS_INTSTS13;
ANA->MISC_A &= ~ANA_MISC_TADCTH;
}
/**
* @brief Fills each TADC_InitStruct member with its default value.
* @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized.
* @retval None
*/
void TADC_StructInit(TADCInitType* TADC_InitStruct)
{
/*--------------- Reset TADC init structure parameters values ---------------*/
/* Initialize the SignalSel member */
TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6;
/* Initialize the ADTREF1 member */
TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9;
/* Initialize the ADTREF2 member */
TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8;
/* Initialize the ADTREF3 member */
TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7;
}
/**
* @brief Tiny ADC initialization.
* @param TADC_InitStruct
SelADT:
ADCTINY_SIGNALSEL_IOE6
ADCTINY_SIGNALSEL_IOE7
ADTREF1:
ADCTINY_REF1_0_9
ADCTINY_REF1_0_7
ADTREF2:
ADCTINY_REF2_1_8
ADCTINY_REF2_1_6
ADTREF3:
ADCTINY_REF3_2_7
ADCTINY_REF3_2_5
* @retval None
*/
void TADC_Init(TADCInitType* TADC_InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel));
assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1));
assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2));
assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3));
tmp = ANA->REGF;
tmp &= ~(ANA_REGF_SELADT \
|ANA_REGF_ADTREF1SEL\
|ANA_REGF_ADTREF2SEL\
|ANA_REGF_ADTREF3SEL);
tmp |= (TADC_InitStruct->SignalSel \
|TADC_InitStruct->ADTREF1\
|TADC_InitStruct->ADTREF2\
|TADC_InitStruct->ADTREF3);
ANA->REGF = tmp;
}
/**
* @brief TADC enable control.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->REGF |= ANA_REGF_PDNADT;
else
ANA->REGF &= ~ANA_REGF_PDNADT;
}
/**
* @brief Get TADC output.
* @param None
* @retval Output of Tiny ADC(0 ~ 3).
*/
uint8_t TADC_GetOutput(void)
{
return ((ANA->COMPOUT & ANA_COMPOUT_TADCO) >> ANA_COMPOUT_TADCO_Pos);
}
/**
* @brief Configure Tiny ADC interrupt threshold.
* @param THSel:
ADCTINY_THSEL_0
ADCTINY_THSEL_1
ADCTINY_THSEL_2
ADCTINY_THSEL_3
* @retval None.
*/
void TADC_IntTHConfig(uint32_t THSel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_THSEL(THSel));
tmp = ANA->MISC_A;
tmp &= ~ANA_MISC_TADCTH;
tmp |= THSel;
ANA->MISC_A = tmp;
}
/**
* @brief TADC interrupt enable control.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_INTConfig(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->INTEN |= ANA_INTEN_INTEN13;
else
ANA->INTEN &= ~ANA_INTEN_INTEN13;
}
/**
* @brief Get Tiny ADC interrupt status.
* @param None
* @retval Interrupt status.
*/
uint8_t TADC_GetINTStatus(void)
{
if (ANA->INTSTS & ANA_INTSTS_INTSTS13)
return 1;
else
return 0;
}
/**
* @brief Clear Tiny ADC interrupt status.
* @param None
* @retval None
*/
void TADC_ClearINTStatus(void)
{
ANA->INTSTS = ANA_INTSTS_INTSTS13;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_ana.h"
/**
* @brief Get analog status.
* @param StatusMask:
ANA_STATUS_AVCCLV
ANA_STATUS_VDCINDROP
ANA_STATUS_VDDALARM
ANA_STATUS_COMP2
ANA_STATUS_COMP1
ANA_STATUS_LOCKL
ANA_STATUS_LOCKH
* @retval Analog status
*/
uint8_t ANA_GetStatus(uint32_t StatusMask)
{
/* Check parameters */
assert_parameters(IS_ANA_STATUS(StatusMask));
if (ANA->COMPOUT & StatusMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Get interrupt status.
* @param IntMask:
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval interrupt status.
*/
uint8_t ANA_GetINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSR(IntMask));
if (ANA->INTSTS&IntMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear interrupt status.
* @param IntMask:
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval None
*/
void ANA_ClearINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSC(IntMask));
ANA->INTSTS = IntMask;
}
/**
* @brief ANA interrupt configure.
* @param IntMask:
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
NewState:
ENABLE
DISABLE
* @retval None
*/
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ANA_INT(IntMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = ANA->INTEN;
if (NewState == ENABLE)
{
tmp |= IntMask;
}
else
{
tmp &= ~IntMask;
}
ANA->INTEN = tmp;
}
/*********************************** END OF FILE ******************************/

635
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337
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/**
******************************************************************************
* @file lib_comp.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief COMP library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_comp.h"
extern __IO uint32_t ana_reg3_tmp;
/**
* @brief Comparator debounce configure.
* @param COMPx:
COMP_1
COMP_2
Debounce:
COMP_DEB_0
COMP_DEB_1
COMP_DEB_2
COMP_DEB_3
* @retval None
*/
void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_DEB(Debounce));
tmp = ANA->CTRL;
tmp &= ~(ANA_CTRL_CMP1DEB << COMPx);
tmp |= Debounce << COMPx;
ANA->CTRL = tmp;
}
/**
* @brief Comparator mode configure.
* @param COMPx:
COMP_1
COMP_2
Mode:
COMP_MODE_OFF
COMP_MODE_RISING
COMP_MODE_FALLING
COMP_MODE_BOTH
* @retval None
*/
void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_MODE(Mode));
tmp = ANA->CTRL;
tmp &= ~(ANA_CTRL_COMP1_SEL << COMPx);
tmp |= Mode << COMPx;
ANA->CTRL = tmp;
}
/**
* @brief Configure signal source.
* @param COMPx:
* COMP_1
* COMP_2
* SourceSelect:
* COMP_SIGNALSRC_P_TO_REF
* COMP_SIGNALSRC_N_TO_REF
* COMP_SIGNALSRC_P_TO_N
* @retval None
*/
void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_SIGNALSRC(SourceSelect));
tmp = ANA->REG2;
tmp &= ~(ANA_REG2_CMP1_SEL << COMPx);
tmp |= SourceSelect << COMPx;
ANA->REG2 = tmp;
}
/**
* @brief Comparator configure REF selection.
* @param COMPx:
* COMP_1
* COMP_2
* REFSelect:
* COMP_REF_VREF
* COMP_REF_BGPREF
* @retval None
*/
void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_REF(REFSelect));
tmp = ANA->REG2;
tmp &= ~(ANA_REG2_REFSEL_CMP1 << (COMPx / 2));
tmp |= REFSelect << (COMPx / 2);
ANA->REG2 = tmp;
}
/**
* @brief Comparator configure Bias current selection.
* @param COMPx:
* COMP_1
* COMP_2
* BiasSel:
* COMP_BIAS_20nA
* COMP_BIAS_100nA
* COMP_BIAS_500nA
* @retval None
*/
void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_BIAS(BiasSel));
tmp = ANA->REG5;
tmp &= ~(ANA_REG5_IT_CMP1 << COMPx);
tmp |= BiasSel << COMPx;
ANA->REG5 = tmp;
}
/**
* @brief Get comparator count value.
* @param COMPx:
COMP_1
COMP_2
* @retval Comparator count value.
*/
uint32_t COMP_GetCNTValue(uint32_t COMPx)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
addr = &ANA->CMPCNT1 + (COMPx / 2);
return (*addr);
}
/**
* @brief Clear comparator counter value.
* @param COMPx:
COMP_1
COMP_2
* @retval None
*/
void COMP_ClearCNTValue(uint32_t COMPx)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
addr = &ANA->CMPCNT1 + (COMPx / 2);
*addr = 0;
}
/**
* @brief comparator output enable control.
* @param COMPx:
COMP_1
COMP_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
if (COMPx == COMP_1)
GPIOAF->SELE |= IOE_SEL_SEL7;
else
PMU->IOASEL |= PMU_IOASEL_SEL6;
}
else
{
if (COMPx == COMP_1)
GPIOAF->SELE &= ~IOE_SEL_SEL7;
else
PMU->IOASEL &= ~PMU_IOASEL_SEL6;
}
}
/**
* @brief Comparator enable control.
* @param COMPx:
COMP_1
COMP_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void COMP_Cmd(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (COMPx == COMP_1)
{
if (NewState == ENABLE)
ana_reg3_tmp |= ANA_REG3_CMP1PDN;
else
ana_reg3_tmp &= ~ANA_REG3_CMP1PDN;
}
else
{
if (NewState == ENABLE)
ana_reg3_tmp |= ANA_REG3_CMP2PDN;
else
ana_reg3_tmp &= ~ANA_REG3_CMP2PDN;
}
ANA->REG3 = ana_reg3_tmp;
}
/**
* @brief Get comparator 1 output level
* @param None
* @retval None
*/
uint8_t COMP1_GetOutputLevel(void)
{
if (ANA->COMPOUT & ANA_COMPOUT_COMP1)
return 1;
else
return 0;
}
/**
* @brief Get comparator 2 output level
* @param None
* @retval None
*/
uint8_t COMP2_GetOutputLevel(void)
{
if (ANA->COMPOUT & ANA_COMPOUT_COMP2)
return 1;
else
return 0;
}
/**
* @brief Comparator interrupt enable control.
* @param COMPx:
* COMP_1
* COMP_2
* NewState:
* ENABLE
* DISABLE
* @retval None
*/
void COMP_INTConfig(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
if (NewState == ENABLE)
{
ANA->INTEN |= ANA_INTEN_INTEN2 << (COMPx/2);
}
else
{
ANA->INTEN &= ~(ANA_INTEN_INTEN2 << (COMPx/2));
}
}
/**
* @brief Get comparator interrupt flag status.
* @param COMPx:
* COMP_1
* COMP_2
* @retval flag status
* 0: status not set
* 1: status set
*/
uint8_t COMP_GetINTStatus(uint32_t COMPx)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
if (ANA->INTSTS & (ANA_INTSTS_INTSTS2 << (COMPx/2)))
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear comparator interrupt flag.
* @param COMPx:
* COMP_1
* COMP_2
* @retval None
*/
void COMP_ClearINTStatus(uint32_t COMPx)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
ANA->INTSTS = ANA_INTSTS_INTSTS2 << (COMPx/2);
}
/*********************************** END OF FILE ******************************/

226
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/**
******************************************************************************
* @file lib_crypt.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief CRYPT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_crypt.h"
/**
* @brief Configure PTRA register, data in this address will be read out to do
* the CRYPT calculation
* @param AddrA: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressAConfig(uint16_t AddrA)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrA));
CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA;
}
/**
* @brief Configure PTRB register, data in this address will be read out to do
* the CRYPT calculation
* @param AddrB: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressBConfig(uint16_t AddrB)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrB));
CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB;
}
/**
* @brief Configure PTRO register, The CRYPT engine will write calculation
* result into this address
* @param AddrO: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressOConfig(uint16_t AddrO)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrO));
CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO;
}
/**
* @brief Get carry/borrow bit of add/sub operation.
* @param None
* @retval carry/borrow bit value
*/
uint8_t CRYPT_GetCarryBorrowBit(void)
{
if (CRYPT->CARRY & CRYPT_CARRY_CARRY)
return (1);
else
return (0);
}
/**
* @brief Start addition operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_ADD \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start multiplication operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_MULTIPLY \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start subtraction operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartSub(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_SUB \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start rigth shift 1-bit operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_RSHIFT1 \
|CRYPT_CTRL_ACT);
}
/**
* @brief Waiting for last operation to complete.
* @param None
* @retval None
*/
void CRYPT_WaitForLastOperation(void)
{
while (CRYPT->CTRL & CRYPT_CTRL_ACT)
{
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_dma.c
* @author Application Team
* @version V4.4.0
* @date 22018-09-27
* @brief DMA library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_dma.h"
//registers default reset values
#define DMA_CxCTL_RSTValue (0UL)
#define DMA_CxSRC_RSTValue (0UL)
#define DMA_CxDST_RSTValue (0UL)
#define DMA_AESCTL_RSTValue (0UL)
#define DMA_AESKEY_RSTValue (0UL)
/**
* @brief Initializes the DMA Cx peripheral registers to their default reset values.
* @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3
* @retval None
*/
void DMA_DeInit(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
/* channel x disable, clear stop */
addr = &DMA->C0CTL + Channel*4;
*addr &= ~(DMA_CxCTL_EN | DMA_CTL_STOP);
/* interrupt disable */
DMA->IE &= ~((1<<(Channel))\
|(1<<(Channel+4))\
|(1<<(Channel+8)));
/* interrupt state clear */
DMA->STS = (1<<(Channel+4))\
|(1<<(Channel+8))\
|(1<<(Channel+12));
/* DMA_CxCTL */
addr = &DMA->C0CTL + Channel*4;
*addr = DMA_CxCTL_RSTValue;
/* DMA_CxSRC */
addr = &DMA->C0SRC + Channel*4;
*addr = DMA_CxSRC_RSTValue;
/* DMA_CxDST */
addr = &DMA->C0DST + Channel*4;
*addr = DMA_CxDST_RSTValue;
}
/**
* @brief DMA channel x initialization.
* @param InitStruct: DMA configuration.
DestAddr : destination address
SrcAddr : source address
FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1)
PackLen : Package length (Ranges 0~255, actual length PackLen+1)
ContMode:
DMA_CONTMODE_ENABLE
DMA_CONTMODE_DISABLE
TransMode:
DMA_TRANSMODE_SINGLE
DMA_TRANSMODE_PACK
ReqSrc:
DMA_REQSRC_SOFT
DMA_REQSRC_UART0TX
DMA_REQSRC_UART0RX
DMA_REQSRC_UART1TX
DMA_REQSRC_UART1RX
DMA_REQSRC_UART2TX
DMA_REQSRC_UART2RX
DMA_REQSRC_UART3TX
DMA_REQSRC_UART3RX
DMA_REQSRC_UART4TX
DMA_REQSRC_UART4RX
DMA_REQSRC_UART5TX
DMA_REQSRC_UART5RX
DMA_REQSRC_ISO78160TX
DMA_REQSRC_ISO78160RX
DMA_REQSRC_ISO78161TX
DMA_REQSRC_ISO78161RX
DMA_REQSRC_TIMER0
DMA_REQSRC_TIMER1
DMA_REQSRC_TIMER2
DMA_REQSRC_TIMER3
DMA_REQSRC_SPI1TX
DMA_REQSRC_SPI1RX
DMA_REQSRC_U32K0
DMA_REQSRC_U32K1
DMA_REQSRC_CMP1
DMA_REQSRC_CMP2
DMA_REQSRC_SPI2TX
DMA_REQSRC_SPI2RX
DestAddrMode:
DMA_DESTADDRMODE_FIX
DMA_DESTADDRMODE_PEND
DMA_DESTADDRMODE_FEND
SrcAddrMode:
DMA_SRCADDRMODE_FIX
DMA_SRCADDRMODE_PEND
DMA_SRCADDRMODE_FEND
TransSize:
DMA_TRANSSIZE_BYTE
DMA_TRANSSIZE_HWORD
DMA_TRANSSIZE_WORD
Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval None
*/
void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel)
{
uint32_t tmp;
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode));
assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode));
assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc));
assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode));
assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode));
assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize));
if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD)
{
assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr));
assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr));
}
if (InitStruct->TransSize == DMA_TRANSSIZE_WORD)
{
assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr));
assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr));
}
addr = &DMA->C0DST + Channel*4;
*addr = InitStruct->DestAddr;
addr = &DMA->C0SRC + Channel*4;
*addr = InitStruct->SrcAddr;
addr = &DMA->C0CTL + Channel*4;
tmp = *addr;
tmp &= ~(DMA_CTL_FLEN\
|DMA_CTL_PLEN\
|DMA_CTL_CONT\
|DMA_CTL_TMODE\
|DMA_CTL_DMASEL\
|DMA_CxCTL_DMODE\
|DMA_CxCTL_SMODE\
|DMA_CxCTL_SIZE);
tmp |= ((InitStruct->FrameLen<<DMA_CTL_FLEN_Pos)\
|(InitStruct->PackLen<<DMA_CTL_PLEN_Pos)\
|(InitStruct->ContMode)\
|(InitStruct->TransMode)\
|(InitStruct->ReqSrc)\
|(InitStruct->DestAddrMode)\
|(InitStruct->SrcAddrMode)\
|(InitStruct->TransSize));
*addr = tmp;
}
/**
* @brief Initializes the DMA AES channel3 registers to their default reset values.
* @param None
* @retval None
*/
void DMA_AESDeInit(void)
{
DMA->AESCTL = DMA_AESCTL_RSTValue;
DMA->AESKEY0 = DMA_AESKEY_RSTValue;
DMA->AESKEY1 = DMA_AESKEY_RSTValue;
DMA->AESKEY2 = DMA_AESKEY_RSTValue;
DMA->AESKEY3 = DMA_AESKEY_RSTValue;
DMA->AESKEY4 = DMA_AESKEY_RSTValue;
DMA->AESKEY5 = DMA_AESKEY_RSTValue;
DMA->AESKEY6 = DMA_AESKEY_RSTValue;
DMA->AESKEY7 = DMA_AESKEY_RSTValue;
}
/**
* @brief AES initialization.
* @param InitStruct: AES configuration.
Mode:
DMA_AESMODE_128
DMA_AESMODE_192
DMA_AESMODE_256
Direction:
DMA_AESDIRECTION_ENCODE
DMA_AESDIRECTION_DECODE
KeyStr: the pointer to DMA_AESKEYx register
* @retval None
*/
void DMA_AESInit(DMA_AESInitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_DMA_AESMOD(InitStruct->Mode));
assert_parameters(IS_DMA_AESDIR(InitStruct->Direction));
tmp = DMA->AESCTL;
tmp &= ~(DMA_AESCTL_MODE\
|DMA_AESCTL_ENC);
tmp |= (InitStruct->Mode\
|InitStruct->Direction);
DMA->AESCTL = tmp;
DMA->AESKEY0 = InitStruct->KeyStr[0];
DMA->AESKEY1 = InitStruct->KeyStr[1];
DMA->AESKEY2 = InitStruct->KeyStr[2];
DMA->AESKEY3 = InitStruct->KeyStr[3];
if ((InitStruct->Mode == DMA_AESMODE_192) ||\
(InitStruct->Mode == DMA_AESMODE_256))
{
DMA->AESKEY4 = InitStruct->KeyStr[4];
DMA->AESKEY5 = InitStruct->KeyStr[5];
}
if (InitStruct->Mode == DMA_AESMODE_256)
{
DMA->AESKEY6 = InitStruct->KeyStr[6];
DMA->AESKEY7 = InitStruct->KeyStr[7];
}
}
/**
* @brief Interrupt configure.
* @param INTMask: can use the ¡®|¡¯ operator
DMA_INT_C3DA
DMA_INT_C2DA
DMA_INT_C1DA
DMA_INT_C0DA
DMA_INT_C3FE
DMA_INT_C2FE
DMA_INT_C1FE
DMA_INT_C0FE
DMA_INT_C3PE
DMA_INT_C2PE
DMA_INT_C1PE
DMA_INT_C0PE
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_INTConfig(uint32_t INTMask, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_DMA_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
DMA->IE |= INTMask;
else
DMA->IE &= ~INTMask;
}
/**
* @brief Get interrupt status.
* @param INTMask:
DMA_INTSTS_C3DA
DMA_INTSTS_C2DA
DMA_INTSTS_C1DA
DMA_INTSTS_C0DA
DMA_INTSTS_C3FE
DMA_INTSTS_C2FE
DMA_INTSTS_C1FE
DMA_INTSTS_C0FE
DMA_INTSTS_C3PE
DMA_INTSTS_C2PE
DMA_INTSTS_C1PE
DMA_INTSTS_C0PE
DMA_INTSTS_C3BUSY
DMA_INTSTS_C2BUSY
DMA_INTSTS_C1BUSY
DMA_INTSTS_C0BUSY
* @retval interrupt status.
*/
uint8_t DMA_GetINTStatus(uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_DMA_INTFLAGR(INTMask));
if (DMA->STS&INTMask)
return 1;
else
return 0;
}
/**
* @brief Clear interrupt status.
* @param INTMask: can use the ¡®|¡¯ operator
DMA_INTSTS_C3DA
DMA_INTSTS_C2DA
DMA_INTSTS_C1DA
DMA_INTSTS_C0DA
DMA_INTSTS_C3FE
DMA_INTSTS_C2FE
DMA_INTSTS_C1FE
DMA_INTSTS_C0FE
DMA_INTSTS_C3PE
DMA_INTSTS_C2PE
DMA_INTSTS_C1PE
DMA_INTSTS_C0PE
* @retval None
*/
void DMA_ClearINTStatus(uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_DMA_INTFLAGC(INTMask));
DMA->STS = INTMask;
}
/**
* @brief DMA channel enable.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_Cmd(uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &DMA->C0CTL + Channel*4;
if (NewState == ENABLE)
*addr |= DMA_CxCTL_EN;
else
*addr &= ~DMA_CxCTL_EN;
}
/**
* @brief Enable AES encrypt/decrypt function of DMA channel3.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_AESCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
DMA->C3CTL |= DMA_CTL_AESEN;
else
DMA->C3CTL &= ~DMA_CTL_AESEN;
}
/**
* @brief DMA stop transmit.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_StopTransmit(uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &DMA->C0CTL + Channel*4;
if (NewState == ENABLE)
*addr |= DMA_CTL_STOP;
else
*addr &= ~DMA_CTL_STOP;
}
/**
* @brief Get current frame transferred length.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval Current frame transferred length.
*/
uint8_t DMA_GetFrameLenTransferred(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
addr = &DMA->C0LEN + Channel*4;
return ((*addr&0xFF00)>>8);
}
/**
* @brief Get current package transferred length.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval Current package transferred length.
*/
uint8_t DMA_GetPackLenTransferred(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
addr = &DMA->C0LEN + Channel*4;
return (*addr&0xFF);
}
/*********************************** END OF FILE ******************************/

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@@ -0,0 +1,297 @@
/**
******************************************************************************
* @file lib_flash.c
* @author Application Team
* @version V4.3.0
* @date 2018-09-27
* @brief FLASH library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_flash.h"
#include "lib_clk.h"
/* FLASH Keys */
#define FLASH_PASS_KEY 0x55AAAA55
#define FLASH_SERASE_KEY 0xAA5555AA
#define FLASH_CERASE_KEY 0xAA5555AA
#define FLASH_DSTB_KEY 0xAA5555AA
#define FLASH_MODE_MASK 0x1F3
/**
* @brief FLASH mode initialization.
* @param CSMode:
FLASH_CSMODE_DISABLE
FLASH_CSMODE_ALWAYSON
FLASH_CSMODE_TIM2OF
FLASH_CSMODE_RTC
* @retval None
*/
void FLASH_Init(uint32_t CSMode)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FLASH_CSMODE(CSMode));
tmp = FLASH->CTRL;
tmp &= ~FLASH_MODE_MASK;
tmp |= CSMode;
FLASH->CTRL = tmp;
}
/**
* @brief Configure FLASH interrupt.
* @param IntMask:
FLASH_INT_CS
NewState:
ENABLE
DISABLE
* @retval None
*/
void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = FLASH->CTRL;
tmp &= ~IntMask;
if (NewState == ENABLE)
{
tmp |= IntMask;
}
FLASH->CTRL = tmp;
}
/**
* @brief Init FLASH 1USCYCLE.
* @param None
* @retval None
*/
void FLASH_CycleInit(void)
{
uint32_t hclk;
hclk = CLK_GetHCLKFreq();
if (hclk > 1000000)
MISC2->FLASHWC = (hclk/1000000)<<8;
else
MISC2->FLASHWC = 0;
}
/**
* @brief Erase FLASH sector.
* @param SectorAddr: sector address.
* @retval None
*/
void FLASH_SectorErase(uint32_t SectorAddr)
{
/* Check parameters */
assert_parameters(IS_FLASH_ADDRESS(SectorAddr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = SectorAddr;
FLASH->SERASE = FLASH_SERASE_KEY;
while (FLASH->SERASE != 0);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH word program.
* @param Addr: program start address
WordBuffer: word's buffer pointer to write
Length: The length of WordBuffer
* @retval None
*/
void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADRRW(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
FLASH->PGDATA = *(WordBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH half-word progarm.
* @param Addr: program start address
HWordBuffer: half-word's buffer pointer to write
Length: The length of HWordBuffer
* @retval None
*/
void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADRRHW(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
if (((Addr + 2*i)&0x3) == 0)
*((__IO uint16_t*)(&FLASH->PGDATA)) = *(HWordBuffer++);
else
*((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH byte progarm.
* @param Addr: program start address
ByteBuffer: byte's buffer pointer to write
Length: The length of ByteBuffer
* @retval None
*/
void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADDRESS(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
if (((Addr + i)&0x3) == 0)
*((__IO uint8_t*)(&FLASH->PGDATA)) = *(ByteBuffer++);
else if (((Addr + i)&0x3) == 1)
*((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++);
else if (((Addr + i)&0x3) == 2)
*((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++);
else
*((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief Get Write status.
* @param None.
* @retval FLASH_WSTA_BUSY
FLASH_WSTA_FINISH
*/
uint32_t FLASH_GetWriteStatus(void)
{
if (FLASH->STS == 1)
{
return FLASH_WSTA_FINISH;
}
else
{
return FLASH_WSTA_BUSY;
}
}
/**
* @brief Set checksum range.
* @param AddrStart: checksum start address
AddrEnd: checksum end address
* @retval None
*/
void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd)
{
/* Check parameters */
assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd));
FLASH->CSSADDR = AddrStart;
FLASH->CSEADDR = AddrEnd;
}
/**
* @brief Set checksum compare value.
* @param Checksum: checksum compare value
* @retval None
*/
void FLASH_SetCheckSumCompValue(uint32_t Checksum)
{
FLASH->CSCVALUE = Checksum;
}
/**
* @brief Get FLASH checksum value.
* @param None
* @retval Checksum
*/
uint32_t FLASH_GetCheckSum(void)
{
return FLASH->CSVALUE;
}
/**
* @brief Get FLASH interrupt status.
* @param IntMask:
FLASH_INT_CS
* @retval 1: interrupt status set
0: interrupt status reset
*/
uint8_t FLASH_GetINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
if (FLASH->INT&FLASH_INT_CSERR)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear FLASH interrupt status.
* @param IntMask:
FLASH_INT_CS
* @retval None
*/
void FLASH_ClearINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
if (IntMask == FLASH_INT_CS)
{
FLASH->INT = FLASH_INT_CSERR;
}
}
/*********************************** END OF FILE ******************************/

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bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c Normal file
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