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Merge pull request #3661 from whik/whik_sf2

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add support for Microsemi SmartFusion2 family FPGA
This commit is contained in:
Bernard Xiong
2020-11-18 08:09:54 +08:00
committed by GitHub
parent 3700283812 2d71df58dd
commit 886ce43403
66 changed files with 21923 additions and 0 deletions
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1
.travis.yml
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@@ -138,6 +138,7 @@ env:
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='smartfusion2' RTT_TOOL_CHAIN='sourcery-arm'
stage: compile
script:

17
bsp/smartfusion2/CMSIS/SConscript Normal file
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@@ -0,0 +1,17 @@
from building import *
import rtconfig
cwd = GetCurrentDir()
src = Glob('*.c')
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup_gcc/startup_m2sxxx.S']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup_arm/startup_m2sxxx.s']
CPPPATH = [cwd]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

810
bsp/smartfusion2/CMSIS/core_cm3.c Normal file
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1844
bsp/smartfusion2/CMSIS/core_cm3.h Normal file
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bsp/smartfusion2/CMSIS/hw_reg_io.h Normal file
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@@ -0,0 +1,113 @@
/*******************************************************************************
* (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
* Access Layer.
*
* This file provides interfaces to perform register and register bit level
* read / write operations. These interfaces support bit-banding in case of
* Cortex-M3 CPU.
*
* SVN $Revision: 5263 $
* SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
*/
#ifndef HW_REG_IO_H_
#define HW_REG_IO_H_
#include <stdint.h> /* Include standard types */
#if defined ( __CC_ARM )
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
/*****************************************************************************************
* Definitions for register access
*/
#define HW_REG(addr) (*((volatile uint32_t *) (addr)))
static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
{
HW_REG(reg) = val;
}
static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
{
return ( HW_REG(reg) );
}
/*****************************************************************************************
* Definitions for register bits access using bit-band aliases for Cortex-M3
*/
#define BITBAND(addr,bitnum) (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
#define HW_REG_BIT(reg,bitnum) (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
/*****************************************************************************************
* Functions to set a bit field in Cortex-M3
*/
static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
/*****************************************************************************************
* Functions to clear a bit field in Cortex-M3
*/
static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
/*****************************************************************************************
* Functions to read a bit field in Cortex-M3
*/
static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
#endif /* HW_REG_IO_H_ */

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bsp/smartfusion2/CMSIS/m2sxxx.h Normal file
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62
bsp/smartfusion2/CMSIS/mss_assert.h Normal file
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@@ -0,0 +1,62 @@
/*******************************************************************************
* (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
*
* Assertion implementation.
*
* This file provides the implementation of the ASSERT macro. This file can be
* modified to cater for project specific requirements regarding the way
* assertions are handled.
*
* SVN $Revision: 6422 $
* SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $
*/
#ifndef __MSS_ASSERT_H_
#define __MSS_ASSERT_H_
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else /* NDEBUG */
#include <assert.h>
#if defined ( __GNUC__ )
/*
* SoftConsole assertion handling
*/
#define ASSERT(CHECK) \
do { \
if (!(CHECK)) \
{ \
__asm volatile ("BKPT\n\t"); \
} \
} while (0);
#elif defined ( __ICCARM__ )
/*
* IAR Embedded Workbench assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#define ASSERT(X) assert(X)
#else
/*
* Keil assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#ifndef __MICROLIB
#define ASSERT(X) assert(X)
#else
#define ASSERT(X)
#endif
#endif /* Tool Chain */
#endif /* NDEBUG */
#endif /* __MSS_ASSERT_H_ */

44
bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c Normal file
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@@ -0,0 +1,44 @@
/*******************************************************************************
* (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved.
*
* Keil-MDK specific system initialization.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
#ifdef MSCC_NO_RELATIVE_PATHS
#include "m2sxxx.h"
#else
#include "..\m2sxxx.h"
#endif
#define ENVM_BASE_ADDRESS 0x60000000U
#define MDDR_BASE_ADDRESS 0xA0000000U
//extern unsigned int Image$$ER_RW$$Base;
//extern unsigned int Image$$ER_RO$$Base;
/*==============================================================================
* The __low_level_init() function is called after SystemInit. Therefore, the
* external RAM should be configured at this stage if it is used.
*/
/* void low_level_init(void)
{
volatile unsigned int rw_region_base;
volatile unsigned int readonly_region_base;
rw_region_base = (unsigned int)&Image$$ER_RW$$Base;
if (rw_region_base >= MDDR_BASE_ADDRESS)
{
/ --------------------------------------------------------------------------
* Remap MDDR to address 0x00000000.
/
SYSREG->ESRAM_CR = 0u;
SYSREG->ENVM_REMAP_BASE_CR = 0u;
SYSREG->DDR_CR = 1u;
}
readonly_region_base = (unsigned int)&Image$$ER_RO$$Base;
SCB->VTOR = readonly_region_base;
} */

150
bsp/smartfusion2/CMSIS/startup_arm/retarget.c Normal file
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@@ -0,0 +1,150 @@
/*******************************************************************************
* (c) Copyright 2013 Microsemi SoC Products Group. All rights reserved.
*
* Redirection of the standard library I/O to one of the SmartFusion2
* MMUART.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
/*==============================================================================
* The content of this source file will only be compiled if either one of the
* following two defined symbols are defined in the project settings:
* - MICROSEMI_STDIO_THRU_MMUART0
* - MICROSEMI_STDIO_THRU_MMUART1
*
*/
#ifdef MICROSEMI_STDIO_THRU_MMUART0
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART0 */
#ifdef MICROSEMI_STDIO_THRU_MMUART1
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART1 */
/*==============================================================================
* Actual implementation.
*/
#ifdef MICROSEMI_STDIO_THRU_UART
#include <stdio.h>
#include <rt_misc.h>
#include "m2sxxx.h"
#include "mss_uart.h"
#include "core_uart_apb.h"
/*
* The baud rate will default to 57600 baud if no baud rate is specified though the
* MICROSEMI_STDIO_BAUD_RATE define.
*/
#ifndef MICROSEMI_STDIO_BAUD_RATE
#define MICROSEMI_STDIO_BAUD_RATE MSS_UART_115200_BAUD
#endif
#ifdef MICROSEMI_STDIO_THRU_MMUART0
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
#else
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
#endif
/*==============================================================================
* Flag used to indicate if the UART driver needs to be initialized.
*/
static int g_stdio_uart_init_done = 0;
#define LSR_THRE_MASK 0x20u
/*
* Disable semihosting apis
*/
#pragma import(__use_no_semihosting_swi)
/*==============================================================================
* sendchar()
*/
int sendchar(int ch)
{
uint32_t tx_ready;
//第一次调用时，初始化串口
if(!g_stdio_uart_init_done)
{
MSS_UART_init(gp_my_uart,
MICROSEMI_STDIO_BAUD_RATE,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
g_stdio_uart_init_done = 1;
}
do {
tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK;
} while(!tx_ready);
gp_my_uart->hw_reg->THR = ch;
return (ch);
}
/*==============================================================================
*
*/
struct __FILE { int handle; /* Add whatever you need here */ };
FILE __stdout;
FILE __stdin;
/*==============================================================================
* fputc()
*/
int fputc(int ch, FILE *f)
{
return (sendchar(ch));
}
/*==============================================================================
* fgetc()
*/
int fgetc(FILE *f)
{
uint8_t rx_size;
uint8_t rx_byte;
do {
rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1);
} while(0u == rx_size);
return rx_byte;
}
/*==============================================================================
* ferror()
*/
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
/*==============================================================================
* _ttywrch()
*/
void _ttywrch(int ch)
{
sendchar(ch);
}
/*==============================================================================
* _sys_exit()
*/
void _sys_exit(int return_code)
{
for(;;)
{
; /* endless loop */
}
}
#endif /* MICROSEMI_STDIO_THRU_UART */

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bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct Normal file
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@@ -0,0 +1,49 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in internal eSRAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
RAM_LOAD 0x20000000 0x10000
{
; First half of RAM allocated to RO Execute and data
ER_RO 0x20000000 0x8000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
; Second half of RAM allocated to RW data, heap and stack
ER_RW 0x20008000 0x8000
{
.ANY (+RW +ZI)
}
}

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bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct Normal file
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@@ -0,0 +1,48 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for executing code in internal eNVM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x00000000 0x40000
{
; All R only code/data is located in ENVM
ER_RO 0x00000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
ER_RW 0x20000000 0x10000
{
.ANY (+RW +ZI)
}
}

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bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct Normal file
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@@ -0,0 +1,54 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in external MDDR.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
; Extern RAM 64M in total
; allocate 1/2 to progam, 1/2 to variable data
RAM_LOAD 0x00000000 0x04000000
{
; Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
ER_RO 0x00000000 0x02000000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; 32 MB- Second half of external memory allocated to RW data
ER_RW 0xA2000000 0x02000000
{
.ANY (+RW +ZI)
}
}

74
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct Normal file
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@@ -0,0 +1,74 @@
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for relocating code to external RAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x60000000 0x40000
{
; All code required on start-up located here before relocation has occured
ER_RO 0x60000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
startup_m2sxxx.o
system_m2sxxx.o
sys_config.o
low_level_init.o
sys_config_SERDESIF_?.o
mscc_post_hw_cfg_init.o
ecc_error_handler.o
}
; MDDR_RAM 0xA0000000 0x4000000
; -MDDR is mapped to address space from 0 on startup
; This allows the use of cache which is restriced to this area.
; Code is copied to RAM_EXEC space on startup by boot code.
RAM_EXEC 0x00000000 0x00040000
{
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; All internal RAM has been allocatd to the stack
; INTERNAL_RAM 0x20008000 0x10000
; {
; .ANY (+RW +ZI)
; }
; MDDR_RAM 0xA0000000 0x4000000 So use top half of this for RW data
; Bottom half has been assigned to R only code already
ER_RW 0xA2000000 0x2000000
{
.ANY (+RW +ZI)
}
}

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bsp/smartfusion2/CMSIS/startup_arm/startup_m2sxxx.s Normal file
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249
bsp/smartfusion2/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld Normal file
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/*******************************************************************************
* (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
*
* file name : debug-in-microsemi-smartfusion2-envm.ld
* SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
* debug image executing in SmartFusion2 internal eNVM.
*
* Some current (April 2015) dev kit memory map possibilities are
* --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
* --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
* --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
* --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
* --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
* --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
* --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
* --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
* --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
* --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
* --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
* --Some older physical memory map possibilities are
* --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
* --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
* --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
*
* Example linker scripts use lowest practicl values so will work accross dev kits
* eNVM=256KB eRAM=64KB External memory = 64MB
*
* On reset, the eNVM region is mapped to 0x00000000
* This is changed below by setting the __smartfusion2_memory_remap variable as required.
* Options are detailed below.
*
* SVN $Revision: 7419 $
* SVN $Date: 2015-05-15 21:20:21 +0530 (Fri, 15 May 2015) $
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lc -lgcc -lm)
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SEARCH_DIR(.)
__DYNAMIC = 0;
/*******************************************************************************
* Start of board customization.
*******************************************************************************/
MEMORY
{
/*
* In general, example LD scripts use lowest common memory footprint
* so will work with all devices.
*/
/*
* WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
* the name of the type of flash memory are all in a specific order.
* Please do not modify that comment line, in order to ensure
* debugging of your application will use the flash memory correctly.
*/
/* SOFTCONSOLE FLASH USE: microsemi-smartfusion2-envm */
rom (rx) : ORIGIN = 0x60000000, LENGTH = 256k
/* SmartFusion2 internal eNVM mirrored to 0x00000000 */
romMirror (rx) : ORIGIN = 0x00000000, LENGTH = 256k
/* SmartFusion2 internal eSRAM */
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
}
RAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
MAIN_STACK_SIZE = 4k; /* Cortex main stack size. */
MIN_SIZE_HEAP = 4k; /* needs to be calculated for your application */
/*******************************************************************************
* End of board customization.
*******************************************************************************/
PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
PROVIDE (_estack = __main_stack_start);
PROVIDE (__mirrored_nvm = 1); /* Indicate to startup code that NVM is mirrored to VMA address and no text copy is required. */
/*
* Remap instruction for startup code and debugger.
* set __smartfusion2_memory_remap to one of the following:
* 0: remap eNVM to address 0x00000000 Production mode or debugging from eNVM
* 1: remap eSRAM to address 0x00000000 Debugging from eSRAM
* 2: remap external DDR memory to address 0x00000000 Debugging from DDR memory
*/
PROVIDE (__smartfusion2_memory_remap = 0);
SECTIONS
{
.vector_table : ALIGN(0x10)
{
__vector_table_load = LOADADDR(.vector_table);
__vector_table_start = .;
__vector_table_vma_base_address = .; /* required by debugger for start address */
KEEP(*(.isr_vector))
. = ALIGN(0x10);
_evector_table = .;
} >romMirror AT>rom
/* all data and code run/used before reloaction must be located here */
/* When all code in NVRAM, no requirement for this section- but adds clarity when looking at .lst file */
.boot_code : ALIGN(0x10)
{
*(.boot_code) /* reset handler */
*system_m2sxxx.o(.text*) /* SystemInit() - called before relocation to RAM so keep in ROM */
*sys_config.o(.rodata*)
. = ALIGN(0x10);
} >romMirror AT>rom
.text : ALIGN(0x10)
{
CREATE_OBJECT_SYMBOLS
__text_load = LOADADDR(.text); /* required when copying to RAM */
__text_start = .; /* required when copying to RAM */
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
. = ALIGN(4);
/* These are for running static constructors and destructors under ELF. */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.vector_table))
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >romMirror AT>rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >ram AT>rom
__exidx_end = .;
_etext = .; /* required when copying to RAM */
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data); /* used when copying to RAM */
_sidata = LOADADDR (.data);
__data_start = .; /* used when copying to RAM */
_sdata = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (0x10);
_edata = .; /* used when copying to RAM */
} >ram AT>rom
.bss : ALIGN(0x10)
{
__bss_start__ = . ;
_sbss = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end__ = .;
_end = .;
__end = _end;
_ebss = .;
PROVIDE(end = .);
} >ram AT>rom
.heap : ALIGN(0x10)
{
__heap_start__ = .;
. += MIN_SIZE_HEAP; /* will generate error if this minimum size not available */
. += ((ABSOLUTE(RAM_START_ADDRESS) + RAM_SIZE - MAIN_STACK_SIZE) - .); /* assumes stack starts after heap */
_eheap = .;
} >ram
.stack : ALIGN(0x10)
{
__stack_start__ = .;
. += MAIN_STACK_SIZE;
_estack = .;
} >ram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

248
bsp/smartfusion2/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld Normal file
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/*******************************************************************************
* (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
*
* file name : debug-in-microsemi-smartfusion2-esram.ld
* SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
* debug image executing in SmartFusion2 internal eSRAM.
*
* Some current (April 2015) dev kit memory map possibilities are
* --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
* --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
* --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
* --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
* --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
* --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
* --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
* --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
* --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
* --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
* --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
* --Some older physical memory map possibilities are
* --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
* --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
* --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
*
* Example linker scripts use lowest practicl values so will work accross dev kits
* eNVM=256KB eRAM=64KB External memory = 64MB
*
* On reset, the eNVM region is mapped to 0x00000000
* This is changed below by setting the __smartfusion2_memory_remap variable as required.
* Options are detailed below.
*
* SVN $Revision: 7478 $
* SVN $Date: 2015-06-18 21:48:18 +0530 (Thu, 18 Jun 2015) $
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lc -lgcc -lm)
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SEARCH_DIR(.)
__DYNAMIC = 0;
/*******************************************************************************
* Start of board customization.
*******************************************************************************/
MEMORY
{
/*
* In general, example LD scripts use lowest common memory footprint
* so will work with all devices.
*/
/*
* WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
* the name of the type of flash memory are all in a specific order.
* Please do not modify that comment line, in order to ensure
* debugging of your application will use the flash memory correctly.
*/
/* SmartFusion2 internal eSRAM */
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
}
RAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
MAIN_STACK_SIZE = 4k; /* Cortex main stack size. */
MIN_SIZE_HEAP = 4k; /* needs to be calculated for your application */
/* Please note that unassigned RAM will be allocated to the .heap section. */
/*******************************************************************************
* End of board customization.
*******************************************************************************/
PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
PROVIDE (_estack = __main_stack_start);
PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
/*
* Remap instruction for start-up code and debugger.
* set __smartfusion2_memory_remap to one of the following:
* 0: remap eNVM to address 0x00000000 Production mode or debugging from eNVM
* 1: remap eSRAM to address 0x00000000 See note 1 below.
* 2: remap external DDR memory to address 0x00000000 Debugging from or production relocate to DDR memory
* note 1: This option should only be used in production mode if required. When debugging using eSRAM, code is not
* relocated and __smartfusion2_memory_remap should be set to option 0. In revision 7419 and below of
* this file, __smartfusion2_memory_remap was set to option 1. This remap was not required and could lead to an issue
* when displaying some invalid memory locations in the debugger using some Libero designs.
*
*/
PROVIDE (__smartfusion2_memory_remap = 0);
SECTIONS
{
.vector_table : ALIGN(0x10)
{
__vector_table_load = LOADADDR(.vector_table);
__vector_table_start = .;
__vector_table_vma_base_address = .;
KEEP(*(.isr_vector))
. = ALIGN(0x10);
_evector_table = .;
} >ram
.boot_code : ALIGN(0x10) /* When all code in RAM, no requirement for this section- but adds clarity when looking at .lst file */
{
*(.boot_code)
. = ALIGN(0x10);
} >ram
.text :
ALIGN(0x10)
{
CREATE_OBJECT_SYMBOLS
__text_load = LOADADDR(.text);
__text_start = .;
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
. = ALIGN(0x4);
/* These are for running static constructors and destructors under ELF. */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.vector_table))
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >ram
__exidx_end = .;
_etext = .;
PROVIDE(__text_end = .);
.data :
ALIGN(0x10)
{
__data_load = LOADADDR (.data);
_sidata = LOADADDR (.data);
__data_start = .;
_sdata = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
_edata = .;
} >ram
.bss : ALIGN(0x10)
{
__bss_start__ = . ;
_sbss = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end__ = .;
_end = .;
__end = _end;
_ebss = .;
PROVIDE(end = .);
} >ram
.heap : ALIGN(0x10)
{
__heap_start__ = .;
. += MIN_SIZE_HEAP; /* will generate error if this minimum size not available */
. += ((ABSOLUTE(RAM_START_ADDRESS) + RAM_SIZE - MAIN_STACK_SIZE) - .); /* assumes stack starts after heap */
_eheap = .;
} >ram
.stack : ALIGN(0x10)
{
__stack_start__ = .;
. += MAIN_STACK_SIZE;
_estack = .;
} >ram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
}

238
bsp/smartfusion2/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-external-ram.ld Normal file
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@@ -0,0 +1,238 @@
/*******************************************************************************
* (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
*
* file name : debug-in-microsemi-smartfusion2-external-ram.ld
* SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
* debug image executing in external eRAM.
*
* Some current (April 2015) dev kit memory map possibilities are
* --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
* --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
* --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
* --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
* --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
* --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
* --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
* --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
* --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
* --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
* --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
* --Some older physical memory map possibilities are
* --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
* --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
* --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
*
* Example linker scripts use lowest practical values so will work accross dev kits
* eNVM=256KB eRAM=64KB External memory = 64MB
*
* On reset, the eNVM region is mapped to 0x00000000
* This is changed below by setting the __smartfusion2_memory_remap variable as required.
* Options are detailed below.
*
* SVN $Revision: 7419 $
* SVN $Date: 2015-05-15 21:20:21 +0530 (Fri, 15 May 2015) $
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lc -lgcc -lm)
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SEARCH_DIR(.)
__DYNAMIC = 0;
/*******************************************************************************
* Start of board customization.
*******************************************************************************/
MEMORY
{
/*
* In general, example LD scripts use lowest common memory footprint
* accross dev boards so will work with all devices. Currently this is 64MB
* Program and data space is split evenly in this example 32MB each
*/
/* SmartFusion2 internal eSRAM */
esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
/* SmartFusion2 development board external RAM */
external_ram (rwx) : ORIGIN = 0x00000000, LENGTH = 32m
/* External MDDR RAM used for data section. */
/* Must be enough room allocated for data section between 0xA0000000 and data_external_ram */
data_external_ram (rw) : ORIGIN = 0xA2000000, LENGTH = 32m
}
ESRAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
ESRAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
MAIN_STACK_SIZE = 64k; /* Cortex main stack size. */
MIN_SIZE_HEAP = 64k; /* needs to be calculated for your application */
TOP_OF_MDDR = 0xA4000000; /* Top address of the external MDDR memory. */
/*******************************************************************************
* End of board customization.
*******************************************************************************/
/*PROVIDE (__main_ram_size = ESRAM_SIZE); */
PROVIDE (__main_stack_start = ESRAM_START_ADDRESS + ESRAM_SIZE);
PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
PROVIDE (_estack = __main_stack_start);
PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
/*
* Remap instruction for startup code and debugger.
* set __smartfusion2_memory_remap to one of the following:
* 0: remap eNVM to address 0x00000000 Production mode or debugging from eNVM
* 1: remap eSRAM to address 0x00000000 Debugging from eSRAM
* 2: remap external DDR memory to address 0x00000000 Debugging from DDR memory
*/
PROVIDE (__smartfusion2_memory_remap = 2);
SECTIONS
{
.vector_table : ALIGN(0x10)
{
__vector_table_load = LOADADDR(.vector_table);
__vector_table_start = .;
__vector_table_vma_base_address = .; /* required by debugger for start address */
KEEP(*(.isr_vector))
. = ALIGN(0x10);
_evector_table = .;
} >external_ram
.text : ALIGN(0x10)
{
CREATE_OBJECT_SYMBOLS
__text_load = LOADADDR(.text);
__text_start = .;
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
. = ALIGN(0x4);
/* These are for running static constructors and destructors under ELF. */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.vector_table))
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >external_ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >external_ram
__exidx_end = .;
_etext = .;
PROVIDE(__text_end = .);
.data : ALIGN(0x10)
{
__data_load = LOADADDR (.data);
_sidata = LOADADDR (.data);
__data_start = .;
_sdata = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
_edata = .;
} >data_external_ram
.bss : ALIGN(0x10)
{
__bss_start__ = . ;
_sbss = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end__ = .;
_end = .;
__end = _end;
_ebss = .;
PROVIDE(end = .);
} >data_external_ram
.heap : ALIGN(0x10)
{
__heap_start__ = .;
. += MIN_SIZE_HEAP; /* will generate error if this minimum size not available */
. += (ABSOLUTE(TOP_OF_MDDR) - . );
. = ALIGN(0x10);
_eheap = .;
} >data_external_ram
.stack : ALIGN(0x10)
{
__stack_start__ = .;
. += MAIN_STACK_SIZE;
. = ALIGN(0x10);
_estack = .;
} >esram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
}

241
bsp/smartfusion2/CMSIS/startup_gcc/production-smartfusion2-execute-in-place.ld Normal file
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/*******************************************************************************
* (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
*
* file name : production-smartfusion2-execute-in-place.ld
* SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
* image executing in SmartFusion2 internal eNVM.
*
* Some current (April 2015) dev kit memory map possibilities are
* --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
* --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
* --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
* --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
* --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
* --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
* --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
* --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
* --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
* --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
* --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
* --Some older physical memory map possibilities are
* --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
* --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
* --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
*
* Example linker scripts use lowest practicl values so will work accross dev kits
* eNVM=256KB eRAM=64KB External memory = 64MB
*
* On reset, the eNVM region is mapped to 0x00000000
* This is changed below by setting the __smartfusion2_memory_remap variable as required.
* Options are detailed below.
*
* SVN $Revision: 7454 $
* SVN $Date: 2015-06-08 20:28:07 +0530 (Mon, 08 Jun 2015) $
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lc -lgcc -lm)
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SEARCH_DIR(.)
__DYNAMIC = 0;
/*******************************************************************************
* Start of board customization.
*******************************************************************************/
MEMORY
{
/*
* In general, example LD scripts use lowest common memory footprint
* so will work with all devices.
*/
/*
* WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
* the name of the type of flash memory are all in a specific order.
* Please do not modify that comment line, in order to ensure
* debugging of your application will use the flash memory correctly.
*/
/* SOFTCONSOLE FLASH USE: microsemi-smartfusion2-envm */
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256k
/* SmartFusion2 internal eSRAM */
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
}
RAM_START_ADDRESS = 0x20000000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
MAIN_STACK_SIZE = 4k; /* Cortex main stack size. */
MIN_SIZE_HEAP = 4k; /* needs to be calculated for your application */
/*******************************************************************************
* End of board customization.
*******************************************************************************/
PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
PROVIDE (_estack = __main_stack_start);
PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
/*
* Remap instruction for startup code and debugger:
* 0: remap eNVM to address 0x00000000
* 1: remap eSRAM to address 0x00000000
* 2: remap external DDR memory to address 0x00000000
*/
PROVIDE (__smartfusion2_memory_remap = 0);
SECTIONS
{
.vector_table :
{
__vector_table_load = LOADADDR(.vector_table);
__vector_table_start = .;
__vector_table_vma_base_address = .;
KEEP(*(.isr_vector))
. = ALIGN(0x10);
_evector_table = .;
} >rom
.boot_code : ALIGN(0x10) /* When all code in NVRAM, no requirement for this section- but adds clarity when looking at .lst file */
{
*(.boot_code)
. = ALIGN(0x10);
} >rom
.text : ALIGN(0x10)
{
CREATE_OBJECT_SYMBOLS
__text_load = LOADADDR(.text);
__text_start = .;
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
. = ALIGN(0x4);
/* These are for running static constructors and destructors under ELF. */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.vector_table))
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >rom
__exidx_end = .;
_etext = .;
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
_sidata = LOADADDR (.data);
__data_start = .;
_sdata = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
_edata = .;
} >ram AT>rom
.bss : ALIGN(0x10)
{
__bss_start__ = . ;
_sbss = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end__ = .;
_end = .;
__end = _end;
_ebss = .;
PROVIDE(end = .);
} >ram AT>rom
.heap : ALIGN(0x10)
{
__heap_start__ = .;
. += MIN_SIZE_HEAP; /* will generate error if this minimum size not available */
. += ((ABSOLUTE(RAM_START_ADDRESS) + RAM_SIZE - MAIN_STACK_SIZE) - .); /* assumes stack starts after heap */
_eheap = .;
} >ram
.stack : ALIGN(0x10)
{
__stack_start__ = .;
. += MAIN_STACK_SIZE;
_estack = .;
} >ram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

260
bsp/smartfusion2/CMSIS/startup_gcc/production-smartfusion2-relocate-to-external-ram.ld Normal file
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@@ -0,0 +1,260 @@
/*******************************************************************************
* (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
*
* file name : production-smartfusion2-relocate-to-external-ram.ld
* SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
* image which is copied from internal eNVM to external RAM during boot-up.
*
* Some current (April 2015) dev kit memory map possibilities are
* --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
* --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
* --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
* --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
* --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
* --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
* --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
* --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
* --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
* --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
* --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
* --Some older physical memory map possibilities are
* --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
* --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
* --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
*
* Example linker scripts use lowest practicl values so will work accross dev kits
* eNVM=256KB eRAM=64KB External memory = 64MB
*
* On reset, the eNVM region is mapped to 0x00000000
* This is changed below by setting the __smartfusion2_memory_remap variable as required.
* Options are detailed below.
*
* SVN $Revision: 7419 $
* SVN $Date: 2015-05-15 21:20:21 +0530 (Fri, 15 May 2015) $
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lc -lgcc -lm)
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SEARCH_DIR(.)
__DYNAMIC = 0;
/*******************************************************************************
* Start of board customization.
*******************************************************************************/
MEMORY
{
/*
* In general, example LD scripts use lowest common memory footprint
* so will work with all devices.
*/
/*
* WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
* the name of the type of flash memory are all in a specific order.
* Please do not modify that comment line, in order to ensure
* debugging of your application will use the flash memory correctly.
*/
/* SOFTCONSOLE FLASH USE: microsemi-smartfusion2-envm */
rom (rx) : ORIGIN = 0x60000000, LENGTH = 256k
/* External MDDR RAM used for data section. */
/* 0xA0000000 where external memory starts */
/* first 0x00FFFFF reserved for relocated progam */
/* Locate external RX data above reserved program area */
/* !!! This must not overlap with external_ram when MDDR is remapped to 0x00000000.!!! */
data_external_ram (rw) : ORIGIN = 0xA2000000, LENGTH = 32m
/* SmartFusion2 development board external RAM */
external_ram (rwx) : ORIGIN = 0x00000000, LENGTH = 32m
/* SmartFusion2 internal eSRAM */
esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
}
ESRAM_START_ADDRESS = 0x20000000; /* Must be the same value as MEMORY region esram ORIGIN above. */
ESRAM_SIZE = 64k; /* Must be the same value as MEMORY region esram LENGTH above. */
MAIN_STACK_SIZE = 64k; /* Cortex main stack size. */
MIN_SIZE_HEAP = 64k; /* needs to be calculated for your application */
TOP_OF_MDDR = 0xA4000000; /* Top address of the external MDDR memory. */
/*******************************************************************************
* End of board customization.
*******************************************************************************/
PROVIDE (__main_stack_start = ESRAM_START_ADDRESS + ESRAM_SIZE);
PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
PROVIDE (_estack = __main_stack_start);
PROVIDE (__mirrored_nvm = 0); /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
/*
* Remap instruction for startup code and debugger.
* set __smartfusion2_memory_remap to one of the following:
* 0: remap eNVM to address 0x00000000 Production mode or debugging from eNVM
* 1: remap eSRAM to address 0x00000000 Debugging from eSRAM
* 2: remap external DDR memory to address 0x00000000 Debugging from DDR memory
*/
PROVIDE (__smartfusion2_memory_remap = 2);
SECTIONS
{
.vector_table : ALIGN(0x10)
{
__vector_table_load = LOADADDR(.vector_table);
__vector_table_start = .;
__vector_table_vma_base_address = .;
KEEP(*(.isr_vector))
. = ALIGN(0x10);
_evector_table = .;
} >external_ram AT>rom
/* all data and code run/used before reloaction must be located here */
.boot_code : ALIGN(0x10)
{
*(.boot_code) /* reset handler */
*system_m2sxxx.o(.text*) /* SystemInit() - called before relocation to RAM so keep in ROM */
*sys_config.o(.rodata*)
*sys_config_SERDESIF_?.o(.rodata*) /* data- used to configure external memeory before use */
/* note ? is a wildcard, can be upto 4 instances */
*mscc_post_hw_cfg_init.o /* used on startup */
*ecc_error_handler.o(.text*) /* do we need this???? */
. = ALIGN(0x10);
} >rom
.text : ALIGN(0x10)
{
CREATE_OBJECT_SYMBOLS
__text_load = LOADADDR(.text);
__text_start = .;
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
. = ALIGN(0x4);
/* These are for running static constructors and destructors under ELF. */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.vector_table))
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >external_ram AT>rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >external_ram AT>rom
__exidx_end = .;
_etext = .;
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
_sidata = LOADADDR (.data);
__data_start = .;
_sdata = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
_edata = .;
} >data_external_ram AT>rom
.bss : ALIGN(0x10)
{
__bss_start__ = . ;
_sbss = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end__ = .;
_end = .;
__end = _end;
_ebss = .;
PROVIDE(end = .);
} >data_external_ram AT>rom
.heap : ALIGN(0x10)
{
__heap_start__ = .;
. += MIN_SIZE_HEAP; /* will generate error if this minimum size not available */
. += (ABSOLUTE(TOP_OF_MDDR) - . );
_eheap = .;
} >data_external_ram
.stack : ALIGN(0x10)
{
__stack_start__ = .;
. += MAIN_STACK_SIZE;
_estack = .;
} >esram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

1297
bsp/smartfusion2/CMSIS/startup_gcc/startup_m2sxxx.S Normal file
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212
bsp/smartfusion2/CMSIS/sys_init_cfg_types.h Normal file
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@@ -0,0 +1,212 @@
/*******************************************************************************
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
*
*
*
* SVN $Revision: 4410 $
* SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $
*/
#ifndef SYSTEM_INIT_CFG_TYPES_H_
#define SYSTEM_INIT_CFG_TYPES_H_
#ifdef __cplusplus
extern "C" {
#endif
/*============================================================================*/
/* DDR Configuration */
/*============================================================================*/
typedef struct
{
/*--------------------------------------------------------------------------
* DDR Controller registers.
*/
struct
{
uint16_t DYN_SOFT_RESET_CR;
uint16_t RESERVED0;
uint16_t DYN_REFRESH_1_CR;
uint16_t DYN_REFRESH_2_CR;
uint16_t DYN_POWERDOWN_CR;
uint16_t DYN_DEBUG_CR;
uint16_t MODE_CR;
uint16_t ADDR_MAP_BANK_CR;
uint16_t ECC_DATA_MASK_CR;
uint16_t ADDR_MAP_COL_1_CR;
uint16_t ADDR_MAP_COL_2_CR;
uint16_t ADDR_MAP_ROW_1_CR;
uint16_t ADDR_MAP_ROW_2_CR;
uint16_t INIT_1_CR;
uint16_t CKE_RSTN_CYCLES_1_CR;
uint16_t CKE_RSTN_CYCLES_2_CR;
uint16_t INIT_MR_CR;
uint16_t INIT_EMR_CR;
uint16_t INIT_EMR2_CR;
uint16_t INIT_EMR3_CR;
uint16_t DRAM_BANK_TIMING_PARAM_CR;
uint16_t DRAM_RD_WR_LATENCY_CR;
uint16_t DRAM_RD_WR_PRE_CR;
uint16_t DRAM_MR_TIMING_PARAM_CR;
uint16_t DRAM_RAS_TIMING_CR;
uint16_t DRAM_RD_WR_TRNARND_TIME_CR;
uint16_t DRAM_T_PD_CR;
uint16_t DRAM_BANK_ACT_TIMING_CR;
uint16_t ODT_PARAM_1_CR;
uint16_t ODT_PARAM_2_CR;
uint16_t ADDR_MAP_COL_3_CR;
uint16_t MODE_REG_RD_WR_CR;
uint16_t MODE_REG_DATA_CR;
uint16_t PWR_SAVE_1_CR;
uint16_t PWR_SAVE_2_CR;
uint16_t ZQ_LONG_TIME_CR;
uint16_t ZQ_SHORT_TIME_CR;
uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;
uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;
uint16_t PERF_PARAM_1_CR;
uint16_t HPR_QUEUE_PARAM_1_CR;
uint16_t HPR_QUEUE_PARAM_2_CR;
uint16_t LPR_QUEUE_PARAM_1_CR;
uint16_t LPR_QUEUE_PARAM_2_CR;
uint16_t WR_QUEUE_PARAM_CR;
uint16_t PERF_PARAM_2_CR;
uint16_t PERF_PARAM_3_CR;
uint16_t DFI_RDDATA_EN_CR;
uint16_t DFI_MIN_CTRLUPD_TIMING_CR;
uint16_t DFI_MAX_CTRLUPD_TIMING_CR;
uint16_t DFI_WR_LVL_CONTROL_1_CR;
uint16_t DFI_WR_LVL_CONTROL_2_CR;
uint16_t DFI_RD_LVL_CONTROL_1_CR;
uint16_t DFI_RD_LVL_CONTROL_2_CR;
uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR;
uint16_t DYN_SOFT_RESET_CR2;
uint16_t AXI_FABRIC_PRI_ID_CR;
} ddrc;
/*--------------------------------------------------------------------------
* DDR PHY configuration registers
*/
struct
{
uint16_t LOOPBACK_TEST_CR;
uint16_t BOARD_LOOPBACK_CR;
uint16_t CTRL_SLAVE_RATIO_CR;
uint16_t CTRL_SLAVE_FORCE_CR;
uint16_t CTRL_SLAVE_DELAY_CR;
uint16_t DATA_SLICE_IN_USE_CR;
uint16_t LVL_NUM_OF_DQ0_CR;
uint16_t DQ_OFFSET_1_CR;
uint16_t DQ_OFFSET_2_CR;
uint16_t DQ_OFFSET_3_CR;
uint16_t DIS_CALIB_RST_CR;
uint16_t DLL_LOCK_DIFF_CR;
uint16_t FIFO_WE_IN_DELAY_1_CR;
uint16_t FIFO_WE_IN_DELAY_2_CR;
uint16_t FIFO_WE_IN_DELAY_3_CR;
uint16_t FIFO_WE_IN_FORCE_CR;
uint16_t FIFO_WE_SLAVE_RATIO_1_CR;
uint16_t FIFO_WE_SLAVE_RATIO_2_CR;
uint16_t FIFO_WE_SLAVE_RATIO_3_CR;
uint16_t FIFO_WE_SLAVE_RATIO_4_CR;
uint16_t GATELVL_INIT_MODE_CR;
uint16_t GATELVL_INIT_RATIO_1_CR;
uint16_t GATELVL_INIT_RATIO_2_CR;
uint16_t GATELVL_INIT_RATIO_3_CR;
uint16_t GATELVL_INIT_RATIO_4_CR;
uint16_t LOCAL_ODT_CR;
uint16_t INVERT_CLKOUT_CR;
uint16_t RD_DQS_SLAVE_DELAY_1_CR;
uint16_t RD_DQS_SLAVE_DELAY_2_CR;
uint16_t RD_DQS_SLAVE_DELAY_3_CR;
uint16_t RD_DQS_SLAVE_FORCE_CR;
uint16_t RD_DQS_SLAVE_RATIO_1_CR;
uint16_t RD_DQS_SLAVE_RATIO_2_CR;
uint16_t RD_DQS_SLAVE_RATIO_3_CR;
uint16_t RD_DQS_SLAVE_RATIO_4_CR;
uint16_t WR_DQS_SLAVE_DELAY_1_CR;
uint16_t WR_DQS_SLAVE_DELAY_2_CR;
uint16_t WR_DQS_SLAVE_DELAY_3_CR;
uint16_t WR_DQS_SLAVE_FORCE_CR;
uint16_t WR_DQS_SLAVE_RATIO_1_CR;
uint16_t WR_DQS_SLAVE_RATIO_2_CR;
uint16_t WR_DQS_SLAVE_RATIO_3_CR;
uint16_t WR_DQS_SLAVE_RATIO_4_CR;
uint16_t WR_DATA_SLAVE_DELAY_1_CR;
uint16_t WR_DATA_SLAVE_DELAY_2_CR;
uint16_t WR_DATA_SLAVE_DELAY_3_CR;
uint16_t WR_DATA_SLAVE_FORCE_CR;
uint16_t WR_DATA_SLAVE_RATIO_1_CR;
uint16_t WR_DATA_SLAVE_RATIO_2_CR;
uint16_t WR_DATA_SLAVE_RATIO_3_CR;
uint16_t WR_DATA_SLAVE_RATIO_4_CR;
uint16_t WRLVL_INIT_MODE_CR;
uint16_t WRLVL_INIT_RATIO_1_CR;
uint16_t WRLVL_INIT_RATIO_2_CR;
uint16_t WRLVL_INIT_RATIO_3_CR;
uint16_t WRLVL_INIT_RATIO_4_CR;
uint16_t WR_RD_RL_CR;
uint16_t RDC_FIFO_RST_ERRCNTCLR_CR;
uint16_t RDC_WE_TO_RE_DELAY_CR;
uint16_t USE_FIXED_RE_CR;
uint16_t USE_RANK0_DELAYS_CR;
uint16_t USE_LVL_TRNG_LEVEL_CR;
uint16_t CONFIG_CR;
uint16_t RD_WR_GATE_LVL_CR;
uint16_t DYN_RESET_CR;
} phy;
/*--------------------------------------------------------------------------
* FIC-64 registers
* These registers are 16-bit wide and 32-bit aligned.
*/
struct
{
uint16_t NB_ADDR_CR;
uint16_t NBRWB_SIZE_CR;
uint16_t WB_TIMEOUT_CR;
uint16_t HPD_SW_RW_EN_CR;
uint16_t HPD_SW_RW_INVAL_CR;
uint16_t SW_WR_ERCLR_CR;
uint16_t ERR_INT_ENABLE_CR;
uint16_t NUM_AHB_MASTERS_CR;
uint16_t LOCK_TIMEOUTVAL_1_CR;
uint16_t LOCK_TIMEOUTVAL_2_CR;
uint16_t LOCK_TIMEOUT_EN_CR;
} fic;
} ddr_subsys_cfg_t;
/*============================================================================*/
/* FDDR Configuration */
/*============================================================================*/
typedef struct
{
uint16_t PLL_CONFIG_LOW_1;
uint16_t PLL_CONFIG_LOW_2;
uint16_t PLL_CONFIG_HIGH;
uint16_t FACC_CLK_EN;
uint16_t FACC_MUX_CONFIG;
uint16_t FACC_DIVISOR_RATIO;
uint16_t PLL_DELAY_LINE_SEL;
uint16_t SOFT_RESET;
uint16_t IO_CALIB;
uint16_t INTERRUPT_ENABLE;
uint16_t AXI_AHB_MODE_SEL;
uint16_t PHY_SELF_REF_EN;
} fddr_sysreg_t;
/*============================================================================*/
/* PCI Express Bridge IP Core configuration. */
/*============================================================================*/
typedef struct
{
uint32_t * p_reg;
uint32_t value;
} cfg_addr_value_pair_t;
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_INIT_CFG_TYPES_H_ */

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49
bsp/smartfusion2/CMSIS/system_m2sxxx.h Normal file
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/*******************************************************************************
* (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 CMSIS system initialization.
*
* SVN $Revision: 5280 $
* SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
*/
#ifndef SYSTEM_M2SXXX_H
#define SYSTEM_M2SXXX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Standard CMSIS global variables. */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/* SmartFusion2 specific clocks. */
extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */
extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */
extern uint32_t g_FrequencyPCLK2; /*!< Clock frequency of APB bus 2. */
extern uint32_t g_FrequencyFIC0; /*!< Clock frequecny of FPGA fabric interface controller 1. */
extern uint32_t g_FrequencyFIC1; /*!< Clock frequecny of FPGA fabric inteface controller 2. */
extern uint32_t g_FrequencyFIC64; /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
/***************************************************************************//**
* The SystemInit() is a standard CMSIS function called during system startup.
* It is meant to perform low level hardware setup such as configuring DDR and
* SERDES controllers.
*/
void SystemInit(void);
/***************************************************************************//**
* The SystemCoreClockUpdate() is a standard CMSIS function which can be called
* by the application in order to ensure that the SystemCoreClock global
* variable contains the up to date Cortex-M3 core frequency. Calling this
* function also updates the global variables containing the frequencies of the
* APB busses connecting the peripherals.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

26
bsp/smartfusion2/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "drivers/Kconfig"
config SOC_SF2_M2S010
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y

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## 移植RT-Thread到Microsemi SmartFusion2系列FPGA芯片
### 1. BSP简介
移植 RT-Thread 操作系统到一款 **FPGA 芯片——M2S010** ，该芯片属于 [Microsemi](https://www.microsemi.com/)（现Microchip）SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 **ARM® Cortex™-M3 内核的 MCU**，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。
> 关于 Microsemi，第三大 FPGA 厂商，原 Actel 半导体，2010 年，Microsemi 收购 Actel，2018 年， Microchip 收购 Microsemi。
SmartFusion2 内部框图
![Microsemi_Smartfusion2_BD](figures/Microsemi_Smartfusion2_BD.jpg)
### 2. 外设支持
移植了 RT-Thread 内核，支持线程调度、线程间同步和通信等，目前已经完成了PIN、Serial设备驱动，FinSH组件默认使用uart0设备。
| **片上外设** | **支持情况** |
| :----------------- | :----------: |
| GPIO | 支持 |
| UART | 支持 |
| SPI | 暂不支持 |
| I2C | 暂不支持 |
| RTC | 暂不支持 |
| USB | 暂不支持 |
### 3. scons构建系统
通过加入`rtconfig.py`，`SConstruct`，`SConscript`文件，可支持scons构建系统，可以输入`scons`调用env工具中包含的arm-gcc编译器构建工程，支持以下scons命令：
- `scons`：使用arm-gcc编译BSP
- `scons -c`：清除执行 scons 时生成的临时文件和目标文件。
- `scons --target=mdk4`：重新生成Keil MDK4环境下的工程。
- `scons --target=mdk5`：重新生成Keil MDK5环境下的工程。
- `scons --dist`：打包BSP工程，包括RT-Thread源码及BSP相关工程文件。
添加Kconfig文件，用于生成rtconfig.h。
### 4. 使用说明
#### 4.1 FPGA 工程设计
FPGA 部分使用 SmartDesign 图形化设计，不需要写 HDL 代码，时钟来自外部 50M 晶体输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示：
![](figures/top_sd.jpg)
MSS 部分仅使用到了GPIO 和UART，GPIO_0配置成输出输出模式用于驱动LED。
配置完成的 FPGA 工程文件下载：[sf2_fpga_prj.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/sf2_fpga_prj.rar)
#### 4.2 ARM 程序设计
ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack)
如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi.M2Sxxx.1.0.64.pack)
在官方生成的示例工程目录下，添加 RT-Thread 相关组件，并实现一些对接函数，最终的文件结构：
![](figures/files.jpg)
### 5. 下载和运行
为了能使用 ARM 调试器连接到 ARM 内核，而不是 FPGA，需要把 JTAG_SEL 引脚置为低电平。使用 ARM 调试器，如 JLink，对应连接 JTAG 口的 TMS、TCK、GND 引脚，如果连接正常，可以检测到 ARM 芯片，如下图所示：
![](figures/jlink-ob.jpg)
配置对应的 Flash 编程算法：
![](figures/flash.jpg)
下载完成：
![](figures/finished.jpg)
如果编译 & 烧写无误，下载完成或者按下复位按键之后，会在串口上看到 RT-Thread 的启动 LOG 信息：
```c
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Jun 2 2020
2006 - 2020 Copyright by rt-thread team
msh >
```
![](figures/log.jpg)
### 6. 注意事项
- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 IDE。
- ARM 开发环境基于 Keil MDK 5.26，如果使用SoftConsole IDE ，需要修改 `libcpu` 内的文件。
- 调试内部 ARM 核，需要把 JTAG_SEL 拉低，否则调试器连接不上。
- 使用 SoftConsole 开发环境可以直接使用官方的 Flash Pro 调试器进行 ARM 程序的调试。
- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`bsp\smartfusion2\libraries\sys_config`文件夹下的文件 。
### 7. 参考资料
- [学习路线 - RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710)
### 8. 联系我
- Github：[whik](https://github.com/whik)
- E-Mail：wangchao149@foxmail.com

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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bsp/smartfusion2/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

10
bsp/smartfusion2/applications/SConscript Normal file
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from building import *
import rtconfig
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

16
bsp/smartfusion2/applications/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}

32
bsp/smartfusion2/applications/main.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN 0
int main(void)
{
int count = 1;
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while(count++)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

10
bsp/smartfusion2/board/SConscript Normal file
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from building import *
import rtconfig
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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bsp/smartfusion2/board/board.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#define _SCB_BASE (0xE000E010UL)
#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
extern void SystemCoreClockUpdate(void);
extern uint32_t SystemCoreClock;
static uint32_t _SysTick_Config(rt_uint32_t ticks)
{
if ((ticks - 1) > 0xFFFFFF)
{
return 1;
}
_SYSTICK_LOAD = ticks - 1;
_SYSTICK_PRI = 0xFF;
_SYSTICK_VAL = 0;
_SYSTICK_CTRL = 0x07;
return 0;
}
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
#define RT_HEAP_SIZE 1024
static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
RT_WEAK void *rt_heap_begin_get(void)
{
return rt_heap;
}
RT_WEAK void *rt_heap_end_get(void)
{
return rt_heap + RT_HEAP_SIZE;
}
#endif
/* This function will initial your board. */
void rt_hw_board_init()
{
/* System Clock Update */
SystemCoreClockUpdate();
/* System Tick Configuration */
_SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
#endif
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}

27
bsp/smartfusion2/board/config.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#include "config.h"
/* hardware initialization */
void boardInit(void)
{
/* disable watchdog timer */
SYSREG->WDOG_CR = 0;
}
INIT_BOARD_EXPORT(boardInit);
/* custom finish command */
extern uint32_t SystemCoreClock;
void sayHello(void)
{
rt_kprintf("Hello RT-Thread! By Microsemi SmartFusion2 Family FPGA-M2S010.\r\n");
rt_kprintf("MSS System Core Clock: %d Hz.\r\n", SystemCoreClock);
}
MSH_CMD_EXPORT(sayHello, "say hello to console");

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bsp/smartfusion2/board/config.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#ifndef __CONFIG_H__
#define __CONFIG_H__
#include "mss_gpio.h"
#include "mss_uart.h"
#include <rthw.h>
#include <rtthread.h>
void sw0_isr(void *args);
void sw1_isr(void *args);
void boardInit(void);
void sayHello(void);
#endif

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menu "Hardware Drivers Config"
menu "On-chip Peripheral Drivers"
menu "UART Drivers"
config BSP_USING_UART0
bool "Enable MSS_UART0"
select RT_USING_SERIAL
default y
help
config MSS_UART0
config BSP_USING_UART1
bool "Enable MSS_UART1"
select RT_USING_SERIAL
default y
help
config MSS_UART1
config RT_CONSOLE_DEVICE_NAME
string "the device name for console"
default "uart0"
endmenu
menu "GPIO Drivers"
config BSP_USING_GPIO
bool "Enable MSS_GPIO"
select RT_USING_PIN
default y
help
config MSS_GPIO
endmenu
endmenu
endmenu

16
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from building import *
cwd = GetCurrentDir()
src = []
# add serial driver code
if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1'):
src += ['drv_uart.c']
if GetDepend('BSP_USING_GPIO'):
src += ['drv_gpio.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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bsp/smartfusion2/drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-09 whik first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "drv_gpio.h"
#ifdef BSP_USING_GPIO
static struct rt_pin_irq_hdr sf2_pin_irq_hdr_tab[] =
{
/* pin, hdr, mode, args */
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
/* configure an individual GPIO port */
static void sf2_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
uint32_t config;
switch (mode)
{
case PIN_MODE_OUTPUT:
config = MSS_GPIO_OUTPUT_MODE;
break;
case PIN_MODE_INPUT:
config = MSS_GPIO_INPUT_MODE;
break;
default:
config = MSS_GPIO_INOUT_MODE;
break;
}
MSS_GPIO_config((mss_gpio_id_t )pin, config);
}
static int sf2_pin_read(rt_device_t dev, rt_base_t pin)
{
uint32_t value;
value = MSS_GPIO_get_inputs() & (1<<pin);
return ((value) ? PIN_HIGH : PIN_LOW);
}
static void sf2_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
if (value == PIN_HIGH)
MSS_GPIO_set_output((mss_gpio_id_t )pin, 1);
else
MSS_GPIO_set_output((mss_gpio_id_t )pin, 0);
}
static rt_err_t sf2_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
level = rt_hw_interrupt_disable();
if (sf2_pin_irq_hdr_tab[pin].pin == pin &&
sf2_pin_irq_hdr_tab[pin].hdr == hdr &&
sf2_pin_irq_hdr_tab[pin].mode == mode &&
sf2_pin_irq_hdr_tab[pin].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (sf2_pin_irq_hdr_tab[pin].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
}
sf2_pin_irq_hdr_tab[pin].pin = pin;
sf2_pin_irq_hdr_tab[pin].hdr = hdr;
sf2_pin_irq_hdr_tab[pin].mode = mode;
sf2_pin_irq_hdr_tab[pin].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t sf2_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
level = rt_hw_interrupt_disable();
if (sf2_pin_irq_hdr_tab[pin].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
sf2_pin_irq_hdr_tab[pin].pin = -1;
sf2_pin_irq_hdr_tab[pin].hdr = RT_NULL;
sf2_pin_irq_hdr_tab[pin].mode = 0;
sf2_pin_irq_hdr_tab[pin].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t sf2_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
uint32_t mode = 0;
rt_base_t level;
if (enabled == PIN_IRQ_ENABLE)
{
level = rt_hw_interrupt_disable();
if (sf2_pin_irq_hdr_tab[pin].pin == -1)
{
rt_hw_interrupt_enable(level);
return -RT_ENOSYS;
}
switch(sf2_pin_irq_hdr_tab[pin].mode)
{
case PIN_IRQ_MODE_RISING :
mode = MSS_GPIO_IRQ_EDGE_POSITIVE;
break;
case PIN_IRQ_MODE_FALLING :
mode = MSS_GPIO_IRQ_EDGE_NEGATIVE;
break;
case PIN_IRQ_MODE_RISING_FALLING:
mode = MSS_GPIO_IRQ_EDGE_BOTH;
break;
case PIN_IRQ_MODE_HIGH_LEVEL :
mode = MSS_GPIO_IRQ_LEVEL_HIGH;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
mode = MSS_GPIO_IRQ_LEVEL_LOW;
break;
}
MSS_GPIO_config((mss_gpio_id_t )pin, MSS_GPIO_INPUT_MODE | mode);
MSS_GPIO_enable_irq((mss_gpio_id_t )pin);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
MSS_GPIO_config((mss_gpio_id_t )pin, MSS_GPIO_INPUT_MODE);
MSS_GPIO_disable_irq((mss_gpio_id_t )pin);
}
else
return -RT_ENOSYS;
return RT_EOK;
}
static const struct rt_pin_ops sf2_pin_ops =
{
sf2_pin_mode,
sf2_pin_write,
sf2_pin_read,
sf2_pin_attach_irq,
sf2_pin_detach_irq,
sf2_pin_irq_enable
};
int rt_hw_pin_init(void)
{
rt_err_t result = RT_EOK;
MSS_GPIO_init();
result = rt_device_pin_register("pin", &sf2_pin_ops, RT_NULL);
RT_ASSERT(result == RT_EOK);
return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(int pin)
{
MSS_GPIO_clear_irq((mss_gpio_id_t )pin);
if (sf2_pin_irq_hdr_tab[pin].hdr)
sf2_pin_irq_hdr_tab[pin].hdr(sf2_pin_irq_hdr_tab[pin].args);
}
void GPIO0_IRQHandler( void )
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(0);
/* leave interrupt */
rt_interrupt_leave();
}
void GPIO1_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(1);
rt_interrupt_leave();
}
void GPIO2_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(2);
rt_interrupt_leave();
}
void GPIO3_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(3);
rt_interrupt_leave();
}
void GPIO4_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(4);
rt_interrupt_leave();
}
void GPIO5_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(5);
rt_interrupt_leave();
}
void GPIO6_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(6);
rt_interrupt_leave();
}
void GPIO7_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(7);
rt_interrupt_leave();
}
void GPIO8_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(8);
rt_interrupt_leave();
}
void GPIO9_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(9);
rt_interrupt_leave();
}
void GPIO10_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(10);
rt_interrupt_leave();
}
void GPIO11_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(11);
rt_interrupt_leave();
}
void GPIO12_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(12);
rt_interrupt_leave();
}
void GPIO13_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(13);
rt_interrupt_leave();
}
void GPIO14_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(14);
rt_interrupt_leave();
}
void GPIO15_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(15);
rt_interrupt_leave();
}
void GPIO16_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(16);
rt_interrupt_leave();
}
void GPIO17_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(17);
rt_interrupt_leave();
}
void GPIO18_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(18);
rt_interrupt_leave();
}
void GPIO19_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(19);
rt_interrupt_leave();
}
void GPIO20_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(20);
rt_interrupt_leave();
}
void GPIO21_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(21);
rt_interrupt_leave();
}
void GPIO22_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(22);
rt_interrupt_leave();
}
void GPIO23_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(23);
rt_interrupt_leave();
}
void GPIO24_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(24);
rt_interrupt_leave();
}
void GPIO25_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(25);
rt_interrupt_leave();
}
void GPIO26_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(26);
rt_interrupt_leave();
}
void GPIO27_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(27);
rt_interrupt_leave();
}
void GPIO28_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(28);
rt_interrupt_leave();
}
void GPIO29_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(29);
rt_interrupt_leave();
}
void GPIO30_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(30);
rt_interrupt_leave();
}
void GPIO31_IRQHandler( void )
{
rt_interrupt_enter();
pin_irq_hdr(31);
rt_interrupt_leave();
}
#endif

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bsp/smartfusion2/drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include "mss_gpio.h"
int rt_hw_pin_init(void);
#endif

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bsp/smartfusion2/drivers/drv_uart.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_uart.h"
struct sf2_uart
{
mss_uart_instance_t *uart;
IRQn_Type irq;
};
struct sf2_uart uart0=
{
&g_mss_uart0,
UART0_IRQn,
};
struct rt_serial_device serial0;
void uart0_rx_handler(mss_uart_instance_t *this_uart)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
/* leave interrupt */
rt_interrupt_leave();
}
struct sf2_uart uart1=
{
&g_mss_uart1,
UART1_IRQn,
};
struct rt_serial_device serial1;
void uart1_rx_handler(mss_uart_instance_t *this_uart)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
/* leave interrupt */
rt_interrupt_leave();
}
static rt_err_t sf2_uart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
uint32_t baudRate;
uint8_t datBits, parity, stopBits;
uint8_t config;
struct sf2_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct sf2_uart *)serial->parent.user_data;
switch(cfg->data_bits)
{
case DATA_BITS_5: datBits = MSS_UART_DATA_5_BITS; break;
case DATA_BITS_6: datBits = MSS_UART_DATA_6_BITS; break;
case DATA_BITS_7: datBits = MSS_UART_DATA_7_BITS; break;
case DATA_BITS_8: datBits = MSS_UART_DATA_8_BITS; break;
default: datBits = MSS_UART_DATA_8_BITS; break;
}
switch(cfg->parity)
{
case PARITY_NONE: parity = MSS_UART_NO_PARITY; break;
case PARITY_EVEN: parity = MSS_UART_EVEN_PARITY; break;
case PARITY_ODD : parity = MSS_UART_ODD_PARITY; break;
default : parity = MSS_UART_NO_PARITY; break;
}
switch(cfg->stop_bits)
{
case STOP_BITS_1: stopBits = MSS_UART_ONE_STOP_BIT; break;
case STOP_BITS_2: stopBits = MSS_UART_TWO_STOP_BITS; break;
case STOP_BITS_3: stopBits = MSS_UART_ONEHALF_STOP_BIT; break;
default : stopBits = MSS_UART_ONE_STOP_BIT;
}
baudRate = cfg->baud_rate;
config = datBits | parity | stopBits;
MSS_UART_init(uart->uart, baudRate, config);
if(uart->uart == &g_mss_uart0)
MSS_UART_set_rx_handler(uart->uart, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
else
MSS_UART_set_rx_handler(uart->uart, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
return RT_EOK;
}
static rt_err_t sf2_uart_control(struct rt_serial_device *serial,
int cmd, void *arg)
{
struct sf2_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct sf2_uart*)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
NVIC_DisableIRQ(uart->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
NVIC_EnableIRQ(uart->irq);
break;
}
return RT_EOK;
}
static int sf2_uart_putc(struct rt_serial_device *serial, char c)
{
struct sf2_uart* uart;
uint32_t tx_ready;
RT_ASSERT(serial != RT_NULL);
uart = (struct sf2_uart*)serial->parent.user_data;
do {
tx_ready = uart->uart->hw_reg->LSR & 0x20u;
} while(!tx_ready);
uart->uart->hw_reg->THR = c;
return 1;
}
static int sf2_uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
uint8_t err_status;
struct sf2_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct sf2_uart*)serial->parent.user_data;
err_status = MSS_UART_get_rx_status(uart->uart);
if(MSS_UART_NO_ERROR == err_status)
MSS_UART_get_rx(uart->uart, (uint8_t *)&ch, 1);
return ch;
}
static const struct rt_uart_ops sf2_uart_ops =
{
sf2_uart_configure,
sf2_uart_control,
sf2_uart_putc,
sf2_uart_getc,
};
int rt_hw_uart_init(void)
{
rt_err_t result = RT_EOK;
struct sf2_uart* uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART0
uart = &uart0;
serial0.ops = &sf2_uart_ops;
/* default config: 115200, 8, no, 1 */
serial0.config = config;
result = rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
RT_ASSERT(result == RT_EOK);
#endif
#ifdef BSP_USING_UART1
uart = &uart1;
serial1.ops = &sf2_uart_ops;
/* default config: 115200, 8, no, 1 */
serial1.config = config;
result = rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
RT_ASSERT(result == RT_EOK);
#endif
return result;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);

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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-06 whik first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include "mss_uart.h"
void uart_rx_handler(mss_uart_instance_t *this_uart);
void uart0_rx_handler(mss_uart_instance_t * this_uart);
void uart1_rx_handler(mss_uart_instance_t * this_uart);
int rt_hw_uart_init(void);
#endif

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bsp/smartfusion2/libraries/SConscript Normal file
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from building import *
import rtconfig
cwd = GetCurrentDir()
src = [cwd + '/sys_config/sys_config.c']
src += [cwd + '/mss_gpio/mss_gpio.c']
src += [cwd + '/mss_uart/mss_uart.c']
CPPPATH = [cwd+'/sys_config']
CPPPATH += [cwd+'/mss_gpio']
CPPPATH += [cwd+'/mss_uart']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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bsp/smartfusion2/libraries/mss_gpio/mss_gpio.c Normal file
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/*******************************************************************************
* (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation.
*
* SVN $Revision: 7749 $
* SVN $Date: 2015-09-04 14:32:09 +0530 (Fri, 04 Sep 2015) $
*/
#include "mss_gpio.h"
#include "../../CMSIS/mss_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------*//**
* Defines.
*/
#define GPIO_INT_ENABLE_MASK ((uint32_t)0x00000008uL)
#define OUTPUT_BUFFER_ENABLE_MASK 0x00000004u
#define NB_OF_GPIO ((uint32_t)32)
/*-------------------------------------------------------------------------*//**
* Lookup table of GPIO configuration registers address indexed on GPIO ID.
*/
static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =
{
&(GPIO->GPIO_0_CFG),
&(GPIO->GPIO_1_CFG),
&(GPIO->GPIO_2_CFG),
&(GPIO->GPIO_3_CFG),
&(GPIO->GPIO_4_CFG),
&(GPIO->GPIO_5_CFG),
&(GPIO->GPIO_6_CFG),
&(GPIO->GPIO_7_CFG),
&(GPIO->GPIO_8_CFG),
&(GPIO->GPIO_9_CFG),
&(GPIO->GPIO_10_CFG),
&(GPIO->GPIO_11_CFG),
&(GPIO->GPIO_12_CFG),
&(GPIO->GPIO_13_CFG),
&(GPIO->GPIO_14_CFG),
&(GPIO->GPIO_15_CFG),
&(GPIO->GPIO_16_CFG),
&(GPIO->GPIO_17_CFG),
&(GPIO->GPIO_18_CFG),
&(GPIO->GPIO_19_CFG),
&(GPIO->GPIO_20_CFG),
&(GPIO->GPIO_21_CFG),
&(GPIO->GPIO_22_CFG),
&(GPIO->GPIO_23_CFG),
&(GPIO->GPIO_24_CFG),
&(GPIO->GPIO_25_CFG),
&(GPIO->GPIO_26_CFG),
&(GPIO->GPIO_27_CFG),
&(GPIO->GPIO_28_CFG),
&(GPIO->GPIO_29_CFG),
&(GPIO->GPIO_30_CFG),
&(GPIO->GPIO_31_CFG)
};
/*-------------------------------------------------------------------------*//**
* Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.
*/
static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =
{
GPIO0_IRQn,
GPIO1_IRQn,
GPIO2_IRQn,
GPIO3_IRQn,
GPIO4_IRQn,
GPIO5_IRQn,
GPIO6_IRQn,
GPIO7_IRQn,
GPIO8_IRQn,
GPIO9_IRQn,
GPIO10_IRQn,
GPIO11_IRQn,
GPIO12_IRQn,
GPIO13_IRQn,
GPIO14_IRQn,
GPIO15_IRQn,
GPIO16_IRQn,
GPIO17_IRQn,
GPIO18_IRQn,
GPIO19_IRQn,
GPIO20_IRQn,
GPIO21_IRQn,
GPIO22_IRQn,
GPIO23_IRQn,
GPIO24_IRQn,
GPIO25_IRQn,
GPIO26_IRQn,
GPIO27_IRQn,
GPIO28_IRQn,
GPIO29_IRQn,
GPIO30_IRQn,
GPIO31_IRQn
};
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_init
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_init( void )
{
uint32_t inc;
/* reset MSS GPIO hardware */
SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
SYSREG_GPIO_15_8_SOFTRESET_MASK |
SYSREG_GPIO_23_16_SOFTRESET_MASK |
SYSREG_GPIO_31_24_SOFTRESET_MASK);
/* Clear any previously pended MSS GPIO interrupt */
for(inc = 0U; inc < NB_OF_GPIO; ++inc)
{
NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
}
/* Take MSS GPIO hardware out of reset. */
SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
SYSREG_GPIO_15_8_SOFTRESET_MASK |
SYSREG_GPIO_23_16_SOFTRESET_MASK |
SYSREG_GPIO_31_24_SOFTRESET_MASK);
SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_config
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_config
(
mss_gpio_id_t port_id,
uint32_t config
)
{
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
*(g_config_reg_lut[gpio_idx]) = config;
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_set_output
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_set_output
(
mss_gpio_id_t port_id,
uint8_t value
)
{
uint32_t gpio_setting;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
gpio_setting = GPIO->GPIO_OUT;
gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
GPIO->GPIO_OUT = gpio_setting;
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_drive_inout
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_drive_inout
(
mss_gpio_id_t port_id,
mss_gpio_inout_state_t inout_state
)
{
uint32_t outputs_state;
uint32_t config;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
switch(inout_state)
{
case MSS_GPIO_DRIVE_HIGH:
/* Set output high */
outputs_state = GPIO->GPIO_OUT;
outputs_state |= (uint32_t)1 << gpio_idx;
GPIO->GPIO_OUT = outputs_state;
/* Enable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config |= OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
case MSS_GPIO_DRIVE_LOW:
/* Set output low */
outputs_state = GPIO->GPIO_OUT;
outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));
GPIO->GPIO_OUT = outputs_state;
/* Enable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config |= OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
case MSS_GPIO_HIGH_Z:
/* Disable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config &= ~OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
default:
ASSERT(0);
break;
}
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_enable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_enable_irq
(
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
cfg_value = *(g_config_reg_lut[gpio_idx]);
*(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);
NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_disable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_disable_irq
(
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
cfg_value = *(g_config_reg_lut[gpio_idx]);
*(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_clear_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_clear_irq
(
mss_gpio_id_t port_id
)
{
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;
}
__ASM volatile ("dsb");
}
#ifdef __cplusplus
}
#endif

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bsp/smartfusion2/libraries/mss_gpio/mss_gpio.h Normal file
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