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Merge pull request #4223 from iysheng/master

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[bsp][gd32103c-eval] Add gd32103c-eval bsp  [src/kservice.c] 更新打印提示時間信息
This commit is contained in:
Bernard Xiong
2021-01-05 09:24:26 +08:00
committed by GitHub
parent 9152c78353 821229f896
commit 84f19b84c5
78 changed files with 41062 additions and 1 deletions
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70
bsp/gd32103c-eval/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_GD32F1
bool
default y
config SOC_GD32103C
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_GD32F1
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
endmenu

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bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h Normal file
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39
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h Normal file
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/**
******************************************************************************
* @brief Configuration file.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CONF_H
#define __GD32F10X_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "gd32f10x_adc.h"
#include "gd32f10x_bkp.h"
#include "gd32f10x_can.h"
#include "gd32f10x_crc.h"
#include "gd32f10x_dac.h"
#include "gd32f10x_dma.h"
#include "gd32f10x_eth.h"
#include "gd32f10x_exmc.h"
#include "gd32f10x_exti.h"
#include "gd32f10x_fmc.h"
#include "gd32f10x_gpio.h"
#include "gd32f10x_i2c.h"
#include "gd32f10x_iwdg.h"
#include "gd32f10x_mcudbg.h"
#include "gd32f10x_misc.h"
#include "gd32f10x_pwr.h"
#include "gd32f10x_rcc.h"
#include "gd32f10x_rcu.h"
#include "gd32f10x_rtc.h"
#include "gd32f10x_sdio.h"
#include "gd32f10x_spi.h"
#include "gd32f10x_timer.h"
#include "gd32f10x_usart.h"
#include "gd32f10x_wwdg.h"
#endif /* __GD32F10X_CONF_H */

64
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h Normal file
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/**
******************************************************************************
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup GD32F10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_GD32F10X_H
#define __SYSTEM_GD32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup GD32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_GD32F10X_H */
/**
* @}
*/
/**
* @}
*/

213
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s Normal file
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/*
* File : isr_tab.s
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2021, RT-Thread Development Team
*
* Change Logs:
* Date Author Notes
* 2021-01-02 iysheng first implementation
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_isr_vectors
.section .isr_vector,"a",%progbits
.type g_isr_vectors, STT_OBJECT
.weak Reset_Handler
g_isr_vectors:
.word _estack /* Top of Stack */
.word Reset_Handler /* Reset Handler */
.word NMI_Handler /* NMI Handler */
.word HardFault_Handler /* Hard Fault Handler */
.word MemManage_Handler /* MPU Fault Handler */
.word BusFault_Handler /* Bus Fault Handler */
.word UsageFault_Handler /* Usage Fault Handler */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler /* SVCall Handler */
.word DebugMon_Handler /* Debug Monitor Handler */
.word 0 /* Reserved */
.word PendSV_Handler /* PendSV Handler */
.word SysTick_Handler /* SysTick Handler */
/* external interrupts handler */
.word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
.word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
.word TAMPER_IRQHandler /* 18:Tamper through EXTI Line detect */
.word RTC_IRQHandler /* 19:RTC through EXTI Line */
.word FMC_IRQHandler /* 20:FMC */
.word RCU_CTC_IRQHandler /* 21:RCU and CTC */
.word EXTI0_IRQHandler /* 22:EXTI Line 0 */
.word EXTI1_IRQHandler /* 23:EXTI Line 1 */
.word EXTI2_IRQHandler /* 24:EXTI Line 2 */
.word EXTI3_IRQHandler /* 25:EXTI Line 3 */
.word EXTI4_IRQHandler /* 26:EXTI Line 4 */
.word DMA0_Channel0_IRQHandler /* 27:DMA0 Channel0 */
.word DMA0_Channel1_IRQHandler /* 28:DMA0 Channel1 */
.word DMA0_Channel2_IRQHandler /* 29:DMA0 Channel2 */
.word DMA0_Channel3_IRQHandler /* 30:DMA0 Channel3 */
.word DMA0_Channel4_IRQHandler /* 31:DMA0 Channel4 */
.word DMA0_Channel5_IRQHandler /* 32:DMA0 Channel5 */
.word DMA0_Channel6_IRQHandler /* 33:DMA0 Channel6 */
.word ADC0_1_IRQHandler /* 34:ADC0 and ADC1 */
.word USBD_HP_CAN0_TX_IRQHandler /* 35:USBD HP and CAN0 TX */
.word USBD_LP_CAN0_RX0_IRQHandler /* 36:USBD LP and CAN0 RX0 */
.word CAN0_RX1_IRQHandler /* 37:CAN0 RX1 */
.word CAN0_EWMC_IRQHandler /* 38:CAN0 EWMC */
.word EXTI5_9_IRQHandler /* 39:EXTI5 to EXTI9 */
.word TIMER0_BRK_IRQHandler /* 40:TIMER0 Break */
.word TIMER0_UP_IRQHandler /* 41:TIMER0 Update */
.word TIMER0_TRG_CMT_IRQHandler /* 42:TIMER0 Trigger and Commutation */
.word TIMER0_Channel_IRQHandler /* 43:TIMER0 Channel Capture Compare */
.word TIMER1_IRQHandler /* 44:TIMER1 */
.word TIMER2_IRQHandler /* 45:TIMER2 */
.word TIMER3_IRQHandler /* 46:TIMER3 */
.word I2C0_EV_IRQHandler /* 47:I2C0 Event */
.word I2C0_ER_IRQHandler /* 48:I2C0 Error */
.word I2C1_EV_IRQHandler /* 49:I2C1 Event */
.word I2C1_ER_IRQHandler /* 50:I2C1 Error */
.word SPI0_IRQHandler /* 51:SPI0 */
.word SPI1_IRQHandler /* 52:SPI1 */
.word USART0_IRQHandler /* 53:USART0 */
.word USART1_IRQHandler /* 54:USART1 */
.word USART2_IRQHandler /* 55:USART2 */
.word EXTI10_15_IRQHandler /* 56:EXTI10 to EXTI15 */
.word RTC_Alarm_IRQHandler /* 57:RTC Alarm */
.word USBD_WKUP_IRQHandler /* 58:USBD Wakeup */
.word TIMER7_BRK_IRQHandler /* 59:TIMER7 Break */
.word TIMER7_UP_IRQHandler /* 60:TIMER7 Update */
.word TIMER7_TRG_CMT_IRQHandler /* 61:TIMER7 Trigger and Commutation */
.word TIMER7_Channel_IRQHandler /* 62:TIMER7 Channel Capture Compare */
.word ADC2_IRQHandler /* 63:ADC2 */
.word EXMC_IRQHandler /* 64:EXMC */
.word SDIO_IRQHandler /* 65:SDIO */
.word TIMER4_IRQHandler /* 66:TIMER4 */
.word SPI2_IRQHandler /* 67:SPI2 */
.word UART3_IRQHandler /* 68:UART3 */
.word UART4_IRQHandler /* 69:UART4 */
.word TIMER5_IRQHandler /* 70:TIMER5 */
.word TIMER6_IRQHandler /* 71:TIMER6 */
.word DMA1_Channel0_IRQHandler /* 72:DMA1 Channel0 */
.word DMA1_Channel1_IRQHandler /* 73:DMA1 Channel1 */
.word DMA1_Channel2_IRQHandler /* 74:DMA1 Channel2 */
.word DMA1_Channel3_4_IRQHandler /* 75:DMA1 Channel3 and Channel4 */
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, STT_FUNC
NMI_Handler:
b .
.weak MemManage_Handler
.type MemManage_Handler, STT_FUNC
MemManage_Handler:
b .
.weak BusFault_Handler
.type BusFault_Handler, STT_FUNC
BusFault_Handler:
b .
.weak UsageFault_Handler
.type UsageFault_Handler, STT_FUNC
UsageFault_Handler:
b .
.weak SVC_Handler
.type SVC_Handler, STT_FUNC
SVC_Handler:
b .
.weak DebugMon_Handler
.type DebugMon_Handler, STT_FUNC
DebugMon_Handler:
b .
.weak PendSV_Handler
.type PendSV_Handler, STT_FUNC
PendSV_Handler:
b .
.weak SysTick_Handler
.type SysTick_Handler, STT_FUNC
SysTick_Handler:
b .
.global default_irq_handler
.section .text.default_irq_handler,"ax",%progbits
.type default_irq_handler, STT_FUNC
default_irq_handler:
b .
.macro IRQ handler
.weak \handler
.set \handler, default_irq_handler
.endm
/* IQR Handler */
IRQ WWDGT_IRQHandler
IRQ LVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FMC_IRQHandler
IRQ RCU_CTC_IRQHandler
IRQ EXTI0_IRQHandler
IRQ EXTI1_IRQHandler
IRQ EXTI2_IRQHandler
IRQ EXTI3_IRQHandler
IRQ EXTI4_IRQHandler
IRQ DMA0_Channel0_IRQHandler
IRQ DMA0_Channel1_IRQHandler
IRQ DMA0_Channel2_IRQHandler
IRQ DMA0_Channel3_IRQHandler
IRQ DMA0_Channel4_IRQHandler
IRQ DMA0_Channel5_IRQHandler
IRQ DMA0_Channel6_IRQHandler
IRQ ADC0_1_IRQHandler
IRQ USBD_HP_CAN0_TX_IRQHandler
IRQ USBD_LP_CAN0_RX0_IRQHandler
IRQ CAN0_RX1_IRQHandler
IRQ CAN0_EWMC_IRQHandler
IRQ EXTI5_9_IRQHandler
IRQ TIMER0_BRK_IRQHandler
IRQ TIMER0_UP_IRQHandler
IRQ TIMER0_TRG_CMT_IRQHandler
IRQ TIMER0_Channel_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ I2C0_EV_IRQHandler
IRQ I2C0_ER_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ SPI0_IRQHandler
IRQ SPI1_IRQHandler
IRQ USART0_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ EXTI10_15_IRQHandler
IRQ RTC_Alarm_IRQHandler
IRQ USBD_WKUP_IRQHandler
IRQ TIMER7_BRK_IRQHandler
IRQ TIMER7_UP_IRQHandler
IRQ TIMER7_TRG_CMT_IRQHandler
IRQ TIMER7_Channel_IRQHandler
IRQ ADC2_IRQHandler
IRQ EXMC_IRQHandler
IRQ SDIO_IRQHandler
IRQ TIMER4_IRQHandler
IRQ SPI2_IRQHandler
IRQ UART3_IRQHandler
IRQ UART4_IRQHandler
IRQ TIMER5_IRQHandler
IRQ TIMER6_IRQHandler
IRQ DMA1_Channel0_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_4_IRQHandler

48
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s Normal file
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/*
* File : startup_gd32f10x_hd.s
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team
*
* Change Logs:
* Date Author Notes
* 2021-01-02 iysheng first implementation
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global Reset_Handler
.section .text.Reset_Handler
.type Reset_Handler, STT_FUNC
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry

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bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c Normal file
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bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h Normal file
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h Normal file
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/**
******************************************************************************
* @brief ADC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_ADC_H
#define __GD32F10X_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum { FALSE = 0, TRUE } BOOL;
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Exported_Types
* @{
*/
/**
* @brief ADC Init structure definition
*/
typedef struct {
uint32_t ADC_Trig_External; /*!< AD conversion of regular channels trigger. */
uint8_t ADC_Channel_Number; /*!< The number of converted ADC channels .
This parameter must range from 1 to 16. */
uint32_t ADC_Data_Align; /*!< ADC data alignment,left or right. */
TypeState ADC_Mode_Scan; /*!< AD conversion mode,multichannels mode or Single channel mode.
This parameter can be ENABLE or DISABLE */
uint32_t ADC_Mode; /*!< AD operation mode,independent mode or dual mode.
This parameter can be a value of @ref ADC_mode */
TypeState ADC_Mode_Continuous; /*!< AD perform mode,continuous mode or single mode.
This parameter can be ENABLE or DISABLE. */
} ADC_InitPara;
/**
* @}
*/
/** @defgroup ADC_Exported_Constants
* @{
*/
/** @defgroup ADC_external_trigger
* @{
*/
#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC2 ((uint32_t)0x00020000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC2 ((uint32_t)0x00060000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_T3_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_T4_CC4 ((uint32_t)0x000A0000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_EXT_IT11_T8_TRGO ((uint32_t)0x000C0000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC3 ((uint32_t)0x00040000) /*!< Used in ADC1,ADC2 and ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_NONE ((uint32_t)0x000E0000) /*!< Used in ADC1,ADC2 and ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T3_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC3 ((uint32_t)0x00020000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T8_CC1 ((uint32_t)0x00060000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T8_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC1 ((uint32_t)0x000A0000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC3 ((uint32_t)0x000C0000) /*!< Only used in ADC3 */
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_CHANNEL_0 ((uint8_t)0x00)
#define ADC_CHANNEL_1 ((uint8_t)0x01)
#define ADC_CHANNEL_2 ((uint8_t)0x02)
#define ADC_CHANNEL_3 ((uint8_t)0x03)
#define ADC_CHANNEL_4 ((uint8_t)0x04)
#define ADC_CHANNEL_5 ((uint8_t)0x05)
#define ADC_CHANNEL_6 ((uint8_t)0x06)
#define ADC_CHANNEL_7 ((uint8_t)0x07)
#define ADC_CHANNEL_8 ((uint8_t)0x08)
#define ADC_CHANNEL_9 ((uint8_t)0x09)
#define ADC_CHANNEL_10 ((uint8_t)0x0A)
#define ADC_CHANNEL_11 ((uint8_t)0x0B)
#define ADC_CHANNEL_12 ((uint8_t)0x0C)
#define ADC_CHANNEL_13 ((uint8_t)0x0D)
#define ADC_CHANNEL_14 ((uint8_t)0x0E)
#define ADC_CHANNEL_15 ((uint8_t)0x0F)
#define ADC_CHANNEL_16 ((uint8_t)0x10)
#define ADC_CHANNEL_17 ((uint8_t)0x11)
#define ADC_CHANNEL_TEMPSENSOR ((uint8_t)ADC_CHANNEL_16)
#define ADC_CHANNEL_VREFINT ((uint8_t)ADC_CHANNEL_17)
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)0x00000800)
/**
* @}
*/
/** @defgroup ADC_mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
#define ADC_MODE_REGINSERTSIMULT ((uint32_t)0x00010000)
#define ADC_MODE_REGSIMULT_ALTERTRIG ((uint32_t)0x00020000)
#define ADC_MODE_INSERTSIMULT_FASTINTERL ((uint32_t)0x00030000)
#define ADC_MODE_INSERTSIMULT_SLOWINTERL ((uint32_t)0x00040000)
#define ADC_MODE_INSERTSIMULT ((uint32_t)0x00050000)
#define ADC_MODE_REGSIMULT ((uint32_t)0x00060000)
#define ADC_MODE_FASTINTERL ((uint32_t)0x00070000)
#define ADC_MODE_SLOWINTERL ((uint32_t)0x00080000)
#define ADC_MODE_ALTERTRIG ((uint32_t)0x00090000)
/**
* @}
*/
/** @defgroup ADC_sampling_time
* @{
*/
#define ADC_SAMPLETIME_1POINT5 ((uint8_t)0x00)
#define ADC_SAMPLETIME_7POINT5 ((uint8_t)0x01)
#define ADC_SAMPLETIME_13POINT5 ((uint8_t)0x02)
#define ADC_SAMPLETIME_28POINT5 ((uint8_t)0x03)
#define ADC_SAMPLETIME_41POINT5 ((uint8_t)0x04)
#define ADC_SAMPLETIME_55POINT5 ((uint8_t)0x05)
#define ADC_SAMPLETIME_71POINT5 ((uint8_t)0x06)
#define ADC_SAMPLETIME_239POINT5 ((uint8_t)0x07)
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_inserted_channels_conversion
* @{
*/
#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO ((uint32_t)0x00002000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1 ((uint32_t)0x00003000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC1 and ADC2 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRIG ((uint32_t)0x00000000) /*!< Used in ADC1,ADC2 and ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4 ((uint32_t)0x00001000) /*!< Used in ADC1,ADC2 and ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_NONE ((uint32_t)0x00007000) /*!< Used in ADC1,ADC2 and ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3 ((uint32_t)0x00002000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2 ((uint32_t)0x00003000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC3 */
#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC3 */
/**
* @}
*/
/** @defgroup ADC_inserted_channel_selection
* @{
*/
#define ADC_INSERTEDCHANNEL_1 ((uint8_t)0x14)
#define ADC_INSERTEDCHANNEL_2 ((uint8_t)0x18)
#define ADC_INSERTEDCHANNEL_3 ((uint8_t)0x1C)
#define ADC_INSERTEDCHANNEL_4 ((uint8_t)0x20)
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_ANALOGWATCHDOG_SINGLEREGENABLE ((uint32_t)0x00800200)
#define ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE ((uint32_t)0x00400200)
#define ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE ((uint32_t)0x00C00200)
#define ADC_ANALOGWATCHDOG_ALLREGENABLE ((uint32_t)0x00800000)
#define ADC_ANALOGWATCHDOG_ALLINSERTENABLE ((uint32_t)0x00400000)
#define ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE ((uint32_t)0x00C00000)
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_INT_EOC ((uint16_t)0x0220)
#define ADC_INT_AWE ((uint16_t)0x0140)
#define ADC_INT_EOIC ((uint16_t)0x0480)
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWE ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_EOIC ((uint8_t)0x04)
#define ADC_FLAG_STIC ((uint8_t)0x08)
#define ADC_FLAG_STRC ((uint8_t)0x10)
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions
* @{
*/
void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue);
void ADC_Calibration(ADC_TypeDef *ADCx);
void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv);
void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx);
void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset);
uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel);
void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefint_Enable(TypeState NewValue);
TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_ADC_H */

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/**
******************************************************************************
* @brief BKP header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_BKP_H
#define __GD32F10X_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @defgroup BKP_Exported_Constants
* @{
*/
/** @defgroup TAMPER_pin_active_level
* @{
*/
#define BKP_TPAL_HIGH ((uint16_t)0x0000)
#define BKP_TPAL_LOW ((uint16_t)0x0002)
/**
* @}
*/
/** @defgroup RTC_output_on_the_TAMPER_pin
* @{
*/
#define BKP_RTCOUTPUT_NULL ((uint16_t)0x0000)
#define BKP_RTCOUTPUT_CLKCAL ((uint16_t)0x0080)
#define BKP_RTCOUTPUT_ALARM ((uint16_t)0x0100)
#define BKP_RTCOUTPUT_SECOND ((uint16_t)0x0300)
/**
* @}
*/
/** @defgroup Backup_Data_Register
* @{
*/
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Functions
* @{
*/
void BKP_DeInit(void);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue);
void BKP_TamperINT_Enable(TypeState NewValue);
TypeState BKP_GetBitState(void);
void BKP_ClearBitState(void);
TypeState BKP_GetIntBitState(void);
void BKP_ClearIntBitState(void);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_BKP_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

512
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h Normal file
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52
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h Normal file
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/**
******************************************************************************
* @brief CRC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CRC_H
#define __GD32F10X_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
void CRC_ResetDTR(void);
uint32_t CRC_CalcSingleData(uint32_t CRC_data);
uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length);
uint32_t CRC_ReadDTR(void);
void CRC_WriteFDTR(uint8_t CRC_fdtr);
uint8_t CRC_ReadFDTR(void);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_CRC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

208
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h Normal file
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/**
******************************************************************************
* @brief DAC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_DAC_H
#define __GD32F10X_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct {
uint32_t DAC_Trigger; /*!< External trigger of the selected DAC channel.
This parameter can be a value of @ref DAC_Trigger */
uint32_t DAC_WaveType; /*!< Wave type of the DAC channel, noise waves or triangle waves.
This parameter can be a value of @ref DAC_wave_type */
uint32_t DAC_LFSRNoise_AmplitudeTriangle; /*!< The LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrnoise_amplitudetriangle */
uint32_t DAC_OutputBuffer; /*!< whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_OutputBuffer */
} DAC_InitPara;
/**
* @}
*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_Trigger
* @{
*/
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< no trigger */
#define DAC_TRIGGER_T2_TRIG ((uint32_t)0x00000024) /*!< TIMER2 TRIG */
#define DAC_TRIGGER_T3_TRIG ((uint32_t)0x0000000C) /*!< TIMER3 TRIG */
#define DAC_TRIGGER_T4_TRIG ((uint32_t)0x0000002C) /*!< TIMER4 TRIG */
#define DAC_TRIGGER_T5_TRIG ((uint32_t)0x0000001C) /*!< TIMER5 TRIG */
#define DAC_TRIGGER_T6_TRIG ((uint32_t)0x00000004) /*!< TIMER6 TRIG */
#define DAC_TRIGGER_T7_TRIG ((uint32_t)0x00000014) /*!< TIMER7 TRIG */
#define DAC_TRIGGER_T8_TRIG ((uint32_t)0x0000000C) /*!< TIMER8 TRIG */
#define DAC_TRIGGER_T15_TRIG ((uint32_t)0x0000001C) /*!< TIMER15 TRIG */
#define DAC_TRIGGER_EXTI_LINE9 ((uint32_t)0x00000034) /*!< EXTI Line9 event */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)0x0000003C) /*!< software trigger */
/**
* @}
*/
/** @defgroup DAC_wave_type
* @{
*/
#define DAC_WAVEGENE_NONE ((uint32_t)0x00000000)
#define DAC_WAVEGENE_NOISE ((uint32_t)0x00000040)
#define DAC_WAVEGENE_TRIANGLE ((uint32_t)0x00000080)
/**
* @}
*/
/** @defgroup DAC_lfsrnoise_amplitudetriangle
* @{
*/
#define DAC_LFSR_BIT0 ((uint32_t)0x00000000) /*!< LFSR bit0 for noise wave generation */
#define DAC_LFSR_BITS1_0 ((uint32_t)0x00000100) /*!< LFSR bit[1:0] for noise wave generation */
#define DAC_LFSR_BITS2_0 ((uint32_t)0x00000200) /*!< LFSR bit[2:0] for noise wave generation */
#define DAC_LFSR_BITS3_0 ((uint32_t)0x00000300) /*!< LFSR bit[3:0] for noise wave generation */
#define DAC_LFSR_BITS4_0 ((uint32_t)0x00000400) /*!< LFSR bit[4:0] for noise wave generation */
#define DAC_LFSR_BITS5_0 ((uint32_t)0x00000500) /*!< LFSR bit[5:0] for noise wave generation */
#define DAC_LFSR_BITS6_0 ((uint32_t)0x00000600) /*!< LFSR bit[6:0] for noise wave generation */
#define DAC_LFSR_BITS7_0 ((uint32_t)0x00000700) /*!< LFSR bit[7:0] for noise wave generation */
#define DAC_LFSR_BITS8_0 ((uint32_t)0x00000800) /*!< LFSR bit[8:0] for noise wave generation */
#define DAC_LFSR_BITS9_0 ((uint32_t)0x00000900) /*!< LFSR bit[9:0] for noise wave generation */
#define DAC_LFSR_BITS10_0 ((uint32_t)0x00000A00) /*!< LFSR bit[10:0] for noise wave generation */
#define DAC_LFSR_BITS11_0 ((uint32_t)0x00000B00) /*!< LFSR bit[11:0] for noise wave generation */
#define DAC_AMPLITUDETRIANGLE_1 ((uint32_t)0x00000000) /*!< max triangle amplitude: 1 */
#define DAC_AMPLITUDETRIANGLE_3 ((uint32_t)0x00000100) /*!< max triangle amplitude: 3 */
#define DAC_AMPLITUDETRIANGLE_7 ((uint32_t)0x00000200) /*!< max triangle amplitude: 7 */
#define DAC_AMPLITUDETRIANGLE_15 ((uint32_t)0x00000300) /*!< max triangle amplitude: 15 */
#define DAC_AMPLITUDETRIANGLE_31 ((uint32_t)0x00000400) /*!< max triangle amplitude: 31 */
#define DAC_AMPLITUDETRIANGLE_63 ((uint32_t)0x00000500) /*!< max triangle amplitude: 63 */
#define DAC_AMPLITUDETRIANGLE_127 ((uint32_t)0x00000600) /*!< max triangle amplitude: 127 */
#define DAC_AMPLITUDETRIANGLE_255 ((uint32_t)0x00000700) /*!< max triangle amplitude: 255 */
#define DAC_AMPLITUDETRIANGLE_511 ((uint32_t)0x00000800) /*!< max triangle amplitude: 511 */
#define DAC_AMPLITUDETRIANGLE_1023 ((uint32_t)0x00000900) /*!< max triangle amplitude: 1023 */
#define DAC_AMPLITUDETRIANGLE_2047 ((uint32_t)0x00000A00) /*!< max triangle amplitude: 2047 */
#define DAC_AMPLITUDETRIANGLE_4095 ((uint32_t)0x00000B00) /*!< max triangle amplitude: 4095 */
/**
* @}
*/
/** @defgroup DAC_OutputBuffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)0x00000002)
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
/**
* @}
*/
/** @defgroup DAC_data_alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_INT_DMAUDR ((uint32_t)0x00002000)
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Functions
* @{
*/
void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct);
void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct);
void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue);
void DAC_IntConfig(uint32_t DAC_Channel, TypeState NewValue);
void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue);
void DAC_DualSoftwareTrigger_Enable(TypeState NewValue);
void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_DAC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h Normal file
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/**
******************************************************************************
* @brief DMA header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_DMA_H
#define __GD32F10X_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Exported_Types
* @{
*/
/**
* @brief DMA Initial Parameters
*/
typedef struct {
uint32_t DMA_PeripheralBaseAddr; /*!< The base address of the peripheral. */
uint32_t DMA_MemoryBaseAddr; /*!< The base address of the memory. */
uint32_t DMA_DIR; /*!< The direction of data transmission.
detailed in @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /*!< The buffer size of data transmission. */
uint32_t DMA_PeripheralInc; /*!< The incremented_mode of the Peripheral address register.
detailed in @ref DMA_peripheral_Address_incremented_mode */
uint32_t DMA_MemoryInc; /*!< The incremented_mode of the memory address register.
detailed in @ref DMA_memory_Address_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< The data transmission width of Peripheral.
detailed in @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< The data transmission width of Memory.
detailed in @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< The mode of circular transmission.
detailed in @ref DMA_circular_normal_mode */
uint32_t DMA_Priority; /*!< The software priority for the DMAy Channelx.
detailed in @ref DMA_priority_level */
uint32_t DMA_MTOM; /*!< The mode of memory-to-memory transfer.
detailed in @ref DMA_memory_to_memory */
} DMA_InitPara;
/**
* @}
*/
/** @defgroup DMA_Exported_Constants
* @{
*/
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PERIPHERALDST DMA_CTLR_DIR
#define DMA_DIR_PERIPHERALSRC ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_peripheral_Address_Increasing_mode
* @{
*/
#define DMA_PERIPHERALINC_ENABLE DMA_CTLR_PNAGA
#define DMA_PERIPHERALINC_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_memory_Address_Increasing_mode
* @{
*/
#define DMA_MEMORYINC_ENABLE DMA_CTLR_MNAGA
#define DMA_MEMORYINC_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PERIPHERALDATASIZE_BYTE ((uint32_t)0x00000000)
#define DMA_PERIPHERALDATASIZE_HALFWORD DMA_CTLR_PSIZE_0
#define DMA_PERIPHERALDATASIZE_WORD DMA_CTLR_PSIZE_1
/**
* @}
*/
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MEMORYDATASIZE_BYTE ((uint32_t)0x00000000)
#define DMA_MEMORYDATASIZE_HALFWORD DMA_CTLR_MSIZE_0
#define DMA_MEMORYDATASIZE_WORD DMA_CTLR_MSIZE_1
/**
* @}
*/
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_MODE_CIRCULAR DMA_CTLR_CIRC
#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_PRIORITY_VERYHIGH DMA_CTLR_PRIO
#define DMA_PRIORITY_HIGH DMA_CTLR_PRIO_1
#define DMA_PRIORITY_MEDIUM DMA_CTLR_PRIO_0
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_MEMTOMEM_ENABLE DMA_CTLR_MEMTOMEM
#define DMA_MEMTOMEM_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_INT_TC DMA_CTLR_TCIE
#define DMA_INT_HT DMA_CTLR_HTIE
#define DMA_INT_ERR DMA_CTLR_ERRIE
#define DMA1_INT_GL1 DMA_IFR_GIF1
#define DMA1_INT_TC1 DMA_IFR_TCIF1
#define DMA1_INT_HT1 DMA_IFR_HTIF1
#define DMA1_INT_ERR1 DMA_IFR_ERRIF1
#define DMA1_INT_GL2 DMA_IFR_GIF2
#define DMA1_INT_TC2 DMA_IFR_TCIF2
#define DMA1_INT_HT2 DMA_IFR_HTIF2
#define DMA1_INT_ERR2 DMA_IFR_ERRIF2
#define DMA1_INT_GL3 DMA_IFR_GIF3
#define DMA1_INT_TC3 DMA_IFR_TCIF3
#define DMA1_INT_HT3 DMA_IFR_HTIF3
#define DMA1_INT_ERR3 DMA_IFR_ERRIF3
#define DMA1_INT_GL4 DMA_IFR_GIF4
#define DMA1_INT_TC4 DMA_IFR_TCIF4
#define DMA1_INT_HT4 DMA_IFR_HTIF4
#define DMA1_INT_ERR4 DMA_IFR_ERRIF4
#define DMA1_INT_GL5 DMA_IFR_GIF5
#define DMA1_INT_TC5 DMA_IFR_TCIF5
#define DMA1_INT_HT5 DMA_IFR_HTIF5
#define DMA1_INT_ERR5 DMA_IFR_ERRIF5
#define DMA1_INT_GL6 DMA_IFR_GIF6
#define DMA1_INT_TC6 DMA_IFR_TCIF6
#define DMA1_INT_HT6 DMA_IFR_HTIF6
#define DMA1_INT_ERR6 DMA_IFR_ERRIF6
#define DMA1_INT_GL7 DMA_IFR_GIF7
#define DMA1_INT_TC7 DMA_IFR_TCIF7
#define DMA1_INT_HT7 DMA_IFR_HTIF7
#define DMA1_INT_ERR7 DMA_IFR_ERRIF7
#define DMA2_INT_GL1 ((uint32_t)0x10000001)
#define DMA2_INT_TC1 ((uint32_t)0x10000002)
#define DMA2_INT_HT1 ((uint32_t)0x10000004)
#define DMA2_INT_TE1 ((uint32_t)0x10000008)
#define DMA2_INT_GL2 ((uint32_t)0x10000010)
#define DMA2_INT_TC2 ((uint32_t)0x10000020)
#define DMA2_INT_HT2 ((uint32_t)0x10000040)
#define DMA2_INT_TE2 ((uint32_t)0x10000080)
#define DMA2_INT_GL3 ((uint32_t)0x10000100)
#define DMA2_INT_TC3 ((uint32_t)0x10000200)
#define DMA2_INT_HT3 ((uint32_t)0x10000400)
#define DMA2_INT_TE3 ((uint32_t)0x10000800)
#define DMA2_INT_GL4 ((uint32_t)0x10001000)
#define DMA2_INT_TC4 ((uint32_t)0x10002000)
#define DMA2_INT_HT4 ((uint32_t)0x10004000)
#define DMA2_INT_TE4 ((uint32_t)0x10008000)
#define DMA2_INT_GL5 ((uint32_t)0x10010000)
#define DMA2_INT_TC5 ((uint32_t)0x10020000)
#define DMA2_INT_HT5 ((uint32_t)0x10040000)
#define DMA2_INT_TE5 ((uint32_t)0x10080000)
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA1_FLAG_GL1 DMA_IFR_GIF1
#define DMA1_FLAG_TC1 DMA_IFR_TCIF1
#define DMA1_FLAG_HT1 DMA_IFR_HTIF1
#define DMA1_FLAG_ERR1 DMA_IFR_ERRIF1
#define DMA1_FLAG_GL2 DMA_IFR_GIF2
#define DMA1_FLAG_TC2 DMA_IFR_TCIF2
#define DMA1_FLAG_HT2 DMA_IFR_HTIF2
#define DMA1_FLAG_ERR2 DMA_IFR_ERRIF2
#define DMA1_FLAG_GL3 DMA_IFR_GIF3
#define DMA1_FLAG_TC3 DMA_IFR_TCIF3
#define DMA1_FLAG_HT3 DMA_IFR_HTIF3
#define DMA1_FLAG_ERR3 DMA_IFR_ERRIF3
#define DMA1_FLAG_GL4 DMA_IFR_GIF4
#define DMA1_FLAG_TC4 DMA_IFR_TCIF4
#define DMA1_FLAG_HT4 DMA_IFR_HTIF4
#define DMA1_FLAG_ERR4 DMA_IFR_ERRIF4
#define DMA1_FLAG_GL5 DMA_IFR_GIF5
#define DMA1_FLAG_TC5 DMA_IFR_TCIF5
#define DMA1_FLAG_HT5 DMA_IFR_HTIF5
#define DMA1_FLAG_ERR5 DMA_IFR_ERRIF5
#define DMA1_FLAG_GL6 DMA_IFR_GIF6
#define DMA1_FLAG_TC6 DMA_IFR_TCIF6
#define DMA1_FLAG_HT6 DMA_IFR_HTIF6
#define DMA1_FLAG_ERR6 DMA_IFR_ERRIF6
#define DMA1_FLAG_GL7 DMA_IFR_GIF7
#define DMA1_FLAG_TC7 DMA_IFR_TCIF7
#define DMA1_FLAG_HT7 DMA_IFR_HTIF7
#define DMA1_FLAG_ERR7 DMA_IFR_ERRIF7
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Functions
* @{
*/
/* Function used to reset the DMA configuration */
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
/* The functions of Initialization and Configuration */
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct);
void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct);
void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue);
/* The functions of Data Counter */
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
/* The functions of Interrupts and flags management */
void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue);
TypeState DMA_GetBitState(uint32_t DMA_FLAG);
void DMA_ClearBitState(uint32_t DMA_FLAG);
TypeState DMA_GetIntBitState(uint32_t DMA_INT);
void DMA_ClearIntBitState(uint32_t DMA_INT);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10x_DMA_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief EXMC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_EXMC_H
#define __GD32F10X_EXMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup EXMC
* @{
*/
/** @defgroup EXMC_Exported_Types
* @{
*/
/**
* @brief Initial Timing Parameters For NOR/SRAM Banks
*/
typedef struct {
uint32_t EXMC_AsynAccessMode; /*!< The asynchronous access mode, detailed in @ref EXMC_AsynAccess_Mode*/
uint32_t EXMC_SynDataLatency; /*!< The number of CLK cycles to configure the data latency,
which may assume a value between 0x0 and 0xF. */
uint32_t EXMC_SynCLKDivision; /*!< The number of HCLK cycles to configure the clock divide ratio,
which can be a value between 0x0 and 0xF. */
uint32_t EXMC_BusLatency; /*!< The number of HCLK cycles to configure the bus latency,
which can be a value between 0x0 and 0xF. */
uint32_t EXMC_AsynDataSetupTime; /*!< The number of HCLK cycles to configure the data setup time
while in the asynchronous access mode, which can be a value
between 0x00 and 0xFF. */
uint32_t EXMC_AsynAddressHoldTime; /*!< The number of HCLK cycles to configure the address hold time
while in the asynchronous access mode, which can be a value
between 0x0 and 0xF. */
uint32_t EXMC_AsynAddressSetupTime; /*!< The number of HCLK cycles to configure the data setup time
while in the asynchronous access mode, which can be a value
between 0x0 and 0xF. */
} EXMC_NORSRAMTimingInitPara;
/**
* @brief EXMC NOR/SRAM Init structure definition
*/
typedef struct {
uint32_t EXMC_NORSRAMBank; /*!< The specified region of NORSRAM Bank1,
choose one from @ref EXMC_NORSRAMBank. */
uint32_t EXMC_WriteMode; /*!< The write mode, details in @ref EXMC_WriteMode. */
uint32_t EXMC_ExtendedMode; /*!< Enable or Disable the extended mode, details in
@ref EXMC_ExtendedMode. */
uint32_t EXMC_AsynWait; /*!< Enable or disable the asynchronous wait feature,detial
in @ref EXMC_AsynWait. */
uint32_t EXMC_NWAITSignal; /*!< Enable or Disable the NWAIT signal while in synchronous
bust mode, details in @ref EXMC_NWAITSignal. */
uint32_t EXMC_MemoryWrite; /*!< Enable or Disable the write operation, details in
@ref EXMC_MemoryWrite. */
uint32_t EXMC_NWAITConfig; /*!< NWAIT signal configuration, details in @ref EXMC_NWAITConfig */
uint32_t EXMC_WrapBurstMode; /*!< Enable or Disable the wrap burst mode, details in
@ref EXMC_WrapBurstMode. */
uint32_t EXMC_NWAITPolarity; /*!< Specifies the polarity of NWAIT signal from memory,
details in @ref EXMC_NWAITPolarity. */
uint32_t EXMC_BurstMode; /*!< Enable or Disable the burst mode, details in
@ref EXMC_BurstMode. */
uint32_t EXMC_DatabusWidth; /*!< Specifies the databus width of external memory,
details in @ref EXMC_DatabusWidth. */
uint32_t EXMC_MemoryType; /*!< Specifies the type of external memory, details in
@ref EXMC_MemoryType. */
uint32_t EXMC_AddressDataMux; /*!< Specifies whether the data bus and address bus are multiplexed
or not,details in @ref EXMC_AddressDataMux. */
EXMC_NORSRAMTimingInitPara *EXMC_ReadWriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
used to define the timing parameters for read and write
if the ExtendedMode is not used or define the timing
parameters for read if the ExtendedMode is used. */
EXMC_NORSRAMTimingInitPara *EXMC_WriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
only used to define the timing parameters for write when
the ExtendedMode is used. */
} EXMC_NORSRAMInitPara;
/**
* @brief Timing parameters For EXMC NAND and PCCARD Banks
*/
typedef struct {
uint32_t EXMC_DatabusHiZTime; /*!< The number of HCLK cycles to configure the dadtabus HiZ time
for write operation, which can be a value between 0x00 and 0xFF. */
uint32_t EXMC_HoldTime; /*!< The number of HCLK cycles to configure the address hold time
(or the data hold time for write operation),which can be a value
between 0x00 and 0xFF. */
uint32_t EXMC_WaitTime; /*!< The number of HCLK cycles to configure the minimum wait time,
which can be a value between 0x00 and 0xFF. */
uint32_t EXMC_SetupTime; /*!< The number of HCLK cycles to configure the address setup time ,
which can be a value between 0x00 and 0xFF. */
} EXMC_NAND_PCCARDTimingInitPara;
/**
* @brief EXMC NAND Init structure definition
*/
typedef struct {
uint32_t EXMC_NANDBank; /*!< The specified Bank of NAND FLASH, choose one
from @ref EXMC_NANDBank. */
uint32_t EXMC_ECCSize; /*!< The page size for the ECC calculation,details
in @ref EXMC_ECCSize. */
uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure the
latency of ALE low to RB low, which can be a
value between 0x0 and 0xF. */
uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure the
latency of CLE low to RB low, which can be a
value between 0x0 and 0xF. */
uint32_t EXMC_ECCLogic; /*!< Enable or Disable the ECC calculation logic,
details in @ref EXMC_ECCLogic. */
uint32_t EXMC_DatabusWidth; /*!< the NAND flash databus width, details in
@ref EXMC_DatabusWidth. */
uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
in @ref EXMC_WaitFeature. */
EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
pointer, which is used to define the timing
parameters for NAND flash Common Space. */
EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
pointer, which is used to define the timing
parameters for NAND flash Attribute Space. */
} EXMC_NANDInitPara;
/**
* @brief EXMC PCCARD Init structure definition
*/
typedef struct {
uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure
the latency of ALE low to RB low, which can
be a value between 0x0 and 0xF. */
uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure
the latency of CLE low to RB low, which can
be a value between 0x0 and 0xF. */
uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
in @ref EXMC_WaitFeature. */
EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
pointer, which is used to define the timing
parameters for PC CARD Common Space. */
EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
pointer, which is used to define the timing
parameters for PC CARD Attribute Space. */
EXMC_NAND_PCCARDTimingInitPara *EXMC_IOSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
pointer, which is used to define the timing
parameters for PC CARD I/O Space. */
} EXMC_PCCARDInitPara;
/**
* @}
*/
/** @defgroup EXMC_Exported_Constants
* @{
*/
/** @defgroup EXMC_NORSRAMBank
* @{
*/
#define EXMC_BANK1_NORSRAM1 ((uint32_t)0x00000001)
#define EXMC_BANK1_NORSRAM2 ((uint32_t)0x00000002)
#define EXMC_BANK1_NORSRAM3 ((uint32_t)0x00000003)
#define EXMC_BANK1_NORSRAM4 ((uint32_t)0x00000004)
/**
* @}
*/
/** @defgroup EXMC_NANDBank
* @{
*/
#define EXMC_BANK2_NAND ((uint32_t)0x00000010)
#define EXMC_BANK3_NAND ((uint32_t)0x00000100)
/**
* @}
*/
/** @defgroup EXMC_PCCARD_Bank
* @{
*/
#define EXMC_BANK4_PCCARD ((uint32_t)0x00001000)
/**
* @}
*/
/** @defgroup NORSRAM_Controller
* @{
*/
/** @defgroup EXMC_AddressDataMux
* @{
*/
#define EXMC_ADDRESS_DATA_MUX_DISABLE ((uint32_t)0x00000000)
#define EXMC_ADDRESS_DATA_MUX_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
/** @defgroup EXMC_MemoryType
* @{
*/
#define EXMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define EXMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
#define EXMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
/**
* @}
*/
/** @defgroup EXMC_DatabusWidth
* @{
*/
#define EXMC_DATABUS_WIDTH_8B ((uint32_t)0x00000000)
#define EXMC_DATABUS_WIDTH_16B ((uint32_t)0x00000010)
/**
* @}
*/
/** @defgroup EXMC_NORFlash_Access
* @{
*/
#define EXMC_NORFLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
#define EXMC_NORFLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
/**
* @}
*/
/** @defgroup EXMC_BurstMode
* @{
*/
#define EXMC_BURST_MODE_DISABLE ((uint32_t)0x00000000)
#define EXMC_BURST_MODE_ENABLE ((uint32_t)0x00000100)
/**
* @}
*/
/** @defgroup EXMC_AsynWait
* @{
*/
#define EXMC_ASYN_WAIT_DISABLE ((uint32_t)0x00000000)
#define EXMC_ASYN_WAIT_ENABLE ((uint32_t)0x00008000)
/**
* @}
*/
/** @defgroup EXMC_NWAITPolarity
* @{
*/
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000)
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200)
/**
* @}
*/
/** @defgroup EXMC_WrapBurstMode
* @{
*/
#define EXMC_WRAP_BURST_MODE_DISABLE ((uint32_t)0x00000000)
#define EXMC_WRAP_BURST_MODE_ENABLE ((uint32_t)0x00000400)
/**
* @}
*/
/** @defgroup EXMC_NWAITConfig
* @{
*/
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000)
#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800)
/**
* @}
*/
/** @defgroup EXMC_MemoryWrite
* @{
*/
#define EXMC_MEMORY_WRITE_DISABLE ((uint32_t)0x00000000)
#define EXMC_MEMORY_WRITE_ENABLE ((uint32_t)0x00001000)
/**
* @}
*/
/** @defgroup EXMC_NWAITSignal
* @{
*/
#define EXMC_NWAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define EXMC_NWAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
/**
* @}
*/
/** @defgroup EXMC_ExtendedMode
* @{
*/
#define EXMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
#define EXMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
/**
* @}
*/
/** @defgroup EXMC_WriteMode
* @{
*/
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000)
#define EXMC_SYN_WRITE ((uint32_t)0x00080000)
/**
* @}
*/
/** @defgroup EXMC_AsynAccess_Mode
* @{
*/
#define EXMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define EXMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define EXMC_ACCESS_MODE_C ((uint32_t)0x20000000)
#define EXMC_ACCESS_MODE_D ((uint32_t)0x30000000)
/**
* @}
*/
/**
* @}
*/
/** @defgroup NAND_PCCARD_Controller
* @{
*/
/** @defgroup EXMC_WaitFeature
* @{
*/
#define EXMC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
#define EXMC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
/**
* @}
*/
/** @defgroup EXMC_ECCLogic
* @{
*/
#define EXMC_ECC_LOGIC_DISABLE ((uint32_t)0x00000000)
#define EXMC_ECC_LOGIC_ENABLE ((uint32_t)0x00000040)
/**
* @}
*/
/** @defgroup EXMC_ECCSize
* @{
*/
#define EXMC_ECC_SIZE_256BYTES ((uint32_t)0x00000000)
#define EXMC_ECC_SIZE_512BYTES ((uint32_t)0x00020000)
#define EXMC_ECC_SIZE_1024BYTES ((uint32_t)0x00040000)
#define EXMC_ECC_SIZE_2048BYTES ((uint32_t)0x00060000)
#define EXMC_ECC_SIZE_4096BYTES ((uint32_t)0x00080000)
#define EXMC_ECC_SIZE_8192BYTES ((uint32_t)0x000A0000)
/**
* @}
*/
/** @defgroup EXMC_Interrupt_Source
* @{
*/
#define EXMC_INT_RISE ((uint32_t)0x00000008)
#define EXMC_INT_LEVEL ((uint32_t)0x00000010)
#define EXMC_INT_FALL ((uint32_t)0x00000020)
/**
* @}
*/
/** @defgroup EXMC_FLAG
* @{
*/
#define EXMC_FLAG_RISE ((uint32_t)0x00000001)
#define EXMC_FLAG_LEVEL ((uint32_t)0x00000002)
#define EXMC_FLAG_FALL ((uint32_t)0x00000004)
#define EXMC_FLAG_FIFOE ((uint32_t)0x00000040)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXMC_Exported_Functions
* @{
*/
void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank);
void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank);
void EXMC_PCCARD_DeInit(void);
void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue);
void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
void EXMC_PCCARD_Enable(TypeState NewValue);
void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank);
void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue);
TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10x_EXMC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief EXTI header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_EXTI_H
#define __GD32F10X_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI Mode enumeration
*/
typedef enum {
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTI_ModePara;
/**
* @brief EXTI Trigger enumeration
*/
typedef enum {
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTI_TriggerPara;
/**
* @brief EXTI Initial Parameters
*/
typedef struct {
uint32_t EXTI_LINE; /*!< The selection of EXTI lines. */
EXTI_ModePara EXTI_Mode; /*!< The mode for the EXTI lines, detailed in @ref EXTIMode_Para. */
EXTI_TriggerPara EXTI_Trigger; /*!< The trigger edge for the EXTI lines, detailed in EXTI_TriggerPara. */
TypeState EXTI_LINEEnable; /*!< The new value of the selected EXTI lines. */
} EXTI_InitPara;
/**
* @}
*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_lines
* @{
*/
#define EXTI_LINE0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
#define EXTI_LINE1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
#define EXTI_LINE2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
#define EXTI_LINE3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
#define EXTI_LINE4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
#define EXTI_LINE5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
#define EXTI_LINE6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
#define EXTI_LINE7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
#define EXTI_LINE8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
#define EXTI_LINE9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
#define EXTI_LINE10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
#define EXTI_LINE11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
#define EXTI_LINE12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
#define EXTI_LINE13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
#define EXTI_LINE14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
#define EXTI_LINE15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
#define EXTI_LINE16 ((uint32_t)0x00010000) /*!< External interrupt line 16
Connected to the LVD */
#define EXTI_LINE17 ((uint32_t)0x00020000) /*!< External interrupt line 17
Connected to the RTC Alarm */
#define EXTI_LINE18 ((uint32_t)0x00040000) /*!< External interrupt line 18
Connected to the USB Wakeup */
#define EXTI_LINE19 ((uint32_t)0x00080000) /*!< External interrupt line 19
Connected to the Ethernet Wakeup */
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct);
void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct);
void EXTI_SWINT_Enable(uint32_t EXTI_LINE);
TypeState EXTI_GetBitState(uint32_t EXTI_LINE);
void EXTI_ClearBitState(uint32_t EXTI_LINE);
TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE);
void EXTI_ClearIntBitState(uint32_t EXTI_LINE);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief FMC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_FMC_H
#define __GD32F10X_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup FMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FMC_Exported_Types
* @{
*/
/**
* @brief FMC State
*/
typedef enum {
FMC_READY,
FMC_BSY,
FMC_WRPERR,
FMC_PGERR,
FMC_TIMEOUT_ERR
} FMC_State;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMC_Exported_Constants
* @{
*/
/** @defgroup FMC_Interrupts
* @{
*/
#define FMC_INT_EOP FMC_CMR_ENDIE /*!< End of programming interrupt source */
#define FMC_INT_ERR FMC_CMR_ERIE /*!< Error interrupt source */
#define FMC_INT_B2_EOP ((uint32_t)0x80000400) /*!< Bank2 End of programming interrupt source */
#define FMC_INT_B2_ERR ((uint32_t)0x80001000) /*!< Bank2 Error interrupt source */
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_Write_Protection
* @{
*/
#define WRP_SECTOR0 ((uint32_t)0x00000001) /*!< Write protection of sector 0 */
#define WRP_SECTOR1 ((uint32_t)0x00000002) /*!< Write protection of sector 1 */
#define WRP_SECTOR2 ((uint32_t)0x00000004) /*!< Write protection of sector 2 */
#define WRP_SECTOR3 ((uint32_t)0x00000008) /*!< Write protection of sector 3 */
#define WRP_SECTOR4 ((uint32_t)0x00000010) /*!< Write protection of sector 4 */
#define WRP_SECTOR5 ((uint32_t)0x00000020) /*!< Write protection of sector 5 */
#define WRP_SECTOR6 ((uint32_t)0x00000040) /*!< Write protection of sector 6 */
#define WRP_SECTOR7 ((uint32_t)0x00000080) /*!< Write protection of sector 7 */
#define WRP_SECTOR8 ((uint32_t)0x00000100) /*!< Write protection of sector 8 */
#define WRP_SECTOR9 ((uint32_t)0x00000200) /*!< Write protection of sector 9 */
#define WRP_SECTOR10 ((uint32_t)0x00000400) /*!< Write protection of sector 10 */
#define WRP_SECTOR11 ((uint32_t)0x00000800) /*!< Write protection of sector 11 */
#define WRP_SECTOR12 ((uint32_t)0x00001000) /*!< Write protection of sector 12 */
#define WRP_SECTOR13 ((uint32_t)0x00002000) /*!< Write protection of sector 13 */
#define WRP_SECTOR14 ((uint32_t)0x00004000) /*!< Write protection of sector 14 */
#define WRP_SECTOR15 ((uint32_t)0x00008000) /*!< Write protection of sector 15 */
#define WRP_SECTOR16 ((uint32_t)0x00010000) /*!< Write protection of sector 16 */
#define WRP_SECTOR17 ((uint32_t)0x00020000) /*!< Write protection of sector 17 */
#define WRP_SECTOR18 ((uint32_t)0x00040000) /*!< Write protection of sector 18 */
#define WRP_SECTOR19 ((uint32_t)0x00080000) /*!< Write protection of sector 19 */
#define WRP_SECTOR20 ((uint32_t)0x00100000) /*!< Write protection of sector 20 */
#define WRP_SECTOR21 ((uint32_t)0x00200000) /*!< Write protection of sector 21 */
#define WRP_SECTOR22 ((uint32_t)0x00400000) /*!< Write protection of sector 22 */
#define WRP_SECTOR23 ((uint32_t)0x00800000) /*!< Write protection of sector 23 */
#define WRP_SECTOR24 ((uint32_t)0x01000000) /*!< Write protection of sector 24 */
#define WRP_SECTOR25 ((uint32_t)0x02000000) /*!< Write protection of sector 25 */
#define WRP_SECTOR26 ((uint32_t)0x04000000) /*!< Write protection of sector 26 */
#define WRP_SECTOR27 ((uint32_t)0x08000000) /*!< Write protection of sector 27 */
#define WRP_SECTOR28 ((uint32_t)0x10000000) /*!< Write protection of sector 28 */
#define WRP_SECTOR29 ((uint32_t)0x20000000) /*!< Write protection of sector 29 */
#define WRP_SECTOR30 ((uint32_t)0x40000000) /*!< Write protection of sector 30 */
#define WRP_SECTOR31 ((uint32_t)0x80000000) /*!< Write protection of sector 31 */
#define WRP_ALLSECTORS ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_Read_Protection
* @{
*/
/**
* @brief FMC_Read Protection Level
*/
#define RDP_LEVEL_0 ((uint8_t)0xA5)
#define RDP_LEVEL_1 ((uint8_t)0xBB)
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_nRST_DEEPSLEEP
* @{
*/
#define OB_DEEPSLEEP_NORST ((uint8_t)0x02) /*!< No reset generated when entering in DEEPSLEEP */
#define OB_DEEPSLEEP_RST ((uint8_t)0x00) /*!< Reset generated when entering in DEEPSLEEP */
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup FMC_Option_Bytes_BOOT
* @{
*/
#define OB_BOOT_B1 ((uint8_t)0x08) /*!< BOOT from Bank1 */
#define OB_BOOT_B2 ((uint8_t)0x00) /*!< BOOT from Bank2 */
#define OB_USER_BFB2 ((uint16_t)0x0008) /*!< Configure BOOT from Bank1 */
/**
* @}
*/
/** @defgroup FMC_Flags
* @{
*/
#define FMC_FLAG_BSY FMC_CSR_BUSY /*!< FMC Busy flag */
#define FMC_FLAG_PERR FMC_CSR_PGEF /*!< FMC Programming error flag */
#define FMC_FLAG_WERR FMC_CSR_WPEF /*!< FMC Write protected error flag */
#define FMC_FLAG_EOP FMC_CSR_ENDF /*!< FMC End of Programming flag */
#define FMC_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FMC Option Byte error flag */
#define FMC_FLAG_B2_BSY ((uint32_t)0x80000001) /*!< FMC Busy flag */
#define FMC_FLAG_B2_PERR ((uint32_t)0x80000004) /*!< FMC Programming error flag */
#define FMC_FLAG_B2_WERR ((uint32_t)0x80000010) /*!< FMC Write protected error flag */
#define FMC_FLAG_B2_EOP ((uint32_t)0x80000020) /*!< FMC End of Programming flag */
/**
* @}
*/
/** @defgroup FMC_Timeout_definition
* @{
*/
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000)
/**
* @}
*/
/* FMC BANK address */
#define FMC_B1_END_ADDRESS ((uint32_t)0x807FFFF)
#define FMC_BANK1_SIZE 0x0200
#define FMC_SIZE (*(uint16_t *)0x1ffff7e0)
/**
* @}
*/
/** @defgroup FMC_Exported_Functions
* @{
*/
/**
* @brief FMC memory functions.
*/
/* FMC Main Memory Programming functions *****************************************/
void FMC_Unlock(void);
void FMC_UnlockB1(void);
void FMC_UnlockB2(void);
void FMC_Lock(void);
void FMC_LockB1(void);
void FMC_LockB2(void);
FMC_State FMC_ErasePage(uint32_t Page_Address);
FMC_State FMC_MassErase(void);
FMC_State FMC_MassB1Erase(void);
FMC_State FMC_MassB2Erase(void);
FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data);
/* FMC Option Bytes Programming functions *****************************************/
void FMC_OB_Unlock(void);
void FMC_OB_Lock(void);
void FMC_OB_Reset(void);
FMC_State FMC_OB_Erase(void);
FMC_State FMC_OB_EnableWRP(uint32_t OB_WRP);
FMC_State FMC_ReadOutProtection(TypeState NewValue);
FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP);
FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY);
FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT);
FMC_State FMC_OB_WriteUser(uint8_t OB_USER);
FMC_State FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data);
uint8_t FMC_OB_GetUser(void);
uint32_t FMC_OB_GetWRP(void);
TypeState FMC_OB_GetRDP(void);
/* FMC Interrupts and flags management functions **********************************/
void FMC_INTConfig(uint32_t FMC_INT, TypeState NewValue);
TypeState FMC_GetBitState(uint32_t FMC_FLAG);
void FMC_ClearBitState(uint32_t FMC_FLAG);
FMC_State FMC_GetState(void);
FMC_State FMC_GetB1State(void);
FMC_State FMC_GetB2State(void);
FMC_State FMC_WaitReady(uint32_t uCount);
FMC_State FMC_B1_WaitReady(uint32_t uCount);
FMC_State FMC_B2_WaitReady(uint32_t uCount);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_FMC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

281
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/**
******************************************************************************
* @brief GPIO header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10x_GPIO_H
#define __GD32F10x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_Exported_Types
* @{
*/
/**
* @brief Output_Maximum_frequency_enumeration
*/
typedef enum {
GPIO_SPEED_10MHZ = 1,
GPIO_SPEED_2MHZ,
GPIO_SPEED_50MHZ
} GPIO_SpeedPara;
/**
* @brief GPIO_Mode_enumeration
*/
typedef enum {
GPIO_MODE_AIN = 0x0,
GPIO_MODE_IN_FLOATING = 0x04,
GPIO_MODE_IPD = 0x28,
GPIO_MODE_IPU = 0x48,
GPIO_MODE_OUT_OD = 0x14,
GPIO_MODE_OUT_PP = 0X10,
GPIO_MODE_AF_OD = 0X1C,
GPIO_MODE_AF_PP = 0X18
} GPIO_ModePara;
/**
* @brief GPIO Initial Parameters
*/
typedef struct {
uint16_t GPIO_Pin; /*!< The GPIO pins to be configured. choose several from @ref GPIO_pins_define */
GPIO_SpeedPara GPIO_Speed; /*!< The speed for This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIO_ModePara GPIO_Mode; /*!< The operating mode for the selected pins. choose one from @ref GPIO_ModePara */
} GPIO_InitPara;
/**
* @brief Bit_State_enumeration
*/
typedef enum {
Bit_RESET = 0,
Bit_SET
} BitState;
/**
* @}
*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001)
#define GPIO_PIN_1 ((uint16_t)0x0002)
#define GPIO_PIN_2 ((uint16_t)0x0004)
#define GPIO_PIN_3 ((uint16_t)0x0008)
#define GPIO_PIN_4 ((uint16_t)0x0010)
#define GPIO_PIN_5 ((uint16_t)0x0020)
#define GPIO_PIN_6 ((uint16_t)0x0040)
#define GPIO_PIN_7 ((uint16_t)0x0080)
#define GPIO_PIN_8 ((uint16_t)0x0100)
#define GPIO_PIN_9 ((uint16_t)0x0200)
#define GPIO_PIN_10 ((uint16_t)0x0400)
#define GPIO_PIN_11 ((uint16_t)0x0800)
#define GPIO_PIN_12 ((uint16_t)0x1000)
#define GPIO_PIN_13 ((uint16_t)0x2000)
#define GPIO_PIN_14 ((uint16_t)0x4000)
#define GPIO_PIN_15 ((uint16_t)0x8000)
#define GPIO_PIN_ALL ((uint16_t)0xFFFF)
/**
* @}
*/
/** @defgroup GPIO_Remap_define
* @{
*/
#define GPIO_REMAP_SPI1 ((uint32_t)0x00000001)
#define GPIO_REMAP_I2C1 ((uint32_t)0x00000002)
#define GPIO_REMAP_USART1 ((uint32_t)0x00000004)
#define GPIO_REMAP_USART2 ((uint32_t)0x00000008)
#define GPIO_PARTIAL_REMAP_USART3 ((uint32_t)0x00140010)
#define GPIO_FULL_REMAP_USART3 ((uint32_t)0x00140030)
#define GPIO_PARTIAL_REMAP_TIMER1 ((uint32_t)0x00160040)
#define GPIO_FULL_REMAP_TIMER1 ((uint32_t)0x001600C0)
#define GPIO_PARTIAL_REMAP1_TIMER2 ((uint32_t)0x00180100)
#define GPIO_PARTIAL_REMAP2_TIMER2 ((uint32_t)0x00180200)
#define GPIO_FULL_REMAP_TIMER2 ((uint32_t)0x00180300)
#define GPIO_PARTIAL_REMAP_TIMER3 ((uint32_t)0x001A0800)
#define GPIO_FULL_REMAP_TIMER3 ((uint32_t)0x001A0C00)
#define GPIO_REMAP_TIMER4 ((uint32_t)0x00001000)
#define GPIO_REMAP1_CAN1 ((uint32_t)0x001D4000)
#define GPIO_REMAP2_CAN1 ((uint32_t)0x001D6000)
#define GPIO_REMAP_PD01 ((uint32_t)0x00008000)
#define GPIO_REMAP_TIMER5CH4_LSI ((uint32_t)0x00200001)
#define GPIO_REMAP_ADC1_ETRGINJ ((uint32_t)0x00200002)
#define GPIO_REMAP_ADC1_ETRGREG ((uint32_t)0x00200004)
#define GPIO_REMAP_ADC2_ETRGINJ ((uint32_t)0x00200008)
#define GPIO_REMAP_ADC2_ETRGREG ((uint32_t)0x00200010)
#define GPIO_REMAP_ETH ((uint32_t)0x00200020)
#define GPIO_REMAP_CAN2 ((uint32_t)0x00200040)
#define GPIO_REMAP_SWJ_NOJTRST ((uint32_t)0x00300100)
#define GPIO_REMAP_SWJ_JTAGDISABLE ((uint32_t)0x00300200)
#define GPIO_REMAP_SWJ_DISABLE ((uint32_t)0x00300400)
#define GPIO_REMAP_SPI3 ((uint32_t)0x00201100)
#define GPIO_REMAP_TIMER2ITR1_PTP_SOF ((uint32_t)0x00202000)
#define GPIO_REMAP_PTP_PPS ((uint32_t)0x00204000)
#define GPIO_REMAP_TIMER15 ((uint32_t)0x80000001)
#define GPIO_REMAP_TIMER16 ((uint32_t)0x80000002)
#define GPIO_REMAP_TIMER17 ((uint32_t)0x80000004)
#define GPIO_REMAP_CEC ((uint32_t)0x80000008)
#define GPIO_REMAP_TIMER1_DMA ((uint32_t)0x80000010)
#define GPIO_REMAP_TIMER9 ((uint32_t)0x80000020)
#define GPIO_REMAP_TIMER10 ((uint32_t)0x80000040)
#define GPIO_REMAP_TIMER11 ((uint32_t)0x80000080)
#define GPIO_REMAP_TIMER13 ((uint32_t)0x80000100)
#define GPIO_REMAP_TIMER14 ((uint32_t)0x80000200)
#define GPIO_REMAP_EXMC_NADV ((uint32_t)0x80000400)
#define GPIO_REMAP_TIMER67_DAC_DMA ((uint32_t)0x80000800)
#define GPIO_REMAP_TIMER12 ((uint32_t)0x80001000)
#define GPIO_REMAP_MISC ((uint32_t)0x80002000)
/**
* @}
*/
/** @defgroup GPIO_Port_Sources
* @{
*/
#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00)
#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01)
#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02)
#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03)
#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04)
#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05)
#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PINSOURCE0 ((uint8_t)0x00)
#define GPIO_PINSOURCE1 ((uint8_t)0x01)
#define GPIO_PINSOURCE2 ((uint8_t)0x02)
#define GPIO_PINSOURCE3 ((uint8_t)0x03)
#define GPIO_PINSOURCE4 ((uint8_t)0x04)
#define GPIO_PINSOURCE5 ((uint8_t)0x05)
#define GPIO_PINSOURCE6 ((uint8_t)0x06)
#define GPIO_PINSOURCE7 ((uint8_t)0x07)
#define GPIO_PINSOURCE8 ((uint8_t)0x08)
#define GPIO_PINSOURCE9 ((uint8_t)0x09)
#define GPIO_PINSOURCE10 ((uint8_t)0x0A)
#define GPIO_PINSOURCE11 ((uint8_t)0x0B)
#define GPIO_PINSOURCE12 ((uint8_t)0x0C)
#define GPIO_PINSOURCE13 ((uint8_t)0x0D)
#define GPIO_PINSOURCE14 ((uint8_t)0x0E)
#define GPIO_PINSOURCE15 ((uint8_t)0x0F)
/**
* @}
*/
/** @defgroup Ethernet_Media_Interface
* @{
*/
#define GPIO_ETH_MEDIAINTERFACE_MII ((uint32_t)0x00000000)
#define GPIO_ETH_MEDIAINTERFACE_RMII ((uint32_t)0x00800000)
/**
* @}
*/
/* output mode definitions */
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
/** @defgroup AFIO_Event_Output
* @{
*/
#define AFIO_ECR_EVOE_SET ((uint32_t)0x00000080)
#define AFIO_ECR_EVOE_RESET ((uint32_t)0xffffff7f)
/* gpio alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */
#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */
#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */
#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */
#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */
#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */
#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */
#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */
#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */
#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */
#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */
#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */
#define GPIO_AF_12 AF(12) /*!< alternate function selected 12 */
#define GPIO_AF_13 AF(13) /*!< alternate function selected 13 */
#define GPIO_AF_14 AF(14) /*!< alternate function selected 14 */
#define GPIO_AF_15 AF(15) /*!< alternate function selected 15 */
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_AFDeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitPara *GPIO_InitStruct);
void GPIO_ParaInit(GPIO_InitPara *GPIO_InitStruct);
uint8_t GPIO_ReadInputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
uint8_t GPIO_ReadOutputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitState BitVal);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputEnable(TypeState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, TypeState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief I2C header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_I2C_H
#define __GD32F10X_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Exported_Types
* @{
*/
/**
* @brief I2C Initial Parameters
*/
typedef struct {
uint16_t I2C_Protocol; /*!< The protocol type, detailed in @ref I2C_Protocol */
uint16_t I2C_DutyCycle; /*!< The fast mode duty cycle, detailed in @ref I2C_Duty_Cycle */
uint32_t I2C_BitRate; /*!< The I2C bit rate which must be lower than 400k bit/s */
uint16_t I2C_AddressingMode; /*!< The I2C addressing mode, detailed in @ref I2C_Addressing_Mode */
uint16_t I2C_DeviceAddress; /*!< The device address */
} I2C_InitPara;
/**
* @}
*/
/** @defgroup I2C_Exported_Constants
* @{
*/
/** @defgroup I2C_Protocol
* @{
*/
#define I2C_PROTOCOL_I2C ((uint16_t)0x0000)
#define I2C_PROTOCOL_SMBUSDEVICE ((uint16_t)0x0002)
#define I2C_PROTOCOL_SMBUSHOST ((uint16_t)0x000A)
/**
* @}
*/
/** @defgroup I2C_Duty_Cycle
* @{
*/
#define I2C_DUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
/**
* @}
*/
/** @defgroup I2C_Addressing_Mode
* @{
*/
#define I2C_ADDRESSING_MODE_7BIT ((uint16_t)0x4000)
#define I2C_ADDRESSING_MODE_10BIT ((uint16_t)0xC000)
/**
* @}
*/
/** @defgroup I2C_Direction
* @{
*/
#define I2C_DIRECTION_TRANSMITTER ((uint8_t)0x00)
#define I2C_DIRECTION_RECEIVER ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup I2C_Registers
* @{
*/
#define I2C_REGISTER_CTLR1 ((uint8_t)0x00)
#define I2C_REGISTER_CTLR2 ((uint8_t)0x04)
#define I2C_REGISTER_AR1 ((uint8_t)0x08)
#define I2C_REGISTER_AR2 ((uint8_t)0x0C)
#define I2C_REGISTER_DTR ((uint8_t)0x10)
#define I2C_REGISTER_STR1 ((uint8_t)0x14)
#define I2C_REGISTER_STR2 ((uint8_t)0x18)
#define I2C_REGISTER_CLKR ((uint8_t)0x1C)
#define I2C_REGISTER_RTR ((uint8_t)0x20)
/**
* @}
*/
/** @defgroup I2C_PEC_Position
* @{
*/
#define I2C_PECPOSITION_NEXT I2C_CTLR1_POAP
#define I2C_PECPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP)
/**
* @}
*/
/** @defgroup I2C_NACK_Position
* @{
*/
#define I2C_NACKPOSITION_NEXT I2C_CTLR1_POAP
#define I2C_NACKPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP)
/**
* @}
*/
/** @defgroup I2C_Interrupt_Control
* @{
*/
#define I2C_INT_EIE I2C_CTLR2_EIE
#define I2C_INT_EE I2C_CTLR2_EE
#define I2C_INT_BIE I2C_CTLR2_BIE
/**
* @}
*/
/** @defgroup I2C_Interrupt_Source
* @{
*/
#define I2C_INT_SMBALTS ((uint32_t)0x01008000)
#define I2C_INT_SMBTO ((uint32_t)0x01004000)
#define I2C_INT_PECE ((uint32_t)0x01001000)
#define I2C_INT_RXORE ((uint32_t)0x01000800)
#define I2C_INT_AE ((uint32_t)0x01000400)
#define I2C_INT_LOSTARB ((uint32_t)0x01000200)
#define I2C_INT_BE ((uint32_t)0x01000100)
#define I2C_INT_TBE ((uint32_t)0x06000080)
#define I2C_INT_RBNE ((uint32_t)0x06000040)
#define I2C_INT_STPSEND ((uint32_t)0x02000010)
#define I2C_INT_ADD10SEND ((uint32_t)0x02000008)
#define I2C_INT_BTC ((uint32_t)0x02000004)
#define I2C_INT_ADDSEND ((uint32_t)0x02000002)
#define I2C_INT_SBSEND ((uint32_t)0x02000001)
/**
* @}
*/
/** @defgroup I2C_FLAG
* @{
*/
/**
* @brief STR2 register flags
*/
#define I2C_FLAG_DUMODF ((uint32_t)0x00800000)
#define I2C_FLAG_HSTSMB ((uint32_t)0x00400000)
#define I2C_FLAG_DEFSMB ((uint32_t)0x00200000)
#define I2C_FLAG_RXGC ((uint32_t)0x00100000)
#define I2C_FLAG_TRS ((uint32_t)0x00040000)
#define I2C_FLAG_I2CBSY ((uint32_t)0x00020000)
#define I2C_FLAG_MASTER ((uint32_t)0x00010000)
/**
* @brief STR1 register flags
*/
#define I2C_FLAG_SMBALTS ((uint32_t)0x10008000)
#define I2C_FLAG_SMBTO ((uint32_t)0x10004000)
#define I2C_FLAG_PECE ((uint32_t)0x10001000)
#define I2C_FLAG_RXORE ((uint32_t)0x10000800)
#define I2C_FLAG_AE ((uint32_t)0x10000400)
#define I2C_FLAG_LOSTARB ((uint32_t)0x10000200)
#define I2C_FLAG_BE ((uint32_t)0x10000100)
#define I2C_FLAG_TBE ((uint32_t)0x10000080)
#define I2C_FLAG_RBNE ((uint32_t)0x10000040)
#define I2C_FLAG_STPSEND ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10SEND ((uint32_t)0x10000008)
#define I2C_FLAG_BTC ((uint32_t)0x10000004)
#define I2C_FLAG_ADDSEND ((uint32_t)0x10000002)
#define I2C_FLAG_SBSEND ((uint32_t)0x10000001)
/**
* @}
*/
/** @defgroup I2C_ProgrammingMode
* @{
*/
#define I2C_PROGRAMMINGMODE_MASTER_SBSEND ((uint32_t)0x00030001) /*!< I2CBSY, MASTER and SBSEND flag */
#define I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND ((uint32_t)0x00070002) /*!< I2CBSY, MASTER, ADDSEND and TRS flags */
#define I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND ((uint32_t)0x00030002) /*!< I2CBSY, MASTER and ADDSEND flags */
#define I2C_PROGRAMMINGMODE_MASTER_ADD10SEND ((uint32_t)0x00030008) /*!< I2CBSY, MASTER and ADD10SEND flags */
#define I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /*!< I2CBSY, MASTER and RBNE flags */
#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /*!< TRS, I2CBSY, MASTER, TBE flags */
#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /*!< TRS, I2CBSY, MASTER, TBE and BTC flags */
#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND ((uint32_t)0x00020002) /*!< I2CBSY and ADDSEND flags */
#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND ((uint32_t)0x00060002) /*!< TRS, I2CBSY and ADDSEND flags */
#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED ((uint32_t)0x00820000) /*!< DUMODF and I2CBSY flags */
#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED ((uint32_t)0x00860080) /*!< DUMODF, TRS, I2CBSY and TBE flags */
#define I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED ((uint32_t)0x00120000) /*!< RXGC and I2CBSY flags */
#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /*!< I2CBSY and RBNE flags */
#define I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /*!< STPSEND flag */
#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /*!< TRS, I2CBSY, TBE and BTC flags */
#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /*!< TRS, I2CBSY and TBE flags */
#define I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /*!< AE flag */
/**
* @}
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Functions
* @{
*/
void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct);
void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct);
void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address);
void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue);
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx);
void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State);
uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx);
TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT);
void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_I2C_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief IWDG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_IWDG_H
#define __GD32F10X_IWDG_H
/* Exported macro ------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WRITEACCESS_ENABLE ((uint16_t)0x5555)
#define IWDG_WRITEACCESS_DISABLE ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00)
#define IWDG_PRESCALER_8 ((uint8_t)0x01)
#define IWDG_PRESCALER_16 ((uint8_t)0x02)
#define IWDG_PRESCALER_32 ((uint8_t)0x03)
#define IWDG_PRESCALER_64 ((uint8_t)0x04)
#define IWDG_PRESCALER_128 ((uint8_t)0x05)
#define IWDG_PRESCALER_256 ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_BIT_PUD IWDG_STR_PUD
#define IWDG_BIT_RUD IWDG_STR_RUD
#define IWDG_BIT_WUD IWDG_STR_WUD
/**
* @}
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_functions
* @{
*/
/* Prescaler and Counter configuration functions ******************************/
void IWDG_Write_Enable(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t PrescalerValue);
void IWDG_SetReloadValue(uint16_t ReloadValue);
void IWDG_ReloadCounter(void);
/* IWDG activation function ***************************************************/
void IWDG_Enable(void);
/* Flag management function ***************************************************/
TypeState IWDG_GetBitState(uint16_t IWDG_FLAG);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IWDG_GD32F10X_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief MCUDBG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_MCUDBG_H
#define __GD32F10X_MCUDBG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup MCUDBG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MCUDBG_Exported_Constants
* @{
*/
#define MCUDBG_SLEEP_HOLD ((uint32_t)0x00000001)
#define MCUDBG_DEEPSLEEP_HOLD ((uint32_t)0x00000002)
#define MCUDBG_STDBY_HOLD ((uint32_t)0x00000004)
#define MCUDBG_IWDG_HOLD ((uint32_t)0x00000100)
#define MCUDBG_WWDG_HOLD ((uint32_t)0x00000200)
#define MCUDBG_TIMER1_HOLD ((uint32_t)0x00000400)
#define MCUDBG_TIMER2_HOLD ((uint32_t)0x00000800)
#define MCUDBG_TIMER3_HOLD ((uint32_t)0x00001000)
#define MCUDBG_TIMER4_HOLD ((uint32_t)0x00002000)
#define MCUDBG_CAN1_HOLD ((uint32_t)0x00004000)
#define MCUDBG_I2C1_HOLD ((uint32_t)0x00008000)
#define MCUDBG_I2C2_HOLD ((uint32_t)0x00010000)
#define MCUDBG_TIMER5_HOLD ((uint32_t)0x00020000)
#define MCUDBG_TIMER6_HOLD ((uint32_t)0x00040000)
#define MCUDBG_TIMER7_HOLD ((uint32_t)0x00080000)
#define MCUDBG_TIMER8_HOLD ((uint32_t)0x00100000)
#define MCUDBG_CAN2_HOLD ((uint32_t)0x00200000)
#define MCUDBG_TIMER12_HOLD ((uint32_t)0x02000000)
#define MCUDBG_TIMER13_HOLD ((uint32_t)0x04000000)
#define MCUDBG_TIMER14_HOLD ((uint32_t)0x08000000)
#define MCUDBG_TIMER9_HOLD ((uint32_t)0x10000000)
#define MCUDBG_TIMER10_HOLD ((uint32_t)0x20000000)
#define MCUDBG_TIMER11_HOLD ((uint32_t)0x40000000)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/** @defgroup MCUDBG_Exported_Functions
* @{
*/
uint32_t MCUDBG_GetREVID(void);
uint32_t MCUDBG_GetDEVID(void);
void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_MCUDBG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief MISC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_MISC_H
#define __GD32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief MISC Initial Parameters
*/
typedef struct {
uint8_t NVIC_IRQ; /*!< The IRQ type,detailed in @ref IRQn_Type */
uint8_t NVIC_IRQPreemptPriority; /*!< The pre-emption priority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
uint8_t NVIC_IRQSubPriority; /*!< The SubPriority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
TypeState NVIC_IRQEnable; /*!< Enable or disable the IRQ,this parameter can be ENABLE or DISABLE */
} NVIC_InitPara;
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup MISC_System_Low_Power
* @{
*/
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
#define NVIC_LOWPOWER_SEVONPEND ((uint8_t)0x10)
#define NVIC_LOWPOWER_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LOWPOWER_SLEEPONEXIT ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup MISC_Preemption_Priority_Group
* @{
*/
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PRIGROUP_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
#define NVIC_PRIGROUP_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
#define NVIC_PRIGROUP_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
#define NVIC_PRIGROUP_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
#define NVIC_PRIGROUP_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
/**
* @}
*/
/** @defgroup MISC_SysTick_clock_source
* @{
*/
#define SYSTICK_CKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFB)
#define SYSTICK_CKSOURCE_HCLK ((uint32_t)0x00000004)
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_Init(NVIC_InitPara *NVIC_InitStruct);
void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue);
void SysTick_CKSource_Enable(uint32_t SysTick_CKSource);
void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief PWR header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_PWR_H
#define __GD32F10X_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PWR_Low_Voltage_Detector_Threshold
* @{
*/
#define PWR_LVDT_0 PWR_CTLR_LVDT_2V2
#define PWR_LVDT_1 PWR_CTLR_LVDT_2V3
#define PWR_LVDT_2 PWR_CTLR_LVDT_2V4
#define PWR_LVDT_3 PWR_CTLR_LVDT_2V5
#define PWR_LVDT_4 PWR_CTLR_LVDT_2V6
#define PWR_LVDT_5 PWR_CTLR_LVDT_2V7
#define PWR_LVDT_6 PWR_CTLR_LVDT_2V8
#define PWR_LVDT_7 PWR_CTLR_LVDT_2V9
/**
* @}
*/
/** @defgroup PWR_LDO_state_in_Deep-sleep_mode
* @{
*/
#define PWR_LDO_ON ((uint32_t)0x00000000)
#define PWR_LDO_LOWPOWER PWR_CTLR_LDOLP
/**
* @}
*/
/** @defgroup PWR_Sleep_mode_entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Deep-sleep_mode_entry
* @{
*/
#define PWR_DEEPSLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_DEEPSLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Standby_mode_entry
* @{
*/
#define PWR_STDBYENTRY_WFI ((uint8_t)0x01)
#define PWR_STDBYENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WKUP PWR_STR_WUF
#define PWR_FLAG_STB PWR_STR_SBF
#define PWR_FLAG_LVDF PWR_STR_LVDF
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccess_Enable(TypeState NewValue);
void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue);
void PWR_WKUP_Pin_Enable(TypeState NewValue);
void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY);
void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY);
void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY);
TypeState PWR_GetBitState(uint32_t PWR_FLAG);
void PWR_ClearBitState(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_PWR_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h Normal file
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h Normal file
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/**
******************************************************************************
* @brief RTC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_RTC_H
#define __GD32F10X_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_Exported_Defines
* @{
*/
/** @defgroup RTC_Interrupt_Def
* @{
*/
#define RTC_INT_OVF ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_INT_AF ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_INT_SF ((uint16_t)0x0001) /*!< Second interrupt */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Flags
* @{
*/
#define RTC_FLAG_LWOFF ((uint16_t)0x0020) /*!< Last write operation finished flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OVF ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_AF ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_SF ((uint16_t)0x0001) /*!< Second flag */
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions
* @{
*/
void RTC_INT_Enable(uint16_t RTC_int, TypeState NewValue);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmTime);
uint32_t RTC_GetDividerValue(void);
void RTC_WaitLWOFF(void);
void RTC_WaitRSF(void);
TypeState RTC_GetBitState(uint16_t RTC_flag);
void RTC_ClearBitState(uint16_t RTC_flag);
TypeState RTC_GetIntBitState(uint16_t RTC_INT);
void RTC_ClearIntBitState(uint16_t RTC_INT);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_RTC_H */
/**
* @}
*/
/**
* @}
*/

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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h Normal file
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/**
******************************************************************************
* @brief SDIO header file of the firmware library
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_SDIO_H
#define __GD32F10X_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_Exported_Types
* @{
*/
typedef struct {
uint32_t SDIO_ClockEdge; /*!< Configure the SDIO Clock edge on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge*/
uint32_t SDIO_ClockBypassState; /*!< Configure the SDIO Clock divider bypass mode
This parameter can be a value of @ref SDIO_Clock_Bypass_State */
uint32_t SDIO_ClockPWRSave; /*!< Configure the SDIO Clock output powersave mode when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusMode; /*!< Configure the SDIO bus mode.
This parameter can be a value of @ref SDIO_Bus_Mode */
uint32_t SDIO_HWFlowCtrlState; /*!< Configure the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_HW_Flow_Control_State */
uint8_t SDIO_ClockDiv; /*!< Configure the clock frequency prescaler of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitPara;
typedef struct {
uint32_t SDIO_CMDParameter; /*!< Configure the SDIO command parameter which is sent to
a card as part of a command message. */
uint32_t SDIO_CMDIndex; /*!< Configure the SDIO command index. */
uint32_t SDIO_ResponseType; /*!< Configure the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_WaitINTState; /*!< Configure whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CSMState; /*!< Configure SDIO Command state machine (CSM) is enabled or disabled.
This parameter can be a value of @ref SDIO_CSM_State */
} SDIO_CmdInitPara;
typedef struct {
uint32_t SDIO_DataTimeOut; /*!< Configure the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /*!< Configure the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /*!< Configure the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransDirection; /*!< Configure the data transfer direction, read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransMode; /*!< Configure whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Mode */
uint32_t SDIO_DSMState; /*!< Configure whether SDIO Data state machine (DSM) is enabled or disabled.
This parameter can be a value of @ref SDIO_DSM_State */
} SDIO_DataInitPara;
/**
* @}
*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_CLOCKEDGE_RISING ((uint32_t)0x00000000)
#define SDIO_CLOCKEDGE_FALLING ((uint32_t)0x00002000)
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass_State
* @{
*/
#define SDIO_CLOCKBYPASSSTATE_DISABLE ((uint32_t)0x00000000)
#define SDIO_CLOCKBYPASSSTATE_ENABLE ((uint32_t)0x00000400)
/**
* @}
*/
/** @defgroup SDIO_Clock_PWR_Save
* @{
*/
#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000)
#define SDIO_CLOCKPWRSAVE_ENABLE ((uint32_t)0x00000200)
/**
* @}
*/
/** @defgroup SDIO_Bus_Mode
* @{
*/
#define SDIO_BUSMODE_1B ((uint32_t)0x00000000)
#define SDIO_BUSMODE_4B ((uint32_t)0x00000800)
#define SDIO_BUSMODE_8B ((uint32_t)0x00001000)
/**
* @}
*/
/** @defgroup SDIO_HW_Flow_Control_State
* @{
*/
#define SDIO_HWFLOWCTRLSTATE_DISABLE ((uint32_t)0x00000000)
#define SDIO_HWFLOWCTRLSTATE_ENABLE ((uint32_t)0x00004000)
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PWRSTATE_OFF ((uint32_t)0x00000000)
#define SDIO_PWRSTATE_ON ((uint32_t)0x00000003)
/**
* @}
*/
/** @defgroup SDIO_Interrupt_sources
* @{
*/
#define SDIO_INT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_INT_DTCRCFAIL ((uint32_t)0x00000002)
#define SDIO_INT_CMDTMOUT ((uint32_t)0x00000004)
#define SDIO_INT_DTTMOUT ((uint32_t)0x00000008)
#define SDIO_INT_TXURE ((uint32_t)0x00000010)
#define SDIO_INT_RXORE ((uint32_t)0x00000020)
#define SDIO_INT_CMDREND ((uint32_t)0x00000040)
#define SDIO_INT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_INT_DTEND ((uint32_t)0x00000100)
#define SDIO_INT_STBITE ((uint32_t)0x00000200)
#define SDIO_INT_DTBLKEND ((uint32_t)0x00000400)
#define SDIO_INT_CMDRUN ((uint32_t)0x00000800)
#define SDIO_INT_TXRUN ((uint32_t)0x00001000)
#define SDIO_INT_RXRUN ((uint32_t)0x00002000)
#define SDIO_INT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_INT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_INT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_INT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_INT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_INT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_INT_TXDTVAL ((uint32_t)0x00100000)
#define SDIO_INT_RXDTVAL ((uint32_t)0x00200000)
#define SDIO_INT_SDIOINT ((uint32_t)0x00400000)
#define SDIO_INT_ATAEND ((uint32_t)0x00800000)
/**
* @}
*/
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_RESPONSETYPE_NO ((uint32_t)0x00000000)
#define SDIO_RESPONSETYPE_SHORT ((uint32_t)0x00000040)
#define SDIO_RESPONSETYPE_LONG ((uint32_t)0x000000C0)
/**
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_WAITINTSTATE_NO ((uint32_t)0x00000000)
#define SDIO_WAITINTSTATE_INT ((uint32_t)0x00000100)
#define SDIO_WAITINTSTATE_PEND ((uint32_t)0x00000200)
/**
* @}
*/
/** @defgroup SDIO_CSM_State
* @{
*/
#define SDIO_CSMSTATE_DISABLE ((uint32_t)0x00000000)
#define SDIO_CSMSTATE_ENABLE ((uint32_t)0x00000400)
/**
* @}
*/
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
/**
* @}
*/
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DATABLOCKSIZE_1B ((uint32_t)0x00000000)
#define SDIO_DATABLOCKSIZE_2B ((uint32_t)0x00000010)
#define SDIO_DATABLOCKSIZE_4B ((uint32_t)0x00000020)
#define SDIO_DATABLOCKSIZE_8B ((uint32_t)0x00000030)
#define SDIO_DATABLOCKSIZE_16B ((uint32_t)0x00000040)
#define SDIO_DATABLOCKSIZE_32B ((uint32_t)0x00000050)
#define SDIO_DATABLOCKSIZE_64B ((uint32_t)0x00000060)
#define SDIO_DATABLOCKSIZE_128B ((uint32_t)0x00000070)
#define SDIO_DATABLOCKSIZE_256B ((uint32_t)0x00000080)
#define SDIO_DATABLOCKSIZE_512B ((uint32_t)0x00000090)
#define SDIO_DATABLOCKSIZE_1024B ((uint32_t)0x000000A0)
#define SDIO_DATABLOCKSIZE_2048B ((uint32_t)0x000000B0)
#define SDIO_DATABLOCKSIZE_4096B ((uint32_t)0x000000C0)
#define SDIO_DATABLOCKSIZE_8192B ((uint32_t)0x000000D0)
#define SDIO_DATABLOCKSIZE_16384B ((uint32_t)0x000000E0)
/**
* @}
*/
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000)
#define SDIO_TRANSDIRECTION_TOSDIO ((uint32_t)0x00000002)
/**
* @}
*/
/** @defgroup SDIO_Transfer_Mode
* @{
*/
#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000)
#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004)
/**
* @}
*/
/** @defgroup SDIO_DSM_State
* @{
*/
#define SDIO_DSMSTATE_DISABLE ((uint32_t)0x00000000)
#define SDIO_DSMSTATE_ENABLE ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup SDIO_Flag
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DTCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CMDTMOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTTMOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXURE ((uint32_t)0x00000010)
#define SDIO_FLAG_RXORE ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DTEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITE ((uint32_t)0x00000200)
#define SDIO_FLAG_DTBLKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800)
#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000)
#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDTVAL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDTVAL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000)
#define SDIO_FLAG_ATAEND ((uint32_t)0x00800000)
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_READWAITMODE_CLK ((uint32_t)0x00000001)
#define SDIO_READWAITMODE_DAT2 ((uint32_t)0x00000000)
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions
* @{
*/
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct);
void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct);
void SDIO_Clock_Enable(TypeState NewState);
void SDIO_SetPWRState(uint32_t SDIO_PWRState);
uint32_t SDIO_GetPWRState(void);
void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewState);
void SDIO_DMA_Enable(TypeState NewState);
void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct);
void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct);
uint8_t SDIO_GetCMDResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct);
void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct);
uint32_t SDIO_GetDataCount(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(TypeState NewState);
void SDIO_StopSDIOReadWait(TypeState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(TypeState NewState);
void SDIO_SendSDIOSuspend_Enable(TypeState NewState);
void SDIO_CMDCompletion_Enable(TypeState NewState);
void SDIO_CEATAInt_Enable(TypeState NewState);
void SDIO_SendCEATA_Enable(TypeState NewState);
TypeState SDIO_GetBitState(uint32_t SDIO_FLAG);
void SDIO_ClearBitState(uint32_t SDIO_FLAG);
TypeState SDIO_GetIntBitState(uint32_t SDIO_INT);
void SDIO_ClearIntBitState(uint32_t SDIO_INT);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_SDIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief SPI header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_SPI_H
#define __GD32F10X_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Initial Parameters
*/
typedef struct {
uint16_t SPI_TransType; /*!< The transfer type, choose one from @ref SPI_transfer_type. */
uint16_t SPI_Mode; /*!< The operating mode, choose one from @ref SPI_mode. */
uint16_t SPI_FrameFormat; /*!< The SPI data frame format, choose one from @ref SPI_data_frame_format. */
uint16_t SPI_SCKPL; /*!< The clock polarity in idel state, choose one from @ref SPI_Clock_Polarity. */
uint16_t SPI_SCKPH; /*!< The clock phase, choose one from @ref SPI_Clock_Phase. */
uint16_t SPI_SWNSSEN; /*!< The NSS signal management, choose one from @ref SPI_Software_NSS_management. */
uint16_t SPI_PSC; /*!< The Baud Rate prescaler value, choose one from @ref SPI_BaudRate_Prescaler. */
uint16_t SPI_FirstBit; /*!< The data transfers start from MSB or LSB bit, choose one from @ref SPI_MSB_LSB_transmission. */
uint16_t SPI_CRCPOL; /*!< The polynomial used for the CRC calculation. */
} SPI_InitPara;
/**
* @brief I2S Initial Parameters
*/
typedef struct {
uint16_t I2S_Mode; /*!< The operating mode and transfer direction, choose one from @ref I2S_Mode. */
uint16_t I2S_STD; /*!< The I2S standard, choose one from @ref I2S_Standard. */
uint16_t I2S_FrameFormat; /*!< The I2S data length and channel length, choose one from @ref I2S_Data_Format. */
uint16_t I2S_MCKOE; /*!< The I2S MCK output is enabled or disable, choose one from @ref I2S_MCLK_Output. */
uint32_t I2S_AudioFreq; /*!< The audio sampling frequency, choose one from @ref I2S_Audio_Frequency. */
uint16_t I2S_CKPL; /*!< The clock polarity in idel state, choose one from @ref I2S_Clock_Polarity. */
} I2S_InitPara;
/**
* @}
*/
/** @defgroup SPI_Exported_Constants
* @{
*/
/** @defgroup SPI_transfer_type
* @{
*/
#define SPI_TRANSTYPE_FULLDUPLEX ((uint16_t)0x0000)
#define SPI_TRANSTYPE_RXONLY SPI_CTLR1_RO
#define SPI_TRANSTYPE_BDMRX SPI_CTLR1_BDM
#define SPI_TRANSTYPE_BDMTX (SPI_CTLR1_BDM | SPI_CTLR1_BDOE)
/**
* @}
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_MODE_MASTER (SPI_CTLR1_MSTMODE|SPI_CTLR1_SWNSS)
#define SPI_MODE_SLAVE ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup SPI_data_frame_format
* @{
*/
#define SPI_FRAMEFORMAT_16BIT SPI_CTLR1_FF16
#define SPI_FRAMEFORMAT_8BIT ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_SCKPL_LOW ((uint16_t)0x0000)
#define SPI_SCKPL_HIGH SPI_CTLR1_SCKPL
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_SCKPH_1EDGE ((uint16_t)0x0000)
#define SPI_SCKPH_2EDGE SPI_CTLR1_SCKPH
/**
* @}
*/
/** @defgroup SPI_Software_NSS_management
* @{
*/
#define SPI_SWNSS_SOFT SPI_CTLR1_SWNSSEN
#define SPI_SWNSS_HARD ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_PSC_2 ((uint16_t)0x0000)
#define SPI_PSC_4 ((uint16_t)0x0008)
#define SPI_PSC_8 ((uint16_t)0x0010)
#define SPI_PSC_16 ((uint16_t)0x0018)
#define SPI_PSC_32 ((uint16_t)0x0020)
#define SPI_PSC_64 ((uint16_t)0x0028)
#define SPI_PSC_128 ((uint16_t)0x0030)
#define SPI_PSC_256 ((uint16_t)0x0038)
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint16_t)0x0000)
#define SPI_FIRSTBIT_LSB SPI_CTLR1_LF
/**
* @}
*/
/** @defgroup I2S_Mode
* @{
*/
#define I2S_MODE_SLAVETX ((uint16_t)0x0000)
#define I2S_MODE_SLAVERX ((uint16_t)0x0100)
#define I2S_MODE_MASTERTX ((uint16_t)0x0200)
#define I2S_MODE_MASTERRX ((uint16_t)0x0300)
/**
* @}
*/
/** @defgroup I2S_Standard
* @{
*/
#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
#define I2S_STD_MSB ((uint16_t)0x0010)
#define I2S_STD_LSB ((uint16_t)0x0020)
#define I2S_STD_PCMSHORT ((uint16_t)0x0030)
#define I2S_STD_PCMLONG ((uint16_t)0x00B0)
/**
* @}
*/
/** @defgroup I2S_Data_Format
* @{
*/
#define I2S_FRAMEFORMAT_DL16b_CL16b ((uint16_t)0x0000)
#define I2S_FRAMEFORMAT_DL16b_CL32b ((uint16_t)0x0001)
#define I2S_FRAMEFORMAT_DL24b_CL32b ((uint16_t)0x0003)
#define I2S_FRAMEFORMAT_DL32b_CL32b ((uint16_t)0x0005)
/**
* @}
*/
/** @defgroup I2S_MCLK_Output
* @{
*/
#define I2S_MCK_ENABLE SPI_I2SCKP_MCKOE
#define I2S_MCK_DISABLE ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency
* @{
*/
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity
* @{
*/
#define I2S_CKPL_LOW ((uint16_t)0x0000)
#define I2S_CKPL_HIGH SPI_I2SCTLR_CKPL
/**
* @}
*/
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMA_TX SPI_CTLR2_DMATE
#define SPI_I2S_DMA_RX SPI_CTLR2_DMARE
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_SWNSS_SET ((uint16_t)0x0001)
#define SPI_SWNSS_RESET ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_TX ((uint8_t)0x00)
#define SPI_CRC_RX ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_BDOE_RX (~SPI_CTLR1_BDOE)
#define SPI_BDOE_TX SPI_CTLR1_BDOE
/**
* @}
*/
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_INT_TBE ((uint8_t)0x71)
#define SPI_I2S_INT_RBNE ((uint8_t)0x60)
#define SPI_I2S_INT_ERR ((uint8_t)0x50)
#define SPI_I2S_INT_OVR ((uint8_t)0x56)
#define SPI_INT_MODF ((uint8_t)0x55)
#define SPI_INT_CRCERR ((uint8_t)0x54)
#define I2S_INT_UDR ((uint8_t)0x53)
/**
* @}
*/
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_FLAG_RBNE SPI_STR_RBNE
#define SPI_FLAG_TBE SPI_STR_TBE
#define SPI_FLAG_CRCERR SPI_STR_CRCE
#define SPI_FLAG_MODF SPI_STR_CONFE
#define SPI_FLAG_OVR SPI_STR_RXORE
#define SPI_FLAG_BSY SPI_STR_TRANS
#define I2S_FLAG_RBNE SPI_STR_RBNE
#define I2S_FLAG_TBE SPI_STR_TBE
#define I2S_FLAG_CHSIDE SPI_STR_I2SCH
#define I2S_FLAG_UDR SPI_STR_TXURE
#define I2S_FLAG_OVR SPI_STR_RXORE
#define I2S_FLAG_BSY SPI_STR_TRANS
/**
* @}
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Functions
* @{
*/
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitPara *SPI_InitParameter);
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitPara *I2S_InitParameter);
void SPI_ParaInit(SPI_InitPara *SPI_InitParameter);
void I2S_ParaInit(I2S_InitPara *I2S_InitParameter);
void SPI_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
void I2S_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
void SPI_I2S_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT, TypeState NewValue);
void SPI_I2S_DMA_Enable(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, TypeState NewValue);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_SWNSSConfig(SPI_TypeDef *SPIx, uint16_t SPI_SWNSS);
void SPI_NSSDRV(SPI_TypeDef *SPIx, TypeState NewValue);
void SPI_FrameFormatConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
void SPI_SendCRCNext(SPI_TypeDef *SPIx);
void SPI_CRC_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
void SPI_BDOEConfig(SPI_TypeDef *SPIx, uint16_t SPI_BDOE);
TypeState SPI_I2S_GetBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
TypeState SPI_I2S_GetIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT);
void SPI_I2S_ClearIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_SPI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief USART header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_USART_H
#define __GD32F10X_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_Exported_Types
* @{
*/
/**
* @brief USART Initial Parameters
*/
typedef struct {
uint32_t USART_BRR; /*!< the USART communication baud rate configuration */
uint16_t USART_WL; /*!< Set by USART_CTLR1_WL Word length 0: 8 Data bits,
1: 9 Data bits */
uint16_t USART_STBits; /*!< Stop bits configuration */
uint16_t USART_Parity; /*!< Set by USART_CTLR1_PCEN */
uint16_t USART_RxorTx; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitPara;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct {
uint16_t USART_CKEN; /*!< USART clock enabled this parameter can be a value of @ref USART_CKEN */
uint16_t USART_CPL; /*!< Clock polarity of Steady state this parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPH; /*!< Clock phase this parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LBCP; /*!< Last bit clock pulse this parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitPara;
/**
* @}
*/
/** @defgroup USART_Exported_Constants
* @{
*/
/** @defgroup USART_WL
* @{
*/
#define USART_WL_8B ((uint16_t)0x0000)
#define USART_WL_9B USART_CTLR1_WL
/**
* @}
*/
/** @defgroup USART_STBits
* @{
*/
#define USART_STBITS_1 ((uint16_t)0x0000)
#define USART_STBITS_0_5 ((uint16_t)0x1000)
#define USART_STBITS_2 USART_CTLR2_STB_1
#define USART_STBITS_1_5 (USART_CTLR2_STB_0 | USART_CTLR2_STB_1)
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_PARITY_RESET ((uint16_t)0x0000)
#define USART_PARITY_SETEVEN USART_CTLR1_PCEN
#define USART_PARITY_SETODD (USART_CTLR1_PCEN | USART_CTLR1_PM)
/**
* @}
*/
/** @defgroup USART_RxorTx
* @{
*/
#define USART_RXORTX_RX USART_CTLR1_REN
#define USART_RXORTX_TX USART_CTLR1_TEN
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HARDWAREFLOWCONTROL_NONE ((uint16_t)0x0000)
#define USART_HARDWAREFLOWCONTROL_RTS USART_CTLR3_RTSEN
#define USART_HARDWAREFLOWCONTROL_CTS USART_CTLR3_CTSEN
#define USART_HARDWAREFLOWCONTROL_RTS_CTS (USART_CTLR3_RTSEN | USART_CTLR3_CTSEN)
/**
* @}
*/
/** @defgroup USART_CKEN
* @{
*/
#define USART_CKEN_RESET ((uint16_t)0x0000)
#define USART_CKEN_SET USART_CTLR2_CKEN
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPL_LOW ((uint16_t)0x0000)
#define USART_CPL_HIGH USART_CTLR2_CPL
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPH_1EDGE ((uint16_t)0x0000)
#define USART_CPH_2EDGE USART_CTLR2_CPH
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LBCP_DISABLE ((uint16_t)0x0000)
#define USART_LBCP_ENABLE USART_CTLR2_LBCP
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAREQ_TX USART_CTLR3_DENT
#define USART_DMAREQ_RX USART_CTLR3_DENR
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @brief USART Interrupt definition
* USART_INT possible values
* @{
*/
#define USART_INT_PE ((uint16_t)0x0028)
#define USART_INT_TBE ((uint16_t)0x0727)
#define USART_INT_TC ((uint16_t)0x0626)
#define USART_INT_RBNE ((uint16_t)0x0525)
#define USART_INT_IDLEF ((uint16_t)0x0424)
#define USART_INT_LBDF ((uint16_t)0x0846)
#define USART_INT_CTSF ((uint16_t)0x096A)
#define USART_INT_ERIE ((uint16_t)0x0060)
#define USART_INT_ORE ((uint16_t)0x0360)
#define USART_INT_NE ((uint16_t)0x0260)
#define USART_INT_FE ((uint16_t)0x0160)
/**
* @}
*/
/** @defgroup USART_MuteMode_WakeUp_methods
* @{
*/
#define USART_WAKEUP_IDLELINE ((uint16_t)0x0000)
#define USART_WAKEUP_ADDRESSMARK USART_CTLR1_WM
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBREAKDETECTLENGTH_10B ((uint16_t)0x0000)
#define USART_LINBREAKDETECTLENGTH_11B USART_CTLR2_LBDL
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IRDAMODE_LOWPOWER USART_CTLR3_IRLP
#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_CTSF ((uint16_t)0x0200)
#define USART_FLAG_LBDF ((uint16_t)0x0100)
#define USART_FLAG_TBE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RBNE ((uint16_t)0x0020)
#define USART_FLAG_IDLEF ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
/**
* @}
*/
/**
* @}
*/
/** @defgroup USART_Exported_Functions
* @{
*/
void USART_DeInit(USART_TypeDef *USARTx);
void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct);
void USART_ParaInit(USART_InitPara *USART_InitParaStruct);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct);
void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data);
uint16_t USART_DataReceive(USART_TypeDef *USARTx);
void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewState);
void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue);
void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue);
void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue);
TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
void USART_SendBreak(USART_TypeDef *USARTx);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_USART_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief WWDG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_WWDG_H
#define __GD32F10X_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_PRESCALER
* @{
*/
#define WWDG_PRESCALER_1 ((uint32_t)0x00000000)
#define WWDG_PRESCALER_2 ((uint32_t)0x00000080)
#define WWDG_PRESCALER_4 ((uint32_t)0x00000100)
#define WWDG_PRESCALER_8 ((uint32_t)0x00000180)
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescalerValue(uint32_t PrescalerValue);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableInt(void);
void WWDG_SetCounterValue(uint8_t CounterValue);
void WWDG_Enable(uint8_t CounterValue);
TypeState WWDG_GetBitState(void);
void WWDG_ClearBitState(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_WWDG_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief BKP functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_bkp.h"
#include "gd32f10x_rcc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup BKP
* @brief BKP driver modules
* @{
*/
/** @defgroup BKP_Private_Defines
* @{
*/
/* RTCOUTPUT bit is masked in BKP_RCCR register */
#define RTCOUTPUT_MASK ((uint16_t)0xFC7F)
/**
* @}
*/
/** @defgroup BKP_Private_Functions
* @{
*/
/**
* @brief Reset the BKP peripheral registers.
* @param None
* @retval None
*/
void BKP_DeInit(void)
{
RCC_BackupReset_Enable(ENABLE);
RCC_BackupReset_Enable(DISABLE);
}
/**
* @brief Write user data to the BKP_DRx register.
* @param BKP_DR: the Backup Data Register.
* This parameter can be BKP_DRx where x can be (1..42)
* @param Data: data to write
* @retval None
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t temp = 0;
temp = (uint32_t)BKP_BASE;
temp += BKP_DR;
/* Store the write data */
*(__IO uint16_t *) temp = Data;
}
/**
* @brief Read data from the BKP_DRx register.
* @param BKP_DR: The Backup Data Register.
* This parameter can be BKP_DRx where x can be (1..42)
* @retval The content of the BKP_DRx register.
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t temp = 0;
temp = (uint32_t)BKP_BASE;
temp += BKP_DR;
/* Return the BKP_DRx register value */
return (*(__IO uint16_t *) temp);
}
/**
* @brief Configure the RTC output on the Tamper pin.
* @param BKP_RTCOUTPUT: the RTC output.
* This parameter can be one of the following values:
* @arg BKP_RTCOUTPUT_NULL: no RTC output on the TAMPER pin.
* @arg BKP_RTCOUTPUT_CLKCAL: output the RTC clock with frequency
* divided by 64 on the TAMPER pin.
* @arg BKP_RTCOUTPUT_ALARM: output the RTC Alarm pulse signal on
* the TAMPER pin.
* @arg BKP_RTCOUTPUT_SECOND: output the RTC Second pulse signal on
* the TAMPER pin.
* @retval None
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT)
{
uint16_t temp = 0;
temp = BKP->RCCR;
/* Clear RCCOE, ROE and ROS bits */
temp &= RTCOUTPUT_MASK;
/* Set RCCOE, ROE and ROS bits according to BKP_RTCOUTPUT value */
temp |= BKP_RTCOUTPUT;
/* Store the new value */
BKP->RCCR = temp;
}
/**
* @brief Set RTC Clock Calibration value.
* @param CalibrationValue: the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* @retval None
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t temp = 0;
temp = BKP->RCCR;
/* Clear RCCV[6:0] bits */
temp &= ~BKP_RCCR_RCCV;
/* Set CAL[6:0] bits according to CalibrationValue */
temp |= CalibrationValue;
/* Store the new value */
BKP->RCCR = temp;
}
/**
* @brief Configure the TAMPER pin active level.
* @param BKP_TPAL: the TAMPER pin active level.
* This parameter can be one of the following values:
* @arg BKP_TPAL_HIGH: TAMPER pin active on high level
* @arg BKP_TPAL_LOW: TAMPER pin active on low level
* @param NewValue: New value of the TAMPER pin state.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue)
{
uint16_t temp = 0;
temp = BKP->TPCR;
/* Clear TPE bit */
temp &= ~((uint16_t)BKP_TPCR_TPE);
/* Configure TPAL bit according to BKP_TPAL value */
temp |= BKP_TPAL;
/* Store the new value */
BKP->TPCR = temp;
/* Enable the TAMPER pin */
if (NewValue != DISABLE) {
/* The TAMPER pin is dedicated for the Backup Reset function */
BKP->TPCR |= BKP_TPCR_TPE;
} else {
/* The TAMPER pin is free for GPIO functions */
BKP->TPCR &= ~((uint16_t)BKP_TPCR_TPE);
}
}
/**
* @brief Enable or disable the Tamper Interrupt.
* @param NewValue: New value of the Tamper Interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_TamperINT_Enable(TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable the tamper interrupt */
BKP->TIER |= BKP_TIER_TIE;
} else {
/* Disable the tamper interrupt */
BKP->TIER &= ~BKP_TIER_TIE;
}
}
/**
* @brief Get the bit flag of Tamper Event.
* @param None
* @retval The new value of Tamper Event flag (SET or RESET).
*/
TypeState BKP_GetBitState(void)
{
/* Check and get the Tamper Event flag */
if ((BKP->TIER & BKP_TIER_TEF) != (uint16_t)RESET) {
/* Tamper Event occured */
return SET;
} else {
/* No Tamper Event occured */
return RESET;
}
}
/**
* @brief Clear the bit flag of Tamper Event.
* @param None
* @retval None
*/
void BKP_ClearBitState(void)
{
/* Set the TER bit to clear Tamper Event flag */
BKP->TIER |= BKP_TIER_TER;
}
/**
* @brief Get the interrupt bit flag of Tamper Interrupt.
* @param None
* @retval The new value of the Tamper Interrupt flag (SET or RESET).
*/
TypeState BKP_GetIntBitState(void)
{
/* Check and get the Tamper Interrupt flag */
if ((BKP->TIER & BKP_TIER_TIF) != (uint16_t)RESET) {
/* Tamper Interrupt occured */
return SET;
} else {
/* No Tamper Interrupt occured */
return RESET;
}
}
/**
* @brief Clear the interrupt bit flag of Tamper Interrupt.
* @param None
* @retval None
*/
void BKP_ClearIntBitState(void)
{
/* Set the TIR bit to clear Tamper Interrupt flag */
BKP->TIER |= BKP_TIER_TIR;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief CRC functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_crc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Reset CRC DTR register to the value of 0xFFFFFFFF.
* @param None
* @retval None
*/
void CRC_ResetDTR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data.
* @param CRC_data: data to compute its CRC value
* @retval 32-bit CRC value
*/
uint32_t CRC_CalcSingleData(uint32_t CRC_data)
{
CRC->DTR = CRC_data;
return (CRC->DTR);
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data array.
* @param pbuffer[]: pointer to the data array
* @param buffer_length: length of the data array
* @retval 32-bit CRC value
*/
uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length)
{
uint32_t index = 0;
for (index = 0; index < buffer_length; index++) {
CRC->DTR = pbuffer[index];
}
return (CRC->DTR);
}
/**
* @brief Read current CRC value.
* @param None
* @retval 32-bit CRC value
*/
uint32_t CRC_ReadDTR(void)
{
return (CRC->DTR);
}
/**
* @brief Write an 8-bit data in FDTR.
* @param CRC_fdtr: 8-bit data to write
* @retval None
*/
void CRC_WriteFDTR(uint8_t CRC_fdtr)
{
CRC->FDTR = CRC_fdtr;
}
/**
* @brief Read the 8-bit data stored in FDTR
* @param None
* @retval 8-bit data
*/
uint8_t CRC_ReadFDTR(void)
{
return (CRC->FDTR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief DAC functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_dac.h"
#include "gd32f10x_rcc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/** @defgroup DAC_Private_Defines
* @{
*/
/* CTLR register bits mask */
#define CTLR_BITS_CLEAR ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/**
* @}
*/
/** @defgroup DAC_Private_Functions
* @{
*/
/**
* @brief Deinitialize the DAC peripheral registers.
* @param DAC_InitParaStruct: DAC_InitPara structure that contains the
* configuration information for the selected DAC channel.
* @retval None
*/
void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct)
{
/* Enable DAC reset state */
RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, DISABLE);
/* Initialize the DAC_Trigger */
DAC_InitParaStruct->DAC_Trigger = DAC_TRIGGER_NONE;
/* Initialize the DAC_WaveGeneration */
DAC_InitParaStruct->DAC_WaveType = DAC_WAVEGENE_NONE;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude */
DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle = DAC_LFSR_BIT0;
/* Initialize the DAC_OutputBuffer */
DAC_InitParaStruct->DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
}
/**
* @brief Initialize the DAC peripheral.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1
* @arg DAC_Channel_2: select DAC Channel2
* @param DAC_InitStruct: DAC_InitTypeDef structure .
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct)
{
uint32_t temp1 = 0, temp2 = 0;
/* DAC CTLR Configuration */
/* Get the DAC CTLR value */
temp1 = DAC->CTLR;
/* Clear BOFF, TEN, TSEL, WAVE and MAMP bits */
temp1 &= ~(CTLR_BITS_CLEAR << DAC_Channel);
/* Configure for the DAC channel: buffer output, trigger, wave generation,
mask/amplitude for wave generation */
/* Set TSEL and TEN bits according to DAC_Trigger */
/* Set WAVE bits according to DAC_WaveType */
/* Set MAMP bits according to DAC_LFSRNoise_AmplitudeTriangle */
/* Set BOFF bit according to DAC_OutputBuffer */
temp2 = (DAC_InitParaStruct->DAC_Trigger | DAC_InitParaStruct->DAC_OutputBuffer |
DAC_InitParaStruct->DAC_WaveType | DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle);
/* Calculate CTLR register value */
temp1 |= temp2 << DAC_Channel;
/* Write to DAC CTLR */
DAC->CTLR = temp1;
}
/**
* @brief Enable or disable the DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1.
* @arg DAC_Channel_2: select DAC Channel2.
* @param NewValue: New value of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable the selected DAC channel */
DAC->CTLR |= (DAC_CTLR_DEN1 << DAC_Channel) ;
} else {
/* Disable the selected DAC channel */
DAC->CTLR &= ~(DAC_CTLR_DEN1 << DAC_Channel);
}
}
/**
* @brief Enable or disable the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1
* @arg DAC_Channel_2: select DAC Channel2
* @param NewValue: New value of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable software trigger for DAC channel1 */
DAC->SWTR |= (uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4);
} else {
/* Disable software trigger for DAC channel1 */
DAC->SWTR &= ~((uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enable or disable simultaneously the two DAC channels software
* triggers.
* @param NewValue: new value of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTrigger_Enable(TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable software trigger */
DAC->SWTR |= DUAL_SWTRIG_SET ;
} else {
/* Disable software trigger */
DAC->SWTR &= ~DUAL_SWTRIG_SET;
}
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1
* @arg DAC_Channel_2: select DAC Channel2
* @param DAC_Wave: the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_WAVE_NOISE: noise wave generation
* @arg DAC_WAVE_TRIANGLE: triangle wave generation
* @param NewValue: new value of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable the selected DAC channel wave generation */
DAC->CTLR |= DAC_Wave << DAC_Channel;
} else {
/* Disable the selected DAC channel wave generation */
DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: select 8bit right data alignment
* @arg DAC_ALIGN_12B_L: select 12bit left data alignment
* @arg DAC_ALIGN_12B_R: select 12bit right data alignment
* @param Data: Data to be loaded.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t temp = 0;
temp = (uint32_t)DAC_BASE;
temp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 */
*(__IO uint32_t *) temp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: select 8bit right data alignment
* @arg DAC_ALIGN_12B_L: select 12bit left data alignment
* @arg DAC_ALIGN_12B_R: select 12bit right data alignment
* @param Data: Data to be loaded.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t temp = 0;
temp = (uint32_t)DAC_BASE;
temp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 */
*(__IO uint32_t *) temp = Data;
}
/**
* @brief Set the specified data for dual channel
* @param DAC_Align: the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: select 8bit right data alignment
* @arg DAC_Align_12b_L: select 12bit left data alignment
* @arg DAC_Align_12b_R: select 12bit right data alignment
* @param Data2: Data for DAC Channel2.
* @param Data1: Data for DAC Channel1.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, temp = 0;
/* set dual DAC data holding register value */
if (DAC_Align == DAC_ALIGN_8B_R) {
data = ((uint32_t)Data2 << 8) | Data1;
} else {
data = ((uint32_t)Data2 << 16) | Data1;
}
temp = (uint32_t)DAC_BASE;
temp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)temp = data;
}
/**
* @brief Return the last data output value.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1
* @arg DAC_Channel_2: select DAC Channel2
* @retval The DAC channel1 data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t temp = 0;
temp = (uint32_t) DAC_BASE;
temp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data */
return (uint16_t)(*(__IO uint32_t *) temp);
}
/**
* @brief Enable or disable DMA request.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: select DAC Channel1
* @arg DAC_Channel_2: select DAC Channel2
* @param NewValue: New value of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable DMA request */
DAC->CTLR |= (DAC_CTLR_DDMAEN1 << DAC_Channel);
} else {
/* Disable DMA request */
DAC->CTLR &= ~(DAC_CTLR_DDMAEN1 << DAC_Channel);
}
}
/**
* @brief Enable or disable the specified DAC interrupts.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewValue: Alternative state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_INTConfig(uint32_t DAC_Channel, TypeState NewValue)
{
if (NewValue != DISABLE) {
/* Enable the DAC DMAUDR interrupts */
DAC->CTLR |= (DAC_INT_DMAUDR << DAC_Channel);
} else {
/* Disable the DAC DMAUDR interrupts */
DAC->CTLR &= (~(uint32_t)(DAC_INT_DMAUDR << DAC_Channel));
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief EXTI functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_exti.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/** @defgroup EXTI_Private_Defines
* @{
*/
/* No interrupt line is selected */
#define EXTI_LINE_NULL ((uint32_t)0x00000000)
/* ----------------- EXTI Reset Configuration Registers ------------------ */
/* The reset value of EXTI_IER */
#define EXTI_IER_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_EER */
#define EXTI_EER_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_RTE */
#define EXTI_RTE_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_FTE */
#define EXTI_FTE_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_PD */
#define EXTI_PD_RST ((uint32_t)0x000FFFFF)
/**
* @}
*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/**
* @brief Reset the EXTI peripheral registers and the struct EXTI_InitPara.
* @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
* @retval None
*/
void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct)
{
/* Reset the EXTI peripheral registers */
EXTI->IER = EXTI_IER_RST;
EXTI->EER = EXTI_EER_RST;
EXTI->RTE = EXTI_RTE_RST;
EXTI->FTE = EXTI_FTE_RST;
EXTI->PD = EXTI_PD_RST;
/* Reset the struct EXTI_InitPara */
EXTI_InitParaStruct->EXTI_LINE = EXTI_LINE_NULL;
EXTI_InitParaStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitParaStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitParaStruct->EXTI_LINEEnable = DISABLE;
}
/**
* @brief Initialize the EXTI peripheral registers.
* @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
* @retval None
*/
void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct)
{
uint32_t temp = 0;
temp = (uint32_t)EXTI_BASE;
if (EXTI_InitParaStruct->EXTI_LINEEnable != DISABLE) {
/* Clear Interrupt and Event from EXTI Lines */
EXTI->IER &= ~EXTI_InitParaStruct->EXTI_LINE;
EXTI->EER &= ~EXTI_InitParaStruct->EXTI_LINE;
temp += EXTI_InitParaStruct->EXTI_Mode;
*(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
/* Clear the Rising and Falling edge trigger enable registers */
EXTI->RTE &= ~EXTI_InitParaStruct->EXTI_LINE;
EXTI->FTE &= ~EXTI_InitParaStruct->EXTI_LINE;
/* Select the trigger type for the selected EXTI Lines */
if (EXTI_InitParaStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
/* Rising and Falling edge trigger are both selected */
EXTI->RTE |= EXTI_InitParaStruct->EXTI_LINE;
EXTI->FTE |= EXTI_InitParaStruct->EXTI_LINE;
} else {
temp = (uint32_t)EXTI_BASE;
temp += EXTI_InitParaStruct->EXTI_Trigger;
*(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
}
} else {
temp += EXTI_InitParaStruct->EXTI_Mode;
/* Disable the selected EXTI lines */
*(__IO uint32_t *) temp &= ~EXTI_InitParaStruct->EXTI_LINE;
}
}
/**
* @brief Activate the software interrupt or event request of the selected EXTI Lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_SWINT_Enable(uint32_t EXTI_LINE)
{
/* Enable the software interrupt or event request of the selected EXTI Lines */
EXTI->SIE |= EXTI_LINE;
}
/**
* @brief Get the bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval The new value of EXTI_LINE (SET or RESET).
*/
TypeState EXTI_GetBitState(uint32_t EXTI_LINE)
{
/* Check and get the selected EXTI lines flag */
if ((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) {
/* EXTI_LINE bit is SET */
return SET;
} else {
/* EXTI_LINE bit is RESET */
return RESET;
}
}
/**
* @brief Clear the bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_ClearBitState(uint32_t EXTI_LINE)
{
/* Clear the bit flag of the selected EXTI lines */
EXTI->PD = EXTI_LINE;
}
/**
* @brief Get the interrupt bit flag of the selected EXTI lines..
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval The new value of EXTI_LINE (SET or RESET).
*/
TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE)
{
/* Check and get the interrupt source is set or not */
if (((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) && ((EXTI->IER & EXTI_LINE) != (uint32_t)RESET)) {
/* The interrupt bit of EXTI_LINE is SET */
return SET;
} else {
/* The interrupt bit of EXTI_LINE is RESET */
return RESET;
}
}
/**
* @brief Clear the interrupt bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_ClearIntBitState(uint32_t EXTI_LINE)
{
/* Clear the interrupt bit flag of the selected EXTI lines */
EXTI->PD = EXTI_LINE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief IWDG functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_iwdg.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/** @defgroup IWDG_Private_Variables
* @{
*/
/* CTLR register bit mask */
#define CTLR_KEY_RELOAD ((uint16_t)0xAAAA)
#define CTLR_KEY_ENABLE ((uint16_t)0xCCCC)
/**
* @}
*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/**
* @brief Enable or disable the IWDG_PSR, IWDG_RLDR and IWDG_WND write protection.
* @param IWDG_WriteAccess: value to enable or disable the write access to registers.
* This parameter can be one of the following values:
* @arg IWDG_WRITEACCESS_ENABLE: Enable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
* @arg IWDG_WRITEACCESS_DISABLE: Disable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
* @retval None
*/
void IWDG_Write_Enable(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/**
* @brief Set IWDG prescaler value.
* @param PrescalerValue: IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_PRESCALER_4: IWDG prescaler set to 4
* @arg IWDG_PRESCALER_8: IWDG prescaler set to 8
* @arg IWDG_PRESCALER_16: IWDG prescaler set to 16
* @arg IWDG_PRESCALER_32: IWDG prescaler set to 32
* @arg IWDG_PRESCALER_64: IWDG prescaler set to 64
* @arg IWDG_PRESCALER_128: IWDG prescaler set to 128
* @arg IWDG_PRESCALER_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t PrescalerValue)
{
IWDG->PSR = PrescalerValue;
}
/**
* @brief Set independent watchdog counter reload value.
* @param ReloadValue: IWDG Reload value.
* This parameter must be between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReloadValue(uint16_t ReloadValue)
{
IWDG->RLDR = ReloadValue;
}
/**
* @brief Reload the counter.
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_RELOAD;
}
/**
* @brief Start the independent watchdog counter.
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_ENABLE;
}
/**
* @brief Check registers' bit state.
* @param IWDG_FLAG: the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_BIT_PUD: A write operation to IWDG_PSR register on going
* @arg IWDG_BIT_RUD: A write operation to IWDG_RLDR register on going
* @arg IWDG_BIT_WUD: A write operation to IWDG_WND register on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
TypeState IWDG_GetBitState(uint16_t IWDG_FLAG)
{
if ((IWDG->STR & IWDG_FLAG) != (uint32_t)RESET) {
return SET;
} else {
return RESET;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief MCUDBG functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_mcudbg.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup MCUDBG
* @brief MCUDBG driver modules
* @{
*/
/** @defgroup MCUDBG_Private_Defines
* @{
*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup MCUDBG_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t MCUDBG_GetREVID(void)
{
return (MCUDBG->IDR >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t MCUDBG_GetDEVID(void)
{
return (MCUDBG->IDR & IDCODE_DEVID_MASK);
}
/**
* @brief Configure the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param MCUDBG_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg MCUDBG_SLEEP_HOLD: Keep debugger connection during SLEEP mode
* @arg MCUDBG_DEEPSLEEP_HOLD: Keep debugger connection during DEEPSLEEP mode
* @arg MCUDBG_STDBY_HOLD: Keep debugger connection during STANDBY mode
* @arg MCUDBG_IWDG_HOLD: Debug IWDG hold when Core is halted
* @arg MCUDBG_WWDG_HOLD: Debug WWDG hold when Core is halted
* @arg MCUDBG_TIMER1_HOLD: TIMER1 counter hold when Core is halted
* @arg MCUDBG_TIMER2_HOLD: TIMER2 counter hold when Core is halted
* @arg MCUDBG_TIMER3_HOLD: TIMER3 counter hold when Core is halted
* @arg MCUDBG_TIMER4_HOLD: TIMER4 counter hold when Core is halted
* @arg MCUDBG_CAN1_HOLD: Debug CAN1 hold when Core is halted
* @arg MCUDBG_I2C1_HOLD: I2C1 SMBUS timeout mode hold when Core is halted
* @arg MCUDBG_I2C2_HOLD: I2C2 SMBUS timeout mode hold when Core is halted
* @arg MCUDBG_TIMER5_HOLD: TIMER5 counter hold when Core is halted
* @arg MCUDBG_TIMER6_HOLD: TIMER6 counter hold when Core is halted
* @arg MCUDBG_TIMER7_HOLD: TIMER7 counter hold when Core is halted
* @arg MCUDBG_TIMER8_HOLD: TIMER8 counter hold when Core is halted
* @arg MCUDBG_CAN2_HOLD: Debug CAN2 hold when Core is halted
* @arg MCUDBG_TIMER12_HOLD: TIMER12 counter hold when Core is halted
* @arg MCUDBG_TIMER13_HOLD: TIMER13 counter hold when Core is halted
* @arg MCUDBG_TIMER14_HOLD: TIMER14 counter hold when Core is halted
* @arg MCUDBG_TIMER9_HOLD: TIMER9 counter hold when Core is halted
* @arg MCUDBG_TIMER10_HOLD: TIMER10 counter hold when Core is halted
* @arg MCUDBG_TIMER11_HOLD: TIMER11 counter hold when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue)
{
if (NewValue != DISABLE) {
MCUDBG->CTLR |= MCUDBG_Periph;
} else {
MCUDBG->CTLR &= ~MCUDBG_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @brief MISC functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_misc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief By the PRIGROUP[10:8] bits of the AIRCR register, Setting the priority grouping:
* pre-emption priority and subpriority.
* @param NVIC_PriGroup: NVIC_PRIGROUP_0, NVIC_PRIGROUP_1,...NVIC_PRIGROUP_4.
* @retval None
*/
void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup)
{
/* Set the priority grouping value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PRIGroup;
}
/**
* @brief The NVIC peripheral Initialization.
* @param NVIC_InitStruct: a NVIC_InitPara structure pointer.
* @retval None
*/
void NVIC_Init(NVIC_InitPara *NVIC_InitStruct)
{
uint32_t temppriority = 0x00, temppreempt = 0x00, tempsub = 0x00;
if (NVIC_InitStruct->NVIC_IRQEnable != DISABLE) {
if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_0) {
temppreempt = 0;
tempsub = 0x4;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_1) {
temppreempt = 1;
tempsub = 0x3;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_2) {
temppreempt = 2;
tempsub = 0x2;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_3) {
temppreempt = 3;
tempsub = 0x1;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_4) {
temppreempt = 4;
tempsub = 0x0;
}
temppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQPreemptPriority << (0x4 - temppreempt);
temppriority |= NVIC_InitStruct->NVIC_IRQSubPriority & (0x0F >> (0x4 - tempsub));
temppriority = temppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQ] = temppriority;
/* Enable the Selected IRQ Channels */
NVIC->ISER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
} else {
/* Disable the Selected IRQ Channels */
NVIC->ICER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
}
}
/**
* @brief Specify the vector table in RAM or FLASH memory and its Offset.
* @param NVIC_VectTab: NVIC_VECTTAB_RAM,NVIC_VECTTAB_FLASH
* @param Offset: Vector Table start address.
* @retval None
*/
void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset)
{
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Specify the state of the system to enter low power mode.
* @param LowPowerMode: NVIC_LOWPOWER_SEVONPEND,NVIC_LOWPOWER_SLEEPDEEP,NVIC_LOWPOWER_SLEEPONEXIT.
* @param NewValue: new value of Low Power state. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue)
{
if (NewValue != DISABLE) {
SCB->SCR |= LowPowerMode;
} else {
SCB->SCR &= (~(uint32_t)LowPowerMode);
}
}
/**
* @brief Specify the SysTick clock source.
* @param SysTick_CKSource: SYSTICK_CKSOURCE_HCLK_DIV8,SYSTICK_CKSOURCE_HCLK.
* @retval None
*/
void SysTick_CKSource_Enable(uint32_t SysTick_CKSource)
{
if (SysTick_CKSource == SYSTICK_CKSOURCE_HCLK) {
SysTick->CTRL |= SYSTICK_CKSOURCE_HCLK;
} else {
SysTick->CTRL &= SYSTICK_CKSOURCE_HCLK_DIV8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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