sync smart & dfs (#8672)

Signed-off-by: xqyjlj <xqyjlj@126.com>
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: xqyjlj <xqyjlj@126.com>

components/lwp/arch/aarch64/cortex-a/lwp_arch.c

@@ -8,6 +8,7 @@
  * 2021-05-18     Jesven       first version
  * 2023-07-16     Shell        Move part of the codes to C from asm in signal handling
  * 2023-10-16     Shell        Support a new backtrace framework
+ * 2023-08-03     Shell        Support of syscall restart (SA_RESTART)
  */
 
 #include <armv8.h>
@@ -123,6 +124,7 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack,
 
 #define ALGIN_BYTES (16)
 
+/* the layout is part of ABI, dont change it */
 struct signal_ucontext
 {
     rt_int64_t sigreturn;
@@ -130,11 +132,62 @@ struct signal_ucontext
 
     siginfo_t si;
 
-    rt_align(16)
+    rt_align(ALGIN_BYTES)
     struct rt_hw_exp_stack frame;
 };
 
-void *arch_signal_ucontext_restore(rt_base_t user_sp)
+RT_STATIC_ASSERT(abi_offset_compatible, offsetof(struct signal_ucontext, si) == UCTX_ABI_OFFSET_TO_SI);
+
+void *arch_signal_ucontext_get_frame(struct signal_ucontext *uctx)
+{
+    return &uctx->frame;
+}
+
+/* internal used only */
+void arch_syscall_prepare_signal(rt_base_t rc, struct rt_hw_exp_stack *exp_frame)
+{
+    long x0 = exp_frame->x0;
+    exp_frame->x0 = rc;
+    exp_frame->x7 = x0;
+    return ;
+}
+
+void arch_syscall_restart(void *sp, void *ksp);
+
+void arch_syscall_set_errno(void *eframe, int expected, int code)
+{
+    struct rt_hw_exp_stack *exp_frame = eframe;
+    if (exp_frame->x0 == -expected)
+        exp_frame->x0 = -code;
+    return ;
+}
+
+void arch_signal_check_erestart(void *eframe, void *ksp)
+{
+    struct rt_hw_exp_stack *exp_frame = eframe;
+    long rc = exp_frame->x0;
+    long sys_id = exp_frame->x8;
+    (void)sys_id;
+
+    if (rc == -ERESTART)
+    {
+        LOG_D("%s(rc=%ld,sys_id=%ld,pid=%d)", __func__, rc, sys_id, lwp_self()->pid);
+        LOG_D("%s: restart rc = %ld", lwp_get_syscall_name(sys_id), rc);
+        exp_frame->x0 = exp_frame->x7;
+        arch_syscall_restart(eframe, ksp);
+    }
+
+    return ;
+}
+
+static void arch_signal_post_action(struct signal_ucontext *new_sp, rt_base_t kernel_sp)
+{
+    arch_signal_check_erestart(&new_sp->frame, (void *)kernel_sp);
+
+    return ;
+}
+
+void *arch_signal_ucontext_restore(rt_base_t user_sp, rt_base_t kernel_sp)
 {
     struct signal_ucontext *new_sp;
     new_sp = (void *)user_sp;
@@ -142,6 +195,7 @@ void *arch_signal_ucontext_restore(rt_base_t user_sp)
     if (lwp_user_accessable(new_sp, sizeof(*new_sp)))
     {
         lwp_thread_signal_mask(rt_thread_self(), LWP_SIG_MASK_CMD_SET_MASK, &new_sp->save_sigmask, RT_NULL);
+        arch_signal_post_action(new_sp, kernel_sp);
     }
     else
     {
@@ -157,7 +211,7 @@ void *arch_signal_ucontext_save(rt_base_t user_sp, siginfo_t *psiginfo,
                                 lwp_sigset_t *save_sig_mask)
 {
     struct signal_ucontext *new_sp;
-    new_sp = (void *)(user_sp - sizeof(struct signal_ucontext));
+    new_sp = (void *)((user_sp - sizeof(struct signal_ucontext)) & ~0xf);
 
     if (lwp_user_accessable(new_sp, sizeof(*new_sp)))
     {

components/lwp/arch/aarch64/cortex-a/lwp_arch.h

@@ -11,8 +11,7 @@
 #ifndef  LWP_ARCH_H__
 #define  LWP_ARCH_H__
 
-#include <lwp.h>
-#include <lwp_arch_comm.h>
+#include <rtconfig.h>
 
 #ifdef ARCH_MM_MMU
 
@@ -26,6 +25,13 @@
 #define USER_VADDR_START  0x00200000UL
 #define USER_LOAD_VADDR   USER_VADDR_START
 
+#define UCTX_ABI_OFFSET_TO_SI 16
+
+#ifndef __ASSEMBLY__
+
+#include <lwp.h>
+#include <lwp_arch_comm.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -34,7 +40,7 @@ unsigned long rt_hw_ffz(unsigned long x);
 
 rt_inline void icache_invalid_all(void)
 {
-    asm volatile ("ic ialluis\n\tisb sy":::"memory");
+    __asm__ volatile ("ic ialluis\n\tisb sy":::"memory");
 }
 
 /**
@@ -57,11 +63,14 @@ void *arch_signal_ucontext_save(rt_base_t user_sp, siginfo_t *psiginfo,
  * @param user_sp sp of user
  * @return void*
  */
-void *arch_signal_ucontext_restore(rt_base_t user_sp);
+void *arch_signal_ucontext_restore(rt_base_t user_sp, rt_base_t kernel_sp);
+void arch_syscall_restart(void *sp, void *ksp);
+
 #ifdef __cplusplus
 }
 #endif
+#endif /* __ASSEMBLY__ */
 
-#endif
+#endif /* ARCH_MM_MMU */
 
 #endif  /*LWP_ARCH_H__*/

components/lwp/arch/aarch64/cortex-a/lwp_gcc.S

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2021-05-18     Jesven       first version
  * 2023-07-16     Shell        Move part of the codes to C from asm in signal handling
+ * 2023-08-03     Shell        Support of syscall restart (SA_RESTART)
  */
 
 #ifndef __ASSEMBLY__
@@ -17,6 +18,7 @@
 #include "asm-generic.h"
 #include "asm-fpu.h"
 #include "armv8.h"
+#include "lwp_arch.h"
 
 /*********************
  *      SPSR BIT     *
@@ -155,6 +157,14 @@ START_POINT_END(SVC_Handler)
 
 .global arch_syscall_exit
 arch_syscall_exit:
+
+    /**
+     * @brief back up former x0 which is required to restart syscall, then setup
+     * syscall return value in stack frame
+     */
+    mov x1, sp
+    bl arch_syscall_prepare_signal
+
     msr daifset, #3
 
     ldp x2, x3, [sp], #0x10  /* SPSR and ELR. */
@@ -177,7 +187,10 @@ arch_syscall_exit:
     ldp x12, x13, [sp], #0x10
     ldp x10, x11, [sp], #0x10
     ldp x8, x9, [sp], #0x10
-    add sp, sp, #0x40
+    ldp x6, x7, [sp], #0x10
+    ldp x4, x5, [sp], #0x10
+    ldp x2, x3, [sp], #0x10
+    ldp x0, x1, [sp], #0x10
     RESTORE_FPU sp
 
 /* the sp is reset to the outer most level, irq and fiq are disabled */
@@ -383,10 +396,53 @@ lwp_check_debug_quit:
     ldp x29, x30, [sp], #0x10
     ret
 
+.global arch_syscall_restart
+arch_syscall_restart:
+    msr daifset, 3
+
+    mov sp, x1
+    /* drop exception frame in user stack */
+    msr sp_el0, x0
+
+    /* restore previous exception frame */
+    msr spsel, #0
+
+    ldp x2, x3, [sp], #0x10
+    msr elr_el1, x2
+    msr spsr_el1, x3
+
+    ldp x29, x30, [sp], #0x10
+
+    ldp x28, x29, [sp], #0x10
+    msr fpcr, x28
+    msr fpsr, x29
+
+    ldp x28, x29, [sp], #0x10
+    ldp x26, x27, [sp], #0x10
+    ldp x24, x25, [sp], #0x10
+    ldp x22, x23, [sp], #0x10
+    ldp x20, x21, [sp], #0x10
+    ldp x18, x19, [sp], #0x10
+    ldp x16, x17, [sp], #0x10
+    ldp x14, x15, [sp], #0x10
+    ldp x12, x13, [sp], #0x10
+    ldp x10, x11, [sp], #0x10
+    ldp x8, x9, [sp], #0x10
+    ldp x6, x7, [sp], #0x10
+    ldp x4, x5, [sp], #0x10
+    ldp x2, x3, [sp], #0x10
+    ldp x0, x1, [sp], #0x10
+    RESTORE_FPU sp
+
+    msr spsel, #1
+
+    b vector_exception
+
 arch_signal_quit:
 
     /* drop current exception frame */
     add sp, sp, #CONTEXT_SIZE
+    mov x1, sp
     mrs x0, sp_el0
     bl  arch_signal_ucontext_restore
     add x0, x0, #-CONTEXT_SIZE
@@ -456,6 +512,11 @@ arch_thread_signal_enter:
 
     /* arch_signal_ucontext_save(user_sp, psiginfo, exp_frame, save_sig_mask); */
     bl arch_signal_ucontext_save
+    mov x22, x0
+    /* get and saved pointer to uframe */
+    bl arch_signal_ucontext_get_frame
+    mov x2, x0
+    mov x0, x22
 
     dc cvau, x0
     dsb sy
@@ -483,12 +544,15 @@ arch_thread_signal_enter:
     /** set the return address to the sigreturn */
     mov x30, x0
 
+    cbnz x21, 1f
+    mov x21, x30
+1:
     /** set the entry address of signal handler */
     msr elr_el1, x21
 
     /* siginfo is above the return address */
-    add x2, x30, 16
-    add x1, x2, #CONTEXT_SIZE
+    add x1, x30, UCTX_ABI_OFFSET_TO_SI
+    /* uframe is saved in x2 */
     mov x0, x19
 
     /**

components/lwp/arch/arm/cortex-a/lwp_arch.c

@@ -192,6 +192,12 @@ void *arch_signal_ucontext_save(rt_base_t lr, siginfo_t *psiginfo,
     return new_sp;
 }
 
+void arch_syscall_set_errno(void *eframe, int expected, int code)
+{
+    /* NO support */
+    return ;
+}
+
 #ifdef LWP_ENABLE_ASID
 #define MAX_ASID_BITS 8
 #define MAX_ASID (1 << MAX_ASID_BITS)

components/lwp/arch/arm/cortex-a/lwp_arch.h

@@ -35,7 +35,7 @@ rt_inline unsigned long rt_hw_ffz(unsigned long x)
 
 rt_inline void icache_invalid_all(void)
 {
-    asm volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu
+    __asm__ volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu
 }
 
 unsigned int arch_get_asid(struct rt_lwp *lwp);

components/lwp/arch/risc-v/rv64/lwp_arch.c

@@ -242,6 +242,7 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack,
      * |                        |
      * +------------------------+ --> thread sp
      */
+    return 0;
 }
 
 #define ALGIN_BYTES (16)
@@ -317,6 +318,12 @@ void *arch_signal_ucontext_save(int signo, siginfo_t *psiginfo,
     return new_sp;
 }
 
+void arch_syscall_set_errno(void *eframe, int expected, int code)
+{
+    /* NO support */
+    return ;
+}
+
 /**
  * void lwp_exec_user(void *args, void *kernel_stack, void *user_entry)
  */