support cv181x c906_little (#8680)

bsp/cvitek/.gitignore

@@ -1,2 +1,6 @@
+cvitek_bootloader
 fip.bin
-boot.sd
+boot.sd
+output
+c906_little/board/script
+Image.lzma

bsp/cvitek/README.md

@@ -8,7 +8,7 @@
 
 | 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 |
 | ------- | ------- |------- | -------- | -------- |
-| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 |
+| cv180x | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 |
 
 - 小核
 
@@ -18,10 +18,30 @@
 
 > 注：异构芯片需单独编译每个核的 OS
 
+## 编译
+异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行:
+
+1. 开发板选择
+Linux平台下，可以先执行：
+```shell
+$ scons --menuconfig
+```
+
+选择当前需要编译的目标开发板类型
+```shell
+Board Type (milkv-duo)  --->
+    ( ) milkv-duo
+    (X) milkv-duo256m
+```
+
+2. 编译
+```shell
+$ scons
+```
 
 ## 运行
 
-编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。
+编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。
 
 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。
 2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。
@@ -39,10 +59,22 @@
 
 ## 支持开发板
 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
+- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m)
 
 ## FAQ
 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。
 
+2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory
+
+可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。
+或使用以下命令下载安装:
+```shell
+$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+```
+
 ## 联系人信息
 
-维护人：[flyingcys](https://github.com/flyingcys)
+维护人：[flyingcys](https://github.com/flyingcys)
+
+更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io)

bsp/cvitek/c906_little/.config

@@ -1001,6 +1001,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
 
 #
 # Display
@@ -1087,3 +1088,5 @@ CONFIG_BSP_USING_C906_LITTLE=y
 CONFIG_PLIC_PHY_ADDR=0x70000000
 CONFIG_IRQ_MAX_NR=128
 CONFIG_TIMER_CLK_FREQ=25000000
+# CONFIG_BOARD_TYPE_MILKV_DUO is not set
+CONFIG_BOARD_TYPE_MILKV_DUO256M=y

bsp/cvitek/c906_little/Kconfig

@@ -37,4 +37,14 @@ config IRQ_MAX_NR
 
 config TIMER_CLK_FREQ
     int
-    default 25000000
+    default 25000000
+
+choice
+    prompt "Board Type"
+    default BOARD_TYPE_MILKV_DUO256M
+
+    config BOARD_TYPE_MILKV_DUO
+        bool "milkv-duo"
+    config BOARD_TYPE_MILKV_DUO256M
+        bool "milkv-duo256m"
+endchoice

bsp/cvitek/c906_little/README.md

@@ -17,20 +17,37 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
 ```
 
 ## 编译
-1. Linux平台下，可以先执行：
+1. 依赖安装
+
+```shell
+$ sudo apt install -y scons libncurses5-dev wget flex bison
+```
+
+
+2. Linux平台下，先执行：
 ```shell
 $ scons --menuconfig
 ```
 
-它会自动下载env相关脚本到~/.env目录，然后执行
+选择当前需要编译的目标开发板类型
+```shell
+Board Type (milkv-duo)  --->
+    ( ) milkv-duo
+    (X) milkv-duo256m
+```
+
+它会自动下载 env 相关脚本到 ~/.env 目录，然后执行
 ```shell
 $ source ~/.env/env.sh
 $ pkgs --update
 ```
-更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。
 
 编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。
 
+第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。
+
+下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。
 
 ## 运行
 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。

bsp/cvitek/c906_little/SConstruct

@@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 # include libraries
 objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
 
+if GetDepend('BOARD_TYPE_MILKV_DUO256M'):
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld')
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x')
+
 # make a building
 DoBuilding(TARGET, objs)

bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld

@@ -7,6 +7,8 @@
  * Date           Author       Notes
  * 2024/01/11     flyingcys    The first version
  */
+INCLUDE ./cvi_board_memmap.ld
+
 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
 /* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
 /*_HEAP_SIZE =  0x20000;*/
@@ -15,9 +17,6 @@ _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
 
-CVIMMAP_FREERTOS_ADDR = 0x83f40000;
-CVIMMAP_FREERTOS_SIZE = 0xc0000;
-
 /* Define Memories in the system */
 
 MEMORY

bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld

@@ -0,0 +1,30 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x82473000;
+CVIMMAP_BOOTLOGO_SIZE = 0x0;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x4000000;
+CVIMMAP_FREERTOS_ADDR = 0x83f40000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0;
+CVIMMAP_FREERTOS_SIZE = 0xc0000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x0;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x82473000;
+CVIMMAP_ION_SIZE = 0x1acd000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x0;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81400000;
+CVIMMAP_UIMAG_SIZE = 0xf00000;

bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024/01/11     flyingcys    The first version
+ */
+INCLUDE ./cvi_board_memmap.ld
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
+/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
+/*_HEAP_SIZE =  0x20000;*/
+
+_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
+_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
+_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE
+}
+
+/* Specify the default entry point to the program */
+
+/*ENTRY(_vector_table)*/
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+
+   /* section information for finsh shell */
+   . = ALIGN(8);
+   __fsymtab_start = .;
+   KEEP(*(FSymTab))
+   __fsymtab_end = .;
+   . = ALIGN(8);
+   __vsymtab_start = .;
+   KEEP(*(VSymTab))
+   __vsymtab_end = .;
+   . = ALIGN(8);
+
+   /* section information for initial. */
+   . = ALIGN(8);
+   __rt_init_start = .;
+   KEEP(*(SORT(.rti_fn*)))
+   __rt_init_end = .;
+   . = ALIGN(8);
+
+   __rt_utest_tc_tab_start = .;
+   KEEP(*(UtestTcTab))
+   __rt_utest_tc_tab_end = .;
+} > psu_ddr_0_MEM_0
+
+.init (ALIGN(64)) : {
+   KEEP (*(.init))
+} > psu_ddr_0_MEM_0
+
+.fini (ALIGN(64)) : {
+   KEEP (*(.fini))
+} > psu_ddr_0_MEM_0
+
+.interp : {
+   KEEP (*(.interp))
+} > psu_ddr_0_MEM_0
+
+.note-ABI-tag : {
+   KEEP (*(.note-ABI-tag))
+} > psu_ddr_0_MEM_0
+
+.rodata : {
+   . = ALIGN(64);
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.srodata*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > psu_ddr_0_MEM_0
+
+.rodata1 : {
+   . = ALIGN(64);
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > psu_ddr_0_MEM_0
+
+.data : {
+   . = ALIGN(64);
+   _data = .;
+   *(.data)
+   *(.data.*)
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   _edata = .;
+} > psu_ddr_0_MEM_0
+
+.data1 : {
+   . = ALIGN(64);
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > psu_ddr_0_MEM_0
+
+.got : {
+   *(.got)
+} > psu_ddr_0_MEM_0
+
+.got1 : {
+   *(.got1)
+} > psu_ddr_0_MEM_0
+
+.got2 : {
+   *(.got2)
+} > psu_ddr_0_MEM_0
+
+.ctors : {
+   . = ALIGN(64);
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.dtors : {
+   . = ALIGN(64);
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > psu_ddr_0_MEM_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > psu_ddr_0_MEM_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > psu_ddr_0_MEM_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > psu_ddr_0_MEM_0
+
+.bss (NOLOAD) : {
+   . = ALIGN(64);
+   _bss = .;
+   *(.bss)
+   *(.bss.*)
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(64);
+   _ebss = .;
+} > psu_ddr_0_MEM_0
+
+/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/
+    _data_lma = LOADADDR(.data);
+
+/* Generate Stack and Heap definitions */
+.stack (NOLOAD) : {
+   . = ALIGN(64);
+   _stack_end_end = .;
+   . += _STACK_SIZE;
+   _stack_top = .;
+  __rt_rvstack = .; 
+} > psu_ddr_0_MEM_0
+
+.heap (NOLOAD) : {
+   . = ALIGN(64);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   *(.heap*)
+   /*. += _HEAP_SIZE;*/
+   /*_heap_size = _HEAP_SIZE; */
+   _heap_end = .;
+   HeapLimit = .;
+} > psu_ddr_0_MEM_0
+
+HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0);
+_end = .;
+}
+

bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld

@@ -0,0 +1,32 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000;
+CVIMMAP_BOOTLOGO_SIZE = 0x1c2000;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x10000000;
+CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000;
+CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000;
+CVIMMAP_FREERTOS_ADDR = 0x8fe00000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000;
+CVIMMAP_FREERTOS_SIZE = 0x200000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x8b300000;
+CVIMMAP_ION_SIZE = 0x4b00000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81800000;
+CVIMMAP_UIMAG_SIZE = 0x1000000;

bsp/cvitek/c906_little/rtconfig.h

@@ -268,5 +268,6 @@
 #define PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 128
 #define TIMER_CLK_FREQ 25000000
+#define BOARD_TYPE_MILKV_DUO256M
 
 #endif

bsp/cvitek/c906_little/rtconfig.py

@@ -18,7 +18,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)
@@ -47,9 +47,10 @@ if PLATFORM == 'gcc':
     CFLAGS += ' -DCONFIG_64BIT'
 
     LINKER_SCRIPTS = r'cv180x_lscript.ld'
+    LINKER_SCRIPTS_PATH = r' -L board/script/cv180x'
 
     AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS  = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    LFLAGS  = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH
     CPATH   = ''
     LPATH   = ''
 
@@ -63,4 +64,4 @@ if PLATFORM == 'gcc':
 
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n'
+POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n'

bsp/cvitek/combine-fip.sh

@@ -1,23 +1,84 @@
 #!/bin/bash
 
-set -e
+PROJECT_PATH=$1
+IMAGE_NAME=$2
 
-LITTLE_BIN=$1
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+	echo "Usage: $0 <PROJECT_DIR> <IMAGE_NAME>"
+	exit 1
+fi
 
-. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \
-./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \
-	'fip.bin' \
-	--MONITOR_RUNADDR="${MONITOR_RUNADDR}" \
-	--BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \
-	--CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \
-	--NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \
-	--NAND_INFO='00000000'\
-	--BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \
-	--BLCP_IMG_RUNADDR=0x05200200 \
-	--BLCP_PARAM_LOADADDR=0 \
-	--BLCP=pre-build/fsbl/test/empty.bin \
-	--DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \
-	--BLCP_2ND=$LITTLE_BIN \
-	--MONITOR='pre-build/fw_dynamic.bin' \
-	--LOADER_2ND='pre-build/u-boot-raw.bin' \
-	--compress='lzma'
+ROOT_PATH=$(pwd)
+echo $ROOT_PATH
+
+function get_board_type()
+{
+	BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M")
+	BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m")
+
+	for ((i=0;i<${#BOARD_CONFIG[@]};i++))
+	do
+		config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2)
+		if [ "$config_value" == "y" ]; then
+			BOARD_TYPE=${BOARD_VALUE[i]}
+			break
+		fi
+	done
+}
+
+get_board_type
+echo "board_type: ${BOARD_TYPE}"
+
+COUNTRY=China
+function get_country()
+{
+	restult=$(curl -m 10 -s http://www.ip-api.com/json)
+	COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/')
+	echo "Country: $COUNTRY"
+}
+
+if [ "$COUNTRY" == "China" ]; then
+	cvitek_bootloader_url=https://gitee.com/flyingcys/cvitek_bootloader
+else
+	cvitek_bootloader_url=https://github.com/flyingcys/cvitek_bootloader
+fi
+
+if [ ! -d cvitek_bootloader ]; then
+	echo "cvitek_bootloader not exist, clone it from ${cvitek_bootloader_url}"
+	git clone ${cvitek_bootloader_url}
+
+	if [ $? -ne 0 ]; then
+    	echo "Failed to clone ${cvitek_bootloader_url} !"
+      	exit 1
+    fi
+fi
+
+export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME}
+
+pushd cvitek_bootloader
+
+. env.sh
+
+get_build_board ${BOARD_TYPE}
+
+echo "board: ${MV_BOARD_LINK}"
+
+if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] ||  [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then
+	do_build
+	
+	CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]')
+	cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L}
+else
+	echo "Build already done, skip build"
+
+	do_combine
+
+	if [ $? -ne 0 ]; then
+		do_build
+	fi
+fi
+
+popd
+
+mkdir -p output/${MV_BOARD}
+cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin

bsp/cvitek/cv1800b/mksdimg.sh

@@ -1,7 +0,0 @@
-#/bin/sh
-set -e
-echo "start compress kernel..."
-
-lzma -c -9 -f -k Image > Image.lzma
-
-./mkimage -f multi.its -r ../boot.sd

bsp/cvitek/cv180x/.config

@@ -1048,6 +1048,7 @@ CONFIG_RT_USING_LDSO=y
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
 
 #
 # Display
@@ -1130,8 +1131,9 @@ CONFIG_UART_IRQ_BASE=44
 # CONFIG_RT_USING_UART4 is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_PWM is not set
-CONFIG_BSP_USING_CV1800B=y
+CONFIG_BSP_USING_CV180X=y
 CONFIG_C906_PLIC_PHY_ADDR=0x70000000
 CONFIG_IRQ_MAX_NR=64
 CONFIG_TIMER_CLK_FREQ=25000000
 CONFIG___STACKSIZE__=4096
+CONFIG_BOARD_TYPE_MILKV_DUO=y

bsp/cvitek/cv180x/Kconfig

@@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 source "board/Kconfig"
 
-config BSP_USING_CV1800B
+config BSP_USING_CV180X
     bool
     select ARCH_RISCV64
     select RT_USING_SYSTEM_WORKQUEUE
@@ -45,3 +45,11 @@ config TIMER_CLK_FREQ
 config __STACKSIZE__
     int "stack size for interrupt"
     default 4096
+
+choice
+    prompt "Board Type"
+    default BOARD_TYPE_MILKV_DUO
+
+    config BOARD_TYPE_MILKV_DUO
+        bool "milkv-duo"
+endchoice

bsp/cvitek/cv180x/README.md

@@ -49,8 +49,9 @@ $ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin
 1. 依赖安装
 
 ```shell
-$ sudo apt install -y device-tree-compiler
+$ sudo apt install -y scons libncurses5-dev device-tree-compiler
 ```
+
 2. Linux平台下，可以先执行：
 ```shell
 $ scons --menuconfig
@@ -61,7 +62,7 @@ $ scons --menuconfig
 $ source ~/.env/env.sh
 $ pkgs --update
 ```
-更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生 rtthread.elf 文件。
 
 编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。
 

bsp/cvitek/cv180x/rtconfig.h

@@ -311,10 +311,11 @@
 #define BSP_USING_UART
 #define RT_USING_UART0
 #define UART_IRQ_BASE 44
-#define BSP_USING_CV1800B
+#define BSP_USING_CV180X
 #define C906_PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 64
 #define TIMER_CLK_FREQ 25000000
 #define __STACKSIZE__ 4096
+#define BOARD_TYPE_MILKV_DUO
 
 #endif

bsp/cvitek/cv180x/rtconfig.py

@@ -25,6 +25,7 @@ if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
 
 BUILD = 'debug'
+CHIP_TYPE = 'cv180x'
 
 if PLATFORM == 'gcc':
     # toolchains
@@ -56,4 +57,5 @@ if PLATFORM == 'gcc':
     CXXFLAGS = CFLAGS
 
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n'

bsp/cvitek/drivers/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/cvitek/drivers/SConscript

@@ -2,17 +2,23 @@ from building import *
 
 cwd     = GetCurrentDir()
 src     = Split('''
-drv_uart.c
-drv_por.c
+    drv_uart.c
+    drv_por.c
 ''')
 CPPDEFINES = []
 
 CPPPATH = [cwd]
 
-if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'):
-    CPPPATH += [cwd + r'/cv1800b']
+CHIP_TYPE = 'cv180x'
+if GetDepend('BOARD_TYPE_MILKV_DUO256M'):
+    CHIP_TYPE = 'cv181x'
+elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'):
+    CHIP_TYPE = 'cv180x'
 
-if GetDepend('BSP_USING_CV1800B'):
+CPPPATH += [cwd + r'/libraries']
+CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE]
+
+if GetDepend('BSP_USING_CV180X'):
     src += ['drv_gpio.c']
 
 if GetDepend('BSP_USING_I2C'):
@@ -26,7 +32,8 @@ if GetDepend('BSP_USING_WDT'):
 
 if GetDepend('BSP_USING_PWM'):
     src += ['drv_pwm.c']
-    CPPPATH += [cwd + r'/cv1800b/pwm']
+    CPPPATH += [cwd + r'/libraries/cv180x/pwm']
+    
 CPPDEFINES += ['-DCONFIG_64BIT']
 
 if GetDepend('BSP_USING_RTC'):

bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h

@@ -0,0 +1,46 @@
+#ifndef _CV181X_PINMUX_H_
+#define _CV181X_PINMUX_H_
+
+#define PINMUX_UART0    0
+#define PINMUX_UART1    1
+#define PINMUX_UART2    2
+#define PINMUX_UART3    3
+#define PINMUX_UART3_2  4
+#define PINMUX_I2C0     5
+#define PINMUX_I2C1     6
+#define PINMUX_I2C2     7
+#define PINMUX_I2C3     8
+#define PINMUX_I2C4     9
+#define PINMUX_I2C4_2   10
+#define PINMUX_SPI0     11
+#define PINMUX_SPI1     12
+#define PINMUX_SPI2     13
+#define PINMUX_SPI2_2   14
+#define PINMUX_SPI3     15
+#define PINMUX_SPI3_2   16
+#define PINMUX_I2S0     17
+#define PINMUX_I2S1     18
+#define PINMUX_I2S2     19
+#define PINMUX_I2S3     20
+#define PINMUX_USBID    21
+#define PINMUX_SDIO0    22
+#define PINMUX_SDIO1    23
+#define PINMUX_ND       24
+#define PINMUX_EMMC     25
+#define PINMUX_SPI_NOR  26
+#define PINMUX_SPI_NAND 27
+#define PINMUX_CAM0     28
+#define PINMUX_CAM1     29
+#define PINMUX_PCM0     30
+#define PINMUX_PCM1     31
+#define PINMUX_CSI0     32
+#define PINMUX_CSI1     33
+#define PINMUX_CSI2     34
+#define PINMUX_DSI      35
+#define PINMUX_VI0      36
+#define PINMUX_VO       37
+#define PINMUX_PWM1     38
+#define PINMUX_UART4    39
+#define PINMUX_SPI_NOR1 40
+
+#endif // end of _CV181X_PINMUX_H_

bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h

@@ -0,0 +1,475 @@
+// $Module: fmux_gpio $
+// $RegisterBank Version: V 1.0.00 $
+// $Author: ghost $
+// $Date: Fri, 30 Jul 2021 08:58:54 PM $
+//
+
+//GEN REG ADDR/OFFSET/MASK
+#define  FMUX_GPIO_REG_IOCTRL_CAM_MCLK0  0x0
+#define  FMUX_GPIO_REG_IOCTRL_CAM_PD0  0x4
+#define  FMUX_GPIO_REG_IOCTRL_CAM_RST0  0x8
+#define  FMUX_GPIO_REG_IOCTRL_CAM_MCLK1  0xc
+#define  FMUX_GPIO_REG_IOCTRL_CAM_PD1  0x10
+#define  FMUX_GPIO_REG_IOCTRL_IIC3_SCL  0x14
+#define  FMUX_GPIO_REG_IOCTRL_IIC3_SDA  0x18
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CLK  0x1c
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CMD  0x20
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D0  0x24
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D1  0x28
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D2  0x2c
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D3  0x30
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CD  0x34
+#define  FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN  0x38
+#define  FMUX_GPIO_REG_IOCTRL_SPK_EN  0x3c
+#define  FMUX_GPIO_REG_IOCTRL_UART0_TX  0x40
+#define  FMUX_GPIO_REG_IOCTRL_UART0_RX  0x44
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_RSTN  0x48
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT2  0x4c
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_CLK  0x50
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT0  0x54
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT3  0x58
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_CMD  0x5c
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT1  0x60
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS  0x64
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK  0x68
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST  0x6c
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SCL  0x70
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SDA  0x74
+#define  FMUX_GPIO_REG_IOCTRL_AUX0  0x78
+#define  FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET  0x7c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_RSTN  0x80
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ1  0x84
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ2  0x88
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ3  0x8c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0  0x90
+#define  FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1  0x94
+#define  FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1  0x98
+#define  FMUX_GPIO_REG_IOCTRL_PWR_ON  0x9c
+#define  FMUX_GPIO_REG_IOCTRL_XTAL_XIN  0xa0
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO0  0xa4
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO1  0xa8
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO2  0xac
+#define  FMUX_GPIO_REG_IOCTRL_CLK32K  0xb0
+#define  FMUX_GPIO_REG_IOCTRL_CLK25M  0xb4
+#define  FMUX_GPIO_REG_IOCTRL_IIC2_SCL  0xb8
+#define  FMUX_GPIO_REG_IOCTRL_IIC2_SDA  0xbc
+#define  FMUX_GPIO_REG_IOCTRL_UART2_TX  0xc0
+#define  FMUX_GPIO_REG_IOCTRL_UART2_RTS  0xc4
+#define  FMUX_GPIO_REG_IOCTRL_UART2_RX  0xc8
+#define  FMUX_GPIO_REG_IOCTRL_UART2_CTS  0xcc
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D3  0xd0
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D2  0xd4
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D1  0xd8
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D0  0xdc
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CMD  0xe0
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CLK  0xe4
+#define  FMUX_GPIO_REG_IOCTRL_RSTN  0xe8
+#define  FMUX_GPIO_REG_IOCTRL_PWM0_BUCK  0xec
+#define  FMUX_GPIO_REG_IOCTRL_ADC3  0xf0
+#define  FMUX_GPIO_REG_IOCTRL_ADC2  0xf4
+#define  FMUX_GPIO_REG_IOCTRL_ADC1  0xf8
+#define  FMUX_GPIO_REG_IOCTRL_USB_ID  0xfc
+#define  FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN  0x100
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE0  0x104
+#define  FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET  0x108
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE1  0x10c
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE2  0x110
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO  0x114
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI  0x118
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS  0x11c
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK  0x120
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM  0x124
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP  0x128
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM  0x12c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP  0x130
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D10  0x134
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D9  0x138
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D8  0x13c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D7  0x140
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D6  0x144
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D5  0x148
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D4  0x14c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D3  0x150
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D2  0x154
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D1  0x158
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D0  0x15c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_CLK  0x160
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N  0x164
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P  0x168
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N  0x16c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P  0x170
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N  0x174
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P  0x178
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N  0x17c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P  0x180
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N  0x184
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P  0x188
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N  0x18c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P  0x190
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4  0x194
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4  0x198
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3  0x19c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3  0x1a0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2  0x1a4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2  0x1a8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1  0x1ac
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1  0x1b0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0  0x1b4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0  0x1b8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC  0x1bc
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC  0x1c0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL  0x1c4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR  0x1c8
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_RTX  0x1cc
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_ZQ  0x1d0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0   0x0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0   0x4
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0   0x8
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1   0xc
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1   0x10
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL   0x14
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA   0x18
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK   0x1c
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD   0x20
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D0   0x24
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D1   0x28
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D2   0x2c
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D3   0x30
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CD   0x34
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN   0x38
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPK_EN   0x3c
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_TX   0x40
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_RX   0x44
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN   0x48
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2   0x4c
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK   0x50
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0   0x54
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3   0x58
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD   0x5c
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1   0x60
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS   0x64
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK   0x68
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST   0x6c
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL   0x70
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA   0x74
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_AUX0   0x78
+#define  FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_AUX0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET   0x7c
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN   0x80
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1   0x84
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2   0x88
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3   0x8c
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0   0x90
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1   0x94
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1   0x98
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_ON   0x9c
+#define  FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_ON_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN   0xa0
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0   0xa4
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1   0xa8
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2   0xac
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CLK32K   0xb0
+#define  FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CLK32K_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CLK25M   0xb4
+#define  FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CLK25M_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL   0xb8
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA   0xbc
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_TX   0xc0
+#define  FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_TX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS   0xc4
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_RX   0xc8
+#define  FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_RX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS   0xcc
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D3   0xd0
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D2   0xd4
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D1   0xd8
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D0   0xdc
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD   0xe0
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK   0xe4
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_RSTN   0xe8
+#define  FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK   0xec
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC3   0xf0
+#define  FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC2   0xf4
+#define  FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC1   0xf8
+#define  FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_ID   0xfc
+#define  FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_ID_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN   0x100
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0   0x104
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET   0x108
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1   0x10c
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2   0x110
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO   0x114
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI   0x118
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS   0x11c
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK   0x120
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM   0x124
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP   0x128
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM   0x12c
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP   0x130
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10   0x134
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9   0x138
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8   0x13c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7   0x140
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6   0x144
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5   0x148
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4   0x14c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3   0x150
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2   0x154
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1   0x158
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0   0x15c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK   0x160
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N   0x164
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P   0x168
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N   0x16c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P   0x170
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N   0x174
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P   0x178
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N   0x17c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P   0x180
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N   0x184
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P   0x188
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N   0x18c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P   0x190
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4   0x194
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4   0x198
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3   0x19c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3   0x1a0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2   0x1a4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2   0x1a8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1   0x1ac
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1   0x1b0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0   0x1b4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0   0x1b8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC   0x1bc
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC   0x1c0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL   0x1c4
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR   0x1c8
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX   0x1cc
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ   0x1d0
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK   0x7

bsp/cvitek/drivers/libraries/cv181x/pinctrl.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
+ *
+ * File Name: pinctrl.h
+ * Description:
+ */
+
+#ifndef __PINCTRL_CV181X_H__
+#define __PINCTRL_CV181X_H__
+
+//#include "../core.h"
+#include "cv181x_pinlist_swconfig.h"
+#include "cv181x_reg_fmux_gpio.h"
+
+#define  PAD_MIPI_TXM4__MIPI_TXM4 0
+#define  PAD_MIPI_TXP4__MIPI_TXP4 0
+#define  PAD_MIPI_TXM3__MIPI_TXM3 0
+#define  PAD_MIPI_TXP3__MIPI_TXP3 0
+#define  PAD_MIPI_TXM2__MIPI_TXM2 0
+#define  PAD_MIPI_TXP2__MIPI_TXP2 0
+#define  PAD_MIPI_TXM1__MIPI_TXM1 0
+#define  PAD_MIPI_TXP1__MIPI_TXP1 0
+#define  PAD_MIPI_TXM0__MIPI_TXM0 0
+#define  PAD_MIPI_TXP0__MIPI_TXP0 0
+
+#define PINMUX_BASE 0x03001000
+#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
+#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
+#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
+#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
+		mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
+		PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
+		PINMUX_VALUE(PIN_NAME, FUNC_NAME))
+
+#endif /* __PINCTRL_CV181X_H__ */

bsp/cvitek/mksdimg.sh

@@ -0,0 +1,37 @@
+#/bin/sh
+set -e
+
+PROJECT_PATH=$1
+IMAGE_NAME=$2
+
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+	echo "Usage: $0 <PROJECT_DIR> <IMAGE_NAME>"
+	exit 1
+fi
+
+ROOT_PATH=$(pwd)
+echo ${ROOT_PATH}
+
+function get_board_type()
+{
+	BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M")
+	BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m")
+
+	for ((i=0;i<${#BOARD_CONFIG[@]};i++))
+	do
+		config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2)
+		if [ "$config_value" == "y" ]; then
+			BOARD_TYPE=${BOARD_VALUE[i]}
+			break
+		fi
+	done
+}
+
+get_board_type
+
+echo "start compress kernel..."
+
+lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/Image.lzma
+
+mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE}
+./mkimage -f ${PROJECT_PATH}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.sd

bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin

@@ -1 +0,0 @@
-ﾭ<EFBFBD>