更新gicv3中断亲和性设置，重构api: arm_gic_send_affinity_sgi, 增加AMP宏判断, rt_ioremap和宏RT_USING_SMART解耦

修改:中断安装默认绑定至当前核心， 修改rt_hw_interrupt_set_target_cpus函数,

libcpu/aarch64/common/gicv3.h

@@ -41,6 +41,7 @@ rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
 
 void arm_gic_clear_active(rt_uint64_t index, int irq);
 
+void arm_gic_set_router_cpu(rt_uint64_t index, int irq, rt_uint64_t aff);
 void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
 rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
 
@@ -55,7 +56,7 @@ rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
 
 rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
 
-#ifdef RT_USING_SMP
+#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
 void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode);
 #endif
 

libcpu/aarch64/common/interrupt.c

@@ -14,12 +14,8 @@
 #include "interrupt.h"
 #include "gic.h"
 #include "gicv3.h"
-
-#ifdef RT_USING_SMART
 #include "ioremap.h"
-#else
-#define rt_ioremap(x, ...) (x)
-#endif
+
 
 /* exception and interrupt handler table */
 struct rt_irq_desc isr_table[MAX_HANDLERS];
@@ -215,9 +211,15 @@ void rt_hw_interrupt_ack(int vector)
  * @param vector:   the interrupt number
  *        cpu_mask: target cpus mask, one bit for one core
  */
-void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
+void rt_hw_interrupt_set_target_cpus(int vector, unsigned long cpu_mask)
 {
-    arm_gic_set_cpu(0, vector, cpu_mask);
+#ifdef BSP_USING_GIC
+#ifdef BSP_USING_GICV3
+    arm_gic_set_router_cpu(0, vector, cpu_mask);
+#else
+    arm_gic_set_cpu(0, vector, (unsigned int) cpu_mask);
+#endif
+#endif
 }
 
 /**
@@ -379,16 +381,31 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         }
     }
 
+#ifdef BSP_USING_GIC
+    if (vector > 32)
+    {
+#ifdef BSP_USING_GICV3
+        rt_uint64_t cpu_affinity_val;
+        __asm__ volatile ("mrs %0, mpidr_el1":"=r"(cpu_affinity_val));
+        rt_hw_interrupt_set_target_cpus(vector, cpu_affinity_val);
+#else
+        rt_hw_interrupt_set_target_cpus(vector, rt_hw_cpu_id());
+#endif /* BSP_USING_GICV3 */
+    }
+#endif
+
     return old_handler;
 }
 
-#ifdef RT_USING_SMP
+#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
 void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
 {
 #ifdef BSP_USING_GICV2
     arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
 #elif defined(BSP_USING_GICV3)
-    arm_gic_send_affinity_sgi(0, ipi_vector, (unsigned int *)&cpu_mask, GICV3_ROUTED_TO_SPEC);
+    rt_uint32_t gicv3_cpu_mask[(RT_CPUS_NR + 31) >> 5];
+    gicv3_cpu_mask[0] = cpu_mask;
+    arm_gic_send_affinity_sgi(0, ipi_vector, gicv3_cpu_mask, GICV3_ROUTED_TO_SPEC);
 #endif
 }
 

libcpu/aarch64/common/interrupt.h

@@ -30,7 +30,7 @@ void rt_hw_interrupt_umask(int vector);
 int rt_hw_interrupt_get_irq(void);
 void rt_hw_interrupt_ack(int vector);
 
-void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask);
+void rt_hw_interrupt_set_target_cpus(int vector, unsigned long cpu_mask);
 unsigned int rt_hw_interrupt_get_target_cpus(int vector);
 
 void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode);
@@ -52,8 +52,7 @@ unsigned int rt_hw_interrupt_get_prior_group_bits(void);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         void *param, const char *name);
 
-#ifdef RT_USING_SMP
-void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask);
+#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
 void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
 #endif