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[imxrt1170]update sdk files (#6405)

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* update sdk files

* add dcd config

* format files

* formating file
This commit is contained in:
xiao xie authored and GitHub committed 2022-09-09 16:59:08 -04:00
1 parent ba4ffc2094
commit 8317b9058a
5 files changed
+152 -54
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bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/MCUX_Config.mex
+126 -15
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File diff suppressed because it is too large. Load diff
bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.c
+11 -16
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@@ -1,5 +1,5 @@
/*
* Copyright 2020-2021 NXP
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -18,12 +18,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v8.0
product: Clocks v10.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 0.8.1
board: MIMXRT1170-EVK
processor_version: 12.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
@@ -39,8 +38,6 @@ board: MIMXRT1170-EVK
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
@@ -154,7 +151,7 @@ outputs:
- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
- {id: M4_CLK_ROOT.outFreq, value: 240 MHz}
- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
@@ -222,7 +219,8 @@ settings:
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true}
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
@@ -233,7 +231,7 @@ settings:
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
@@ -366,6 +364,7 @@ void BOARD_BootClockRUN(void)
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
@@ -435,26 +434,22 @@ void BOARD_BootClockRUN(void)
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
#endif
/* Configure M4 using SYS_PLL3_PFD3_CLK */
/* Configure M4 using SYS_PLL3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
rootCfg.div = 1;
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* Configure BUS using SYS_PLL3_CLK */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
#endif
/* Configure BUS_LPSR using SYS_PLL3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
rootCfg.div = 3;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
#endif
/* Configure SEMC using SYS_PLL2_PFD1_CLK */
#ifndef SKIP_SEMC_INIT
bsp/imxrt/imxrt1170-nxp-evk/board/MCUX_Config/clock_config.h
+2 -9
View File
@@ -1,10 +1,3 @@
/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
@@ -45,7 +38,7 @@ void BOARD_InitBootClocks(void);
#if __CORTEX_M == 7
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
#else
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */
#endif
/* Clock outputs (values are in Hz): */
@@ -127,7 +120,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 240000000UL
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
bsp/imxrt/imxrt1170-nxp-evk/board/dcd.c
+11 -12
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@@ -27,11 +27,11 @@ __attribute__((section(".boot_hdr.dcd_data"), used))
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: DCDx V2.0
product: DCDx v3.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 0.0.0
processor_version: 12.0.0
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
@@ -40,7 +40,7 @@ const uint8_t dcd_data[] = {
/* Tag */
0xD2,
/* Image Length */
0x05, 0x08,
0x05, 0x10,
/* Version */
0x41,
@@ -49,8 +49,8 @@ const uint8_t dcd_data[] = {
/* group: 'Imported Commands' */
/* #1.1-139, command header bytes for merged 'Write - value' command */
0xCC, 0x04, 0x5C, 0x04,
/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4 */
0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03,
/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */
0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02,
/* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4 */
0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
/* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4 */
@@ -387,13 +387,12 @@ const uint8_t dcd_data[] = {
0xC0, 0x00, 0x04, 0x00,
/* #24, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #25.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */
0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09
};
/* #25, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #26, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #27, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
#else
bsp/imxrt/imxrt1170-nxp-evk/board/dcd.h
+2 -2
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@@ -17,8 +17,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.1. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************