mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-08-21 06:23:35 +08:00
Add RT1021-EVK BSP Support For RTThread By JiCheng
This commit is contained in:
jicheng0622
@@ -0,0 +1,121 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,266 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,197 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U
|
||||
#define ARM_MPU_AP_PRIV 1U
|
||||
#define ARM_MPU_AP_URO 2U
|
||||
#define ARM_MPU_AP_FULL 3U
|
||||
#define ARM_MPU_AP_PRO 5U
|
||||
#define ARM_MPU_AP_RO 6U
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(MPU_RASR_ENABLE_Msk))
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Pos) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@@ -0,0 +1,201 @@
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
other entities that control, are controlled by, or are under common
|
||||
control with that entity. For the purposes of this definition,
|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
exercising permissions granted by this License.
|
||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
including but not limited to software source code, documentation
|
||||
source, and configuration files.
|
||||
|
||||
"Object" form shall mean any form resulting from mechanical
|
||||
transformation or translation of a Source form, including but
|
||||
not limited to compiled object code, generated documentation,
|
||||
and conversions to other media types.
|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or
|
||||
Object form, made available under the License, as indicated by a
|
||||
copyright notice that is included in or attached to the work
|
||||
(an example is provided in the Appendix below).
|
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object
|
||||
form, that is based on (or derived from) the Work and for which the
|
||||
editorial revisions, annotations, elaborations, or other modifications
|
||||
represent, as a whole, an original work of authorship. For the purposes
|
||||
of this License, Derivative Works shall not include works that remain
|
||||
separable from, or merely link (or bind by name) to the interfaces of,
|
||||
the Work and Derivative Works thereof.
|
||||
|
||||
"Contribution" shall mean any work of authorship, including
|
||||
the original version of the Work and any modifications or additions
|
||||
to that Work or Derivative Works thereof, that is intentionally
|
||||
submitted to Licensor for inclusion in the Work by the copyright owner
|
||||
or by an individual or Legal Entity authorized to submit on behalf of
|
||||
the copyright owner. For the purposes of this definition, "submitted"
|
||||
means any form of electronic, verbal, or written communication sent
|
||||
to the Licensor or its representatives, including but not limited to
|
||||
communication on electronic mailing lists, source code control systems,
|
||||
and issue tracking systems that are managed by, or on behalf of, the
|
||||
Licensor for the purpose of discussing and improving the Work, but
|
||||
excluding communication that is conspicuously marked or otherwise
|
||||
designated in writing by the copyright owner as "Not a Contribution."
|
||||
|
||||
"Contributor" shall mean Licensor and any individual or Legal Entity
|
||||
on behalf of whom a Contribution has been received by Licensor and
|
||||
subsequently incorporated within the Work.
|
||||
|
||||
2. Grant of Copyright License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
copyright license to reproduce, prepare Derivative Works of,
|
||||
publicly display, publicly perform, sublicense, and distribute the
|
||||
Work and such Derivative Works in Source or Object form.
|
||||
|
||||
3. Grant of Patent License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
(except as stated in this section) patent license to make, have made,
|
||||
use, offer to sell, sell, import, and otherwise transfer the Work,
|
||||
where such license applies only to those patent claims licensable
|
||||
by such Contributor that are necessarily infringed by their
|
||||
Contribution(s) alone or by combination of their Contribution(s)
|
||||
with the Work to which such Contribution(s) was submitted. If You
|
||||
institute patent litigation against any entity (including a
|
||||
cross-claim or counterclaim in a lawsuit) alleging that the Work
|
||||
or a Contribution incorporated within the Work constitutes direct
|
||||
or contributory patent infringement, then any patent licenses
|
||||
granted to You under this License for that Work shall terminate
|
||||
as of the date such litigation is filed.
|
||||
|
||||
4. Redistribution. You may reproduce and distribute copies of the
|
||||
Work or Derivative Works thereof in any medium, with or without
|
||||
modifications, and in Source or Object form, provided that You
|
||||
meet the following conditions:
|
||||
|
||||
(a) You must give any other recipients of the Work or
|
||||
Derivative Works a copy of this License; and
|
||||
|
||||
(b) You must cause any modified files to carry prominent notices
|
||||
stating that You changed the files; and
|
||||
|
||||
(c) You must retain, in the Source form of any Derivative Works
|
||||
that You distribute, all copyright, patent, trademark, and
|
||||
attribution notices from the Source form of the Work,
|
||||
excluding those notices that do not pertain to any part of
|
||||
the Derivative Works; and
|
||||
|
||||
(d) If the Work includes a "NOTICE" text file as part of its
|
||||
distribution, then any Derivative Works that You distribute must
|
||||
include a readable copy of the attribution notices contained
|
||||
within such NOTICE file, excluding those notices that do not
|
||||
pertain to any part of the Derivative Works, in at least one
|
||||
of the following places: within a NOTICE text file distributed
|
||||
as part of the Derivative Works; within the Source form or
|
||||
documentation, if provided along with the Derivative Works; or,
|
||||
within a display generated by the Derivative Works, if and
|
||||
wherever such third-party notices normally appear. The contents
|
||||
of the NOTICE file are for informational purposes only and
|
||||
do not modify the License. You may add Your own attribution
|
||||
notices within Derivative Works that You distribute, alongside
|
||||
or as an addendum to the NOTICE text from the Work, provided
|
||||
that such additional attribution notices cannot be construed
|
||||
as modifying the License.
|
||||
|
||||
You may add Your own copyright statement to Your modifications and
|
||||
may provide additional or different license terms and conditions
|
||||
for use, reproduction, or distribution of Your modifications, or
|
||||
for any such Derivative Works as a whole, provided Your use,
|
||||
reproduction, and distribution of the Work otherwise complies with
|
||||
the conditions stated in this License.
|
||||
|
||||
5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||
any Contribution intentionally submitted for inclusion in the Work
|
||||
by You to the Licensor shall be under the terms and conditions of
|
||||
this License, without any additional terms or conditions.
|
||||
Notwithstanding the above, nothing herein shall supersede or modify
|
||||
the terms of any separate license agreement you may have executed
|
||||
with Licensor regarding such Contributions.
|
||||
|
||||
6. Trademarks. This License does not grant permission to use the trade
|
||||
names, trademarks, service marks, or product names of the Licensor,
|
||||
except as required for reasonable and customary use in describing the
|
||||
origin of the Work and reproducing the content of the NOTICE file.
|
||||
|
||||
7. Disclaimer of Warranty. Unless required by applicable law or
|
||||
agreed to in writing, Licensor provides the Work (and each
|
||||
Contributor provides its Contributions) on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied, including, without limitation, any warranties or conditions
|
||||
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. You are solely responsible for determining the
|
||||
appropriateness of using or redistributing the Work and assume any
|
||||
risks associated with Your exercise of permissions under this License.
|
||||
|
||||
8. Limitation of Liability. In no event and under no legal theory,
|
||||
whether in tort (including negligence), contract, or otherwise,
|
||||
unless required by applicable law (such as deliberate and grossly
|
||||
negligent acts) or agreed to in writing, shall any Contributor be
|
||||
liable to You for damages, including any direct, indirect, special,
|
||||
incidental, or consequential damages of any character arising as a
|
||||
result of this License or out of the use or inability to use the
|
||||
Work (including but not limited to damages for loss of goodwill,
|
||||
work stoppage, computer failure or malfunction, or any and all
|
||||
other commercial damages or losses), even if such Contributor
|
||||
has been advised of the possibility of such damages.
|
||||
|
||||
9. Accepting Warranty or Additional Liability. While redistributing
|
||||
the Work or Derivative Works thereof, You may choose to offer,
|
||||
and charge a fee for, acceptance of support, warranty, indemnity,
|
||||
or other liability obligations and/or rights consistent with this
|
||||
License. However, in accepting such obligations, You may act only
|
||||
on Your own behalf and on Your sole responsibility, not on behalf
|
||||
of any other Contributor, and only if You agree to indemnify,
|
||||
defend, and hold each Contributor harmless for any liability
|
||||
incurred by, or claims asserted against, such Contributor by reason
|
||||
of your accepting any such warranty or additional liability.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
APPENDIX: How to apply the Apache License to your work.
|
||||
|
||||
To apply the Apache License to your work, attach the following
|
||||
boilerplate notice, with the fields enclosed by brackets "{}"
|
||||
replaced with your own identifying information. (Don't include
|
||||
the brackets!) The text should be enclosed in the appropriate
|
||||
comment syntax for the file format. We also recommend that a
|
||||
file or class name and description of purpose be included on the
|
||||
same "printed page" as the copyright notice for easier
|
||||
identification within third-party archives.
|
||||
|
||||
Copyright {yyyy} {name of copyright owner}
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
@@ -0,0 +1,10 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
|
||||
CPPPATH = [cwd + '/Include']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,14 @@
|
||||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,27 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
Import('rtconfig')
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('drivers/*.c')
|
||||
|
||||
SrcRemove(src, 'drivers/dataqueue.c')
|
||||
src += Glob('common/chip/*.c')
|
||||
src += [cwd + '/system_MIMXRT1021.c']
|
||||
|
||||
CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/Include']
|
||||
CPPDEFINES = ['CPU_MIMXRT1021DAG5A', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [cwd + '/gcc/startup_MIMXRT1021.S']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [cwd + '/arm/startup_MIMXRT1021.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [cwd + '/iar/startup_MIMXRT1021.s']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,119 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1020RM Rev. C, 02/2018
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b180316
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x007FDC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00010000
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_rom_config m_flash_config_start m_flash_config_size { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_rom_ivt m_ivt_start m_ivt_size { ; load region size_region
|
||||
RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1020RM Rev. C, 02/2018
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b180316
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x007FDC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x01E00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00010000
|
||||
|
||||
#define m_data3_start 0x20200000
|
||||
#define m_data3_size 0x00020000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_rom_config m_flash_config_start m_flash_config_size { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_rom_ivt m_ivt_start m_ivt_size { ; load region size_region
|
||||
RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,99 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1020RM Rev. C, 02/2018
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b180316
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0000FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00010000
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,109 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1020RM Rev. C, 02/2018
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b180316
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0000FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x01E00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00010000
|
||||
|
||||
#define m_data3_start 0x20200000
|
||||
#define m_data3_size 0x00020000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,109 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1021CAF4A
|
||||
** MIMXRT1021CAG4A
|
||||
** MIMXRT1021DAF5A
|
||||
** MIMXRT1021DAG5A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1020RM Rev. C, 02/2018
|
||||
** Version: rev. 0.1, 2017-06-06
|
||||
** Build: b180316
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_data_start 0x20200000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00010000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x01C00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPI2C_CMSIS_H_
|
||||
#define _FSL_LPI2C_CMSIS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "Driver_I2C.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "fsl_lpi2c.h"
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
|
||||
#include "fsl_lpi2c_dma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpi2c_edma.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPI2C0)
|
||||
extern ARM_DRIVER_I2C Driver_I2C0;
|
||||
#endif /* LPI2C0 */
|
||||
|
||||
#if defined(LPI2C1)
|
||||
extern ARM_DRIVER_I2C Driver_I2C1;
|
||||
#endif /* LPI2C1 */
|
||||
|
||||
#if defined(LPI2C2)
|
||||
extern ARM_DRIVER_I2C Driver_I2C2;
|
||||
#endif /* LPI2C2 */
|
||||
|
||||
#if defined(LPI2C3)
|
||||
extern ARM_DRIVER_I2C Driver_I2C3;
|
||||
#endif /* LPI2C3 */
|
||||
|
||||
#if defined(LPI2C4)
|
||||
extern ARM_DRIVER_I2C Driver_I2C4;
|
||||
#endif /* LPI2C4 */
|
||||
|
||||
#if defined(LPI2C5)
|
||||
extern ARM_DRIVER_I2C Driver_I2C5;
|
||||
#endif /* LPI2C5*/
|
||||
|
||||
#if defined(LPI2C6)
|
||||
extern ARM_DRIVER_I2C Driver_I2C6;
|
||||
#endif /* LPI2C6 */
|
||||
|
||||
/* I2C Driver state flags */
|
||||
#define I2C_FLAG_UNINIT (0)
|
||||
#define I2C_FLAG_INIT (1 << 0)
|
||||
#define I2C_FLAG_POWER (1 << 1)
|
||||
|
||||
#endif /* _FSL_LPI2C_CMSIS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPSPI_CMSISI_H_
|
||||
#define _FSL_LPSPI_CMSISI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "Driver_SPI.h"
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpspi_edma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPSPI0)
|
||||
extern ARM_DRIVER_SPI Driver_SPI0;
|
||||
#endif /* LPSPI0 */
|
||||
|
||||
#if defined(LPSPI1)
|
||||
extern ARM_DRIVER_SPI Driver_SPI1;
|
||||
#endif /* LPSPI1 */
|
||||
|
||||
#if defined(LPSPI2)
|
||||
extern ARM_DRIVER_SPI Driver_SPI2;
|
||||
#endif /* LPSPI2 */
|
||||
|
||||
#if defined(LPSPI3)
|
||||
extern ARM_DRIVER_SPI Driver_SPI3;
|
||||
#endif /* LPSPI3 */
|
||||
|
||||
#if defined(LPSPI4)
|
||||
extern ARM_DRIVER_SPI Driver_SPI4;
|
||||
#endif /* LPSPI4 */
|
||||
|
||||
#if defined(LPSPI5)
|
||||
extern ARM_DRIVER_SPI Driver_SPI5;
|
||||
#endif /* LPSPI5 */
|
||||
|
||||
/* SPI Driver state flags */
|
||||
#define SPI_FLAG_UNINIT (0)
|
||||
#define SPI_FLAG_INIT (1 << 0)
|
||||
#define SPI_FLAG_POWER (1 << 1)
|
||||
#define SPI_FLAG_CONFIGURED (1 << 2)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPUART_CMSIS_H_
|
||||
#define _FSL_LPUART_CMSIS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "Driver_USART.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "fsl_lpuart.h"
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
|
||||
#include "fsl_lpuart_dma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpuart_edma.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPUART0)
|
||||
extern ARM_DRIVER_USART Driver_USART0;
|
||||
#endif /* LPUART0 */
|
||||
|
||||
#if defined(LPUART1)
|
||||
extern ARM_DRIVER_USART Driver_USART1;
|
||||
#endif /* LPUART1 */
|
||||
|
||||
#if defined(LPUART2)
|
||||
extern ARM_DRIVER_USART Driver_USART2;
|
||||
#endif /* LPUART2 */
|
||||
|
||||
#if defined(LPUART3)
|
||||
extern ARM_DRIVER_USART Driver_USART3;
|
||||
#endif /* LPUART3 */
|
||||
|
||||
#if defined(LPUART4)
|
||||
extern ARM_DRIVER_USART Driver_USART4;
|
||||
#endif /* LPUART4 */
|
||||
|
||||
#if defined(LPUART5)
|
||||
extern ARM_DRIVER_USART Driver_USART5;
|
||||
#endif /* LPUART5 */
|
||||
|
||||
#if defined(LPUART6)
|
||||
extern ARM_DRIVER_USART Driver_USART6;
|
||||
#endif /* LPUART6 */
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 3)
|
||||
|
||||
extern ARM_DRIVER_USART Driver_USART3;
|
||||
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 4)
|
||||
|
||||
extern ARM_DRIVER_USART Driver_USART4;
|
||||
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 5)
|
||||
extern ARM_DRIVER_USART Driver_USART5;
|
||||
|
||||
#endif
|
||||
|
||||
/* USART Driver state flags */
|
||||
#define USART_FLAG_UNINIT (0)
|
||||
#define USART_FLAG_INIT (1 << 0)
|
||||
#define USART_FLAG_POWER (1 << 1)
|
||||
#define USART_FLAG_CONFIGURED (1 << 2)
|
||||
|
||||
#endif /* _FSL_LPUART_CMSIS_H_ */
|
||||
@@ -0,0 +1,306 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_adc.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address
|
||||
*/
|
||||
static uint32_t ADC_GetInstance(ADC_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to ADC bases for each instance. */
|
||||
static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
|
||||
|
||||
/*! @brief Pointers to ADC clocks for each instance. */
|
||||
static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t ADC_GetInstance(ADC_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
|
||||
{
|
||||
if (s_adcBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_adcBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
/* Enable the clock. */
|
||||
CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
/* ADCx_CFG */
|
||||
tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
|
||||
tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
|
||||
ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution);
|
||||
if (config->enableOverWrite)
|
||||
{
|
||||
tmp32 |= ADC_CFG_OVWREN_MASK;
|
||||
}
|
||||
if (config->enableLongSample)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADLSMP_MASK;
|
||||
}
|
||||
if (config->enableLowPower)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADLPC_MASK;
|
||||
}
|
||||
if (config->enableHighSpeed)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADHSC_MASK;
|
||||
}
|
||||
base->CFG = tmp32;
|
||||
|
||||
/* ADCx_GC */
|
||||
tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK);
|
||||
if (config->enableContinuousConversion)
|
||||
{
|
||||
tmp32 |= ADC_GC_ADCO_MASK;
|
||||
}
|
||||
if (config->enableAsynchronousClockOutput)
|
||||
{
|
||||
tmp32 |= ADC_GC_ADACKEN_MASK;
|
||||
}
|
||||
base->GC = tmp32;
|
||||
}
|
||||
|
||||
void ADC_Deinit(ADC_Type *base)
|
||||
{
|
||||
/* Disable the clock. */
|
||||
CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
}
|
||||
|
||||
void ADC_GetDefaultConfig(adc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
config->enableAsynchronousClockOutput = true;
|
||||
config->enableOverWrite = false;
|
||||
config->enableContinuousConversion = false;
|
||||
config->enableHighSpeed = false;
|
||||
config->enableLowPower = false;
|
||||
config->enableLongSample = false;
|
||||
config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
|
||||
config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
|
||||
config->clockSource = kADC_ClockSourceAD;
|
||||
config->clockDriver = kADC_ClockDriver1;
|
||||
config->resolution = kADC_Resolution12Bit;
|
||||
}
|
||||
|
||||
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
assert(channelGroup < ADC_HC_COUNT);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_HC_ADCH(config->channelNumber);
|
||||
if (config->enableInterruptOnConversionCompleted)
|
||||
{
|
||||
tmp32 |= ADC_HC_AIEN_MASK;
|
||||
}
|
||||
base->HC[channelGroup] = tmp32;
|
||||
}
|
||||
|
||||
/*
|
||||
*To complete calibration, the user must follow the below procedure:
|
||||
* 1. Configure ADC_CFG with actual operating values for maximum accuracy.
|
||||
* 2. Configure the ADC_GC values along with CAL bit.
|
||||
* 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
|
||||
* 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
|
||||
*/
|
||||
status_t ADC_DoAutoCalibration(ADC_Type *base)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
bool bHWTrigger = false;
|
||||
|
||||
/* The calibration would be failed when in hardwar mode.
|
||||
* Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
|
||||
if (0U != (ADC_CFG_ADTRG_MASK & base->CFG))
|
||||
{
|
||||
bHWTrigger = true;
|
||||
ADC_EnableHardwareTrigger(base, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear the CALF and launch the calibration. */
|
||||
base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */
|
||||
base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */
|
||||
|
||||
/* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */
|
||||
while (0U != (base->GC & ADC_GC_CAL_MASK))
|
||||
{
|
||||
/* Check the CALF when the calibration is active. */
|
||||
if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag))
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */
|
||||
if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Clear conversion done flag. */
|
||||
ADC_GetChannelConversionValue(base, 0U);
|
||||
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
/* Restore original trigger mode. */
|
||||
if (true == bHWTrigger)
|
||||
{
|
||||
ADC_EnableHardwareTrigger(base, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_OFS_OFS(config->offsetValue);
|
||||
if (config->enableSigned)
|
||||
{
|
||||
tmp32 |= ADC_OFS_SIGN_MASK;
|
||||
}
|
||||
base->OFS = tmp32;
|
||||
}
|
||||
|
||||
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
|
||||
{
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK);
|
||||
if (NULL == config) /* Pass "NULL" to disable the feature. */
|
||||
{
|
||||
base->GC = tmp32;
|
||||
return;
|
||||
}
|
||||
/* Enable the feature. */
|
||||
tmp32 |= ADC_GC_ACFE_MASK;
|
||||
|
||||
/* Select the hardware compare working mode. */
|
||||
switch (config->hardwareCompareMode)
|
||||
{
|
||||
case kADC_HardwareCompareMode0:
|
||||
break;
|
||||
case kADC_HardwareCompareMode1:
|
||||
tmp32 |= ADC_GC_ACFGT_MASK;
|
||||
break;
|
||||
case kADC_HardwareCompareMode2:
|
||||
tmp32 |= ADC_GC_ACREN_MASK;
|
||||
break;
|
||||
case kADC_HardwareCompareMode3:
|
||||
tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
base->GC = tmp32;
|
||||
|
||||
/* Load the compare values. */
|
||||
tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
|
||||
base->CV = tmp32;
|
||||
}
|
||||
|
||||
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
|
||||
{
|
||||
uint32_t tmp32;
|
||||
|
||||
if (mode == kADC_HardwareAverageDiasable)
|
||||
{
|
||||
base->GC &= ~ADC_GC_AVGE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK;
|
||||
tmp32 |= ADC_CFG_AVGS(mode);
|
||||
base->CFG = tmp32;
|
||||
base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */
|
||||
}
|
||||
}
|
||||
|
||||
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp32 = 0;
|
||||
|
||||
if (0U != (mask & kADC_CalibrationFailedFlag))
|
||||
{
|
||||
tmp32 |= ADC_GS_CALF_MASK;
|
||||
}
|
||||
if (0U != (mask & kADC_ConversionActiveFlag))
|
||||
{
|
||||
tmp32 |= ADC_GS_ADACT_MASK;
|
||||
}
|
||||
base->GS = tmp32;
|
||||
}
|
||||
@@ -0,0 +1,446 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ADC_H_
|
||||
#define _FSL_ADC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup adc_12b1msps_sar
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief ADC driver version */
|
||||
#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
|
||||
/*!
|
||||
* @brief Converter's status flags.
|
||||
*/
|
||||
typedef enum _adc_status_flags
|
||||
{
|
||||
kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
|
||||
kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
|
||||
kADC_AsynchronousWakeupInterruptFlag =
|
||||
ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
|
||||
} adc_status_flags_t;
|
||||
|
||||
/*!
|
||||
* @brief Reference voltage source.
|
||||
*/
|
||||
typedef enum _adc_reference_voltage_source
|
||||
{
|
||||
kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */
|
||||
} adc_reference_voltage_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Sample time duration.
|
||||
*/
|
||||
typedef enum _adc_sample_period_mode
|
||||
{
|
||||
/* This group of enumeration is for internal use which is related to register setting. */
|
||||
kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */
|
||||
kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */
|
||||
kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */
|
||||
kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */
|
||||
/* This group of enumeration is for a public user. */
|
||||
/* For long sample mode. */
|
||||
kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */
|
||||
kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */
|
||||
kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */
|
||||
kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */
|
||||
/* For short sample mode. */
|
||||
kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */
|
||||
kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */
|
||||
kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */
|
||||
kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */
|
||||
} adc_sample_period_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Clock source.
|
||||
*/
|
||||
typedef enum _adc_clock_source
|
||||
{
|
||||
kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */
|
||||
kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
|
||||
kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
|
||||
#endif
|
||||
kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */
|
||||
} adc_clock_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Clock divider for the converter.
|
||||
*/
|
||||
typedef enum _adc_clock_drvier
|
||||
{
|
||||
kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */
|
||||
kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */
|
||||
kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */
|
||||
kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */
|
||||
} adc_clock_driver_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter's resolution.
|
||||
*/
|
||||
typedef enum _adc_resolution
|
||||
{
|
||||
kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */
|
||||
kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
|
||||
kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
|
||||
} adc_resolution_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter hardware compare mode.
|
||||
*/
|
||||
typedef enum _adc_hardware_compare_mode
|
||||
{
|
||||
kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */
|
||||
kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */
|
||||
kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or
|
||||
the result is Greater than value2.
|
||||
Value1 > Value2, compare true if the result is less than value1 And the
|
||||
result is greater than value2*/
|
||||
kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal
|
||||
to value1 And the result is less than or equal to value2.
|
||||
Value1 > Value2, compare true if the result is greater than or equal to
|
||||
value1 Or the result is less than or equal to value2. */
|
||||
} adc_hardware_compare_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter hardware average mode.
|
||||
*/
|
||||
typedef enum _adc_hardware_average_mode
|
||||
{
|
||||
kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
|
||||
kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
|
||||
kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
|
||||
kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
|
||||
kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
|
||||
} adc_hardware_average_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter configuration.
|
||||
*/
|
||||
typedef struct _adc_config
|
||||
{
|
||||
bool enableOverWrite; /*!< Enable the overwriting. */
|
||||
bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */
|
||||
bool enableHighSpeed; /*!< Enable the high-speed mode. */
|
||||
bool enableLowPower; /*!< Enable the low power mode. */
|
||||
bool enableLongSample; /*!< Enable the long sample mode. */
|
||||
bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */
|
||||
adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
|
||||
adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */
|
||||
adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */
|
||||
adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */
|
||||
adc_resolution_t resolution; /*!< Select the ADC resolution mode. */
|
||||
} adc_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter Offset configuration.
|
||||
*/
|
||||
typedef struct _adc_offest_config
|
||||
{
|
||||
bool enableSigned; /*!< if false,The offset value is added with the raw result.
|
||||
if true,The offset value is subtracted from the raw converted value. */
|
||||
uint32_t offsetValue; /*!< User configurable offset value(0-4095). */
|
||||
} adc_offest_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC hardware compare configuration.
|
||||
*
|
||||
* In kADC_HardwareCompareMode0, compare true if the result is less than the value1.
|
||||
* In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1.
|
||||
* In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is
|
||||
* Greater than value2.
|
||||
* Value1 > Value2, compare true if the result is less than value1 And the result is
|
||||
* Greater than value2.
|
||||
* In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the
|
||||
* result is less than or equal to value2.
|
||||
* Value1 > Value2, compare true if the result is greater than or equal to value1 Or the
|
||||
* result is less than or equal to value2.
|
||||
*/
|
||||
typedef struct _adc_hardware_compare_config
|
||||
{
|
||||
adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
|
||||
See "adc_hardware_compare_mode_t". */
|
||||
uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */
|
||||
uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */
|
||||
} adc_hardware_compare_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC channel conversion configuration.
|
||||
*/
|
||||
typedef struct _adc_channel_config
|
||||
{
|
||||
uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
|
||||
See channel connection information for each chip in Reference
|
||||
Manual document. */
|
||||
bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
|
||||
} adc_channel_config_t;
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to "adc_config_t" structure.
|
||||
*/
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*/
|
||||
void ADC_Deinit(ADC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available pre-defined settings for the converter's configuration.
|
||||
*
|
||||
* This function initializes the converter configuration structure with available settings. The default values are:
|
||||
* @code
|
||||
* config->enableAsynchronousClockOutput = true;
|
||||
* config->enableOverWrite = false;
|
||||
* config->enableContinuousConversion = false;
|
||||
* config->enableHighSpeed = false;
|
||||
* config->enableLowPower = false;
|
||||
* config->enableLongSample = false;
|
||||
* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
|
||||
* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
|
||||
* config->clockSource = kADC_ClockSourceAD;
|
||||
* config->clockDriver = kADC_ClockDriver1;
|
||||
* config->resolution = kADC_Resolution12Bit;
|
||||
* @endcode
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void ADC_GetDefaultConfig(adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures the conversion channel.
|
||||
*
|
||||
* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
|
||||
* configures the channel while the external trigger source helps to trigger the conversion.
|
||||
*
|
||||
* Note that the "Channel Group" has a detailed description.
|
||||
* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
|
||||
* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
|
||||
* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
|
||||
* registers. The
|
||||
* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
|
||||
* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
|
||||
* hardware
|
||||
* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
|
||||
* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
|
||||
* about the
|
||||
* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
|
||||
* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
|
||||
* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
|
||||
* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
|
||||
* conversion aborts the current conversion.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
* @param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
|
||||
*/
|
||||
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets the conversion value.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
*
|
||||
* @return Conversion value.
|
||||
*/
|
||||
static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
|
||||
{
|
||||
assert(channelGroup < ADC_R_COUNT);
|
||||
|
||||
return base->R[channelGroup];
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the status flags of channel.
|
||||
*
|
||||
* A conversion is completed when the result of the conversion is transferred into the data
|
||||
* result registers. (provided the compare function & hardware averaging is disabled), this is
|
||||
* indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only,
|
||||
* if the last of the selected number of conversions is complete. If the compare function is
|
||||
* enabled, COCOn sets and conversion result data is transferred only if the compare
|
||||
* condition is true. If both hardware averaging and compare functions are enabled, then
|
||||
* COCOn sets only if the last of the selected number of conversions is complete and the
|
||||
* compare condition is true.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
*
|
||||
* @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1.
|
||||
*/
|
||||
static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
|
||||
{
|
||||
assert(channelGroup < ADC_HC_COUNT);
|
||||
|
||||
/* If flag is set,return 1,otherwise, return 0. */
|
||||
return (((base->HS) & (1U << channelGroup)) >> channelGroup);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Automates the hardware calibration.
|
||||
*
|
||||
* This auto calibration helps to adjust the plus/minus side gain automatically.
|
||||
* Execute the calibration before using the converter. Note that the software trigger should be used
|
||||
* during calibration.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*
|
||||
* @return Execution status.
|
||||
* @retval kStatus_Success Calibration is done successfully.
|
||||
* @retval kStatus_Fail Calibration has failed.
|
||||
*/
|
||||
status_t ADC_DoAutoCalibration(ADC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Set user defined offset.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to "adc_offest_config_t" structure.
|
||||
*/
|
||||
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Enables generating the DMA trigger when the conversion is complete.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
|
||||
*/
|
||||
static inline void ADC_EnableDMA(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GC |= ADC_GC_DMAEN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GC &= ~ADC_GC_DMAEN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the hardware trigger mode.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode.
|
||||
*/
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CFG |= ADC_CFG_ADTRG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CFG &= ~ADC_CFG_ADTRG_MASK;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Configures the hardware compare mode.
|
||||
*
|
||||
* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
|
||||
* result
|
||||
* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
|
||||
* reference
|
||||
* manual for more information.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param Pointer to "adc_hardware_compare_config_t" structure.
|
||||
*
|
||||
*/
|
||||
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures the hardware average mode.
|
||||
*
|
||||
* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
|
||||
* multiple
|
||||
* conversion results are accumulated and averaged internally making them easier to read.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
|
||||
*/
|
||||
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode);
|
||||
|
||||
/*!
|
||||
* @brief Gets the converter's status flags.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*
|
||||
* @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t".
|
||||
*/
|
||||
static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
|
||||
{
|
||||
return base->GS;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the converter's status falgs.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mask Mask value for the cleared flags. See "adc_status_flags_t".
|
||||
*/
|
||||
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_ADC_H_ */
|
||||
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_adc_etc.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.adc_etc"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/*!
|
||||
* @brief Get instance number for ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address
|
||||
*/
|
||||
static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to ADC_ETC bases for each instance. */
|
||||
static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
|
||||
|
||||
/*! @brief Pointers to ADC_ETC clocks for each instance. */
|
||||
static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
|
||||
{
|
||||
uint32_t instance = 0U;
|
||||
uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < adcetcArrayCount; instance++)
|
||||
{
|
||||
if (s_adcetcBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return instance;
|
||||
}
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
|
||||
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/* Open clock gate. */
|
||||
CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Disable software reset. */
|
||||
ADC_ETC_DoSoftwareReset(base, false);
|
||||
|
||||
/* Set ADC_ETC_CTRL register. */
|
||||
tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
|
||||
ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
|
||||
ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
| ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
;
|
||||
if (config->enableTSCBypass)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
|
||||
}
|
||||
if (config->enableTSC0Trigger)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
|
||||
}
|
||||
if (config->enableTSC1Trigger)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
|
||||
}
|
||||
base->CTRL = tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_Deinit(ADC_ETC_Type *base)
|
||||
{
|
||||
/* Do software reset to clear all logical. */
|
||||
ADC_ETC_DoSoftwareReset(base, true);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/* Close clock gate. */
|
||||
CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
|
||||
{
|
||||
config->enableTSCBypass = true;
|
||||
config->enableTSC0Trigger = false;
|
||||
config->enableTSC1Trigger = false;
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
config->TSC0triggerPriority = 0U;
|
||||
config->TSC1triggerPriority = 0U;
|
||||
config->clockPreDivider = 0U;
|
||||
config->XBARtriggerMask = 0U;
|
||||
}
|
||||
|
||||
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
/* Set ADC_ETC_TRGn_CTRL register. */
|
||||
tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) |
|
||||
ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority);
|
||||
if (config->enableSyncMode)
|
||||
{
|
||||
tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK;
|
||||
}
|
||||
if (config->enableSWTriggerMode)
|
||||
{
|
||||
tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK;
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CTRL = tmp32;
|
||||
|
||||
/* Set ADC_ETC_TRGn_COUNTER register. */
|
||||
tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) |
|
||||
ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay);
|
||||
base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
|
||||
uint32_t triggerGroup,
|
||||
uint32_t chainGroup,
|
||||
const adc_etc_trigger_chain_config_t *config)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
|
||||
uint32_t tmp;
|
||||
uint32_t tmp32;
|
||||
uint8_t mRemainder = chainGroup % 2U;
|
||||
|
||||
/* Set ADC_ETC_TRIGn_CHAINm register. */
|
||||
tmp = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable);
|
||||
if (config->enableB2BMode)
|
||||
{
|
||||
tmp |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK;
|
||||
}
|
||||
switch (chainGroup / 2U)
|
||||
{
|
||||
case 0U: /* Configurate trigger chain0 and chain 1. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0;
|
||||
if (mRemainder == 0U) /* Chain 0. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 1. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmp32;
|
||||
break;
|
||||
case 1U: /* Configurate trigger chain2 and chain 3. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2;
|
||||
if (mRemainder == 0U) /* Chain 2. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 3. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmp32;
|
||||
break;
|
||||
case 2U: /* Configurate trigger chain4 and chain 5. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4;
|
||||
if (mRemainder == 0U) /* Chain 4. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 5. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmp32;
|
||||
break;
|
||||
case 3U: /* Configurate trigger chain6 and chain 7. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6;
|
||||
if (mRemainder == 0U) /* Chain 6. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 7. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmp32;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
|
||||
{
|
||||
uint32_t tmp32 = 0U;
|
||||
|
||||
if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
return tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
|
||||
{
|
||||
if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
|
||||
{
|
||||
base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */
|
||||
{
|
||||
base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
|
||||
{
|
||||
base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
|
||||
{
|
||||
base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
|
||||
|
||||
uint32_t mADCResult;
|
||||
uint8_t mRemainder = chainGroup % 2U;
|
||||
|
||||
switch (chainGroup / 2U)
|
||||
{
|
||||
case 0U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 1U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 2U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 3U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return 0U;
|
||||
}
|
||||
return mADCResult;
|
||||
}
|
||||
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ADC_ETC_H_
|
||||
#define _FSL_ADC_ETC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup adc_etc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief ADC_ETC driver version */
|
||||
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*! @brief The mask of status flags cleared by writing 1. */
|
||||
#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC customized status flags mask.
|
||||
*/
|
||||
enum _adc_etc_status_flag_mask
|
||||
{
|
||||
kADC_ETC_Done0StatusFlagMask = 1U,
|
||||
kADC_ETC_Done1StatusFlagMask = 2U,
|
||||
kADC_ETC_Done2StatusFlagMask = 4U,
|
||||
kADC_ETC_ErrorStatusFlagMask = 8U,
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief External triggers sources.
|
||||
*/
|
||||
typedef enum _adc_etc_external_trigger_source
|
||||
{
|
||||
/* External XBAR sources. Support HW or SW mode. */
|
||||
kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
|
||||
kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
|
||||
kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
|
||||
kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
|
||||
kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
|
||||
kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
|
||||
kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
|
||||
kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
|
||||
/* External TSC sources. Only support HW mode. */
|
||||
kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
|
||||
kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
|
||||
} adc_etc_external_trigger_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Interrupt enable/disable mask.
|
||||
*/
|
||||
typedef enum _adc_etc_interrupt_enable
|
||||
{
|
||||
kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
|
||||
kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
|
||||
kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
|
||||
kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
|
||||
} adc_etc_interrupt_enable_t;
|
||||
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
/*!
|
||||
* @brief DMA mode selection.
|
||||
*/
|
||||
typedef enum _adc_etc_dma_mode_selection
|
||||
{
|
||||
kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
|
||||
kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
|
||||
} adc_etc_dma_mode_selection_t;
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_config
|
||||
{
|
||||
bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
|
||||
Otherwise TSC would trigger ADC through ADC_ETC. */
|
||||
bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
|
||||
bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
|
||||
Clock would be divided by (clockPreDivider+1). */
|
||||
uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
|
||||
trigger7:0x80
|
||||
For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
|
||||
enabled. */
|
||||
} adc_etc_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC trigger chain configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_trigger_chain_config
|
||||
{
|
||||
bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
|
||||
wait until interval delay is reached. */
|
||||
uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
|
||||
uint32_t ADCChannelSelect; /* Select ADC sample channel. */
|
||||
adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
|
||||
} adc_etc_trigger_chain_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC trigger configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_trigger_config
|
||||
{
|
||||
bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
|
||||
In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
|
||||
bool enableSWTriggerMode; /* Enable the sofware trigger mode. */
|
||||
uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
|
||||
uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
|
||||
uint32_t initialDelay; /* Set trigger initial delay. */
|
||||
} adc_etc_trigger_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param config Pointer to "adc_etc_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-Initialize the ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
*/
|
||||
void ADC_ETC_Deinit(ADC_ETC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
|
||||
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
|
||||
* @code
|
||||
* config->enableTSCBypass = true;
|
||||
* config->enableTSC0Trigger = false;
|
||||
* config->enableTSC1Trigger = false;
|
||||
* config->TSC0triggerPriority = 0U;
|
||||
* config->TSC1triggerPriority = 0U;
|
||||
* config->clockPreDivider = 0U;
|
||||
* config->XBARtriggerMask = 0U;
|
||||
* @endCode
|
||||
*
|
||||
* @param config Pointer to "adc_etc_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Set the external XBAR trigger configuration.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index.
|
||||
* @param config Pointer to "adc_etc_trigger_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Set the external XBAR trigger chain configuration.
|
||||
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
|
||||
* configurated.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
* @param chainGroup Trigger chain group index. Available number is 0~7.
|
||||
* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
|
||||
uint32_t triggerGroup,
|
||||
uint32_t chainGroup,
|
||||
const adc_etc_trigger_chain_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param sourceIndex trigger source index.
|
||||
*
|
||||
* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||||
*/
|
||||
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
|
||||
|
||||
/*!
|
||||
* @brief Clears the ADC_ETC's interrupt status falgs.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param sourceIndex trigger source index.
|
||||
* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||||
*/
|
||||
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
|
||||
adc_etc_external_trigger_source_t sourceIndex,
|
||||
uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Enable the DMA corresponding to each trigger source.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
/* Avoid clearing status flags at the same time. */
|
||||
base->DMA_CTRL =
|
||||
(base->DMA_CTRL | (ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the DMA corresponding to each trigger sources.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
/* Avoid clearing status flags at the same time. */
|
||||
base->DMA_CTRL =
|
||||
(base->DMA_CTRL & ~(ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
|
||||
* trigger7:0x80.
|
||||
*/
|
||||
static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
|
||||
{
|
||||
return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
|
||||
* trigger7:0x80.
|
||||
*/
|
||||
static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief When enable ,all logical will be reset.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param enable Enable/Disable the software reset.
|
||||
*/
|
||||
static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Do software trigger corresponding to each XBAR trigger sources.
|
||||
* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
|
||||
* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
|
||||
* can only work in hardware trigger mode.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
|
||||
base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get ADC conversion result from external XBAR sources.
|
||||
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
|
||||
* return Trigger0 source's chain1 conversion result.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
* @param chainGroup Trigger chain group index. Available number is 0~7.
|
||||
* @return ADC conversion result value.
|
||||
*/
|
||||
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_ADC_ETC_H_ */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_aipstz.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.aipstz"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
|
||||
{
|
||||
uint32_t mask = ((uint32_t)master >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)master & 0xFF;
|
||||
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
|
||||
}
|
||||
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
|
||||
{
|
||||
volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
|
||||
uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)peripheral & 0xFF;
|
||||
|
||||
*reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_AIPSTZ_H_
|
||||
#define _FSL_AIPSTZ_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aipstz
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of AIPSTZ privilege configuration.*/
|
||||
typedef enum _aipstz_master_privilege_level {
|
||||
kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
|
||||
kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
|
||||
kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
|
||||
kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
|
||||
} aipstz_master_privilege_level_t;
|
||||
|
||||
/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_master {
|
||||
kAIPSTZ_Master0 = (0x400U | 28U),
|
||||
kAIPSTZ_Master1 = (0x400U | 24U),
|
||||
kAIPSTZ_Master2 = (0x400U | 20U),
|
||||
kAIPSTZ_Master3 = (0x400U | 16U),
|
||||
kAIPSTZ_Master5 = (0x400U | 8U)
|
||||
} aipstz_master_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripheral access control configuration.*/
|
||||
typedef enum _aipstz_peripheral_access_control {
|
||||
kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
|
||||
kAIPSTZ_PeripheralWriteProtected = (1U << 1),
|
||||
kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
|
||||
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
|
||||
} aipstz_peripheral_access_control_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_peripheral {
|
||||
kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
|
||||
} aipstz_peripheral_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configure the privilege level for master.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Masters for AIPSTZ.
|
||||
* @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t.
|
||||
*/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig);
|
||||
|
||||
/*!
|
||||
* @brief Configure the access for peripheral.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Peripheral for AIPSTZ.
|
||||
* @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t.
|
||||
*/
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_AIPSTZ_H_ */
|
||||
@@ -0,0 +1,157 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "fsl_aoi.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.aoi"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to aoi bases for each instance. */
|
||||
static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to aoi clocks for each instance. */
|
||||
static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for AOI module.
|
||||
*
|
||||
* @param base AOI peripheral base address
|
||||
*
|
||||
* @return The AOI instance
|
||||
*/
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base);
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++)
|
||||
{
|
||||
if (s_aoiBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_aoiBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void AOI_Init(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the clock gate from clock manager. */
|
||||
CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void AOI_Deinit(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock gate from clock manager */
|
||||
CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
|
||||
{
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
assert(config != NULL);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Read BFCRT01 register at event index. */
|
||||
value = base->BFCRT[event].BFCRT01;
|
||||
|
||||
config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT);
|
||||
config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT);
|
||||
config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT);
|
||||
config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT);
|
||||
|
||||
config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT);
|
||||
config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT);
|
||||
config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT);
|
||||
config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT);
|
||||
|
||||
/* Read BFCRT23 register at event index. */
|
||||
value = 0;
|
||||
value = base->BFCRT[event].BFCRT23;
|
||||
|
||||
config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT);
|
||||
config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT);
|
||||
config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT);
|
||||
config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT);
|
||||
|
||||
config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT);
|
||||
config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT);
|
||||
config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT);
|
||||
config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
|
||||
}
|
||||
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
|
||||
{
|
||||
assert(eventConfig != NULL);
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Calculate value to configure product term 0, 1 */
|
||||
value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) |
|
||||
AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) |
|
||||
AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) |
|
||||
AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT01 = value;
|
||||
|
||||
/* Reset and calculate value to configure product term 2, 3 */
|
||||
value = 0;
|
||||
value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) |
|
||||
AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) |
|
||||
AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) |
|
||||
AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT23 = value;
|
||||
}
|
||||
@@ -0,0 +1,213 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_AOI_H_
|
||||
#define _FSL_AOI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aoi
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef AOI
|
||||
#define AOI AOI0 /*!< AOI peripheral address */
|
||||
#endif
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief AOI input configurations.
|
||||
*
|
||||
* The selection item represents the Boolean evaluations.
|
||||
*/
|
||||
typedef enum _aoi_input_config
|
||||
{
|
||||
kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */
|
||||
kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */
|
||||
kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
|
||||
kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */
|
||||
} aoi_input_config_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event indexes, where an event is the collection of the four product
|
||||
* terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
|
||||
*/
|
||||
typedef enum _aoi_event
|
||||
{
|
||||
kAOI_Event0 = 0x0U, /*!< Event 0 index */
|
||||
kAOI_Event1 = 0x1U, /*!< Event 1 index */
|
||||
kAOI_Event2 = 0x2U, /*!< Event 2 index */
|
||||
kAOI_Event3 = 0x3U /*!< Event 3 index */
|
||||
} aoi_event_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event configuration structure
|
||||
*
|
||||
* Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make
|
||||
* whole event configuration.
|
||||
*/
|
||||
typedef struct _aoi_event_config
|
||||
{
|
||||
aoi_input_config_t PT0AC; /*!< Product term 0 input A */
|
||||
aoi_input_config_t PT0BC; /*!< Product term 0 input B */
|
||||
aoi_input_config_t PT0CC; /*!< Product term 0 input C */
|
||||
aoi_input_config_t PT0DC; /*!< Product term 0 input D */
|
||||
aoi_input_config_t PT1AC; /*!< Product term 1 input A */
|
||||
aoi_input_config_t PT1BC; /*!< Product term 1 input B */
|
||||
aoi_input_config_t PT1CC; /*!< Product term 1 input C */
|
||||
aoi_input_config_t PT1DC; /*!< Product term 1 input D */
|
||||
aoi_input_config_t PT2AC; /*!< Product term 2 input A */
|
||||
aoi_input_config_t PT2BC; /*!< Product term 2 input B */
|
||||
aoi_input_config_t PT2CC; /*!< Product term 2 input C */
|
||||
aoi_input_config_t PT2DC; /*!< Product term 2 input D */
|
||||
aoi_input_config_t PT3AC; /*!< Product term 3 input A */
|
||||
aoi_input_config_t PT3BC; /*!< Product term 3 input B */
|
||||
aoi_input_config_t PT3CC; /*!< Product term 3 input C */
|
||||
aoi_input_config_t PT3DC; /*!< Product term 3 input D */
|
||||
} aoi_event_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @name AOI Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an AOI instance for operation.
|
||||
*
|
||||
* This function un-gates the AOI clock.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Init(AOI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes an AOI instance for operation.
|
||||
*
|
||||
* This function shutdowns AOI module.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Deinit(AOI_Type *base);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name AOI Get Set Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the Boolean evaluation associated.
|
||||
*
|
||||
* This function returns the Boolean evaluation associated.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Index of the event which will be set of type aoi_event_t.
|
||||
* @param config Selected input configuration .
|
||||
*/
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures an AOI event.
|
||||
*
|
||||
* This function configures an AOI event according
|
||||
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
|
||||
* of all product terms (0, 1, 2, and 3) of a desired event.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
|
||||
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
|
||||
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
|
||||
|
||||
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Event which will be configured of type aoi_event_t.
|
||||
* @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
|
||||
* filling out the members of this structure and passing the pointer to this function.
|
||||
*/
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!* @} */
|
||||
|
||||
#endif /* _FSL_AOI_H_*/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user