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[bsp][stm32/libraries] update STM32G0xx_HAL lib to V1.3.0

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yangjie committed 2019-09-05 17:43:00 +08:00
1 parent 0cde9a27c6
commit 804e3967d0
127 files changed
+6104 -4444
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bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h
+13 -38
View File
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -95,7 +95,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -146,6 +146,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
@@ -517,7 +518,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
@@ -577,7 +577,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -618,7 +617,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -637,7 +635,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -652,7 +649,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1280,9 +1276,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
@@ -1728,27 +1725,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -2264,7 +2240,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
@@ -3864,6 +3839,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
@@ -4347,10 +4323,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5070,7 +5046,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -5242,7 +5217,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -6934,7 +6908,6 @@ typedef struct
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
@@ -7074,7 +7047,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -7100,6 +7072,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -7295,7 +7268,9 @@ typedef struct
((INSTANCE) == TIM3))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h
+10 -38
View File
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -99,7 +99,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -151,6 +151,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
@@ -550,7 +551,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
@@ -615,7 +615,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -661,7 +660,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -680,7 +678,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -695,7 +692,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1323,9 +1319,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
@@ -1771,27 +1768,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -2346,7 +2322,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
@@ -4041,6 +4016,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
@@ -4562,10 +4538,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5314,7 +5290,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -5486,7 +5461,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -7395,7 +7369,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
@@ -7568,7 +7541,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -7594,6 +7566,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -7840,7 +7813,6 @@ typedef struct
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h
+10 -38
View File
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -99,7 +99,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -152,6 +152,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
@@ -592,7 +593,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
@@ -659,7 +659,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -705,7 +704,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -727,7 +725,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -742,7 +739,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1370,9 +1366,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
@@ -2007,27 +2004,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -2582,7 +2558,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
@@ -4277,6 +4252,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
@@ -4816,10 +4792,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5612,7 +5588,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -5784,7 +5759,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -7699,7 +7673,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
@@ -7874,7 +7847,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -7902,6 +7874,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -8148,7 +8121,6 @@ typedef struct
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h
+11 -16
View File
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -98,7 +98,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -150,6 +150,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
@@ -521,7 +522,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
@@ -590,7 +590,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -636,7 +635,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -657,7 +655,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -674,7 +671,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1302,9 +1298,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
@@ -2265,7 +2262,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
@@ -4505,10 +4501,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5242,7 +5238,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -5414,7 +5409,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -7128,7 +7122,6 @@ typedef struct
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
@@ -7280,7 +7273,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -7306,6 +7298,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -7532,7 +7525,9 @@ typedef struct
((INSTANCE) == TIM15))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h
+8 -16
View File
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -101,7 +101,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -152,6 +152,7 @@ typedef struct
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief HDMI-CEC
*/
@@ -633,7 +634,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
@@ -714,7 +714,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -771,7 +770,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -794,7 +792,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -811,7 +808,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1439,9 +1435,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
/* */
@@ -2868,7 +2865,6 @@ typedef struct
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
/******************************************************************************/
/* */
/* FLASH */
@@ -5265,10 +5261,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -6049,7 +6045,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -6221,7 +6216,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -8233,7 +8227,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
@@ -8750,7 +8743,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -8776,6 +8768,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -9055,7 +9048,6 @@ typedef struct
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h
+8 -16
View File
@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
@@ -101,7 +101,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -153,6 +153,7 @@ typedef struct
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief HDMI-CEC
*/
@@ -675,7 +676,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
@@ -758,7 +758,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -815,7 +814,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -841,7 +839,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -858,7 +855,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
@@ -1486,9 +1482,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
/* */
@@ -3104,7 +3101,6 @@ typedef struct
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
/******************************************************************************/
/* */
/* FLASH */
@@ -5519,10 +5515,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -6347,7 +6343,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
@@ -6519,7 +6514,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@@ -8537,7 +8531,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
@@ -9056,7 +9049,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -9084,6 +9076,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
@@ -9363,7 +9356,6 @@ typedef struct
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h
+11 -2
View File
@@ -57,10 +57,13 @@
application
*/
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx)
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx)
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -79,7 +82,7 @@
* @brief CMSIS Device version number $VERSION$
*/
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
@@ -101,6 +104,12 @@
#include "stm32g081xx.h"
#elif defined(STM32G070xx)
#include "stm32g070xx.h"
#elif defined(STM32G031xx)
#include "stm32g031xx.h"
#elif defined(STM32G041xx)
#include "stm32g041xx.h"
#elif defined(STM32G030xx)
#include "stm32g030xx.h"
#else
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
#endif
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s
+6 -7
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g030xx.s
* @author MCD Application Team
* @brief STM32G030xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G030xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
@@ -218,8 +217,8 @@ g_pfnVectors:
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s
+7 -5
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g031xx.s
* @author MCD Application Team
* @brief STM32G031xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G031xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
@@ -273,5 +272,8 @@ g_pfnVectors:
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s
+4 -5
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g041xx.s
* @author MCD Application Team
* @brief STM32G041xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G041xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s
+4 -5
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g070xx.s
* @author MCD Application Team
* @brief STM32G070xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G070xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
+3 -4
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g071xx.s
* @author MCD Application Team
* @brief STM32G071xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G071xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,7 +84,7 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
/* bl __libc_init_array */
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl entry
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s
+4 -5
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g081xx.s
* @author MCD Application Team
* @brief STM32G051xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G081xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s
+1 -2
View File
@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c
+20 -19
View File
@@ -79,19 +79,19 @@
#include "stm32g0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of LSI in Hz*/
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
@@ -140,10 +140,10 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000U;
uint32_t SystemCoreClock = 16000000UL;
const uint32_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint32_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
@@ -241,25 +241,26 @@ void SystemCoreClockUpdate(void)
break;
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
switch (pllsource)
{
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
case 0x02: /* HSI used as PLL clock source */
default:
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
else /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
SystemCoreClock = pllvco/pllr;
break;
}
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+233 -13
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h
+49
View File
@@ -89,6 +89,23 @@ extern "C" {
* @}
*/
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/** @defgroup SYSCFG_ClampingDiode Clamping Diode
* @{
*/
#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */
#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */
#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */
#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */
#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */
#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */
#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */
#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */
/**
* @}
*/
#endif
/** @defgroup HAL_Pin_remapping Pin remapping
* @{
@@ -107,6 +124,8 @@ extern "C" {
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
#if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx)
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */
#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx)
#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
#endif
/**
@@ -495,6 +514,18 @@ extern "C" {
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/** @brief Clamping Diode on specific pins enable/disable macros
* @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
*/
#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
SET_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#endif
/** @brief ISR wrapper check
* @note Allow to determine interrupt source per line.
@@ -561,11 +592,25 @@ extern "C" {
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#endif
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \
(((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \
(((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \
(((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \
(((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
(((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \
(((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \
(((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2))
#endif
#if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
#endif
#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
@@ -696,6 +741,10 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
#endif
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
#endif
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h
+12 -8
View File
@@ -359,7 +359,11 @@ typedef struct
/**
* @brief ADC handle Structure definition
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
typedef struct __ADC_HandleTypeDef
#else
typedef struct
#endif
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
@@ -421,7 +425,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking,
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
@@ -508,19 +512,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#if defined(TIM2)
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#if defined(TIM6)
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#if defined(TIM15)
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h
+46 -34
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -111,8 +111,8 @@ typedef struct
} CEC_InitTypeDef;
/**
* @brief HAL CEC State structures definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -121,14 +121,14 @@ typedef struct
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b5 CEC peripheral initilisation status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -138,9 +138,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b5 CEC peripheral initilisation status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -149,27 +149,16 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
} HAL_CEC_StateTypeDef;
typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
typedef struct __CEC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
@@ -194,8 +183,10 @@ typedef struct __CEC_HandleTypeDef
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
*hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
@@ -221,7 +212,8 @@ typedef enum
* @brief HAL CEC Callback pointer definition
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -231,7 +223,25 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_State_Definition CEC State Code Definition
* @{
*/
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
/**
* @}
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
@@ -413,7 +423,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -635,7 +645,8 @@ void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
@@ -649,7 +660,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h
+18 -17
View File
@@ -38,13 +38,13 @@ extern "C" {
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
/**
* @brief COMP Init structure definition
*/
typedef struct
{
@@ -80,7 +80,7 @@ typedef struct
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
}COMP_InitTypeDef;
} COMP_InitTypeDef;
/**
* @brief HAL COMP state machine: HAL COMP states definition
@@ -94,9 +94,9 @@ typedef enum
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
}HAL_COMP_StateTypeDef;
} HAL_COMP_StateTypeDef;
/**
/**
* @brief COMP Handle Structure definition
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
@@ -297,10 +297,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
@@ -311,7 +311,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
@@ -389,7 +389,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
@@ -597,7 +597,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
* @{
*/
/**
@@ -605,8 +605,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
/**
* @}
*/
@@ -694,13 +694,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h
+2 -5
View File
@@ -61,7 +61,6 @@ extern "C" {
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_UCPD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## Register Callbacks selection ############################## */
@@ -109,6 +108,7 @@ extern "C" {
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
@@ -138,6 +138,7 @@ in voltage and temperature.*/
#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
@@ -282,10 +283,6 @@ in voltage and temperature.*/
#include "stm32g0xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_UCPD_MODULE_ENABLED
#include "stm32g0xx_ll_ucpd.h"
#endif /* HAL_UCPD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32g0xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h
+32 -7
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -64,9 +64,12 @@ typedef struct
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
@@ -122,7 +125,7 @@ typedef struct
__IO uint16_t CrypOutCount; /*!< Counter of output data */
uint16_t Size; /*!< length of input data in word */
uint16_t Size; /*!< length of input data in words */
uint32_t Phase; /*!< CRYP peripheral phase */
@@ -136,6 +139,13 @@ typedef struct
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
configuration can be skipped */
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
for a single signature computation after several
messages processing */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
@@ -161,7 +171,7 @@ typedef struct
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
@@ -247,7 +257,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
/**
* @}
@@ -322,6 +332,18 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
* @}
*/
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
* @{
*/
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
/**
* @}
*/
/**
* @}
*/
@@ -540,6 +562,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h
+37 -28
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -110,8 +110,7 @@ typedef struct
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
}
DAC_SampleAndHoldConfTypeDef;
} DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
@@ -156,8 +155,8 @@ typedef enum
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
@@ -196,17 +195,18 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
/**
* @}
*/
@@ -272,16 +272,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
*/
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
* @{
*/
#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */
/**
* @}
*/
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
@@ -291,7 +289,6 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
@@ -322,7 +319,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
@@ -330,7 +327,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
@@ -450,12 +447,13 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@@ -469,7 +467,8 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -503,6 +502,16 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h
+9 -9
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -122,7 +122,7 @@ extern "C" {
((CONNECT) == DAC_CHIPCONNECT_ENABLE))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
@@ -160,8 +160,8 @@ extern "C" {
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
@@ -186,7 +186,8 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
@@ -197,7 +198,6 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
@@ -209,8 +209,8 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
* @}
*/
/**
* @}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h
+3
View File
@@ -277,6 +277,7 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_UCPD2_RX 60U /*!< DMAMUX UCPD2 RX request */
#define DMA_REQUEST_UCPD2_TX 61U /*!< DMAMUX UCPD2 TX request */
#endif
/**
* @}
*/
@@ -668,6 +669,8 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#if defined(STM32G081xx)||defined(STM32G071xx)||defined(STM32G070xx)
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD2_TX)
#elif defined(STM32G041xx)||defined(STM32G031xx)||defined(STM32G030xx)
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX)
#endif
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h
+143 -129
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h
+7 -7
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -44,8 +44,8 @@ extern "C" {
/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
* @{
*/
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
/**
* @}
*/
@@ -86,8 +86,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
* @{
*/
#define FLASH_PCROP_GRANULARITY_OFFSET 9u
#define FLASH_PCROP_GRANULARITY (1u << FLASH_PCROP_GRANULARITY_OFFSET)
#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */
/**
* @}
*/
@@ -97,7 +97,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
* @{
*/
#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
void FLASH_PageErase(uint32_t Page);
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h
+2 -2
View File
@@ -251,8 +251,8 @@ typedef enum
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h
+147
View File
@@ -47,6 +47,8 @@ extern "C" {
* @{
*/
#if defined (STM32G081xx) || defined (STM32G071xx)
/*------------------------- STM32G081xx / STM32G071xx ------------------------*/
/**
@@ -228,7 +230,152 @@ extern "C" {
#endif /* STM32G070xx */
#if defined (STM32G031xx) || defined (STM32G041xx)
/*------------------------- STM32G041xx / STM32G031xx ------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */
#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */
#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */
#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */
#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */
#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
#endif /* STM32G031xx || STM32G041xx */
#if defined (STM32G030xx)
/*------------------------- STM32G030xx --------------------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */
#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */
#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */
#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
#endif /* STM32G030xx */
/**
* @}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h
+5 -5
View File
@@ -86,17 +86,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 IP initilisation status\n
* 0 : Reset (IP not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h
+3
View File
@@ -117,6 +117,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h
+60 -18
View File
@@ -83,7 +83,11 @@ typedef enum
/**
* @brief I2S handle Structure definition
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
typedef struct __I2S_HandleTypeDef
#else
typedef struct
#endif
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
@@ -265,6 +269,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
@@ -459,29 +465,65 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR regsiter.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun error flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_CHSIDE: Channel side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
((FORMAT) == I2S_DATAFORMAT_24B) || \
((FORMAT) == I2S_DATAFORMAT_32B))
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 regsiter.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX))
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the I2S serial clock steady state.
* This parameter can be a value of @ref I2S_Clock_Polarity
* @retval None
*/
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h
+31 -27
View File
@@ -169,7 +169,7 @@ typedef struct
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
uint32_t ErrorCode; /*!< IRDA Error code */
__IO uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
@@ -302,7 +302,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @}
*/
/** @defgroup IRDA_ClockPrescaler Clock Prescaler
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
@@ -456,8 +456,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
*/
/**
* @}
*/
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
@@ -487,10 +487,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -605,7 +605,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -620,8 +621,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -659,7 +660,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -706,7 +708,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
@@ -720,17 +723,17 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
/** @brief Ensure that IRDA state is valid.
* @param __STATE__ IRDA state mode.
@@ -775,8 +778,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32g0xx_hal_irda_ex.h"
@@ -798,7 +801,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h
+73 -39
View File
@@ -33,6 +33,7 @@ extern "C" {
*/
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
@@ -74,8 +75,8 @@ extern "C" {
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -91,12 +92,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -112,14 +113,47 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif
#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32G081xx || STM32G071xx || STM32G070xx */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
@@ -128,44 +162,44 @@ extern "C" {
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h
+4 -3
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -119,7 +119,7 @@ typedef struct
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@@ -219,6 +219,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h
+25 -11
View File
@@ -27,6 +27,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_rcc.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
@@ -2126,19 +2127,32 @@ typedef struct
*/
#if defined(RCC_PLLQ_SUPPORT)
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
(RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \
(uint32_t) (__PLLQ__) | \
(uint32_t) (__PLLP__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLM__) | \
(uint32_t) (__PLLSOURCE__)))
MODIFY_REG( RCC->PLLCFGR, \
(RCC_PLLCFGR_PLLSRC | \
RCC_PLLCFGR_PLLM | \
RCC_PLLCFGR_PLLN | \
RCC_PLLCFGR_PLLP | \
RCC_PLLCFGR_PLLQ | \
RCC_PLLCFGR_PLLR), \
((uint32_t) (__PLLSOURCE__) | \
(uint32_t) (__PLLM__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLP__) | \
(uint32_t) (__PLLQ__) | \
(uint32_t) (__PLLR__)))
#else
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \
(RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \
(uint32_t) (__PLLP__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLM__) | \
(uint32_t) (__PLLSOURCE__)))
MODIFY_REG( RCC->PLLCFGR, \
(RCC_PLLCFGR_PLLSRC | \
RCC_PLLCFGR_PLLM | \
RCC_PLLCFGR_PLLN | \
RCC_PLLCFGR_PLLP | \
RCC_PLLCFGR_PLLR), \
((uint32_t) (__PLLSOURCE__) | \
(uint32_t) (__PLLM__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLP__) | \
(uint32_t) (__PLLR__)))
#endif
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h
+30
View File
@@ -683,6 +683,36 @@ void HAL_RCCEx_DisableLSCO(void);
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G041xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
#elif defined(STM32G031xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
#elif defined(STM32G030xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#endif /* STM32G081xx */
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h
+17 -7
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -22,10 +22,9 @@
#define STM32G0xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if defined(STM32G081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
@@ -33,6 +32,8 @@ extern "C" {
* @{
*/
#if defined (RNG)
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
@@ -76,7 +77,11 @@ typedef enum
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
typedef struct __RNG_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
{
RNG_TypeDef *Instance; /*!< Register base address */
@@ -166,12 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
@@ -341,6 +348,7 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
/**
* @brief Verify the RNG Clock Error Detection mode.
* @param __MODE__ RNG Clock Error Detection mode
@@ -356,15 +364,17 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
* @}
*/
#endif /* RNG */
/**
* @}
*/
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h
+18 -17
View File
@@ -467,10 +467,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
* @}
*/
/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
* @{
*/
#define RTC_IT_MASK 0x001Fu /*!< RTC interruptions flags mask */
#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */
/**
* @}
*/
@@ -480,23 +480,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
* - YYYYY : Interrupt flag position in the XX register (5bits)
* - XX : Interrupt status register (2bits)
* - 01: ICSR register
* - 10: SR register
* - 10: SR or SCR or MISR or SMISR registers
* @{
*/
#define RTC_FLAG_RECALPF 0x00000110u /*!< Recalibration pending Flag */
#define RTC_FLAG_INITF 0x00000106u /*!< Initialization flag */
#define RTC_FLAG_RSF 0x00000105u /*!< Registers synchronization flag */
#define RTC_FLAG_INITS 0x00000104u /*!< Initialization status flag */
#define RTC_FLAG_SHPF 0x00000103u /*!< Shift operation pending flag */
#define RTC_FLAG_WUTWF 0x00000102u /*!< Wakeup timer write flag */
#define RTC_FLAG_ALRBWF 0x00000101u /*!< Alarm B write flag */
#define RTC_FLAG_ALRAWF 0x00000100u /*!< Alarm A write flag */
#define RTC_FLAG_ITSF 0x00000205u /*!< Internal Time-stamp flag */
#define RTC_FLAG_TSOVF 0x00000204u /*!< Time-stamp overflow flag */
#define RTC_FLAG_TSF 0x00000203u /*!< Time-stamp flag */
#define RTC_FLAG_WUTF 0x00000202u /*!< Wakeup timer flag */
#define RTC_FLAG_ALRBF 0x00000201u /*!< Alarm B flag */
#define RTC_FLAG_ALRAF 0x00000200u /*!< Alarm A flag */
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */
#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
/**
* @}
*/
@@ -936,6 +936,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h
+5 -8
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -391,8 +391,8 @@ typedef struct
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
* @retval None
*/
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U) :\
((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U))
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\
((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U))
/* ---------------------------------WAKEUPTIMER---------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
@@ -581,8 +581,7 @@ typedef struct
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \
(__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF)))
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
/**
* @brief Enable interrupt on the RTC Timestamp associated Exti line.
@@ -961,12 +960,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc,
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h
+80 -40
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h
+12 -12
View File
@@ -207,7 +207,7 @@ extern "C" {
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
@@ -238,29 +238,29 @@ extern "C" {
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
/**
* @}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h
+1 -1
View File
@@ -673,7 +673,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Slelect management parameter.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h
+305 -248
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h
+73 -67
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h
+24 -16
View File
@@ -806,9 +806,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
@@ -973,7 +973,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
@@ -998,8 +999,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@@ -1161,7 +1162,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
@@ -1169,7 +1171,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
@@ -1177,7 +1180,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle.
@@ -1238,10 +1242,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
*/
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
@@ -1509,7 +1513,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -1589,10 +1594,13 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h
+150 -52
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h
+58 -19
View File
@@ -434,10 +434,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -591,7 +591,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -614,8 +615,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
@@ -702,7 +703,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
@@ -714,8 +716,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -731,12 +733,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -752,7 +754,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
@@ -767,7 +769,40 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif
#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32G081xx || STM32G071xx || STM32G070xx */
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
@@ -890,7 +925,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -905,13 +941,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h
+32 -32
View File
@@ -130,44 +130,44 @@ extern "C" {
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h
+4
View File
@@ -64,7 +64,11 @@ typedef struct
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif
{
WWDG_TypeDef *Instance; /*!< Register base address */
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h
+48 -47
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h
+7 -7
View File
@@ -216,7 +216,7 @@ extern "C" {
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
@@ -241,7 +241,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
@@ -262,7 +262,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
@@ -284,7 +284,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
@@ -306,7 +306,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
@@ -329,7 +329,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
@@ -356,7 +356,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
* @note (*) RNG & CRYP IP available only on STM32G081xx
* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h
+29 -37
View File
@@ -81,7 +81,7 @@ extern "C" {
* @retval Pointer to register address
*/
#define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -100,32 +100,32 @@ typedef struct
{
uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
This parameter can be a value of @ref COMP_LL_EC_POWERMODE
This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
uint32_t OutputPolarity; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
} LL_COMP_InitTypeDef;
@@ -240,7 +240,7 @@ typedef struct
*/
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
* @note Only COMP IP HW delays are defined in COMP LL driver driver,
* @note Only COMP peripheral HW delays are defined in COMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -347,14 +347,14 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM
{
/* Note: On this STM32 serie, window mode can be set from one of the pair */
/* of COMP instances: COMP1 or COMP2. */
register uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
/* Clear the potential previous setting of window mode */
register uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
CLEAR_BIT(*preg_clear,
COMP_CSR_WINMODE
);
/* Set window mode */
MODIFY_REG(*preg,
COMP_CSR_WINMODE,
@@ -377,10 +377,10 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy
{
/* Note: On this STM32 serie, window mode can be set from one of the pair */
/* of COMP instances: COMP1 or COMP2. */
register uint32_t window_mode_comp_odd = READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
register uint32_t window_mode_comp_even = READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
return (uint32_t)( window_mode_comp_odd
register const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
register const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
return (uint32_t)(window_mode_comp_odd
| window_mode_comp_even
| ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK));
}
@@ -400,16 +400,16 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
{
register uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
/* Clear the potential previous setting of window output on the relevant comparator instance */
/* (clear bit of window output unless specific case of setting of comparator both output selected) */
register uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
MODIFY_REG(*preg_clear,
COMP_CSR_WINOUT,
((WindowOutput & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW)
);
/* Set window output */
MODIFY_REG(*preg,
COMP_CSR_WINOUT,
@@ -431,11 +431,11 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C
*/
__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON)
{
register uint32_t window_output_comp_odd = READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
register uint32_t window_output_comp_even = READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
register const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
register const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
/* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */
return (uint32_t)( window_output_comp_odd
return (uint32_t)(window_output_comp_odd
| window_output_comp_even
| ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
| (window_output_comp_odd + window_output_comp_even));
@@ -493,10 +493,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "xxxx".
*/
//#warning "Specify parameter name in STM32G0 datasheet"
/*
* Refer to device datasheet, parameter "tSTART_SCALER".
* @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
* CSR INPSEL LL_COMP_ConfigInputs\n
* @param COMPx Comparator instance
@@ -567,10 +564,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "xxxx".
*/
//#warning "Specify parameter name in STM32G0 datasheet"
/*
* Refer to device datasheet, parameter "tSTART_SCALER".
* @rmtoll CSR INMSEL LL_COMP_SetInputMinus
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
@@ -694,7 +688,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3 (1)
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
*
*
* (1) Parameter availability depending on timer availability
* on the selected device.
* @retval None
@@ -719,7 +713,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3 (1)
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
*
*
* (1) Parameter availability depending on timer availability
* on the selected device.
*/
@@ -740,9 +734,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
* @brief Enable comparator instance.
* @note After enable from off state, comparator requires a delay
* to reach reach propagation delay specification.
*/
//#warning "Specify startup time naming in datasheet for the selected IP"
/*
* Refer to device datasheet, parameter "tSTART".
* @rmtoll CSR EN LL_COMP_Enable
* @param COMPx Comparator instance
* @retval None
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h
+1 -1
View File
@@ -338,7 +338,7 @@ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h
+35 -31
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h
+83 -43
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File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h
+77 -26
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File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h
+3 -2
View File
@@ -32,7 +32,7 @@ extern "C" {
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF)
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
/** @defgroup GPIO_LL GPIO
* @{
@@ -681,6 +681,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKK register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
@@ -938,7 +939,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOF) */
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h
+3 -3
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -327,7 +327,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
* @}
*/
#endif /* IWDG) */
#endif /* IWDG */
/**
* @}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h
+2 -2
View File
@@ -301,7 +301,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__))
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
@@ -309,7 +309,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h
+11 -5
View File
@@ -442,7 +442,8 @@ typedef struct
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
+ (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
@@ -1341,7 +1342,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
}
@@ -1380,6 +1382,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t
{
brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
}
else
{
brrresult = 0x0UL;
}
return (brrresult);
}
@@ -2481,12 +2487,12 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32
if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) & (LPUARTx->TDR);
data_reg_addr = (uint32_t) &(LPUARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) & (LPUARTx->RDR);
data_reg_addr = (uint32_t) &(LPUARTx->RDR);
}
return data_reg_addr;
@@ -2508,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32
*/
__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
{
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h
+11 -11
View File
@@ -99,8 +99,8 @@ extern "C" {
/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
* @{
*/
#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_0)
#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_1)
#define LL_PWR_MODE_STOP0 (0x00000000UL)
#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
#if defined (PWR_CR1_LPMS_2)
#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
@@ -164,6 +164,9 @@ extern "C" {
#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#if defined(GPIOE)
#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#endif
#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
/**
* @}
@@ -896,7 +899,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
SET_BIT(*((uint32_t *)GPIO), GPIONumber);
SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -933,7 +936,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -970,7 +973,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
return ((READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
@@ -1007,8 +1010,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIO
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
register uint32_t temp = (uint32_t)(GPIO) + 4U;
SET_BIT(*((uint32_t *)(temp)), GPIONumber);
SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
@@ -1045,8 +1047,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
register uint32_t temp = (uint32_t)(GPIO) + 4U;
CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
@@ -1083,8 +1084,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
register uint32_t temp = (uint32_t)(GPIO) + 4UL;
return ((READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h
+6 -6
View File
@@ -116,7 +116,7 @@ typedef struct
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */
#define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
#endif /* EXTERNAL_CLOCK_VALUE */
/**
* @}
@@ -2442,7 +2442,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
/**
* @brief Disable PLL output mapped on ADC domain clock
* @note Cannot be disabled if the PLL clock is used as the system clock
* @note User shall check that PLL is not used by any other IP
* @note User shall check that PLL is not used by any other peripheral
* (ex: I2S1)
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
@@ -2469,7 +2469,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void)
/**
* @brief Disable PLL output mapped on I2S1 domain clock
* @note Cannot be disabled if the PLL clock is used as the system clock
* @note User shall check that PLL is not used by any other IP
* @note User shall check that PLL is not used by any other peripheral
* (ex: RNG)
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
@@ -2497,7 +2497,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
/**
* @brief Disable PLL output mapped on RNG domain clock
* @note Cannot be disabled if the PLL clock is used as the system clock
* @note User shall check that PLL is not used by any other IP
* @note User shall check that PLL is not used by any other peripheral
* (ex: TIM, TIM15)
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
@@ -2526,7 +2526,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void)
/**
* @brief Disable PLL output mapped on TIM1 domain clock
* @note Cannot be disabled if the PLL clock is used as the system clock
* @note User shall check that PLL is not used by any other IP
* @note User shall check that PLL is not used by any other peripheral
* (ex: RNG, TIM15)
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
@@ -2555,7 +2555,7 @@ __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void)
/**
* @brief Disable PLL output mapped on TIM15 domain clock
* @note Cannot be disabled if the PLL clock is used as the system clock
* @note User shall check that PLL is not used by any other IP
* @note User shall check that PLL is not used by any other peripheral
* (ex: RNG, TIM1)
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h
+6 -6
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -32,7 +32,7 @@ extern "C" {
* @{
*/
#if defined(RNG)
#if defined (RNG)
/** @defgroup RNG_LL RNG
* @{
@@ -49,6 +49,7 @@ extern "C" {
* @{
*/
/**
* @brief LL RNG Init Structure Definition
*/
@@ -64,7 +65,6 @@ typedef struct
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
* @{
@@ -386,7 +386,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
* @}
*/
#endif /* defined(RNG) */
#endif /* RNG */
/**
* @}
@@ -396,6 +396,6 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
}
#endif
#endif /* STM32G0xx_LL_RNG_H */
#endif /* __STM32G0xx_LL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h
+10 -10
View File
@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -240,7 +240,7 @@ typedef struct
#define LL_RTC_SCR_TSF RTC_SCR_CTSF
#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF
#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
@@ -322,8 +322,8 @@ typedef struct
/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
* @{
*/
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */
/**
* @}
*/
@@ -2412,7 +2412,7 @@ __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
* @brief Set Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
* @rmtoll RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge
* @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge
* @param RTCx RTC Instance
* @param Edge This parameter can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
@@ -2427,7 +2427,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
/**
* @brief Get Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge
* @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
@@ -2468,7 +2468,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
* @brief Get Timestamp Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n
* RTC_TSTR HU LL_RTC_TS_GetMinute
* RTC_TSTR MNU LL_RTC_TS_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
@@ -2481,7 +2481,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
* @brief Get Timestamp Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n
* RTC_TSTR HU LL_RTC_TS_GetSecond
* RTC_TSTR SU LL_RTC_TS_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
@@ -3056,7 +3056,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup
tmp = &(TAMPx->BKP0R) + BackupRegister;
/* Write the specified register */
/* Write the specified register */
*tmp = Data;
}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h
+95 -1
View File
@@ -130,7 +130,7 @@ extern "C" {
* @{
*/
#define LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 STROBE sw configuration */
#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD2 STROBE sw configuration */
#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 STROBE sw configuration */
/**
* @}
*/
@@ -177,6 +177,22 @@ extern "C" {
* @}
*/
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/** @defgroup SYSTEM_LL_EC_CLAMPING_DIODE SYSCFG CLAMPING DIODE
* @{
*/
#define LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping diode of PA1 */
#define LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping diode of PA3 */
#define LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping diode of PA5 */
#define LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping diode of PA6 */
#define LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping diode of PA13 */
#define LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping diode of PB0 */
#define LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping diode of PB1 */
#define LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping diode of PB2 */
/**
* @}
*/
#endif
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
@@ -1335,6 +1351,84 @@ __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
}
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/**
* @brief Enable Clamping Diode on specific pin
* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_EnableClampingDiode\n
* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_EnableClampingDiode
* @param ConfigClampingDiode This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableClampingDiode(uint32_t ConfigClampingDiode)
{
SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
}
/**
* @brief Disable Clamping Diode on specific pin
* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_DisableClampingDiode\n
* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_DisableClampingDiode
* @param ConfigClampingDiode This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableClampingDiode(uint32_t ConfigClampingDiode)
{
CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
}
/**
* @brief Indicates whether clamping diode(s) is(are) enabled.
* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_IsEnabledClampingDiode
* @param ConfigClampingDiode This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
* @retval None
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode(uint32_t ConfigClampingDiode)
{
return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL);
}
#endif
/**
* @}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h
+150 -146
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h
+11 -11
View File
@@ -58,18 +58,18 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk().*/
uint32_t transwin; /*!< Specifies the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal
tTransitionWindow (set according to IP clock to define an interval of between 12 and 20 us).
This parameter can be a value between 0x1 and 0x3FF
tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us).
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin().*/
uint32_t IfrGap; /*!< Specifies the definition of the clock divider (minus 1) in order to generate tInterframeGap
from the IP clock.
This parameter can be a value between 0x1 and 0x3FF
from the peripheral clock.
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap().*/
uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at the IP for a half bit clock e.g. program 3
for a bit clock that takes 8 cycles of the IP clock "UCPD1_CLK"..
This parameter can be a value between 0x0 and 0x1F.
uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3
for a bit clock that takes 8 cycles of the peripheral clock "UCPD1_CLK"..
This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv().*/
} LL_UCPD_InitTypeDef;
@@ -370,7 +370,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const * const UCPDx)
* @brief Set the receiver ordered set detection enable
* @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
* @param UCPDx UCPD Instance
* @param OrderSet This parameter can be combinaison of the following values:
* @param OrderSet This parameter can be combination of the following values:
* @arg @ref LL_UCPD_ORDERSET_SOP
* @arg @ref LL_UCPD_ORDERSET_SOP1
* @arg @ref LL_UCPD_ORDERSET_SOP2
@@ -408,7 +408,7 @@ __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
* @brief Set the number of cycles (minus 1) of the half bit clock
* @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
* @param UCPDx UCPD Instance
* @param TransWin a value between 1 and 0x3FF
* @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
@@ -420,7 +420,7 @@ __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
* @param UCPDx UCPD Instance
* @param IfrGap a value between 1 and 0x3FF
* @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
@@ -432,7 +432,7 @@ __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
* @param UCPDx UCPD Instance
* @param HbitClock a value between 0 and 31
* @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h
+34 -33
View File
@@ -44,33 +44,26 @@ extern "C" {
* @{
*/
/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
static const uint16_t USART_PRESCALER_TAB[] =
static const uint32_t USART_PRESCALER_TAB[] =
{
(uint16_t)1,
(uint16_t)2,
(uint16_t)4,
(uint16_t)6,
(uint16_t)8,
(uint16_t)10,
(uint16_t)12,
(uint16_t)16,
(uint16_t)32,
(uint16_t)64,
(uint16_t)128,
(uint16_t)256
1UL,
2UL,
4UL,
6UL,
8UL,
10UL,
12UL,
16UL,
32UL,
64UL,
128UL,
256UL
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Constants USART Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -570,7 +563,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -592,7 +586,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -1864,22 +1859,27 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling,
uint32_t BaudRate)
{
register uint32_t usartdiv;
uint32_t usartdiv;
register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
/* Do not overstep the size of USART_PRESCALER_TAB */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
USARTx->BRR = brrtemp;
}
else
{
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
}
}
@@ -1909,11 +1909,12 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
register uint32_t usartdiv;
register uint32_t brrresult = 0x0U;
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
@@ -3264,7 +3265,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
/**
* @brief Clear Noise Error detected Flag
* @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
*/
@@ -4200,12 +4201,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) & (USARTx->TDR);
data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) & (USARTx->RDR);
data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
@@ -4227,7 +4228,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c
+35 -4
View File
@@ -56,7 +56,7 @@
* @brief STM32G0xx HAL Driver version number
*/
#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32G0xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32G0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
@@ -331,7 +331,7 @@ uint32_t HAL_GetTickPrio(void)
/**
* @brief Set new tick Freq.
* @retval Status
* @retval status
*/
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
{
@@ -340,10 +340,12 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
if (uwTickFreq != Freq)
{
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status == HAL_OK)
{
uwTickFreq = Freq;
}
}
return status;
@@ -676,6 +678,35 @@ void HAL_SYSCFG_DisableRemap(uint32_t PinRemap)
CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
}
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/**
* @brief Enable Clamping Diode on specified IO
* @param PinConfig specifies on which pins clamping Diode has to be enabled
* This parameter can be any combination of the following values:
* @arg @ref SYSCFG_ClampingDiode
* @retval None
*/
void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
SET_BIT(SYSCFG->CFGR2, PinConfig);
}
/**
* @brief Disable Clamping Diode on specified IO
* @param PinConfig specifies on which pins clamping Diode has to be disabled
* This parameter can be any combination of the following values:
* @arg @ref SYSCFG_ClampingDiode
* @retval None
*/
void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
CLEAR_BIT(SYSCFG->CFGR2, PinConfig);
}
#endif
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
/**
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c
+16 -16
View File
@@ -484,12 +484,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U)
if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
@@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
@@ -706,7 +706,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
}
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* ensure of no potential problem of ADC core peripheral clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
@@ -728,7 +728,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
@@ -926,7 +926,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
@@ -951,7 +951,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
return HAL_ERROR;
}
if ((hadc->State & HAL_ADC_STATE_READY) != 0)
if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
{
switch (CallbackID)
{
@@ -1041,7 +1041,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
@@ -1386,7 +1386,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
@@ -1966,7 +1966,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
@@ -2692,7 +2692,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@@ -2728,7 +2728,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@@ -2764,7 +2764,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@@ -2808,7 +2808,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@@ -2825,7 +2825,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@@ -2883,7 +2883,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c
+1
View File
@@ -61,6 +61,7 @@
/* Calibration time max = 116 / fADC (refer to datasheet) */
/* = 193 024 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
/**
* @}
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c
+86 -72
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c
+107 -107
View File
File diff suppressed because it is too large. Load diff
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c
+1167 -616
View File
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c
+9 -5
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@@ -9,11 +9,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -100,7 +100,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)hcryp->Size * 8U; /* input length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if (hcryp->State == HAL_CRYP_STATE_READY)
@@ -139,7 +139,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Set the encrypt operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
/*TinyAES IP from V3.1.1 : data has to be inserted normally (no swapping)*/
/*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
/* Write into the AES_DINR register the number of bits in header (64 bits)
followed by the number of bits in the payload */
@@ -220,6 +220,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Process locked */
__HAL_LOCK(hcryp);
/* Disable interrupts in case they were kept enabled to proceed
a single message in several iterations */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
@@ -318,7 +322,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
==============================================================================
[..] This section provides functions allowing to Enable or Disable the
the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
These function are allowed only in TinyAES IP.
These function are allowed only in TinyAES peripheral.
@endverbatim
* @{
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c
+34 -45
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c
+18 -10
View File
@@ -12,9 +12,15 @@
##### How to use this driver #####
==============================================================================
[..]
*** Dual mode IO operation ***
==============================
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@@ -28,11 +34,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -68,8 +74,8 @@
*/
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
* @brief Extended IO operation functions
*
* @brief Extended IO operation functions
*
@verbatim
==============================================================================
##### Extended features functions #####
@@ -201,7 +207,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data, tmp;
uint32_t data;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
@@ -435,7 +442,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -491,8 +499,8 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
* @brief Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -532,7 +540,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
* @brief Extended private functions
* @{
*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c
+6 -6
View File
@@ -220,12 +220,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
hdma->DMAmuxRequestGenStatusMask = 0U;
}
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -293,6 +287,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c
+83 -90
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c
+62 -78
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c
+10 -9
View File
@@ -314,9 +314,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FuL << (8u * (position & 0x03u)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))))
{
tmp = 0x0FuL << (8u * (position & 0x03u));
EXTI->EXTICR[position >> 2u] &= ~tmp;
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
@@ -324,6 +321,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = 0x0FuL << (8u * (position & 0x03u));
EXTI->EXTICR[position >> 2u] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@@ -432,13 +432,13 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BSRR = GPIO_Pin;
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
@@ -469,9 +469,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{
return HAL_OK;
@@ -514,7 +515,7 @@ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
*/
}
@@ -529,7 +530,7 @@ __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
*/
}
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c
+50 -29
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c
+125 -109
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_irda.c
+74 -45
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bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c
+14 -14
View File
@@ -36,7 +36,7 @@
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32G0xx
@@ -48,19 +48,19 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(+) wait for status flags to be reset"
(+) Depending on window parameter:
(++) If Window Init parameter is same as Window register value,
(++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
(++) Else modify Window register. This will automatically reload
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
@@ -79,11 +79,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
@@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automaticaly */
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_lptim.c
+9 -6
View File
@@ -92,19 +92,19 @@
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback.
@@ -117,15 +117,18 @@
(+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback.
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
@@ -133,6 +136,7 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -148,8 +152,7 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c
-10
View File
@@ -5,16 +5,6 @@
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
This file is generated automatically by STM32CubeMX and eventually modified
by the user
@endverbatim
******************************************************************************
* @attention
*
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c
+25 -5
View File
@@ -273,7 +273,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -399,7 +399,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -680,7 +680,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
return HAL_ERROR;
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
#endif
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
{
return HAL_ERROR;
}
}
}
}
return HAL_OK;
@@ -870,7 +890,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(TICK_INT_PRIORITY);
return HAL_InitTick(uwTickPrio);
}
/**
@@ -1067,7 +1087,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU));
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
}
/**
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