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Merge pull request #832 from TanekLiang/gd32f450z

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[BSP] add bsp for GD32F450Z-EVAL
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Bernard Xiong authored and GitHub committed 2017-08-31 20:20:31 +08:00
2 parents d32e78a4cd 09d3599ff9
commit 7ff28e6ff1
128 files changed
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bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h
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bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/system_gd32f4xx.h
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/*!
\file system_gd32f4xx.h
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
GD32F4xx Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32F4XX_H
#define SYSTEM_GD32F4XX_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32F4XX_H */
bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s
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bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s
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bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c
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bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h
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bsp/gd32450z-eval/Libraries/CMSIS/core_cm4_simd.h
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bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h
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bsp/gd32450z-eval/Libraries/CMSIS/core_cmInstr.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h
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/*!
\file gd32f4xx_crc.h
\brief definitions for the CRC
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_CRC_H
#define GD32F4XX_CRC_H
#include "gd32f4xx.h"
/* CRC definitions */
#define CRC CRC_BASE
/* registers definitions */
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* reset data register to the value of initializaiton data register */
void crc_data_register_reset(void);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* CRC calculate a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* CRC calculate a 32-bit data array */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32F4XX_CRC_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h
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/*!
\file gd32f4xx_ctc.h
\brief definitions for the CTC
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_CTC_H
#define GD32F4XX_CTC_H
#include "gd32f4xx.h"
/* CTC definitions */
#define CTC CTC_BASE
/* registers definitions */
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
/* CTC_CTL1 */
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
/* CTC_STAT */
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
/* CTC_INTC */
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
/* constants definitions */
/* hardware automatically trim mode definitions */
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
/* reference signal source polarity definitions */
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
/* USBFS or USBHS SOF signal selection definitions */
#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/
#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/
/* reference signal source selection definitions */
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */
/* reference signal source prescaler definitions */
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
/* CTC interrupt enable definitions */
#define CTC_INT_CKOKIE CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARNIE CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERRIE CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREFIE CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
/* CTC interrupt source definitions */
#define CTC_INT_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
/* CTC flag definitions */
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
/* function declarations */
/* reset ctc clock trim controller */
void ctc_deinit(void);
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t ctc_interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t ctc_interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t ctc_interrupt);
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t ctc_flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t ctc_flag);
/* configure the IRC48M trim value */
void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value);
/* generate software reference source sync pulse */
void ctc_software_refsource_pulse_generate(void);
/* configure hardware automatically trim mode */
void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode);
/* enable CTC counter */
void ctc_counter_enable(void);
/* disable CTC counter */
void ctc_counter_disable(void);
/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t ctc_polarity);
/* select USBFS or USBHS SOF signal */
void ctc_usbsof_signal_select(uint32_t ctc_usbsof);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t ctc_refs);
/* configure reference signal source prescaler */
void ctc_refsource_prescaler_config(uint32_t ctc_prescaler);
/* configure clock trim base limit value */
void ctc_clock_limit_value_config(uint8_t ctc_limit_value);
/* configure CTC counter reload value */
void ctc_counter_reload_value_config(uint16_t ctc_reload_value);
/* read CTC counter capture value when reference sync pulse occurred */
uint16_t ctc_counter_capture_value_read(void);
/* read CTC trim counter direction when reference sync pulse occurred */
FlagStatus ctc_counter_direction_read(void);
/* read CTC counter reload value */
uint16_t ctc_counter_reload_value_read(void);
/* read the IRC48M trim value */
uint8_t ctc_irc48m_trim_value_read(void);
#endif /* GD32F4XX_CTC_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h
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/*!
\file gd32f4xx_dbg.h
\brief definitions for the DBG
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_DBG_H
#define GD32F4XX_DBG_H
#include "gd32f4xx.h"
/* DBG definitions */
#define DBG DBG_BASE
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL0 */
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
/* DBG_CTL1 */
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */
#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */
#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */
#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */
#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */
#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */
#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */
#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */
#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */
#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */
#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */
#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */
#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */
#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */
/* DBG_CTL2 */
#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */
#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */
#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */
#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */
#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
typedef enum
{
DBG_TIMER1_HOLD = BIT(0), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = BIT(1), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = BIT(2), /*!< hold TIMER3 counter when core is halted */
DBG_TIMER4_HOLD = BIT(3), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = BIT(4), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = BIT(5), /*!< hold TIMER6 counter when core is halted */
DBG_TIMER11_HOLD = BIT(6), /*!< hold TIMER11 counter when core is halted */
DBG_TIMER12_HOLD = BIT(7), /*!< hold TIMER12 counter when core is halted */
DBG_TIMER13_HOLD = BIT(8), /*!< hold TIMER13 counter when core is halted */
DBG_RTC_HOLD = BIT(10), /*!< hold RTC calendar and wakeup counter when core is halted */
DBG_WWDGT_HOLD = BIT(11), /*!< debug WWDGT kept when core is halted */
DBG_FWDGT_HOLD = BIT(12), /*!< debug FWDGT kept when core is halted */
DBG_I2C0_HOLD = BIT(21), /*!< hold I2C0 smbus when core is halted */
DBG_I2C1_HOLD = BIT(22), /*!< hold I2C1 smbus when core is halted */
DBG_I2C2_HOLD = BIT(23), /*!< hold I2C2 smbus when core is halted */
DBG_CAN0_HOLD = BIT(25), /*!< debug CAN0 kept when core is halted */
DBG_CAN1_HOLD = BIT(26), /*!< debug CAN1 kept when core is halted */
DBG_TIMER0_HOLD = (BIT(0) | BIT(30)), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER7_HOLD = (BIT(1) | BIT(30)), /*!< hold TIMER7 counter when core is halted */
DBG_TIMER8_HOLD = (BIT(16) | BIT(30)), /*!< hold TIMER8 counter when core is halted */
DBG_TIMER9_HOLD = (BIT(17) | BIT(30)), /*!< hold TIMER9 counter when core is halted */
DBG_TIMER10_HOLD = (BIT(18) | BIT(30)), /*!< hold TIMER10 counter when core is halted */
}dbg_periph_enum;
#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
/* function declarations */
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
/* enable trace pin assignment */
void dbg_trace_pin_enable(void);
/* disable trace pin assignment */
void dbg_trace_pin_disable(void);
/* set trace pin mode */
void dbg_trace_pin_mode_set(uint32_t trace_mode);
#endif /* GD32F4XX_DBG_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h
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/*!
\file gd32f4xx_dci.h
\brief definitions for the DCI
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_DCI_H
#define GD32F4XX_DCI_H
#include "gd32f4xx.h"
/* DCI definitions */
#define DCI DCI_BASE
/* registers definitions */
#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */
#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */
/* bits definitions */
/* DCI_CTL */
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
#define DCI_CTL_JM BIT(3) /*!< jpeg mode */
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
#define DCI_CTL_DCIEN BIT(14) /*!< dci enable */
/* DCI_STAT0 */
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
#define DCI_STAT0_VS BIT(1) /*!< VS line status */
#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
/* DCI_STAT1 */
#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
/* DCI_INTEN */
#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
/* DCI_INTF */
#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
/* DCI_INTC */
#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
/* DCI_SC */
#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
/* DCI_SCUNMSK */
#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
/* DCI_CWSPOS */
#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
/* DCI_CWSZ */
#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
/* constants definitions */
/* DCI parameter struct definitions */
typedef struct
{
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
uint32_t clock_polarity; /*!< clock polarity selection */
uint32_t hsync_polarity; /*!< horizontal polarity selection */
uint32_t vsync_polarity; /*!< vertical polarity selection */
uint32_t frame_rate; /*!< frame capture rate */
uint32_t interface_format; /*!< digital camera interface format */
}dci_parameter_struct;
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
/* DCI interrupt constants definitions */
#define DCI_INT_EF ((uint32_t)0x00000001U) /*!< end of frame interrupt */
#define DCI_INT_OVR ((uint32_t)0x00000002U) /*!< FIFO overrun interrupt */
#define DCI_INT_ESE ((uint32_t)0x00000004U) /*!< embedded synchronous error interrupt */
#define DCI_INT_VS ((uint32_t)0x00000008U) /*!< vsync interrupt */
#define DCI_INT_EL ((uint32_t)0x00000010U) /*!< end of line interrupt */
/* DCI flag definitions */
#define DCI_FLAG_HS ((uint8_t)0x01U) /*!< HS line status */
#define DCI_FLAG_VS ((uint8_t)0x02U) /*!< VS line status */
#define DCI_FLAG_FV ((uint8_t)0x03U) /*!< FIFO valid */
#define DCI_FLAG_EFF ((uint8_t)0x04U) /*!< end of frame flag */
#define DCI_FLAG_OVRF ((uint8_t)0x05U) /*!< FIFO overrun flag */
#define DCI_FLAG_ESEF ((uint8_t)0x06U) /*!< embedded synchronous error flag */
#define DCI_FLAG_VSF ((uint8_t)0x07U) /*!< vsync flag */
#define DCI_FLAG_ELF ((uint8_t)0x08U) /*!< end of line flag */
/* function declarations */
/* DCI deinit */
void dci_deinit(void);
/* initialize DCI registers */
void dci_init(dci_parameter_struct* dci_struct);
/* enable DCI function */
void dci_enable(void);
/* disble DCI function */
void dci_disable(void);
/* enable DCI capture */
void dci_capture_enable(void);
/* disble DCI capture */
void dci_capture_disable(void);
/* enable DCI jpeg mode */
void dci_jpeg_enable(void);
/* disble DCI jpeg mode */
void dci_jpeg_disable(void);
/* enable cropping window function */
void dci_crop_window_enable(void);
/* disble cropping window function */
void dci_crop_window_disable(void);
/* config DCI cropping window */
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
/* enable sync codes function */
void dci_sync_codes_enable(void);
/* disble sync codes function */
void dci_sync_codes_disable(void);
/* config sync codes */
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* config sync codes unmask */
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* read DCI data register */
uint32_t dci_data_read(void);
/* enable specified DCI interrupt */
void dci_interrupt_enable(uint32_t interrupt);
/* disble specified DCI interrupt */
void dci_interrupt_disable(uint32_t interrupt);
/* clear specified interrupt */
void dci_interrupt_clear(uint32_t interrupt);
/* get specified flag */
FlagStatus dci_flag_get(uint32_t flag);
/* get specified interrupt flag */
FlagStatus dci_interrupt_flag_get(uint32_t interrupt);
#endif /* GD32F4XX_DCI_H */
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/*!
\file gd32f4xx_fwdgt.h
\brief definitions for the FWDGT
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_FWDGT_H
#define GD32F4XX_FWDGT_H
#include "gd32f4xx.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
/* constants definitions */
/* psc register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* function declarations */
/* disable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
void fwdgt_enable(void);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32F4XX_FWDGT_H */
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/*!
\file gd32f4xx_iref.h
\brief definitions for the IREF
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_IREF_H
#define GD32F4XX_IREF_H
#include "gd32f4xx.h"
/* IREF definitions */
#define IREF IREF_BASE /*!< IREF base address */
/* registers definitions */
#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */
/* bits definitions */
/* IREF_CTL */
#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */
#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */
#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */
#define IREF_CTL_SSEL BIT(14) /*!< step selection */
#define IREF_CTL_CREN BIT(15) /*!< current reference enable */
/* constants definitions */
/* IREF current precision trim */
#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8))
#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */
#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */
#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */
#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */
#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */
#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */
#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */
#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */
#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */
#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */
#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */
#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */
#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */
#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */
#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */
#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */
#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */
#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */
#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */
#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */
#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */
#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */
#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */
#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */
#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */
#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */
#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */
#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */
#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */
#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */
#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */
#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */
/* IREF current step */
#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0))
#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */
#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */
#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */
#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */
#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */
#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */
#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */
#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */
#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */
#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */
#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */
#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */
#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */
#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */
#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */
#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */
#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */
#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */
#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */
#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */
#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */
#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */
#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */
#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */
#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */
#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */
#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */
#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */
#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */
#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */
#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */
#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */
#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */
#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */
#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */
#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */
#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */
#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */
#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */
#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */
#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */
#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */
#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */
#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */
#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */
#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */
#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */
#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */
#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */
#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */
#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */
#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */
#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */
#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */
#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */
#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */
#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */
#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */
#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */
#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */
#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */
/* IREF mode selection */
#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14))
#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */
#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */
/* IREF sink current mode*/
#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */
#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */
/* function declarations */
/* deinit IREF */
void iref_deinit(void);
/* enable IREF */
void iref_enable(void);
/* disable IREF */
void iref_disable(void);
/* set IREF mode*/
void iref_mode_set(uint32_t step);
/* set IREF sink current mode*/
void iref_sink_set(uint32_t sinkmode);
/* set IREF current precision trim value */
void iref_precision_trim_value_set(uint32_t precisiontrim);
/* set IREF step data*/
void iref_step_data_config(uint32_t stepdata);
#endif /* GD32F4XX_IREF_H */
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/*!
\file gd32f4xx_misc.h
\brief definitions for the MISC
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_MISC_H
#define GD32F4XX_MISC_H
#include "gd32f4xx.h"
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/* priority group - define the pre-emption priority and the subpriority */
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
/* choose the method to enter or exit the lowpower mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
/* function declarations */
/* set the priority group */
void nvic_priority_group_set(uint32_t nvic_prigroup);
/* enable NVIC request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC request */
void nvic_irq_disable(uint8_t nvic_irq);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#endif /* GD32F4XX_MISC_H */
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/*!
\file gd32f4xx_pmu.h
\brief definitions for the PMU
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_PMU_H
#define GD32F4XX_PMU_H
#include "gd32f4xx.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
/* bits definitions */
/* PMU_CTL */
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */
#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */
#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */
#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
/* PMU LDO output voltage select definitions */
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
/* PMU low-driver mode enable in deep-sleep mode */
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
/* PMU high-driver mode switch */
#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
/* PMU low-driver mode when use low power LDO */
#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
/* PMU low-driver mode when use normal power LDO */
#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11))
#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
/* PMU low power mode ready flag definitions */
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
/* PMU backup SRAM LDO on or off */
#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
/* PMU flag definitions */
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */
#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */
#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */
#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* function declarations */
/* reset PMU register */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t pmu_lvdt_n);
/* LDO output voltage select */
void pmu_ldo_output_select(uint32_t ldo_output);
/* PMU lvd disable */
void pmu_lvd_disable(void);
/* functions of low-driver mode and high-driver mode in deep-sleep mode */
/* high-driver mode switch */
void pmu_highdriver_switch_select(uint32_t highdr_switch);
/* high-driver mode enable */
void pmu_highdriver_mode_enable(void);
/* high-driver mode disable */
void pmu_highdriver_mode_disable(void);
/* low-driver mode enable in deep-sleep mode */
void pmu_low_driver_mode_enable(uint32_t lowdr_mode);
/* in deep-sleep mode, low-driver mode when use low power LDO */
void pmu_lowdriver_lowpower_config(uint32_t mode);
/* in deep-sleep mode, low-driver mode when use normal power LDO */
void pmu_lowdriver_normalpower_config(uint32_t mode);
/* set PMU mode */
/* PMU work at sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* PMU work at deepsleep mode */
void pmu_to_deepsleepmode(uint32_t pmu_ldo, uint8_t deepsleepmodecmd);
/* PMU work at standby mode */
void pmu_to_standbymode(uint8_t standbymodecmd);
/* PMU wakeup pin enable */
void pmu_wakeup_pin_enable(void);
/* PMU wakeup pin disable */
void pmu_wakeup_pin_disable(void);
/* backup related functions */
/* backup SRAM LDO on */
void pmu_backup_ldo_config(uint32_t bkp_ldo);
/* backup domain write enable */
void pmu_backup_write_enable(void);
/* backup domain write disable */
void pmu_backup_write_disable(void);
/* flag functions */
/* reset flag bit */
void pmu_flag_reset(uint32_t flag_reset);
/* get flag status */
FlagStatus pmu_flag_get(uint32_t pmu_flag);
#endif /* GD32F4XX_PMU_H */
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/*!
\file gd32f4xx_syscfg.h
\brief definitions for the SYSCFG
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_SYSCFG_H
#define GD32F4XX_SYSCFG_H
#include "gd32f4xx.h"
/* SYSCFG definitions */
#define SYSCFG SYSCFG_BASE
/* registers definitions */
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U) /*!< system I/O compensation control register */
/* SYSCFG_CFG0 bits definitions */
#define SYSCFG_CFG0_BOOT_MODE BITS(0,2) /*!< SYSCFG memory remap config */
#define SYSCFG_CFG0_FMC_SWP BIT(8) /*!< FMC memory swap config */
#define SYSCFG_CFG0_EXMC_SWP BITS(10,11) /*!< EXMC memory swap config */
/* SYSCFG_CFG1 bits definitions */
#define SYSCFG_CFG1_ENET_PHY_SEL BIT(23) /*!< Ethernet PHY selection config */
/* SYSCFG_EXTISS0 bits definitions */
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
/* SYSCFG_EXTISS1 bits definitions */
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
/* SYSCFG_EXTISS2 bits definitions */
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
/* SYSCFG_EXTISS3 bits definitions */
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
/* SYSCFG_CPSCTL bits definitions */
#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */
#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */
/* constants definitions */
/* boot mode definitions */
#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< main flash memory remap */
#define SYSCFG_BOOTMODE_BOOTLOADER ((uint8_t)0x01U) /*!< boot loader remap */
#define SYSCFG_BOOTMODE_EXMC_SRAM ((uint8_t)0x02U) /*!< SRAM/NOR 0 and 1 of EXMC remap */
#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< SRAM0 of on-chip SRAM remap */
#define SYSCFG_BOOTMODE_EXMC_SDRAM ((uint8_t)0x04U) /*!< SDRAM bank0 of EXMC remap */
/* FMC swap definitions */
#define SYSCFG_FMC_SWP_BANK0 ((uint32_t)0x00000000U) /*!< main flash Bank 0 is mapped at address 0x08000000 */
#define SYSCFG_FMC_SWP_BANK1 ((uint32_t)0x00000100U) /*!< main flash Bank 1 is mapped at address 0x08000000 */
/* EXMC swap enable/disable */
#define SYSCFG_EXMC_SWP_ENABLE ((uint32_t)0x00000400U) /*!< SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card */
#define SYSCFG_EXMC_SWP_DISABLE ((uint32_t)0x00000000U) /*!< no memory mapping swap */
/* EXTI source select definition */
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select GPIOx pin 0~3 */
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select GPIOx pin 4~7 */
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select GPIOx pin 8~11 */
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */
/* EXTI source select mask bits definition */
#define EXTI_SS_MASK BITS(0,3)
/* EXTI source select jumping step definition */
#define EXTI_SS_JSTEP ((uint8_t)(0x04U))
/* EXTI source select moving step definition */
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP))
/* EXTI source port definitions */
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */
#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */
#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */
#define EXTI_SOURCE_GPIOI ((uint8_t)0x08U) /*!< EXTI GPIOI configuration */
/* EXTI source pin definitions */
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
/* ethernet PHY selection */
#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U)
#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U)
/* I/O compensation cell enable/disable */
#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U)
#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U)
/* function declarations */
/* deinit syscfg module */
void syscfg_deinit(void);
/* configure the boot mode */
void syscfg_bootmode_config(uint8_t syscfg_bootmode);
/* FMC memory mapping swap */
void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap);
/* configure the EXMC swap */
void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap);
/* configure the GPIO pin as EXTI Line */
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
/* configure the PHY interface for the ethernet MAC */
void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface);
/* configure the I/O compensation cell */
void syscfg_compensation_config(uint32_t syscfg_compensation);
/* check the I/O compensation cell is ready or not */
FlagStatus syscfg_flag_get(void);
#endif /* GD32F4XX_SYSCFG_H */
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/*!
\file gd32f4xx_trng.h
\brief definitions for the TRNG
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_TRNG_H
#define GD32F4XX_TRNG_H
#include "gd32f4xx.h"
/* EXTI definitions */
#define TRNG TRNG_BASE
/* registers definitions */
#define TRNG_CTL REG32(TRNG + 0x00U) /*!< interrupt enable register */
#define TRNG_STAT REG32(TRNG + 0x04U) /*!< event enable register */
#define TRNG_DATA REG32(TRNG + 0x08U) /*!< rising edge trigger enable register */
/* bits definitions */
/* TRNG_CTL */
#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */
#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */
/* TRNG_STAT */
#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */
#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */
#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */
#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */
#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */
/* TRNG_DATA */
#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */
/* constants definitions */
/* trng status flag */
typedef enum
{
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */
}trng_flag_enum;
/* trng inerrupt flag */
typedef enum
{
TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */
TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */
}trng_int_flag_enum;
/* function declarations */
/* deinitialize the TRNG */
void trng_deinit(void);
/* enable the TRNG interface */
void trng_enable(void);
/* disable the TRNG interface */
void trng_disable(void);
/* get the true random data */
uint32_t trng_get_true_random_data(void);
/* get the trng status flags */
FlagStatus trng_flag_get(trng_flag_enum flag);
/* clear the trng status flags */
void trng_flag_clear(trng_flag_enum flag);
/* the trng interrupt enable */
void trng_interrupt_enable(void);
/* the trng interrupt disable */
void trng_interrupt_disable(void);
/* get the trng interrupt flags */
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
/* clear the trng interrupt flags */
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
#endif /* GD32F4XX_TRNG_H */
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/*!
\file gd32f4xx_wwdgt.h
\brief definitions for the WWDGT
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef GD32F4XX_WWDGT_H
#define GD32F4XX_WWDGT_H
#include "gd32f4xx.h"
/* WWDGT definitions */
#define WWDGT WWDGT_BASE
/* registers definitions */
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
/* bits definitions */
/* WWDGT_CTL */
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
/* WWDGT_CFG */
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
/* WWDGT_STAT */
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
/* constants definitions */
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
/* function declarations */
/* reset the window watchdog timer configuration */
void wwdgt_deinit(void);
/* start the window watchdog timer counter */
void wwdgt_enable(void);
/* configure the window watchdog timer counter value */
void wwdgt_counter_update(uint16_t counter_value);
/* configure counter value, window value, and prescaler divider value */
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
/* enable early wakeup interrupt of WWDGT */
void wwdgt_interrupt_enable(void);
/* check early wakeup interrupt state of WWDGT */
FlagStatus wwdgt_flag_get(void);
/* clear early wakeup interrupt state of WWDGT */
void wwdgt_flag_clear(void);
#endif /* GD32F4XX_WWDGT_H */
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c
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/*!
\file gd32f4xx_crc.c
\brief CRC driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_crc.h"
/*!
\brief deinit CRC calculation unit
\param[in] none
\param[out] none
\retval none
*/
void crc_deinit(void)
{
CRC_DATA = (uint32_t)0xFFFFFFFFU;
CRC_FDATA = (uint32_t)0x00000000U;
CRC_CTL = CRC_CTL_RST;
}
/*!
\brief reset data register to the value of initializaiton data register
\param[in] none
\param[out] none
\retval none
*/
void crc_data_register_reset(void)
{
CRC_CTL |= (uint32_t)CRC_CTL_RST;
}
/*!
\brief read the data register
\param[in] none
\param[out] none
\retval 32-bit value of the data register
*/
uint32_t crc_data_register_read(void)
{
uint32_t data;
data = CRC_DATA;
return (data);
}
/*!
\brief read the free data register
\param[in] none
\param[out] none
\retval 8-bit value of the free data register
*/
uint8_t crc_free_data_register_read(void)
{
uint8_t fdata;
fdata = (uint8_t)CRC_FDATA;
return (fdata);
}
/*!
\brief write the free data register
\param[in] free_data: specify 8-bit data
\param[out] none
\retval none
*/
void crc_free_data_register_write(uint8_t free_data)
{
CRC_FDATA = (uint32_t)free_data;
}
/*!
\brief CRC calculate a 32-bit data
\param[in] sdata: specify 32-bit data
\param[out] none
\retval 32-bit CRC calculate value
*/
uint32_t crc_single_data_calculate(uint32_t sdata)
{
CRC_DATA = sdata;
return (CRC_DATA);
}
/*!
\brief CRC calculate a 32-bit data array
\param[in] array: pointer to an array of 32 bit data words
\param[in] size: size of the array
\param[out] none
\retval 32-bit CRC calculate value
*/
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
{
uint32_t index;
for(index = 0U; index < size; index++){
CRC_DATA = array[index];
}
return (CRC_DATA);
}
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c
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/*!
\file gd32f4xx_dbg.c
\brief DBG driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_dbg.h"
/*!
\brief read DBG_ID code register
\param[in] none
\param[out] none
\retval DBG_ID code
*/
uint32_t dbg_id_get(void)
{
return DBG_ID;
}
/*!
\brief enable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
this parameter can be any combination of the following values:
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_enable(uint32_t dbg_low_power)
{
DBG_CTL0 |= dbg_low_power;
}
/*!
\brief disable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
this parameter can be any combination of the following values:
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_disable(uint32_t dbg_low_power)
{
DBG_CTL0 &= ~dbg_low_power;
}
/*!
\brief enable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: dbg_periph_enum
\param[out] none
\retval none
*/
void dbg_periph_enable(dbg_periph_enum dbg_periph)
{
if(RESET == ((uint32_t)dbg_periph & BIT(30))){
DBG_CTL1 |= (uint32_t)dbg_periph;
}else{
DBG_CTL2 |= ((uint32_t)dbg_periph & (~BIT(30)));
}
}
/*!
\brief disable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: dbg_periph_enum
\param[out] none
\retval none
*/
void dbg_periph_disable(dbg_periph_enum dbg_periph)
{
if(RESET == ((uint32_t)dbg_periph & BIT(30))){
DBG_CTL1 &= ~(uint32_t)dbg_periph;
}else{
DBG_CTL2 &= ~((uint32_t)dbg_periph & (~BIT(30)));
}
}
/*!
\brief enable trace pin assignment
\param[in] none
\param[out] none
\retval none
*/
void dbg_trace_pin_enable(void)
{
DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
}
/*!
\brief disable trace pin assignment
\param[in] none
\param[out] none
\retval none
*/
void dbg_trace_pin_disable(void)
{
DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
}
/*!
\brief trace pin mode selection
\param[in] trace_mode:
\arg TRACE_MODE_ASYNC: trace pin used for async mode
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
\param[out] none
\retval none
*/
void dbg_trace_pin_mode_set(uint32_t trace_mode)
{
DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
DBG_CTL0 |= trace_mode;
}
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c
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/*!
\file gd32f4xx_fwdgt.c
\brief FWDGT driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_fwdgt.h"
/* write value to FWDGT_CTL_CMD bit field */
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
/* write value to FWDGT_RLD_RLD bit field */
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
/*!
\brief disable write access to FWDGT_PSC and FWDGT_RLD
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_write_disable(void)
{
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
}
/*!
\brief reload the counter of FWDGT
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_counter_reload(void)
{
FWDGT_CTL = FWDGT_KEY_RELOAD;
}
/*!
\brief start the free watchdog timer counter
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_enable(void)
{
FWDGT_CTL = FWDGT_KEY_ENABLE;
}
/*!
\brief configure counter reload value, and prescaler divider value
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
\param[in] prescaler_div: FWDGT prescaler value
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
\param[out] none
\retval ErrStatus: ERROR or SUCCESS
*/
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
uint32_t timeout = FWDGT_PSC_TIMEOUT;
uint32_t flag_status = RESET;
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the PUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
return ERROR;
}
/* configure FWDGT */
FWDGT_PSC = (uint32_t)prescaler_div;
timeout = FWDGT_RLD_TIMEOUT;
/* wait until the RUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
return ERROR;
}
FWDGT_RLD = RLD_RLD(reload_value);
/* reload the counter */
FWDGT_CTL = FWDGT_KEY_RELOAD;
return SUCCESS;
}
/*!
\brief get flag state of FWDGT
\param[in] flag: flag to get
\arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going
\arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fwdgt_flag_get(uint16_t flag)
{
if(FWDGT_STAT & flag){
return SET;
}
return RESET;
}
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c
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/*!
\file gd32f4xx_iref.c
\brief IREF driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_iref.h"
/*!
\brief deinit IREF
\param[in] none
\param[out] none
\retval none
*/
void iref_deinit(void)
{
rcu_periph_reset_enable(RCU_IREFRST);
rcu_periph_reset_disable(RCU_IREFRST);
}
/*!
\brief enable IREF
\param[in] none
\param[out] none
\retval none
*/
void iref_enable(void)
{
IREF_CTL |= IREF_CTL_CREN;
}
/*!
\brief disable IREF
\param[in] none
\param[out] none
\retval none
*/
void iref_disable(void)
{
IREF_CTL &= ~IREF_CTL_CREN;
}
/*!
\brief set IREF mode
\param[in] step
\arg IREF_MODE_LOW_POWER: 1uA step
\arg IREF_MODE_HIGH_CURRENT: 8uA step
\param[out] none
\retval none
*/
void iref_mode_set(uint32_t step)
{
IREF_CTL &= ~IREF_CTL_SSEL;
IREF_CTL |= step;
}
/*!
\brief set IREF precision_trim_value
\param[in] precisiontrim
\arg IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)%
\param[out] none
\retval none
*/
void iref_precision_trim_value_set(uint32_t precisiontrim)
{
IREF_CTL &= ~IREF_CTL_CPT;
IREF_CTL |= precisiontrim;
}
/*!
\brief set IREF sink mode
\param[in] sinkmode
\arg IREF_SOURCE_CURRENT : source current.
\arg IREF_SINK_CURRENT: sink current
\param[out] none
\retval none
*/
void iref_sink_set(uint32_t sinkmode)
{
IREF_CTL &= ~IREF_CTL_SCMOD;
IREF_CTL |= sinkmode;
}
/*!
\brief set IREF step data
\param[in] stepdata
\arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x
\param[out] none
\retval none
*/
void iref_step_data_config(uint32_t stepdata)
{
IREF_CTL &= ~IREF_CTL_CSDT;
IREF_CTL |= stepdata;
}
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c
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/*!
\file gd32f4xx_misc.c
\brief MISC driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_misc.h"
/*!
\brief set the priority group
\param[in] nvic_prigroup: the NVIC priority group
\arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
\arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
\arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
\arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
\arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
\param[out] none
\retval none
*/
void nvic_priority_group_set(uint32_t nvic_prigroup)
{
/* set the priority group value */
SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
}
/*!
\brief enable NVIC request
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
\param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
\param[in] nvic_irq_sub_priority: the subpriority needed to set
\param[out] none
\retval none
*/
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
uint8_t nvic_irq_sub_priority)
{
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
/* use the priority group value to get the temp_pre and the temp_sub */
if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
temp_pre=0U;
temp_sub=0x4U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
temp_pre=1U;
temp_sub=0x3U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
temp_pre=2U;
temp_sub=0x2U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
temp_pre=3U;
temp_sub=0x1U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
temp_pre=4U;
temp_sub=0x0U;
}else{
}
/* get the temp_priority to fill the NVIC->IP register */
temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
temp_priority = temp_priority << 0x04U;
NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
/* enable the selected IRQ */
NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
}
/*!
\brief disable NVIC request
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
\param[out] none
\retval none
*/
void nvic_irq_disable(uint8_t nvic_irq)
{
/* disable the selected IRQ.*/
NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
}
/*!
\brief set the NVIC vector table base address
\param[in] nvic_vict_tab: the RAM or FLASH base address
\arg NVIC_VECTTAB_RAM: RAM base address
\are NVIC_VECTTAB_FLASH: Flash base address
\param[in] offset: Vector Table offset
\param[out] none
\retval none
*/
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
{
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
}
/*!
\brief set the state of the low power mode
\param[in] lowpower_mode: the low power mode state
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
mode by exiting from ISR
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
by all the enable and disable interrupts
\param[out] none
\retval none
*/
void system_lowpower_set(uint8_t lowpower_mode)
{
SCB->SCR |= (uint32_t)lowpower_mode;
}
/*!
\brief reset the state of the low power mode
\param[in] lowpower_mode: the low power mode state
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
mode by exiting from ISR
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
woke up by the enable interrupts
\param[out] none
\retval none
*/
void system_lowpower_reset(uint8_t lowpower_mode)
{
SCB->SCR &= (~(uint32_t)lowpower_mode);
}
/*!
\brief set the systick clock source
\param[in] systick_clksource: the systick clock source needed to choose
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
\param[out] none
\retval none
*/
void systick_clksource_set(uint32_t systick_clksource)
{
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
/* set the systick clock source from HCLK */
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}else{
/* set the systick clock source from HCLK/8 */
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
}
}
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/*!
\file gd32f4xx_syscfg.c
\brief SYSCFG driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_syscfg.h"
/*!
\brief reset the SYSCFG registers
\param[in] none
\param[out] none
\retval none
*/
void syscfg_deinit(void)
{
rcu_periph_reset_enable(RCU_SYSCFGRST);
rcu_periph_reset_disable(RCU_SYSCFGRST);
}
/*!
\brief configure the boot mode
\param[in] syscfg_bootmode: selects the memory remapping
\arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000
\arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000
\arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000
\arg SYSCFG_BOOTMODE_SRAM: SRAM0 of on-chip SRAM (0x20000000~0x2001BFFF) is mapped at address 0x00000000
\arg SYSCFG_BOOTMODE_EXMC_SDRAM: SDRAM bank0 of EXMC (0xC0000000~0xC7FFFFFF) is mapped at address 0x00000000
\param[out] none
\retval none
*/
void syscfg_bootmode_config(uint8_t syscfg_bootmode)
{
/* reset the SYSCFG_CFG0_BOOT_MODE bit and set according to syscfg_bootmode */
SYSCFG_CFG0 &= ~SYSCFG_CFG0_BOOT_MODE;
SYSCFG_CFG0 |= (uint32_t)syscfg_bootmode;
}
/*!
\brief FMC memory mapping swap
\param[in] syscfg_fmc_swap: selects the interal flash bank swapping
\arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000
\arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000
\param[out] none
\retval none
*/
void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap)
{
uint32_t reg;
reg = SYSCFG_CFG0;
/* reset the FMC_SWP bit and set according to syscfg_fmc_swap */
reg &= ~SYSCFG_CFG0_FMC_SWP;
SYSCFG_CFG0 = (reg | syscfg_fmc_swap);
}
/*!
\brief EXMC memory mapping swap
\param[in] syscfg_exmc_swap: selects the memories in EXMC swapping
\arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card
\arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap
\param[out] none
\retval none
*/
void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap)
{
uint32_t reg;
reg = SYSCFG_CFG0;
/* reset the SYSCFG_CFG0_EXMC_SWP bits and set according to syscfg_exmc_swap */
reg &= ~SYSCFG_CFG0_EXMC_SWP;
SYSCFG_CFG0 = (reg | syscfg_exmc_swap);
}
/*!
\brief configure the GPIO pin as EXTI Line
\param[in] exti_port: specify the GPIO port used in EXTI
\arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port
\param[in] exti_pin: specify the EXTI line
\arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
\param[out] none
\retval none
*/
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
{
uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
switch(exti_pin/EXTI_SS_JSTEP){
case EXTISS0:
/* clear EXTI source line(0..3) */
SYSCFG_EXTISS0 &= clear_exti_mask;
/* configure EXTI soure line(0..3) */
SYSCFG_EXTISS0 |= config_exti_mask;
break;
case EXTISS1:
/* clear EXTI soure line(4..7) */
SYSCFG_EXTISS1 &= clear_exti_mask;
/* configure EXTI soure line(4..7) */
SYSCFG_EXTISS1 |= config_exti_mask;
break;
case EXTISS2:
/* clear EXTI soure line(8..11) */
SYSCFG_EXTISS2 &= clear_exti_mask;
/* configure EXTI soure line(8..11) */
SYSCFG_EXTISS2 |= config_exti_mask;
break;
case EXTISS3:
/* clear EXTI soure line(12..15) */
SYSCFG_EXTISS3 &= clear_exti_mask;
/* configure EXTI soure line(12..15) */
SYSCFG_EXTISS3 |= config_exti_mask;
break;
default:
break;
}
}
/*!
\brief configure the PHY interface for the ethernet MAC
\param[in] syscfg_enet_phy_interface: specifies the media interface mode.
\arg SYSCFG_ENET_PHY_MII: MII mode is selected
\arg SYSCFG_ENET_PHY_RMII: RMII mode is selected
\param[out] none
\retval none
*/
void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface)
{
uint32_t reg;
reg = SYSCFG_CFG1;
/* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */
reg &= ~SYSCFG_CFG1_ENET_PHY_SEL;
SYSCFG_CFG1 = (reg | syscfg_enet_phy_interface);
}
/*!
\brief configure the I/O compensation cell
\param[in] syscfg_compensation: specifies the I/O compensation cell mode
\arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled
\arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled
\param[out] none
\retval none
*/
void syscfg_compensation_config(uint32_t syscfg_compensation)
{
uint32_t reg;
reg = SYSCFG_CPSCTL;
/* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
reg &= ~SYSCFG_CPSCTL_CPS_EN;
SYSCFG_CPSCTL = (reg | syscfg_compensation);
}
/*!
\brief checks whether the I/O compensation cell ready flag is set or not
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus syscfg_flag_get(void)
{
if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){
return SET;
}else{
return RESET;
}
}
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c
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/*!
\file gd32f4xx_trng.c
\brief TRNG driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_trng.h"
/*!
\brief deinitialize the TRNG
\param[in] none
\param[out] none
\retval none
*/
void trng_deinit(void)
{
rcu_periph_reset_enable(RCU_TRNGRST);
rcu_periph_reset_disable(RCU_TRNGRST);
}
/*!
\brief enable the TRNG interface
\param[in] none
\param[out] none
\retval none
*/
void trng_enable(void)
{
TRNG_CTL |= TRNG_CTL_TRNGEN;
}
/*!
\brief disable the TRNG interface
\param[in] none
\param[out] none
\retval none
*/
void trng_disable(void)
{
TRNG_CTL &= ~TRNG_CTL_TRNGEN;
}
/*!
\brief get the true random data
\param[in] none
\param[out] none
\retval the generated random data
*/
uint32_t trng_get_true_random_data(void)
{
return (TRNG_DATA);
}
/*!
\brief get the trng status flags
\param[in] flag: trng status flag, refer to trng_flag_enum
only one parameter can be selected which is shown as below:
\arg TRNG_FLAG_DRDY: Random Data ready status
\arg TRNG_FLAG_CECS: Clock error current status
\arg TRNG_FLAG_SECS: Seed error current status
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus trng_flag_get(trng_flag_enum flag)
{
if(RESET != (TRNG_STAT & flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear the trng status flags
\param[in] flag: the special status flag
only one parameter can be selected which is shown as below:
\arg TRNG_FLAG_CECS: Clock error current status
\arg TRNG_FLAG_SECS: Seed error current status
\param[out] none
\retval none
*/
void trng_flag_clear(trng_flag_enum flag)
{
TRNG_STAT &= ~(uint32_t)flag;
}
/*!
\brief enable the TRNG interrupt
\param[in] none
\param[out] none
\retval none
*/
void trng_interrupt_enable(void)
{
TRNG_CTL |= TRNG_CTL_IE;
}
/*!
\brief disable the TRNG interrupt
\param[in] none
\param[out] none
\retval none
*/
void trng_interrupt_disable(void)
{
TRNG_CTL &= ~TRNG_CTL_IE;
}
/*!
\brief get the trng interrupt flags
\param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum
only one parameter can be selected which is shown as below:
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
\arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag)
{
if(RESET != (TRNG_STAT & int_flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear the trng interrupt flags
\param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum
only one parameter can be selected which is shown as below:
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
\arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag
\param[out] none
\retval none
*/
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag)
{
TRNG_STAT &= ~(uint32_t)int_flag;
}
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c
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/*!
\file gd32f4xx_wwdgt.c
\brief WWDGT driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "gd32f4xx_wwdgt.h"
/* write value to WWDGT_CTL_CNT bit field */
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
/* write value to WWDGT_CFG_WIN bit field */
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
/*!
\brief reset the window watchdog timer configuration
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_deinit(void)
{
rcu_periph_reset_enable(RCU_WWDGTRST);
rcu_periph_reset_disable(RCU_WWDGTRST);
}
/*!
\brief configure the window watchdog timer counter value
\param[in] counter_value: 0x00 - 0x7F
\param[out] none
\retval none
*/
void wwdgt_counter_update(uint16_t counter_value)
{
uint32_t reg = 0U;
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
reg |= CTL_CNT(counter_value);
WWDGT_CTL = reg;
}
/*!
\brief start the window watchdog timer counter
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_enable(void)
{
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
}
/*!
\brief configure counter value, window value, and prescaler divider value
\param[in] counter: 0x00 - 0x7F
\param[in] window: 0x00 - 0x7F
\param[in] prescaler: wwdgt prescaler value
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
\param[out] none
\retval none
*/
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
{
uint32_t reg_cfg = 0U, reg_ctl = 0U;
/* clear WIN and PSC bits, clear CNT bit */
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
/* configure WIN and PSC bits, configure CNT bit */
reg_cfg |= CFG_WIN(window);
reg_cfg |= prescaler;
reg_ctl |= CTL_CNT(counter);
WWDGT_CTL = reg_ctl;
WWDGT_CFG = reg_cfg;
}
/*!
\brief enable early wakeup interrupt of WWDGT
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_interrupt_enable(void)
{
WWDGT_CFG |= WWDGT_CFG_EWIE;
}
/*!
\brief check early wakeup interrupt state of WWDGT
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus wwdgt_flag_get(void)
{
if(WWDGT_STAT & WWDGT_STAT_EWIF){
return SET;
}
return RESET;
}
/*!
\brief clear early wakeup interrupt state of WWDGT
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_flag_clear(void)
{
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
}
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h
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/*!
\file usb_defines.h
\brief USB core defines
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USB_DEFINES_H
#define USB_DEFINES_H
#include "usb_conf.h"
#ifndef NULL
#define NULL (void *)0 /*!< USB null marco value*/
#endif /* NULL */
#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
#define GRSTATR_RPCKST_IN 2U /* IN data packet received */
#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */
#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* Data toggle error (generates an interrupt if poped) */
#define GRSTATR_RPCKST_CH_HALTED 7U /* Channel halted (generates an interrupt if poped) */
#define DEVICE_MODE 0U /* USB core in device mode */
#define HOST_MODE 1U /* USB core in host mode */
#define OTG_MODE 2U /* USB core in OTG mode */
#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */
#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */
#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */
#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */
#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */
#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */
#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */
#define DPID_MDATA 3U /* device endpoint data PID is MDATA */
#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */
#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */
#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */
#define HC_PID_SETUP 3U /* host channel data PID is SETUP */
#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
#define HCCHAR_CTRL 0U /* control channel type */
#define HCCHAR_ISOC 1U /* synchronous channel type */
#define HCCHAR_BULK 2U /* bulk channel type */
#define HCCHAR_INTR 3U /* interrupt channel type */
typedef enum
{
USB_HS_CORE_ID = 0,
USB_FS_CORE_ID = 1
}usb_core_id_enum;
typedef enum
{
USB_SPEED_UNKNOWN = 0,
USB_SPEED_LOW,
USB_SPEED_FULL,
USB_SPEED_HIGH
}usb_speed_enum;
#endif /* USB_DEFINES_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h
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/*!
\file usb_std.h
\brief USB 2.0 standard defines
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USB_STD_H
#define USB_STD_H
#include "usb_conf.h"
#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */
#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */
#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */
#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */
#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */
#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */
/* bit 7 of bmRequestType: data phase transfer direction */
#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */
#define USB_DIR_OUT 0x00U /*!< USB transfer OUT direction */
#define USB_DIR_IN 0x80U /*!< USB transfer IN direction */
/* bit 6..5 of bmRequestType: request type */
#define USB_STANDARD_REQ 0x00U /*!< USB standard request */
#define USB_CLASS_REQ 0x20U /*!< USB class request */
#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */
#define USB_REQ_MASK 0x60U /*!< USB request mask */
/* bit 4..0 of bmRequestType: recipient type */
#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */
#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/
#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/
#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/
/* bRequest value */
#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/
#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/
#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/
#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/
#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/
#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/
#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/
#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/
#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/
#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/
#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/
/* descriptor types of usb specifications */
#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/
#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/
#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/
#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/
#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/
#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/
#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/
#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/
#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/
#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/
#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/
#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/
#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/
#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/
/* descriptor type and descriptor index */
/* use the following values when USB host need to get descriptor */
#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */
#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */
#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */
#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */
#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */
#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */
#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */
#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */
#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */
#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
/* supported classes */
#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/
#define USB_HID_CLASS 0x03U /*!< USB HID class*/
/* interface descriptor field values for hid boot protocol */
#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/
#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/
#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/
/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
standard request with no data stage timeout : 50ms */
#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/
#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/
#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
+ (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */
#pragma pack(1)
typedef union
{
uint8_t data[8];
struct _setup_packet_struct
{
uint8_t bmRequestType; /*!< type of request */
uint8_t bRequest; /*!< request of setup packet */
uint16_t wValue; /*!< value of setup packet */
uint16_t wIndex; /*!< index of setup packet */
uint16_t wLength; /*!< length of setup packet */
} b;
}usb_setup_union;
typedef struct
{
uint8_t bLength; /*!< size of the descriptor */
uint8_t bDescriptorType; /*!< type of the descriptor */
} usb_descriptor_header_struct;
typedef struct
{
usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */
uint16_t bcdUSB; /*!< BCD of the supported USB specification */
uint8_t bDeviceClass; /*!< USB device class */
uint8_t bDeviceSubClass; /*!< USB device subclass */
uint8_t bDeviceProtocol; /*!< USB device protocol */
uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */
uint16_t idVendor; /*!< vendor ID for the USB product */
uint16_t idProduct; /*!< unique product ID for the USB product */
uint16_t bcdDevice; /*!< product release (version) number */
uint8_t iManufacturer; /*!< string index for the manufacturer's name */
uint8_t iProduct; /*!< string index for the product name/details */
uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */
uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */
} usb_descriptor_device_struct;
typedef struct
{
usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */
uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */
uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */
uint8_t bConfigurationValue; /*!< configuration index of the current configuration */
uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */
uint8_t bmAttributes; /*!< configuration attributes */
uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */
} usb_descriptor_configuration_struct;
typedef struct
{
usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */
uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */
uint8_t bAlternateSetting; /*!< alternate setting for the interface number */
uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */
uint8_t bInterfaceClass; /*!< interface class ID */
uint8_t bInterfaceSubClass; /*!< interface subclass ID */
uint8_t bInterfaceProtocol; /*!< interface protocol ID */
uint8_t iInterface; /*!< index of the string descriptor describing the interface */
} usb_descriptor_interface_struct;
typedef struct
{
usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */
uint8_t bEndpointAddress; /*!< logical address of the endpoint */
uint8_t bmAttributes; /*!< endpoint attributes */
uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */
uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */
} usb_descriptor_endpoint_struct;
typedef struct
{
usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */
uint16_t wLANGID; /*!< LANGID code */
}usb_descriptor_language_id_struct;
#pragma pack()
#endif /* USB_STD_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h
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/*!
\file usbd_core.h
\brief USB device-mode core driver header file
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBD_CORE_H
#define USBD_CORE_H
#include "usbd_conf.h"
#include "usb_core.h"
#include "usbd_std.h"
/* device status */
#define USB_STATUS_DEFAULT 1U /* default status */
#define USB_STATUS_ADDRESSED 2U /* addressed status */
#define USB_STATUS_CONFIGURED 3U /* configured status */
#define USB_STATUS_SUSPENDED 4U /* suspended status */
/* function declarations */
/* initailizes the USB device-mode handler stack */
void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
/* endpoint initialization */
void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *pep_desc);
/* endpoint deinitialize */
void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr);
/* endpoint prepare to receive data */
void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
/* endpoint prepare to transmit data */
void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
/* transmit data on the control channel */
usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
/* receive data on the control channel */
usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
/* transmit status on the control channel */
usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev);
/* receive status on the control channel */
usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev);
/* set an endpoint to STALL status */
void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
/* clear endpoint stalled status */
void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
/* flushes the FIFOs */
void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr);
/* get the received data length */
uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_id);
#endif /* USBD_CORE_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_int.h
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/*!
\file usbd_int.h
\brief USB device-mode interrupt handler header file
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBD_INT_H
#define USBD_INT_H
#include "usbd_core.h"
/* function declarations */
/* USB device-mode interrupts global service routine handler */
uint32_t usbd_isr (usb_core_handle_struct *pudev);
#ifdef USBHS_DEDICATED_EP1_ENABLED
/* USB dedicated OUT endpoint 1 interrupt service routine handler */
uint32_t USBD_EP1OUT_ISR_Handler (usb_core_handle_struct *pudev);
/* USB dedicated IN endpoint 1 interrupt service routine handler */
uint32_t USBD_EP1IN_ISR_Handler (usb_core_handle_struct *pudev);
#endif /* USBHS_DEDICATED_EP1_ENABLED */
#endif /* USBD_INT_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h
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/*!
\file usbd_std.h
\brief USB 2.0 standard driver
*/
/*
Copyright (C) 2016 GigaDevice
2016-06-30, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBD_STD_H
#define USBD_STD_H
#include "usb_std.h"
#include "usbd_core.h"
#include "usbd_conf.h"
#include <wchar.h>
#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/
#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/
#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/
#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/
#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/
#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/
#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/
#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/
#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/
#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/
#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/
#define ENG_LANGID 0x0409U /*!< USB english language id*/
#define CHN_LANGID 0x0804U /*!< USB chinese language id*/
#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/
#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/
#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/
#define WIDE_STRING(string) _WIDE_STRING(string)
#define _WIDE_STRING(string) L##string
#define USBD_STRING_DESC(string) \
(uint8_t *)&(struct { \
uint8_t _len; \
uint8_t _type; \
wchar_t _data[sizeof(string)]; \
}) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \
USB_DESCTYPE_STRING, \
WIDE_STRING(string) \
}
#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
/* function declarations */
/* USB device setup transaction*/
usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev);
/* USB device out transaction*/
usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
/* USB device in transaction*/
usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
/* USB device enum error handle*/
void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req);
#endif /* USBD_STD_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_ctrl.h
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/*!
\file usbh_ctrl.h
\brief header file for usbh_ctrl.c
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBH_CTRL_H
#define USBH_CTRL_H
#include "usbh_core.h"
#include "usbh_usr.h"
#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */
extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE];
extern uint8_t ctrl_polling_handle_flag;
/* the enum of CTRL event */
typedef enum
{
CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
CTRL_EVENT_SETUP, /* the ctrl setup event */
CTRL_EVENT_DATA, /* the ctrl data event */
CTRL_EVENT_STATUS, /* the ctrl status event */
CTRL_EVENT_COMPLETE, /* the ctrl complete event */
CTRL_EVENT_ERROR, /* the ctrl error event */
CTRL_EVENT_STALLED, /* the ctrl stalled event */
}ctrl_event_enum;
/* function declarations */
/* the polling function of control transfer state handle */
usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
/* send datas from the host channel */
usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len);
/* send the setup packet to the device */
usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num);
/* this function prepare a hc and start a transfer */
uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num);
#endif /* USBH_CTRL_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_hcs.h
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/*!
\file usbh_hcs.h
\brief header file for usbh_hcs.c
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBH_HCS_H
#define USBH_HCS_H
#include "usbh_core.h"
#define HC_MAX 8U
#define HC_OK 0x0000U
#define HC_USED 0x8000U
#define HC_ERROR 0xFFFFU
#define HC_USED_MASK 0x7FFFU
/* function declarations */
/* allocate a new channel for the pipe */
uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr);
/* free all usb host channel */
uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev);
/* free the usb host channel */
uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index);
/* open a channel */
uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
uint8_t channel_num,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t ep_type,
uint16_t ep_mps);
/* modify a channel */
uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
uint8_t channel_num,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t ep_type,
uint16_t ep_mps);
#endif /* USBH_HCS_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_int.h
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/*!
\file usbh_int.h
\brief USB host mode interrupt handler header file
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.1, firmware for GD32F4xx
*/
#ifndef USBH_INT_H
#define USBH_INT_H
#include "usb_core.h"
typedef struct
{
uint8_t (*sof) (usb_core_handle_struct *pudev);
uint8_t (*device_connected) (usb_core_handle_struct *pudev);
uint8_t (*device_disconnected) (usb_core_handle_struct *pudev);
}usbh_hcd_int_cb_struct;
extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops;
/* function declarations */
/* handle global host interrupt */
uint32_t usbh_isr (usb_core_handle_struct *pudev);
#endif /* USBH_INT_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h
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/*!
\file usbh_std.h
\brief header file for usbh_std.c
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef USBH_STD_H
#define USBH_STD_H
#include "usbh_core.h"
#include "usbh_usr.h"
/* standard feature selector for clear feature command */
#define FEATURE_SELECTOR_ENDPOINT 0x00U
#define FEATURE_SELECTOR_DEVICE 0x01U
#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */
extern uint8_t usbh_cfg_desc[512];
extern uint8_t enum_polling_handle_flag;
extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE];
typedef enum
{
ENUN_EVENT_IDLE = 0, /* the enum idle event */
ENUM_EVENT_SET_ADDR, /* the enum set address event */
ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
}enum_event_enum;
/* function declarations */
/* the polling function of enumeration state */
usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
/* get descriptor in usb host enumeration stage */
void usbh_enum_desc_get (usb_core_handle_struct *pudev,
usbh_host_struct *puhost,
uint8_t *buf,
uint8_t req_type,
uint16_t value_idx,
uint16_t len);
/* set address in usb host enumeration stage */
void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address);
/* set configuration in usb host enumeration stage */
void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx);
/* parse the device descriptor */
void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len);
/* parse the configuration descriptor */
void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
usb_descriptor_interface_struct *itf_desc,
usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
uint8_t *buf,
uint16_t len);
/* parse the interface descriptor */
void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf);
/* parse the endpoint descriptor */
void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf);
/* parse the string descriptor */
void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
/* get the next descriptor header */
usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr);
#endif /* USBH_STD_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c
+758
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c
+699
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c
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/*!
\file usbh_hcs.c
\brief this file implements functions for opening and closing host channels
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#include "usbh_hcs.h"
static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev);
/*!
\brief open a channel
\param[in] pudev: pointer to usb device
\param[in] channel_num: host channel number which is in (0..7)
\param[in] dev_addr: USB device address allocated to attached device
\param[in] dev_speed: USB device speed (Full speed/Low speed)
\param[in] ep_type: endpoint type (bulk/int/ctl)
\param[in] ep_mps: max packet size
\param[out] none
\retval operation status
*/
uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
uint8_t channel_num,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t ep_type,
uint16_t ep_mps)
{
usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
uint16_t channel_info = puhc->info;
puhc->endp_id = (uint8_t)channel_info & 0x7FU;
puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
puhc->endp_type = ep_type;
puhc->endp_mps = ep_mps;
puhc->dev_addr = dev_addr;
puhc->dev_speed = dev_speed;
puhc->data_tg_in = 0U;
puhc->data_tg_out = 0U;
if (HPRT_PRTSPD_HIGH_SPEED == dev_speed) {
puhc->do_ping = 1U;
}
usb_hostchannel_init(pudev, channel_num);
return (uint8_t)HC_OK;
}
/*!
\brief modify a channel
\param[in] pudev: pointer to usb device
\param[in] channel_num: host channel number which is in (0..7)
\param[in] dev_addr: USB Device address allocated to attached device
\param[in] dev_speed: USB device speed (Full speed/Low speed)
\param[in] ep_type: endpoint type (bulk/int/ctl)
\param[in] ep_mps: max packet size
\param[out] none
\retval operation status
*/
uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
uint8_t channel_num,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t ep_type,
uint16_t ep_mps)
{
usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
if (0U != dev_addr) {
puhc->dev_addr = dev_addr;
}
if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
puhc->endp_mps = ep_mps;
}
if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
puhc->dev_speed = dev_speed;
}
usb_hostchannel_init(pudev, channel_num);
return (uint8_t)HC_OK;
}
/*!
\brief allocate a new channel for the pipe
\param[in] pudev: pointer to usb device
\param[in] ep_addr: endpoint for which the channel to be allocated
\param[out] none
\retval host channel number
*/
uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
{
uint16_t hc_num = usbh_freechannel_get(pudev);
if ((uint16_t)HC_ERROR != hc_num) {
pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
}
return (uint8_t)hc_num;
}
/*!
\brief free the usb host channel
\param[in] pudev: pointer to usb device
\param[in] index: channel number to be freed which is in (0..7)
\param[out] none
\retval host operation status
*/
uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
{
if (index < HC_MAX) {
pudev->host.host_channel[index].info &= HC_USED_MASK;
}
return USBH_OK;
}
/*!
\brief free all usb host channel
\param[in] pudev: pointer to usb device
\param[out] none
\retval host operation status
*/
uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
{
uint8_t index;
for (index = 2U; index < HC_MAX; index ++) {
pudev->host.host_channel[index].info = 0U;
}
return USBH_OK;
}
/*!
\brief get a free channel number for allocation to a device endpoint
\param[in] pudev: pointer to usb device
\param[out] none
\retval free channel number
*/
static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev)
{
uint8_t index = 0U;
for (index = 0U; index < HC_MAX; index++) {
if (0U == (pudev->host.host_channel[index].info & HC_USED)) {
return (uint16_t)index;
}
}
return HC_ERROR;
}
bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c
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bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c
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bsp/gd32450z-eval/Libraries/SConscript
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('GD32F4xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
print '================================================='
print 'Not support gcc yet!'
print '================================================='
exit(0)
elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [cwd + '/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
path = [
cwd + '/CMSIS/GD/GD32F4xx/Include',
cwd + '/CMSIS',
cwd + '/GD32F4xx_standard_peripheral/Include',]
if GetDepend(['RT_USING_BSP_USB']):
path += [cwd + '/GD32F4xx_usb_driver/Include']
src += [cwd + '/GD32F4xx_usb_driver/Source']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F4XX']
group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/gd32450z-eval/SConscript
+14
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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/gd32450z-eval/SConstruct
+39
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@@ -0,0 +1,39 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print 'Cannot found RT-Thread root directory, please check RTT_ROOT'
print RTT_ROOT
exit(-1)
TARGET = 'rtthread-gd32f4xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
bsp/gd32450z-eval/applications/SConscript
+11
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@@ -0,0 +1,11 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/gd32450z-eval/applications/application.c
+83
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@@ -0,0 +1,83 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2014-04-27 Bernard make code cleanup.
*/
#include <board.h>
#include <rtthread.h>
#include <finsh.h>
#ifdef RT_USING_GUIENGINE
#include "rtgui_demo.h"
#include <rtgui/driver.h>
#endif
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs_init.h>
/* dfs filesystem:ELM filesystem init */
#include <dfs_elm.h>
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#include <dfs_posix.h>
#endif
#include <gd32f4xx.h>
void rt_init_thread_entry(void* parameter)
{
/* initialization RT-Thread Components */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_init();
#endif
#ifdef RT_USING_GUIENGINE
{
rt_device_t device;
device = rt_device_find("lcd");
/* re-set graphic device */
rtgui_graphic_set_device(device);
rt_gui_demo_init();
}
#endif
#ifdef RT_USING_DFS
#ifdef RT_USING_DFS_ELMFAT
/* mount sd card fat partition 0 as root directory */
if (dfs_mount("gd25q16", "/", "elm", 0, 0) == 0)
{
rt_kprintf("spi flash mount to / !\n");
}
else
{
rt_kprintf("spi flash mount to / failed!\n");
}
#endif /* RT_USING_DFS_ELMFAT */
#endif /* DFS */
}
int rt_application_init()
{
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
bsp/gd32450z-eval/applications/rtgui_demo.c
+127
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@@ -0,0 +1,127 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <finsh.h>
#include "rtgui_demo.h"
#define DEBUG
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#endif
#ifdef RT_USING_GUIENGINE
#include <rtgui/rtgui.h>
#include <rtgui/rtgui_system.h>
#include <rtgui/rtgui_app.h>
#include <rtgui/widgets/window.h>
#include <rtgui/dc.h>
#include <rtgui/dc_hw.h>
struct rtgui_win *main_win;
rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event);
static void rt_gui_demo_entry(void *parameter)
{
struct rtgui_app *app;
//struct rtgui_dc *dc;
DEBUG_PRINTF("gui demo entry\n");
/* create gui app */
app = rtgui_app_create("gui_demo");
if (app == RT_NULL)
{
DEBUG_PRINTF("rtgui_app_create faild\n");
return;
}
/* create main window */
main_win = rtgui_mainwin_create(RT_NULL,
"UiWindow", RTGUI_WIN_STYLE_NO_TITLE | RTGUI_WIN_STYLE_NO_BORDER);
if (main_win == RT_NULL)
{
DEBUG_PRINTF("main_win is null\n");
rtgui_app_destroy(app);
return;
}
rtgui_object_set_event_handler(RTGUI_OBJECT(main_win), dc_event_handler);
DEBUG_PRINTF("rtgui_win_show\n");
rtgui_win_show(main_win, RT_FALSE);
DEBUG_PRINTF("rtgui_app_run\n");
rtgui_app_run(app);
DEBUG_PRINTF("rtgui_win_destroy\n");
rtgui_win_destroy(main_win);
DEBUG_PRINTF("rtgui_app_destroy\n");
rtgui_app_destroy(app);
}
rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event)
{
struct rtgui_widget *widget = RTGUI_WIDGET(object);
if (event->type == RTGUI_EVENT_PAINT)
{
struct rtgui_dc *dc;
rtgui_rect_t rect;
rt_kprintf("\r\n RTGUI_EVENT_PAINT \r\n");
rtgui_win_event_handler(RTGUI_OBJECT(widget), event);
rtgui_widget_get_rect(widget, &rect);
DEBUG_PRINTF("widget react x1: %d, y1: %d, x2: %d, y2: %d\r\n",
rect.x1, rect.y1, rect.x2, rect.y2);
dc = rtgui_dc_begin_drawing(widget);
if(dc == RT_NULL)
{
DEBUG_PRINTF("\r\n dc is null \r\n");
return RT_FALSE;
}
rtgui_dc_draw_line(dc, rect.x1, rect.y1, rect.x2, rect.y2);
rtgui_dc_draw_line(dc, rect.x1, rect.y2, rect.x2, rect.y1);
rect.x1 += (rect.x2 - rect.x1) / 2;
rect.y1 += (rect.y2 - rect.y1) / 2;
rtgui_dc_draw_text_stroke(dc, __DATE__"--"__TIME__, &rect, HIGH_LIGHT, BLUE);
rtgui_dc_end_drawing(dc);
}
return RT_FALSE;
}
int rt_gui_demo_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("mygui",
rt_gui_demo_entry, RT_NULL,
2048, 25, 10);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
#endif /* RT_USING_GUIENGINE */
bsp/gd32450z-eval/applications/rtgui_demo.h
+20
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@@ -0,0 +1,20 @@
/*
* File : dc.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-06-02 tanek first version
*/
#ifndef __APP_GUI_DEMO_H__
#define __APP_GUI_DEMO_H__
extern int rt_gui_demo_init(void);
#endif
bsp/gd32450z-eval/applications/startup.c
+107
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@@ -0,0 +1,107 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include <gd32f4xx.h>
#include "board.h"
/**
* @addtogroup GD32F4xx
*/
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
/*******************************************************************************
* Function Name : assert_failed
* Description : Reports the name of the source file and the source line number
* where the assert error has occurred.
* Input : - file: pointer to the source file name
* - line: assert error line source number
* Output : None
* Return : None
*******************************************************************************/
void assert_failed(uint8_t* file, uint32_t line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
}
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_EXT_SDRAM
rt_system_heap_init((void*)EXT_SDRAM_BEGIN, (void*)EXT_SDRAM_END);
#else
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
/*@}*/
bsp/gd32450z-eval/drivers/SConscript
+33
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@@ -0,0 +1,33 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drivers.
src = Split("""
board.c
drv_exmc_sdram.c
drv_usart.c
""")
CPPPATH = [cwd]
# add Ethernet drivers.
if GetDepend('RT_USING_LWIP'):
src += ['drv_enet.c', 'synopsys_emac.c']
# add lcd drivers.
if GetDepend('RT_USING_GUIENGINE'):
src += ['drv_lcd.c', 'gd32f450z_lcd_eval.c']
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
src += ['drv_spi_flash.c', 'drv_spi.c']
elif GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/gd32450z-eval/drivers/board.c
+87
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@@ -0,0 +1,87 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include <gd32f4xx.h>
#include <board.h>
#include <drv_usart.h>
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler */
}
/** System Clock Configuration
*/
void SystemClock_Config(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x08000000 */
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
#endif
SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(CONSOLE_DEVICE);
#endif
}
/*@}*/
bsp/gd32450z-eval/drivers/board.h
+84
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@@ -0,0 +1,84 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include <gd32f4xx.h>
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
#else
#define GD32_SRAM_SIZE 128
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END GD32_SRAM_END
// <o> Console on USART:
// <127=> no console
// <0=>USART 0 <1=>USART 1 <2=>USART 2 <3=> USART 3
// <4=>USART 4 <5=>USART 5 <6=>USART 6 <7=> USART 7
// <i>Default: 1
#define GD32_CONSOLE_USART 0
void rt_hw_board_init(void);
#if GD32_CONSOLE_USART == 127
#define CONSOLE_DEVICE "no"
#elif GD32_CONSOLE_USART == 0
#define CONSOLE_DEVICE "uart0"
#elif GD32_CONSOLE_USART == 1
#define CONSOLE_DEVICE "uart1"
#elif GD32_CONSOLE_USART == 2
#define CONSOLE_DEVICE "uart2"
#elif GD32_CONSOLE_USART == 3
#define CONSOLE_DEVICE "uart3"
#elif GD32_CONSOLE_USART == 4
#define CONSOLE_DEVICE "uart4"
#elif GD32_CONSOLE_USART == 5
#define CONSOLE_DEVICE "uart5"
#elif GD32_CONSOLE_USART == 6
#define CONSOLE_DEVICE "uart6"
#elif GD32_CONSOLE_USART == 7
#define CONSOLE_DEVICE "uart7"
#endif
#define FINSH_DEVICE_NAME CONSOLE_DEVICE
void Error_Handler(void);
#endif
//*** <<< end of configuration section >>> ***
bsp/gd32450z-eval/drivers/drv_enet.c
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