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delete essemi bsp es32f0334 (libraries)

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liuhy
2021-09-10 18:04:14 +08:00
parent aa55441a03
commit 7d5a97e3ea
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bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h
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bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s
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;*******************************************************************************
; file : startup_es32f033x.s
; description: es32f033x Device Startup File
; author : AE Team
; data : 10 Dec 2018
; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
;*******************************************************************************
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ;0, load top of stack
DCD Reset_Handler ;1, reset handler
DCD NMI_Handler ;2, nmi handler
DCD HardFault_Handler ;3, hard fault handler
DCD 0 ;4, MPU Fault Handler
DCD 0 ;5, Bus Fault Handler
DCD 0 ;6, Usage Fault Handler
DCD 0 ;7, Reserved
DCD 0 ;8, Reserved
DCD 0 ;9, Reserved
DCD 0 ;10, Reserved
DCD SVC_Handler ;11, svcall handler
DCD DebugMon_Handler ;12, Debug Monitor Handler
DCD 0 ;13, Reserved
DCD PendSV_Handler ;14, pendsv handler
DCD SysTick_Handler ;15, systick handler
DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler
DCD LVD_Handler ;17, irq1 LVD handler
DCD RTC_TEMP_Handler ;18, irq2 RTC handler
DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler
DCD CMU_Handler ;20, irq4 CMU handler
DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler
DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler
DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler
DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler
DCD DMA_Handler ;25, irq9 DMA handler
DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler
DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler
DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler
DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler
DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler
DCD BS16T0_Handler ;31, irq15 BS16T0 handler
DCD 0 ;32, irq16 Reserved
DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler
DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler
DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler
DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler
DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler
DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler
DCD I2C0_Handler ;39, irq23 I2C0 handler
DCD I2C1_Handler ;40, irq24 I2C1 handler
DCD SPI0_Handler ;41, irq25 SPI0 handler
DCD SPI1_Handler ;42, irq26 SPI1 handler
DCD UART0_Handler ;43, irq27 UART0 handler
DCD UART1_Handler ;44, irq28 UART1 handler
DCD USART0_Handler ;45, irq29 USART0 handler
DCD USART1_Handler ;46, irq30 USART1 handler
DCD LPUART0_Handler ;47, irq31 LPUART0 handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IWDG_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IWDG_Handler
B WWDG_IWDG_Handler
PUBWEAK LVD_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_Handler
B LVD_Handler
PUBWEAK RTC_TEMP_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TEMP_Handler
B RTC_TEMP_Handler
PUBWEAK CRYPT_TRNG_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYPT_TRNG_Handler
B CRYPT_TRNG_Handler
PUBWEAK CMU_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
CMU_Handler
B CMU_Handler
PUBWEAK EXTI0_3_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_3_Handler
B EXTI0_3_Handler
PUBWEAK EXTI4_7_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_7_Handler
B EXTI4_7_Handler
PUBWEAK EXTI8_11_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI8_11_Handler
B EXTI8_11_Handler
PUBWEAK EXTI12_15_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI12_15_Handler
B EXTI12_15_Handler
PUBWEAK DMA_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA_Handler
B DMA_Handler
PUBWEAK CAN0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN0_Handler
B CAN0_Handler
PUBWEAK LPTIM0_SPI2_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM0_SPI2_Handler
B LPTIM0_SPI2_Handler
PUBWEAK ADC_ACMP_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_ACMP_Handler
B ADC_ACMP_Handler
PUBWEAK AD16C4T0_BRK_UP_TRIG_COM_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
AD16C4T0_BRK_UP_TRIG_COM_Handler
B AD16C4T0_BRK_UP_TRIG_COM_Handler
PUBWEAK AD16C4T0_CC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
AD16C4T0_CC_Handler
B AD16C4T0_CC_Handler
PUBWEAK BS16T0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BS16T0_Handler
B BS16T0_Handler
PUBWEAK GP16C2T0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
GP16C2T0_Handler
B GP16C2T0_Handler
PUBWEAK GP16C2T1_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
GP16C2T1_Handler
B GP16C2T1_Handler
PUBWEAK BS16T1_UART2_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BS16T1_UART2_Handler
B BS16T1_UART2_Handler
PUBWEAK BS16T2_UART3_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BS16T2_UART3_Handler
B BS16T2_UART3_Handler
PUBWEAK GP16C4T0_LCD_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
GP16C4T0_LCD_Handler
B GP16C4T0_LCD_Handler
PUBWEAK BS16T3_DAC0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BS16T3_DAC0_Handler
B BS16T3_DAC0_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK I2C1_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_Handler
B I2C1_Handler
PUBWEAK SPI0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_Handler
B SPI0_Handler
PUBWEAK SPI1_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_Handler
B SPI1_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UART0_Handler
B UART0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UART1_Handler
B UART1_Handler
PUBWEAK USART0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_Handler
B USART0_Handler
PUBWEAK USART1_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_Handler
B USART1_Handler
PUBWEAK LPUART0_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART0_Handler
B LPUART0_Handler
END
bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s
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;*******************************************************************************
; file : startup_es32f033x.s
; description: es32f033x Device Startup File
; author : AE Team
; data : 29 Aug 2017
; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
;*******************************************************************************
;Stack Configuration------------------------------------------------------------
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
;-------------------------------------------------------------------------------
;Heap Configuration-------------------------------------------------------------
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
;-------------------------------------------------------------------------------
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset-------------------------------------
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ;0, load top of stack
DCD Reset_Handler ;1, reset handler
DCD NMI_Handler ;2, nmi handler
DCD HardFault_Handler ;3, hard fault handler
DCD 0 ;4, MPU Fault Handler
DCD 0 ;5, Bus Fault Handler
DCD 0 ;6, Usage Fault Handler
DCD 0 ;7, Reserved
DCD 0 ;8, Reserved
DCD 0 ;9, Reserved
DCD 0 ;10, Reserved
DCD SVC_Handler ;11, svcall handler
DCD DebugMon_Handler ;12, Debug Monitor Handler
DCD 0 ;13, Reserved
DCD PendSV_Handler ;14, pendsv handler
DCD SysTick_Handler ;15, systick handler
DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler
DCD LVD_Handler ;17, irq1 LVD handler
DCD RTC_TEMP_Handler ;18, irq2 RTC handler
DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler
DCD CMU_Handler ;20, irq4 CMU handler
DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler
DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler
DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler
DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler
DCD DMA_Handler ;25, irq9 DMA handler
DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler
DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler
DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler
DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler
DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler
DCD BS16T0_Handler ;31, irq15 BS16T0 handler
DCD 0 ;32, irq16 Reserved
DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler
DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler
DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler
DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler
DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler
DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler
DCD I2C0_Handler ;39, irq23 I2C0 handler
DCD I2C1_Handler ;40, irq24 I2C1 handler
DCD SPI0_Handler ;41, irq25 SPI0 handler
DCD SPI1_Handler ;42, irq26 SPI1 handler
DCD UART0_Handler ;43, irq27 UART0 handler
DCD UART1_Handler ;44, irq28 UART1 handler
DCD USART0_Handler ;45, irq29 USART0 handler
DCD USART1_Handler ;46, irq30 USART1 handler
DCD LPUART0_Handler ;47, irq31 LPUART0 handler
;-------------------------------------------------------------------------------
AREA INT, CODE, READONLY ;code begin
;Reset Handler----------------------------------------------
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
NOP
ALIGN
ENDP
;system int-------------------------------------------------
NMI_Handler PROC ;int 2
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler \
PROC ;int3
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler \
PROC ;int11
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler \
PROC ;int12
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC ;int14
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler \
PROC ;int15
EXPORT SysTick_Handler [WEAK]
B .
ENDP
;peripheral module int -----------------------------------------------
WWDG_IWDG_Handler \
PROC ;int16
EXPORT WWDG_IWDG_Handler [WEAK]
B .
ENDP
LVD_Handler \
PROC ;int17
EXPORT LVD_Handler [WEAK]
B .
ENDP
RTC_TEMP_Handler \
PROC ;int18
EXPORT RTC_TEMP_Handler [WEAK]
B .
ENDP
CRYPT_TRNG_Handler \
PROC ;int19
EXPORT CRYPT_TRNG_Handler [WEAK]
B .
ENDP
CMU_Handler \
PROC ;int20
EXPORT CMU_Handler [WEAK]
B .
ENDP
EXTI0_3_Handler \
PROC ;int21
EXPORT EXTI0_3_Handler [WEAK]
B .
ENDP
EXTI4_7_Handler \
PROC ;int22
EXPORT EXTI4_7_Handler [WEAK]
B .
ENDP
EXTI8_11_Handler \
PROC ;int23
EXPORT EXTI8_11_Handler [WEAK]
B .
ENDP
EXTI12_15_Handler \
PROC ;int24
EXPORT EXTI12_15_Handler [WEAK]
B .
ENDP
DMA_Handler \
PROC ;int25
EXPORT DMA_Handler [WEAK]
B .
ENDP
CAN0_Handler \
PROC ;int26
EXPORT CAN0_Handler [WEAK]
B .
ENDP
LPTIM0_SPI2_Handler \
PROC ;int27
EXPORT LPTIM0_SPI2_Handler [WEAK]
B .
ENDP
ADC_ACMP_Handler \
PROC ;int28
EXPORT ADC_ACMP_Handler [WEAK]
B .
ENDP
AD16C4T0_BRK_UP_TRIG_COM_Handler \
PROC ;int29
EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK]
B .
ENDP
AD16C4T0_CC_Handler \
PROC ;int30
EXPORT AD16C4T0_CC_Handler [WEAK]
B .
ENDP
BS16T0_Handler \
PROC ;int31
EXPORT BS16T0_Handler [WEAK]
B .
ENDP
GP16C2T0_Handler PROC ;int33
EXPORT GP16C2T0_Handler [WEAK]
B .
ENDP
GP16C2T1_Handler PROC ;int34
EXPORT GP16C2T1_Handler [WEAK]
B .
ENDP
BS16T1_UART2_Handler \
PROC ;int35
EXPORT BS16T1_UART2_Handler [WEAK]
B .
ENDP
BS16T2_UART3_Handler \
PROC ;int36
EXPORT BS16T2_UART3_Handler [WEAK]
B .
ENDP
GP16C4T0_LCD_Handler \
PROC ;int37
EXPORT GP16C4T0_LCD_Handler [WEAK]
B .
ENDP
BS16T3_DAC0_Handler \
PROC ;int38
EXPORT BS16T3_DAC0_Handler [WEAK]
B .
ENDP
I2C0_Handler \
PROC ;int39
EXPORT I2C0_Handler [WEAK]
B .
ENDP
I2C1_Handler \
PROC ;int40
EXPORT I2C1_Handler [WEAK]
B .
ENDP
SPI0_Handler \
PROC ;int41
EXPORT SPI0_Handler [WEAK]
B .
ENDP
SPI1_Handler \
PROC ;int42
EXPORT SPI1_Handler [WEAK]
B .
ENDP
UART0_Handler \
PROC ;int43
EXPORT UART0_Handler [WEAK]
B .
ENDP
UART1_Handler \
PROC ;int44
EXPORT UART1_Handler [WEAK]
B .
ENDP
USART0_Handler \
PROC ;int45
EXPORT USART0_Handler [WEAK]
B .
ENDP
USART1_Handler \
PROC ;int46
EXPORT USART1_Handler [WEAK]
B .
ENDP
LPUART0_Handler \
PROC ;int47
EXPORT LPUART0_Handler [WEAK]
B .
ENDP
; User Initial Stack & Heap-----------------------------------------------------
ALIGN
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c
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/**
*********************************************************************************
*
* @file system_es32f033x.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer
*
* @version V1.0
* @date 6 Dec 2018
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "utils.h"
/**
* @brief Configuring system clock before startup.
* @note This function must be used after reset.
* @retval None
*/
void system_init (void)
{
/* do nothing */
}
bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif
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bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmFunc.h
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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmInstr.h
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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmSimd.h
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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */
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/**
*********************************************************************************
*
* @file ald_acmp.h
* @brief Header file of ACMP module driver.
*
* @version V1.0
* @date 13 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_ACMP_H__
#define __ALD_ACMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup ACMP
* @{
*/
/** @defgroup ACMP_Public_Types ACMP Public Types
* @{
*/
/**
* @brief Acmp interrupt
*/
typedef enum {
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
} acmp_it_t;
/**
* @brief Acmp interrupt
*/
typedef enum {
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_flag_t;
/**
* @brief Acmp interrupt flag
*/
typedef enum {
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_status_t;
/**
* @brief Acmp positive input
*/
typedef enum {
ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */
} acmp_pos_input_t;
/**
* @brief Acmp negative input
*/
typedef enum {
ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10U, /**< VDD as negative input */
} acmp_neg_input_t;
/**
* @brief Acmp mode
*/
typedef enum {
ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */
ACMP_LOW_POWER = 1U, /**< Low power mode */
ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */
ACMP_HIGH_POWER = 3U, /**< High power mode */
} acmp_mode_t;
/**
* @brief Acmp warm-up time
*/
typedef enum {
ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */
} acmp_warm_time_t;
/**
* @brief Acmp hysteresis level
*/
typedef enum {
ACMP_HYST_0 = 0U, /**< No hysteresis */
ACMP_HYST_15 = 1U, /**< 15mV hysteresis */
ACMP_HYST_22 = 2U, /**< 22mV hysteresis */
ACMP_HYST_29 = 3U, /**< 29mV hysteresis */
ACMP_HYST_36 = 4U, /**< 36mV hysteresis */
ACMP_HYST_43 = 5U, /**< 43mV hysteresis */
ACMP_HYST_50 = 6U, /**< 50mV hysteresis */
ACMP_HYST_57 = 7U, /**< 57mV hysteresis */
} acmp_hystsel_t;
/**
* @brief Acmp inactive state
*/
typedef enum {
ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */
} acmp_inactval_t;
/**
* @brief which edges set up interrupt
*/
typedef enum {
ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */
} acmp_edge_t;
/**
* @brief Acmp output function
*/
typedef enum {
ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */
} acmp_out_func_t;
/**
* @brief Acmp warm-up interrupt function
*/
typedef enum {
ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */
} acmp_warm_it_func;
/**
* @brief Acmp gpio output invert
*/
typedef enum {
ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */
} acmp_invert_t;
/**
* @brief Acmp output config structure definition
*/
typedef struct {
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
} acmp_output_config_t;
/**
* @brief Acmp init structure definition
*/
typedef struct {
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */
acmp_pos_input_t pos_port; /**< Acmp positive port select */
acmp_neg_input_t neg_port; /**< Acmp negative port select */
acmp_inactval_t inactval; /**< Acmp inavtive output value */
acmp_edge_t edge; /** Select edges to set interrupt flag */
uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */
} acmp_init_t;
/**
* @brief ACMP Handle Structure definition
*/
typedef struct acmp_handle_s {
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */
void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */
} acmp_handle_t;
/**
* @}
*/
/** @defgroup ACMP_Public_Macros ACMP Public Macros
* @{
*/
#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
/**
* @}
*/
/** @defgroup ACMP_Private_Macros ACMP Private Macros
* @{
*/
#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \
((x) == ACMP1))
#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \
((x) == ACMP_IT_WARMUP))
#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \
((x) == ACMP_FLAG_WARMUP))
#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \
((x) == ACMP_STATUS_WARMUP))
#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD))
#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \
((x) == ACMP_INACTVAL_HIGH))
#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \
((x) == ACMP_OUT_ENABLE))
#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \
((x) == ACMP_GPIO_INV))
#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \
((x) == ACMP_WARM_ENABLE))
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions
* @{
*/
/** @addtogroup ACMP_Public_Functions_Group1
* @{
*/
ald_status_t ald_acmp_init(acmp_handle_t *hperh);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group2
* @{
*/
ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
ald_status_t ald_acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it);
it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it);
it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group3
* @{
*/
void ald_acmp_irq_handler(acmp_handle_t *hperh);
ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config);
uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
extern "C" }
#endif
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
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/**
*********************************************************************************
*
* @file ald_bkpc.h
* @brief Header file of BKPC module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_BKPC_H__
#define __ALD_BKPC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup BKPC
* @{
*/
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup BKPC_Public_Types BKPC Public Types
* @{
*/
/**
* @brief BKPC ldo output select
*/
typedef enum {
BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief Standby wakeup port select
*/
typedef enum {
PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */
PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */
PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */
PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */
PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */
} bkpc_wakeup_port_t;
/**
* @brief Standby wakeup level
*/
typedef enum {
PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */
PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */
} bkpc_wakeup_level_t;
/**
* @}
*/
/**
* @defgroup BKPC_Private_Macros BKPC Private Macros
* @{
*/
#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_NONE))
#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \
((x) == PMU_STANDBY_LEVEL_LOW))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions
* @{
*/
/** @addtogroup BKPC_Public_Functions_Group1
* @{
*/
/* control functions */
extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions_Group2
* @{
*/
/* IO operation functions */
extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value);
extern uint32_t ald_bkpc_read_ram(uint8_t idx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_BKPC_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_calc.h
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/**
*********************************************************************************
*
* @file ald_calc.h
* @brief Header file of CALC module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_CALC_H__
#define __ALD_CALC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CALC
* @{
*/
/** @addtogroup CALC_Public_Functions
* @{
*/
extern uint32_t ald_calc_sqrt(uint32_t data);
extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
extern flag_status_t ald_calc_get_dz_status(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CALC_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_conf.h
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/**
*********************************************************************************
*
* @file ald_conf.h
* @brief Enable/Disable the peripheral module.
*
* @version V1.0
* @date 18 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CONF_H__
#define __ALD_CONF_H__
#define ALD_DMA
#define ALD_GPIO
#define ALD_UART
#define ALD_LPUART
#define ALD_USART
#define ALD_SMARTCARD /* The ALD_SMARTCARD depend on ALD_USART */
#define ALD_I2C
#define ALD_CMU
#define ALD_RMU
#define ALD_PMU
#define ALD_WDT
#define ALD_LCD
#define ALD_RTC
#define ALD_CAN
#define ALD_FLASH
#define ALD_ADC
#define ALD_CRC
#define ALD_CRYPT
#define ALD_TIMER
#define ALD_LPTIM
#define ALD_PIS
#define ALD_SPI
#define ALD_CALC
#define ALD_ACMP
#define ALD_OPAMP
#define ALD_TRNG
#define ALD_TEMP
#define ALD_BKPC
#define ALD_DAC
#define ALD_IAP
#define TICK_INT_PRIORITY 3
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h
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/**
*********************************************************************************
*
* @file ald_crc.h
* @brief Header file of CRC module driver.
*
* @version V1.0
* @date 6 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRC_H__
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Public_Types CRC Public Types
* @{
*/
/**
* @brief CRC mode
*/
typedef enum {
CRC_MODE_CCITT = 0U, /**< Ccitt */
CRC_MODE_8 = 1U, /**< Crc8 */
CRC_MODE_16 = 2U, /**< Crc16 */
CRC_MODE_32 = 3U, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum {
CRC_LEN_AUTO = 0U, /**< Auto */
CRC_DATASIZE_8 = 1U, /**< Byte */
CRC_DATASIZE_16 = 2U, /**< Half word */
CRC_DATASIZE_32 = 3U, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum {
CRC_WERR_NO = 0U, /**< No error */
CRC_WERR_ERR = 1U, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum {
CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4U, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct {
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
} crc_init_t;
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s {
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
#ifdef ALD_DMA
dma_handle_t hdma; /**< CRC DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
} crc_handle_t;
/**
* @}
*/
/** @defgroup CRC_Public_Macros CRC Public Macros
* @{
*/
#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
/**
* @}
*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_CRC(x) ((x) == CRC)
#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
/**
* @}
*/
/** @addtogroup CRC_Public_Functions
* @{
*/
/** @addtogroup CRC_Public_Functions_Group1
* @{
*/
ald_status_t ald_crc_init(crc_handle_t *hperh);
void ald_crc_reset(crc_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRC_Public_Functions_Group2
* @{
*/
uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size);
uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size);
/**
* @}
*/
#ifdef ALD_DMA
/** @addtogroup CRC_Public_Functions_Group3
* @{
*/
ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t ald_crc_dma_pause(crc_handle_t *hperh);
ald_status_t ald_crc_dma_resume(crc_handle_t *hperh);
ald_status_t ald_crc_dma_stop(crc_handle_t *hperh);
/**
* @}
*/
#endif
/** @addtogroup CRC_Public_Functions_Group4
* @{
*/
crc_state_t ald_crc_get_state(crc_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CRC_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h
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/**
*********************************************************************************
*
* @file ald_crypt.h
* @brief Header file of CRYPT module driver.
*
* @version V1.0
* @date 7 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRYPT_H__
#define __ALD_CRYPT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRYPT
* @{
*/
/** @defgroup CRYPT_Public_Types CRYPT Public Types
* @{
*/
/**
* @brief CRYPT encrypt or decrypt select
*/
typedef enum {
CRYPT_DECRYPT = 0U, /**< Decrypt */
CRYPT_ENCRYPT = 1U, /**< Encrypt */
} crypt_encs_t;
/**
* @brief CRYPT mode select
*/
typedef enum {
CRYPT_MODE_ECB = 0U, /**< ECB */
CRYPT_MODE_CBC = 1U, /**< CBC */
CRYPT_MODE_CTR = 2U, /**< CTR */
} crypt_mode_t;
/**
* @brief CRYPT data type
*/
typedef enum {
CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */
} crypt_datatype_t;
/**
* @brief CRYPT interrupt
*/
typedef enum {
CRYPT_IT_IT = 0x80U, /**< Interrupt */
} crypt_it_t;
/**
* @brief CRYPT interrupt flag
*/
typedef enum {
CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */
} crypt_flag_t;
/**
* @brief CRYPT state structures definition
*/
typedef enum {
CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4U, /**< Error */
} crypt_state_t;
/**
* @brief CRYPT data type
*/
typedef enum {
DATA_32_BIT = 0U, /**< 32 bit data,don't swap */
DATA_16_BIT = 1U, /**< 16 bit data,swap */
DATA_8_BIT = 2U, /**< 8 bit data,swap */
DATA_1_BIT = 3U, /**< 1 bit data, swap */
} crypt_data_t;
/**
* @brief CRYPT init structure definition
*/
typedef struct {
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
} crypt_init_t;
/**
* @brief CRYPT Handle Structure definition
*/
typedef struct crypt_handle_s {
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
#ifdef ALD_DMA
dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */
dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */
#endif
uint8_t *plain_text; /**< Pointer to plain text */
uint8_t *cipher_text; /**< Pointer to cipher text */
uint32_t size; /**< The size of crypt data buf */
uint32_t count; /**< The count of crypt data buf */
uint32_t step; /**< The step of once crypt 4(aes) */
uint32_t dir; /**< ENCRYPT or DECRYPT */
uint32_t iv[4]; /**< The iv of crypt */
uint32_t key[4]; /**< The key of crypt */
lock_state_t lock; /**< Locking object */
crypt_state_t state; /**< CRYPT operation state */
void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */
void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */
} crypt_handle_t;
/**
* @}
*/
/** @defgroup CRYPT_Public_Macros CRYPT Public Macros
* @{
*/
#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
/**
* @}
*/
/** @defgroup CRYPT_Private_Macros CRYPT Private Macros
* @{
*/
#define IS_CRYPT(x) ((x) == CRYPT)
#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \
((x) == CRYPT_FLAG_DONE))
#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \
((x) == IV_4_LEN))
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions
* @{
*/
/** @addtogroup CRYPT_Public_Functions_Group1
* @{
*/
ald_status_t ald_crypt_init(crypt_handle_t *hperh);
ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv);
ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group2
* @{
*/
ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
#ifdef ALD_DMA
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
#endif
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group3
* @{
*/
#ifdef ALD_DMA
ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh);
ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh);
ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh);
#endif
void ald_crypt_irq_handler(crypt_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group4
* @{
*/
void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group5
* @{
*/
crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h
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@@ -1,156 +0,0 @@
/**
*********************************************************************************
*
* @file ald_dbgc.h
* @brief DEBUGCON module driver.
*
* @version V1.0
* @date 04 Jun 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_DBGC_H__
#define __ALD_DBGC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup DBGC DBGC
* @brief DBGC module driver
* @{
*/
/** @defgroup DBGC_Public_Types DBGC Public Types
* @{
*/
/**
* @brief Debug mode select
*/
typedef enum {
DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */
} dbgc_mode_t;
/**
* @brief Debug peripheral select
*/
typedef enum {
DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1U << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */
DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */
DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */
} dbgc_perh_t;
/**
* @}
*/
/** @defgroup DBGC_Public_Functions DBGC Public Functions
* @{
*/
/**
* @brief Gets version.
* @retval Version
*/
__INLINE uint32_t ald_dbgc_get_rev_id(void)
{
return (DBGC->IDCODE >> 16);
}
/**
* @brief Gets core id.
* @retval Core id
*/
__INLINE uint32_t ald_dbgc_get_core_id(void)
{
return (DBGC->IDCODE >> 12) & 0xF;
}
/**
* @brief Gets device id
* @retval device id
*/
__INLINE uint32_t ald_dbgc_get_device_id(void)
{
return DBGC->IDCODE & 0xFFF;
}
/**
* @brief Configures low power debug mode
* @param mode: The mode of low power.
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
{
if (state)
SET_BIT(DBGC->CR, mode);
else
CLEAR_BIT(DBGC->CR, mode);
}
/**
* @brief Configures peripheral debug mode
* @param perh: The peripheral.
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
{
if ((perh >> 16) & 0x1) {
if (state)
SET_BIT(DBGC->APB2FZ, perh);
else
CLEAR_BIT(DBGC->APB2FZ, perh);
}
else {
if (state)
SET_BIT(DBGC->APB1FZ, perh);
else
CLEAR_BIT(DBGC->APB1FZ, perh);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h
-421
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@@ -1,421 +0,0 @@
/**
*********************************************************************************
*
* @file ald_dma.h
* @brief DMA module Library.
*
* @version V1.0
* @date 09 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_DMA_H__
#define __ALD_DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup DMA
* @{
*/
/**
* @defgroup DMA_Public_Macros DMA Public Macros
* @{
*/
#define DMA_CH_COUNT 6U
#define DMA_ERR 31U
/**
* @}
*/
/**
* @defgroup DMA_Public_Types DMA Public Types
* @{
*/
/**
* @brief Input source to DMA channel
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum {
DMA_MSEL_NONE = 0x0U, /**< NONE */
DMA_MSEL_GPIO = 0x1U, /**< GPIO */
DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */
DMA_MSEL_ACMP = 0x3U, /**< ACMP */
DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */
DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */
DMA_MSEL_CRC = 0x7U, /**< CRC */
DMA_MSEL_UART0 = 0x8U, /**< UART0 */
DMA_MSEL_UART1 = 0x9U, /**< UART1 */
DMA_MSEL_UART2 = 0xAU, /**< UART2 */
DMA_MSEL_UART3 = 0xBU, /**< UART3 */
DMA_MSEL_USART0 = 0xCU, /**< USART0 */
DMA_MSEL_USART1 = 0xDU, /**< USART1 */
DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */
DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */
DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */
DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */
DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */
DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */
DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */
DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */
DMA_MSEL_RTC = 0x16U, /**< RTC */
DMA_MSEL_LPTIM0 = 0x17U, /**< LPTIM0 */
DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */
DMA_MSEL_DMA = 0x19U, /**< DMA */
DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */
DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */
DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */
DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */
DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */
DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */
DMA_MSEL_PIS = 0x20U, /**< PIS */
DMA_MSEL_TRNG = 0x21U, /**< TRNG */
} dma_msel_t;
/**
* @brief Input signal to DMA channel
*/
typedef enum {
DMA_MSIGSEL_NONE = 0x0U, /**< NONE */
DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */
DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */
DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */
DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */
DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */
DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */
DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */
DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */
DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */
DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */
DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */
DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */
DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */
DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */
DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */
DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */
DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */
DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */
DMA_MSIGSEL_CALC_WRITE = 0x0U, /**< CALC write mode */
DMA_MSIGSEL_CALC_READ = 0x1U, /**< CALC read mode */
DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */
DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */
DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */
DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART transmit */
DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART receive */
DMA_MSIGSEL_USART_RNR = 0x0U, /**< USART reveive */
DMA_MSIGSEL_USART_TXEMPTY = 0x1U, /**< USART transmit */
DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */
DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */
DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */
DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */
DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */
DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */
DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */
DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */
DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */
DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */
DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */
DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */
DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */
DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */
DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */
DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */
DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */
DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */
DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */
DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */
DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */
DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */
DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */
DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */
DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */
DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */
DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */
DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */
DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */
} dma_msigsel_t;
/**
* @brief DMA Descriptor control type
*/
typedef union {
struct {
uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */
uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */
uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */
uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */
uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */
uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */
uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */
uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */
uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */
};
uint32_t word;
} dma_ctrl_t;
/**
* @brief Channel control data structure
*/
typedef struct {
void *src; /**< Source data end pointer */
void *dst; /**< Destination data end pointer */
dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */
uint32_t use; /**< Reserve for user */
} dma_descriptor_t;
/**
* @brief data increment
*/
typedef enum {
DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */
DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */
DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */
DMA_DATA_INC_NONE = 0x3U, /**< No increment */
} dma_data_inc_t;
/**
* @brief Data size
*/
typedef enum {
DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */
DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */
DMA_DATA_SIZE_WORD = 0x2U, /**< Word */
} dma_data_size_t;
/**
* @brief The operating mode of the DMA cycle
*/
typedef enum {
DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */
DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */
DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */
DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */
DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */
DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */
DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */
} dma_cycle_ctrl_t;
/**
* @brief Control how many DMA transfers can occur
* before the controller re-arbitrates
*/
typedef enum {
DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */
DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */
DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */
DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */
DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */
DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */
DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */
DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */
DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */
DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */
DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */
} dma_arbiter_config_t;
/**
* @brief Callback function pointer and param
*/
typedef struct {
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void* arg); /**< DMA occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_call_back_t;
/**
* @brief DMA channal configure structure
*/
typedef struct {
void *src; /**< Source data begin pointer */
void *dst; /**< Destination data begin pointer */
uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */
dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */
dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */
dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */
dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
type_func_t primary; /**< Use primary descriptor or alternate descriptor */
type_func_t burst; /**< Enable/Disable the useburst setting for this channel */
type_func_t high_prio; /**< High priority or default priority */
type_func_t interrupt; /**< Enable/disable interrupt */
dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */
dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */
uint8_t channel; /**< Channel index */
} dma_config_t;
/**
* @brief DMA handle structure definition
*/
typedef struct {
DMA_TypeDef *perh; /**< DMA registers base address */
dma_config_t config; /**< Channel configure structure. @ref dma_config_t */
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_handle_t;
/**
* @brief Descriptor complete state
*/
typedef enum {
DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */
DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */
DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */
} dma_descrp_cplt_t;
/**
* @}
*/
/**
* @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG)
#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \
((x) == DMA_DATA_INC_HALFWORD) || \
((x) == DMA_DATA_INC_WORD) || \
((x) == DMA_DATA_INC_NONE))
#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \
((x) == DMA_DATA_SIZE_HALFWORD) || \
((x) == DMA_DATA_SIZE_WORD))
#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \
((x) == DMA_CYCLE_CTRL_BASIC) || \
((x) == DMA_CYCLE_CTRL_AUTO) || \
((x) == DMA_CYCLE_CTRL_PINGPONG) || \
((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \
((x) == DMA_R_POWER_2) || \
((x) == DMA_R_POWER_4) || \
((x) == DMA_R_POWER_8) || \
((x) == DMA_R_POWER_16) || \
((x) == DMA_R_POWER_32) || \
((x) == DMA_R_POWER_64) || \
((x) == DMA_R_POWER_128) || \
((x) == DMA_R_POWER_256) || \
((x) == DMA_R_POWER_512) || \
((x) == DMA_R_POWER_1024))
#define IS_DMA(x) ((x) == DMA0)
#define IS_DMA_CHANNEL(x) ((x) <= 5)
#define IS_DMA_DATA_SIZE(x) ((x) <= 1024)
#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31))
/**
* @}
*/
/**
* @addtogroup DMA_Public_Functions
* @{
*/
/** @addtogroup DMA_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void ald_dma_reset(DMA_TypeDef *DMAx);
extern void ald_dma_init(DMA_TypeDef *DMAx);
extern void ald_dma_config_struct(dma_config_t *p);
extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory);
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group2
* @{
*/
/* Configure DMA channel functions */
extern void ald_dma_config_auto(dma_handle_t *hperh);
extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
uint16_t size, uint8_t channel, void (*cbk)(void *arg));
extern void ald_dma_config_basic(dma_handle_t *hperh);
extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
uint8_t first, void (*cbk)(void *arg));
extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc,
uint32_t nr, uint8_t channel, void (*cbk)(void *arg));
extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group3
* @{
*/
/* DMA control functions */
extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel);
extern void ald_dma_irq_handler(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__ALD_DMA_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h
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/**
*********************************************************************************
*
* @file ald_flash.h
* @brief Header file of FLASH driver
*
* @version V1.0
* @date 20 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_FLASH_H__
#define __ALD_FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup FLASH
* @{
*/
/**
* @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \
} \
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000U
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define INFO_PAGE_SIZE 1024UL
#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#endif
/**
* @}
*/
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum {
FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2U, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */
} flash_cmd_type;
typedef enum {
OP_FLASH = 0U, /**< Operate Pragram area */
OP_INFO = 1U, /**< Operate info area */
} op_cmd_type;
/**
* @}
*/
/** @addtogroup Flash_Private_Functions
* @{
*/
ald_status_t flash_page_erase(uint32_t addr);
ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo);
/**
* @}
*/
/** @addtogroup Flash_Public_Functions
* @{
*/
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
ald_status_t ald_flash_erase(uint32_t addr, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_FLASH_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h
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/**
*********************************************************************************
*
* @file ald_gpio.h
* @brief Header file of GPIO module driver
*
* @version V1.0
* @date 07 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_GPIO_H__
#define __ALD_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup GPIO
* @{
*/
/**
* @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
#define GPIO_PIN_0 (1U << 0)
#define GPIO_PIN_1 (1U << 1)
#define GPIO_PIN_2 (1U << 2)
#define GPIO_PIN_3 (1U << 3)
#define GPIO_PIN_4 (1U << 4)
#define GPIO_PIN_5 (1U << 5)
#define GPIO_PIN_6 (1U << 6)
#define GPIO_PIN_7 (1U << 7)
#define GPIO_PIN_8 (1U << 8)
#define GPIO_PIN_9 (1U << 9)
#define GPIO_PIN_10 (1U << 10)
#define GPIO_PIN_11 (1U << 11)
#define GPIO_PIN_12 (1U << 12)
#define GPIO_PIN_13 (1U << 13)
#define GPIO_PIN_14 (1U << 14)
#define GPIO_PIN_15 (1U << 15)
#define GPIO_PIN_ALL (0xFFFFU)
/**
* @}
*/
/**
* @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @brief GPIO mode
*/
typedef enum {
GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1U, /**< Input */
GPIO_MODE_OUTPUT = 0x2U, /**< Output */
} gpio_mode_t;
/**
* @brief GPIO open-drain or push-pull
*/
typedef enum {
GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */
GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */
} gpio_odos_t;
/**
* @brief GPIO push-up or push-down
*/
typedef enum {
GPIO_FLOATING = 0x0U, /**< Floating */
GPIO_PUSH_UP = 0x1U, /**< Push-Up */
GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */
} gpio_push_t;
/**
* @brief GPIO output drive
*/
typedef enum {
GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */
} gpio_out_drive_t;
/**
* @brief GPIO filter
*/
typedef enum {
GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */
} gpio_filter_t;
/**
* @brief GPIO type
*/
typedef enum {
GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1U, /**< TTL Type */
} gpio_type_t;
/**
* @brief GPIO functions
*/
typedef enum {
GPIO_FUNC_0 = 0U, /**< function #0 */
GPIO_FUNC_1 = 1U, /**< function #1 */
GPIO_FUNC_2 = 2U, /**< function #2 */
GPIO_FUNC_3 = 3U, /**< function #3 */
GPIO_FUNC_4 = 4U, /**< function #4 */
GPIO_FUNC_5 = 5U, /**< function #5 */
GPIO_FUNC_6 = 6U, /**< function #6 */
GPIO_FUNC_7 = 7U, /**< function #7 */
} gpio_func_t;
/**
* @brief GPIO Init Structure definition
*/
typedef struct {
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
This parameter can be any value of @ref gpio_mode_t */
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
This parameter can be a value of @ref gpio_odos_t */
gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins.
This parameter can be a value of @ref gpio_push_t */
gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins.
This parameter can be a value of @ref gpio_out_drive_t */
gpio_filter_t flt; /**< Specifies the input filter for the selected pins.
This parameter can be a value of @ref gpio_filter_t */
gpio_type_t type; /**< Specifies the type for the selected pins.
This parameter can be a value of @ref gpio_type_t */
gpio_func_t func; /**< Specifies the function for the selected pins.
This parameter can be a value of @ref gpio_func_t */
} gpio_init_t;
/**
* @brief EXTI trigger style
*/
typedef enum {
EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */
} exti_trigger_style_t;
/**
* @brief EXTI filter clock select
*/
typedef enum {
EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */
} exti_filter_clock_t;
/**
* @brief EXTI Init Structure definition
*/
typedef struct {
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
} exti_init_t;
/**
* @}
*/
/**
* @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define PIN_MASK 0xFFFFU
#define UNLOCK_KEY 0x55AAU
#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))
#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \
((x) == GPIO_OUT_DRIVE_STRONG))
#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \
((x) == GPIO_FILTER_ENABLE))
#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \
((x) == GPIO_TYPE_CMOS))
#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \
((x) == EXTI_FILTER_CLOCK_32K))
#define IS_GPIO_FUNC(x) ((x) <= 7)
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions
* @{
*/
/** @addtogroup GPIO_Public_Functions_Group1
* @{
*/
void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
void ald_gpio_func_default(GPIO_TypeDef *GPIOx);
void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group2
* @{
*/
uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx);
void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group3
* @{
*/
void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin);
void ald_gpio_exti_clear_flag_status(uint16_t pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_GPIO_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h
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/**
*********************************************************************************
*
* @file ald_iap.h
* @brief Header file of IAP module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_IAP_H__
#define __ALD_IAP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup IAP
* @{
*/
/**
* @defgroup IAP_Private_Macros IAP Private Macros
* @{
*/
#define IAP_WSP_ADDR 0x10000000U
#define IAP_PE_ADDR 0x10000004U
#define IAP_WP_ADDR 0x10000008U
#define IAP_DWP_ADDR 0x1000000cU
/**
* @}
*/
/** @defgroup IAP_Private_Types IAP Private Types
* @{
*/
typedef uint32_t (*IAP_PE)(uint32_t addr);
typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data);
typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h);
typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
/**
* @}
*/
/** @addtogroup IAP_Public_Functions
* @{
*/
uint32_t ald_iap_erase_page(uint32_t addr);
uint32_t ald_iap_program_word(uint32_t addr, uint32_t data);
uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h);
uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_IAP_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h
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/**
*********************************************************************************
*
* @file ald_lcd.h
* @brief Header file of LCD module driver.
*
* @version V1.0
* @date 29 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_LCD_H__
#define __ALD_LCD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LCD
* @{
*/
/** @defgroup LCD_Public_Types LCD Public Types
* @{
*/
/**
* @brief Lcd vlcd voltage type
*/
typedef enum {
LCD_VCHPS_3V2 = 0U, /**< 3.2V */
LCD_VCHPS_3V8 = 1U, /**< 3.8V */
LCD_VCHPS_4V8 = 2U, /**< 4.8V */
LCD_VCHPS_5V4 = 3U, /**< 5.4V */
} lcd_vchps_t;
/**
* @brief Lcd function type
*/
typedef enum {
LCD_FUNC_DISABLE = 0U, /**< Lcd's function disable */
LCD_FUNC_ENABLE = 1U, /**< Lcd's function enable */
} lcd_func_t;
/**
* @brief Lcd voltage type
*/
typedef enum {
LCD_VSEL_VDD = 0U, /**< VDD */
LCD_VSEL_CP = 1U, /**< Charge pump output */
LCD_VSEL_VLCD = 2U, /**< VLCD input */
} lcd_vsel_t;
/**
* @brief Lcd resistance select bit
*/
typedef enum {
LCD_RES_1MOHM = 0U, /**< 1M ohm */
LCD_RES_2MOHM = 1U, /**< 2M ohm */
LCD_RES_3MOHM = 2U, /**< 3M ohm */
} lcd_res_t;
/**
* @brief Lcd bias selector
*/
typedef enum {
LCD_BIAS_1_4 = 0U, /**< 1/4 bias */
LCD_BIAS_1_2 = 2U, /**< 1/2 bias */
LCD_BIAS_1_3 = 3U, /**< 1/3 bias */
} lcd_bias_t;
/**
* @brief Lcd duty
*/
typedef enum {
LCD_DUTY_STATIC = 0U, /**< Static duty (COM0) */
LCD_DUTY_1_2 = 1U, /**< 1/2 duty (COM0~COM1) */
LCD_DUTY_1_3 = 2U, /**< 1/3 duty (COM0~COM2) */
LCD_DUTY_1_4 = 3U, /**< 1/4 duty (COM0~COM3) */
LCD_DUTY_1_6 = 4U, /**< 1/6 duty (COM0~COM5) */
LCD_DUTY_1_8 = 5U, /**< 1/8 duty (COM0~COM7) */
} lcd_duty_t;
/**
* @brief Lcd prescaler
*/
typedef enum {
LCD_PRS_1 = 0U, /**< CLKPRS = LCDCLK / 1 */
LCD_PRS_2 = 1U, /**< CLKPRS = LCDCLK / 2 */
LCD_PRS_4 = 2U, /**< CLKPRS = LCDCLK / 4 */
LCD_PRS_8 = 3U, /**< CLKPRS = LCDCLK / 8 */
LCD_PRS_16 = 4U, /**< CLKPRS = LCDCLK / 16 */
LCD_PRS_32 = 5U, /**< CLKPRS = LCDCLK / 32 */
LCD_PRS_64 = 6U, /**< CLKPRS = LCDCLK / 64 */
LCD_PRS_128 = 7U, /**< CLKPRS = LCDCLK / 128 */
LCD_PRS_256 = 8U, /**< CLKPRS = LCDCLK / 256 */
LCD_PRS_512 = 9U, /**< CLKPRS = LCDCLK / 512 */
LCD_PRS_1024 = 10U, /**< CLKPRS = LCDCLK / 1024 */
LCD_PRS_2048 = 11U, /**< CLKPRS = LCDCLK / 2048 */
LCD_PRS_4096 = 12U, /**< CLKPRS = LCDCLK / 4096 */
LCD_PRS_8192 = 13U, /**< CLKPRS = LCDCLK / 8192 */
LCD_PRS_16384 = 14U, /**< CLKPRS = LCDCLK / 16384 */
LCD_PRS_32768 = 15U, /**< CLKPRS = LCDCLK / 32768 */
} lcd_prs_t;
/**
* @brief Lcd divider
*/
typedef enum {
LCD_DIV_16 = 0U, /**< DIVCLK = CLKPRS / 16 */
LCD_DIV_17 = 1U, /**< DIVCLK = CLKPRS / 17 */
LCD_DIV_18 = 2U, /**< DIVCLK = CLKPRS / 18 */
LCD_DIV_19 = 3U, /**< DIVCLK = CLKPRS / 19 */
LCD_DIV_20 = 4U, /**< DIVCLK = CLKPRS / 20 */
LCD_DIV_21 = 5U, /**< DIVCLK = CLKPRS / 21 */
LCD_DIV_22 = 6U, /**< DIVCLK = CLKPRS / 22 */
LCD_DIV_23 = 7U, /**< DIVCLK = CLKPRS / 23 */
LCD_DIV_24 = 8U, /**< DIVCLK = CLKPRS / 24 */
LCD_DIV_25 = 9U, /**< DIVCLK = CLKPRS / 25 */
LCD_DIV_26 = 10U, /**< DIVCLK = CLKPRS / 26 */
LCD_DIV_27 = 11U, /**< DIVCLK = CLKPRS / 27 */
LCD_DIV_28 = 12U, /**< DIVCLK = CLKPRS / 28 */
LCD_DIV_29 = 13U, /**< DIVCLK = CLKPRS / 29 */
LCD_DIV_30 = 14U, /**< DIVCLK = CLKPRS / 30 */
LCD_DIV_31 = 15U, /**< DIVCLK = CLKPRS / 31 */
} lcd_div_t;
/**
* @brief Lcd blink mode
*/
typedef enum {
LCD_BLINK_OFF = 0U, /**< Blink disabled */
LCD_BLINK_SEG0_COM0 = 1U, /**< Blink enabled on SEG0, COM0 */
LCD_BLINK_SEG0_COMX2 = 2U, /**< Blink enabled on SEG0, COMx2 */
LCD_BLINK_ALLSEG_ALLCOM = 3U, /**< Blink enabled on all SEG and all COM */
} lcd_blink_t;
/**
* @brief Lcd blink frequency
*/
typedef enum {
LCD_BLFRQ_8 = 0U, /**< DIVCLK / 8 */
LCD_BLFRQ_16 = 1U, /**< DIVCLK / 16 */
LCD_BLFRQ_32 = 2U, /**< DIVCLK / 32 */
LCD_BLFRQ_64 = 3U, /**< DIVCLK / 64 */
LCD_BLFRQ_128 = 4U, /**< DIVCLK / 128 */
LCD_BLFRQ_256 = 5U, /**< DIVCLK / 256 */
LCD_BLFRQ_512 = 6U, /**< DIVCLK / 512 */
LCD_BLFRQ_1024 = 7U, /**< DIVCLK / 1024 */
} lcd_blfrq_t;
/**
* @brief Lcd dead time
*/
typedef enum {
LCD_DEAD_TIME_NONE = 0U, /**< No dead time */
LCD_DEAD_TIME_1_DIVCLK = 1U, /**< Dead time is 1 divclk */
LCD_DEAD_TIME_2_DIVCLK = 2U, /**< Dead time is 2 divclk */
LCD_DEAD_TIME_3_DIVCLK = 3U, /**< Dead time is 3 divclk */
LCD_DEAD_TIME_4_DIVCLK = 4U, /**< Dead time is 4 divclk */
LCD_DEAD_TIME_5_DIVCLK = 5U, /**< Dead time is 5 divclk */
LCD_DEAD_TIME_6_DIVCLK = 6U, /**< Dead time is 6 divclk */
LCD_DEAD_TIME_7_DIVCLK = 7U, /**< Dead time is 7 divclk */
} lcd_dead_t;
/**
* @brief Lcd pulse keep time
*/
typedef enum {
LCD_PON_NONE = 0U, /**< No pulse keep time */
LCD_PON_1_PRSCLK = 1U, /**< Pulse keep 1 prsclk */
LCD_PON_2_PRSCLK = 2U, /**< Pulse keep 2 prsclk */
LCD_PON_3_PRSCLK = 3U, /**< Pulse keep 3 prsclk */
LCD_PON_4_PRSCLK = 4U, /**< Pulse keep 4 prsclk */
LCD_PON_5_PRSCLK = 5U, /**< Pulse keep 5 prsclk */
LCD_PON_6_PRSCLK = 6U, /**< Pulse keep 6 prsclk */
LCD_PON_7_PRSCLK = 7U, /**< Pulse keep 7 prsclk */
} lcd_pluse_on_t;
/**
* @brief Lcd vgs select
*/
typedef enum {
LCD_VGS_0 = 0U, /**< Grey level display voltage is 30/45 vlcd */
LCD_VGS_1 = 1U, /**< Grey level display voltage is 31/45 vlcd */
LCD_VGS_2 = 2U, /**< Grey level display voltage is 32/45 vlcd */
LCD_VGS_3 = 3U, /**< Grey level display voltage is 33/45 vlcd */
LCD_VGS_4 = 4U, /**< Grey level display voltage is 34/45 vlcd */
LCD_VGS_5 = 5U, /**< Grey level display voltage is 35/45 vlcd */
LCD_VGS_6 = 6U, /**< Grey level display voltage is 36/45 vlcd */
LCD_VGS_7 = 7U, /**< Grey level display voltage is 37/45 vlcd */
LCD_VGS_8 = 8U, /**< Grey level display voltage is 38/45 vlcd */
LCD_VGS_9 = 9U, /**< Grey level display voltage is 39/45 vlcd */
LCD_VGS_10 = 10U, /**< Grey level display voltage is 40/45 vlcd */
LCD_VGS_11 = 11U, /**< Grey level display voltage is 41/45 vlcd */
LCD_VGS_12 = 12U, /**< Grey level display voltage is 42/45 vlcd */
LCD_VGS_13 = 13U, /**< Grey level display voltage is 43/45 vlcd */
LCD_VGS_14 = 14U, /**< Grey level display voltage is 44/45 vlcd */
LCD_VGS_15 = 15U, /**< Grey level display voltage is equal to vlcd */
} lcd_vgs_t;
/**
* @brief Lcd wave choose
*/
typedef enum {
LCD_WAVE_A = 0U, /**< Wave type is A */
LCD_WAVE_B = 1U, /**< Wave type is B */
} lcd_wfs_t;
/**
* @brief Lcd status select bit
*/
typedef enum {
LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */
LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/
LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */
LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */
LCD_STATUS_ALL = 0xFFFFFFFU, /**< All flag */
} lcd_status_t;
/**
* @brief Lcd interrupt type
*/
typedef enum {
LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */
LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/
} lcd_it_t;
/**
* @brief Lcd interrupt flag
*/
typedef enum {
LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
} lcd_flag_t;
/**
* @brief Lcd interrupt type
*/
typedef enum {
SEG_0_TO_31 = 0U, /**< Segment 0 to 31 to be set */
SEG_32_TO_59 = 1U, /**< Segment 32 to 59 to be set */
} lcd_seg_t;
/**
* @brief Lcd configure
*/
typedef struct
{
lcd_vsel_t lcd_vsel; /**< Lcd power choose */
lcd_vchps_t lcd_vchps; /**< Charge pump voltage choose */
lcd_func_t lcd_vbufld; /**< Low drive mode function */
lcd_func_t lcd_vbufhd; /**< High drive mode function */
uint32_t lcd_dsld; /**< Low drive mode level */
uint32_t lcd_dshd; /**< High drive mode level */
lcd_res_t lcd_resld; /**< Low dirve mode resistance choose */
lcd_res_t lcd_reshd; /**< High dirve mode resistance choose */
lcd_bias_t lcd_bias; /**< LCD bias */
lcd_duty_t lcd_duty; /**< LCD duty */
lcd_wfs_t lcd_wfs; /**< Wave choose */
lcd_prs_t lcd_prs; /**< Lcd clock prs */
lcd_div_t lcd_div; /**< Lcd div */
lcd_dead_t lcd_dead; /**< Lcd dead time */
lcd_pluse_on_t lcd_pon; /**< Lcd pluse on time */
lcd_vgs_t lcd_vgs; /**< Lcd gray level display voltage */
cmu_lcd_clock_sel_t clock; /**< Lcd clock choose */
} lcd_init_t;
/**
* @brief Lcd handle Structure definition
*/
typedef struct lcd_handle_s {
LCD_TypeDef *perh; /**< LCD registers base address */
lcd_init_t init; /**< LCD initialize parameters */
lock_state_t lock; /**< Locking object */
void (*display_cplt_cbk)(struct lcd_handle_s *arg); /**< Display completed callback */
void (*frame_start_cbk)(struct lcd_handle_s *arg); /**< Frame start callback */
} lcd_handle_t;
/**
* @}
*/
/** @defgroup LCD_Public_Macro LCD Public Macros
* @{
*/
#define LCD_HD_ENABLE(x) (SET_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
#define LCD_HD_DISABLE(x) (CLEAR_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
/**
* @}
*/
/**
* @defgroup LCD_Private_Macros LCD Private Macros
* @{
*/
#define IS_LCD_PERH_TYPE(x) ((x) == LCD)
#define IS_LCD_VCHPS_TYPE(x) (((x) == LCD_VCHPS_3V2) || \
((x) == LCD_VCHPS_3V8) || \
((x) == LCD_VCHPS_4V8) || \
((x) == LCD_VCHPS_5V4))
#define IS_LCD_VSEL_TYPE(x) (((x) == LCD_VSEL_VDD) || \
((x) == LCD_VSEL_CP) || \
((x) == LCD_VSEL_VLCD))
#define IS_LCD_FUNC_TYPE(x) (((x) == LCD_FUNC_DISABLE) || \
((x) == LCD_FUNC_ENABLE))
#define IS_LCD_LEVEL_TYPE(x) (((x) > 0) | ((x) <= 0xF))
#define IS_LCD_RES_TYPE(x) (((x) == LCD_RES_1MOHM) || \
((x) == LCD_RES_2MOHM) || \
((x) == LCD_RES_3MOHM))
#define IS_LCD_BIAS_TYPE(x) (((x) == LCD_BIAS_1_4) || \
((x) == LCD_BIAS_1_2) || \
((x) == LCD_BIAS_1_3))
#define IS_LCD_DUTY_TYPE(x) (((x) == LCD_DUTY_STATIC) || \
((x) == LCD_DUTY_1_2) || \
((x) == LCD_DUTY_1_3) || \
((x) == LCD_DUTY_1_4) || \
((x) == LCD_DUTY_1_6) || \
((x) == LCD_DUTY_1_8))
#define IS_LCD_WFS_TYPE(x) (((x) == LCD_WAVE_A) || \
((x) == LCD_WAVE_B))
#define IS_LCD_PRS_TYPE(x) (((x) == LCD_PRS_1) || \
((x) == LCD_PRS_2) || \
((x) == LCD_PRS_4) || \
((x) == LCD_PRS_8) || \
((x) == LCD_PRS_16) || \
((x) == LCD_PRS_32) || \
((x) == LCD_PRS_64) || \
((x) == LCD_PRS_128) || \
((x) == LCD_PRS_256) || \
((x) == LCD_PRS_512) || \
((x) == LCD_PRS_1024) || \
((x) == LCD_PRS_2048) || \
((x) == LCD_PRS_4096) || \
((x) == LCD_PRS_8192) || \
((x) == LCD_PRS_16384) || \
((x) == LCD_PRS_32768))
#define IS_LCD_DIV_TYPE(x) (((x) == LCD_DIV_16) || \
((x) == LCD_DIV_17) || \
((x) == LCD_DIV_18) || \
((x) == LCD_DIV_19) || \
((x) == LCD_DIV_20) || \
((x) == LCD_DIV_21) || \
((x) == LCD_DIV_22) || \
((x) == LCD_DIV_23) || \
((x) == LCD_DIV_24) || \
((x) == LCD_DIV_25) || \
((x) == LCD_DIV_26) || \
((x) == LCD_DIV_27) || \
((x) == LCD_DIV_28) || \
((x) == LCD_DIV_29) || \
((x) == LCD_DIV_30) || \
((x) == LCD_DIV_31))
#define IS_LCD_BLINK_MODE(x) (((x) == LCD_BLINK_OFF) || \
((x) == LCD_BLINK_SEG0_COM0) || \
((x) == LCD_BLINK_SEG0_COMX2) || \
((x) == LCD_BLINK_ALLSEG_ALLCOM))
#define IS_LCD_BLFRQ_TYPE(x) (((x) == LCD_BLFRQ_8) || \
((x) == LCD_BLFRQ_16) || \
((x) == LCD_BLFRQ_32) || \
((x) == LCD_BLFRQ_64) || \
((x) == LCD_BLFRQ_128) || \
((x) == LCD_BLFRQ_256) || \
((x) == LCD_BLFRQ_512) || \
((x) == LCD_BLFRQ_1024))
#define IS_LCD_STATUS_TYPE(x) (((x) == LCD_STATUS_RDY) || \
((x) == LCD_STATUS_ENS) || \
((x) == LCD_STATUS_UDR) || \
((x) == LCD_STATUS_FCRSF) || \
((x) == LCD_STATUS_ALL))
#define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \
((x) == LCD_FLAG_UDD) || \
((x) == LCD_STATUS_ALL))
#define IS_LCD_IT_TYPE(x) (((x) == LCD_IT_SOF) || \
((x) == LCD_IT_UDD))
#define IS_LCD_FLAG_TYPE(x) (((x) == LCD_FLAG_SOF) || \
((x) == LCD_FLAG_UDD))
#define IS_LCD_SEG_TYPE(x) (((x) == SEG_0_TO_31) || \
((x) == SEG_32_TO_59))
#define IS_LCD_DEAD_TYPE(x) (((x) == LCD_DEAD_TIME_NONE) || \
((x) == LCD_DEAD_TIME_1_DIVCLK) || \
((x) == LCD_DEAD_TIME_2_DIVCLK) || \
((x) == LCD_DEAD_TIME_3_DIVCLK) || \
((x) == LCD_DEAD_TIME_4_DIVCLK) || \
((x) == LCD_DEAD_TIME_5_DIVCLK) || \
((x) == LCD_DEAD_TIME_6_DIVCLK) || \
((x) == LCD_DEAD_TIME_7_DIVCLK))
#define IS_LCD_PON_TYPE(x) (((x) == LCD_PON_NONE) || \
((x) == LCD_PON_1_PRSCLK) || \
((x) == LCD_PON_2_PRSCLK) || \
((x) == LCD_PON_3_PRSCLK) || \
((x) == LCD_PON_4_PRSCLK) || \
((x) == LCD_PON_5_PRSCLK) || \
((x) == LCD_PON_6_PRSCLK) || \
((x) == LCD_PON_7_PRSCLK))
#define IS_LCD_VGS_TYPE(x) (((x) == LCD_VGS_0) || \
((x) == LCD_VGS_1) || \
((x) == LCD_VGS_2) || \
((x) == LCD_VGS_3) || \
((x) == LCD_VGS_4) || \
((x) == LCD_VGS_5) || \
((x) == LCD_VGS_6) || \
((x) == LCD_VGS_7) || \
((x) == LCD_VGS_8) || \
((x) == LCD_VGS_9) || \
((x) == LCD_VGS_10) || \
((x) == LCD_VGS_11) || \
((x) == LCD_VGS_12) || \
((x) == LCD_VGS_13) || \
((x) == LCD_VGS_14) || \
((x) == LCD_VGS_15))
#define IS_LCD_BUFFER_TYPE(x) ((x) <= 15)
/**
* @}
*/
/** @addtogroup LCD_Public_Functions
* @{
*/
/**
* @addtogroup LCD_Public_Functions_Group1
* @{
*/
/* Initialization and enable functions */
ald_status_t ald_lcd_init(lcd_handle_t *hperh);
ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group2
* @{
*/
/* Config output and blink function */
ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq);
ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data);
ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group3
* @{
*/
/* Query lcd status function */
uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_flag);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group4
* @{
*/
/* Interrupt function */
ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state);
flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it);
it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
void ald_lcd_irq_handler(lcd_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LCD_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h
-370
View File
@@ -1,370 +0,0 @@
/**
*********************************************************************************
*
* @file ald_lptim.c
* @brief LPTIM module driver.
* This is the common part of the LPTIM initialization
*
* @version V1.0
* @date 09 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_LPTIM_H__
#define __ALD_LPTIM_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LPTIM
* @{
*/
/** @defgroup LPTIM_Public_Types LPTIM Public Types
* @{
*/
/**
* @brief LPTIM clock select
*/
typedef enum {
LPTIM_CKSEL_INTERNAL = 0U, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1U, /**< Select external clock */
} lptim_cksel_t;
/**
* @brief LPTIM clock pol
*/
typedef enum {
LPTIM_CKPOL_RISING = 0U, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1U, /**< using falling edge */
} lptim_ckpol_t;
/**
* @brief LPTIM clock fliter
*/
typedef enum {
LPTIM_CKFLT_0 = 0U, /**< not clock filter */
LPTIM_CKFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3U, /**< 8 cycle filter */
} lptim_ckflt_t;
/**
* @brief LPTIM trigger fliter
*/
typedef enum {
LPTIM_TRGFLT_0 = 0U, /**< not clock filter */
LPTIM_TRGFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3U, /**< 8 cycle filter */
} lptim_trgflt_t;
/**
* @brief LPTIM prescaler
*/
typedef enum {
LPTIM_PRESC_1 = 0U, /**< No prescaler is used */
LPTIM_PRESC_2 = 1U, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2U, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3U, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4U, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5U, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6U, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7U, /**< Clock is divided by 128 */
} lptim_presc_t;
/**
* @brief LPTIM trig select
*/
typedef enum {
LPTIM_TRIGSEL_EXT0 = 0U, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1U, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2U, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3U, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4U, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5U, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6U, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7U, /**< Trigger select external channel 7 */
} lptim_trigsel_t;
/**
* @brief LPTIM start mode select
*/
typedef enum {
LPTIM_MODE_SINGLE = 0U, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1U, /**< Start continuous mode */
} lptim_mode_t;
/**
* @brief LPTIM trig en
*/
typedef enum {
LPTIM_TRIGEN_SW = 0U, /**< software trigger */
LPTIM_TRIGEN_RISING = 1U, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2U, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3U, /**< rising and falling edge trigger */
} lptim_trigen_t;
/**
* @brief LPTIM wave
*/
typedef enum {
LPTIM_WAVE_NONE = 0U, /**< Output close */
LPTIM_WAVE_TOGGLE = 1U, /**< Output toggle */
LPTIM_WAVE_PULSE = 2U, /**< Output pulse */
LPTIM_WAVE_PWM = 3U, /**< Output PWM */
} lptim_wave_t;
/**
* @brief LPTIM interrupt
*/
typedef enum {
LPTIM_IT_CMPMAT = 1U, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2U, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4U, /**< external trigger interrupt bit */
} lptim_it_t;
/**
* @brief LPTIM Interrupt flag
*/
typedef enum {
LPTIM_FLAG_CMPMAT = 1U, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2U, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4U, /**< Update interrupt flag */
} lptim_flag_t;
/**
* @brief LPTIM state structures definition
*/
typedef enum {
LPTIM_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02U, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04U, /**< Reception process is ongoing */
} lptim_state_t;
/**
* @brief LPTIM Init Structure definition
*/
typedef struct {
lptim_presc_t psc; /**< Specifies the prescaler value */
uint16_t arr; /**< Specifies the update value */
uint16_t cmp; /**< Specifies the compare value */
cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */
lptim_mode_t mode; /**< Specifies the start mode */
} lptim_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct {
lptim_trigen_t mode; /**< Specifies the trigger mode */
lptim_trigsel_t sel; /**< Specifies the trigger source select */
} lptim_trigger_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct {
lptim_cksel_t sel; /**< Specifies the clock select */
lptim_ckpol_t polarity; /**< Specifies the clock polarity */
} lptim_clock_source_init_t;
/**
* @brief LPTIM Handle Structure definition
*/
typedef struct lptim_handle_s {
LPTIM_TypeDef *perh; /**< Register base address */
lptim_init_t init; /**< LPTIM Time required parameters */
lock_state_t lock; /**< Locking object */
lptim_state_t state; /**< LPTIM operation state */
void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */
void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */
void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */
} lptim_handle_t;
/**
* @}
*/
/** @defgroup LPTIM_Public_Macros LPTIM Public Macros
* @{
*/
#define LPTIM_ENABLE(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
#define LPTIM_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
#define LPTIM_CNTSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_CNTSTRT_MSK))
#define LPTIM_SNGSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_SNGSTRT_MSK))
#define LPTIM_UPDATE_ENABLE(x) (SET_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
#define LPTIM_UPDATE_DISABLE(x) (CLEAR_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
#define LPTIM_PRELOAD_IMM(x) (SET_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
#define LPTIM_PRELOAD_WAIT(x) (CLEAR_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
#define LPTIM_WAVEPOL_NORMAL(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 0 << LP16T_CON0_WAVE_POSS))
#define LPTIM_WAVEPOL_INVERSE(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 1 << LP16T_CON0_WAVE_POSS))
/**
* @}
*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
* @{
*/
#define IS_LPTIM(x) ((x) == LPTIM0)
#define IS_LPTIM_CKSEL(x) (((x) == LPTIM_CKSEL_INTERNAL) || \
((x) == LPTIM_CKSEL_EXTERNAL))
#define IS_LPTIM_CKPOL(x) (((x) == LPTIM_CKPOL_RISING) || \
((x) == LPTIM_CKPOL_FALLING))
#define IS_LPTIM_MODE(x) (((x) == LPTIM_MODE_SINGLE) || \
((x) == LPTIM_MODE_CONTINUOUS))
#define IS_LPTIM_CKFLT(x) (((x) == LPTIM_CKFLT_0) || \
((x) == LPTIM_CKFLT_2) || \
((x) == LPTIM_CKFLT_4) || \
((x) == LPTIM_CKFLT_8))
#define IS_LPTIM_TRGFLT(x) (((x) == LPTIM_TRGFLT_0) || \
((x) == LPTIM_TRGFLT_2) || \
((x) == LPTIM_TRGFLT_4) || \
((x) == LPTIM_TRGFLT_8))
#define IS_LPTIM_PRESC(x) (((x) == LPTIM_PRESC_1) || \
((x) == LPTIM_PRESC_2) || \
((x) == LPTIM_PRESC_4) || \
((x) == LPTIM_PRESC_8) || \
((x) == LPTIM_PRESC_16) || \
((x) == LPTIM_PRESC_32) || \
((x) == LPTIM_PRESC_64) || \
((x) == LPTIM_PRESC_128))
#define IS_LPTIM_TRIGSEL(x) (((x) == LPTIM_TRIGSEL_EXT0) || \
((x) == LPTIM_TRIGSEL_EXT1) || \
((x) == LPTIM_TRIGSEL_EXT2) || \
((x) == LPTIM_TRIGSEL_EXT3) || \
((x) == LPTIM_TRIGSEL_EXT4) || \
((x) == LPTIM_TRIGSEL_EXT5) || \
((x) == LPTIM_TRIGSEL_EXT6) || \
((x) == LPTIM_TRIGSEL_EXT7))
#define IS_LPTIM_TRIGEN(x) (((x) == LPTIM_TRIGEN_SW) || \
((x) == LPTIM_TRIGEN_RISING) || \
((x) == LPTIM_TRIGEN_FALLING) || \
((x) == LPTIM_TRIGEN_BOTH))
#define IS_LPTIM_IT(x) (((x) == LPTIM_IT_CMPMAT) || \
((x) == LPTIM_IT_ARRMAT) || \
((x) == LPTIM_IT_EXTTRIG))
#define IS_LPTIM_FLAG(x) (((x) == LPTIM_FLAG_CMPMAT) || \
((x) == LPTIM_FLAG_ARRMAT) || \
((x) == LPTIM_FLAG_EXTTRIG))
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions
* @{
*/
/** @addtogroup LPTIM_Public_Functions_Group1
* @{
*/
void ald_lptim_reset(lptim_handle_t *hperh);
void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config);
void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config);
void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt);
void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group2
* @{
*/
ald_status_t ald_lptim_base_init(lptim_handle_t *hperh);
void ald_lptim_base_start(lptim_handle_t *hperh);
void ald_lptim_base_stop(lptim_handle_t *hperh);
void ald_lptim_base_start_by_it(lptim_handle_t *hperh);
void ald_lptim_base_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
* @{
*/
ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh);
void ald_lptim_toggle_start(lptim_handle_t *hperh);
void ald_lptim_toggle_stop(lptim_handle_t *hperh);
void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh);
void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group4
* @{
*/
ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh);
void ald_lptim_pulse_start(lptim_handle_t *hperh);
void ald_lptim_pulse_stop(lptim_handle_t *hperh);
void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh);
void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group5
* @{
*/
ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh);
void ald_lptim_pwm_start(lptim_handle_t *hperh);
void ald_lptim_pwm_stop(lptim_handle_t *hperh);
void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh);
void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group6
* @{
*/
void ald_lptim_irq_handler(lptim_handle_t *hperh);
void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state);
it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it);
flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group7
* @{
*/
lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LPTIM_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h
-468
View File
@@ -1,468 +0,0 @@
/**
*********************************************************************************
*
* @file ald_lpuart.h
* @brief Header file of Low Power UART module library.
*
* @version V1.0
* @date 30 May 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_LPUART_H__
#define __ALD_LPUART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LPUART
* @{
*/
/**
* @defgroup LPUART_Public_Macros LPUART Public Macros
* @{
*/
/**
* @defgroup LPUART_Public_Macros1 LPUART FIFO Reset
* @{
*/
#define LPUART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_TXRESET_MSK))
#define LPUART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_RXRESET_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros2 LPUART RS485 RX Enable
* @{
*/
#define LPUART_RS485_RX_DISABLE(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
#define LPUART_RS485_RX_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros4 LPUART LoopMode Enable
* @{
*/
#define LPUART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
#define LPUART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros5 LPUART IrDA TX Enable
* @{
*/
#define LPUART_IRTX_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
#define LPUART_IRTX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros6 LPUART IRWIDTH Enable
* @{
*/
#define LPUART_IRWIDTH_DISABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
#define LPUART_IRWIDTH_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros7 LPUART CTS/RTS Enable
* @{
*/
#define LPUART_CTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
#define LPUART_CTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
#define LPUART_RTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
#define LPUART_RTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros8 LPUART CTS/RTS Polarity
* @{
*/
#define LPUART_CTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
#define LPUART_CTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
#define LPUART_RTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
#define LPUART_RTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros10 LPUART Update Enable
* @{
*/
#define LPUART_UPDATE_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
#define LPUART_UPDATE_DISABLE(hperh) (SET_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup LPUART_Public_Types LPUART Public Types
* @{
*/
/**
* @brief LPUART Word Length
*/
typedef enum {
LPUART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4U, /**< 9-bits */
} lpuart_word_length_t;
/**
* @brief LPUART Stop Bits
*/
typedef enum {
LPUART_STOP_BITS_1 = 0x0U, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1U, /**< 2-bits */
} lpuart_stop_bits_t;
/**
* @brief LPUART Parity
*/
typedef enum {
LPUART_PARITY_NONE = 0x0U, /**< Not parity */
LPUART_PARITY_ODD = 0x1U, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3U, /**< Even parity */
} lpuart_parity_t;
/**
* @brief LPUART Mode
*/
typedef enum {
LPUART_MODE_UART = 0x0U, /**< UART */
LPUART_MODE_IrDA = 0x2U, /**< IrDA */
LPUART_MODE_RS485 = 0x3U, /**< RS485 */
} lpuart_mode_t;
/**
* @brief LPUART Hardware Flow Control
*/
typedef enum {
LPUART_HW_FLOW_CTL_NONE = 0x0U, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS */
} lpuart_hw_flow_ctl_t;
/**
* @brief ALD LPUART State
*/
typedef enum {
LPUART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPUART_STATE_ERROR = 0x04U, /**< Error */
} lpuart_state_t;
/**
* @brief LPUART Error Codes
*/
typedef enum {
LPUART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} lpuart_error_t;
/**
* @brief LPUART Init structure definition
*/
typedef struct {
uint32_t baud; /**< Specifies the lpuart communication baud rate */
lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
lpuart_parity_t parity; /**< Specifies the parity mode */
lpuart_mode_t mode; /**< Specifies uart mode */
lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */
} lpuart_init_t;
/**
* @brief LPUART handle structure definition
*/
typedef struct lpuart_handle_s {
LPUART_TypeDef *perh; /**< LPUART registers base address */
lpuart_init_t init; /**< LPUART communication parameters */
uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */
uint16_t tx_size; /**< LPUART Tx Transfer size */
uint16_t tx_count; /**< LPUART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */
uint16_t rx_size; /**< LPUART Rx Transfer size */
uint16_t rx_count; /**< LPUART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
lpuart_state_t state; /**< LPUART communication state */
lpuart_error_t err_code; /**< LPUART Error code */
void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */
} lpuart_handle_t;
/**
* @brief LPUART RS485 Configure Structure definition
*/
typedef struct {
type_func_t RS485_NMM; /**< Normal Point Mode */
type_func_t RS485_AAD; /**< Auto-Address Detect */
type_func_t RS485_AUD; /**< Auto-Direction Mode */
type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */
uint8_t RS485_ADDCMP; /**< Address for compare */
} lpuart_rs485_config_t;
/**
* @brief LPUART DMA Requests
*/
typedef enum {
LPUART_DMA_REQ_TX = 0x0U, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1U, /**< RX dma */
} lpuart_dma_req_t;
/**
* @brief LPUART RXFIFO size
*/
typedef enum {
LPUART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
} lpuart_rxfifo_t;
/**
* @brief LPUART Interrupts Types
*/
typedef enum {
LPUART_IT_RBR = (1U << 0), /**< RBR */
LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IT_RXTO = (1U << 3), /**< RXTO */
LPUART_IT_RXOV = (1U << 4), /**< RXOV */
LPUART_IT_TXOV = (1U << 5), /**< TXOV */
LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IT_DATWK = (1U << 8), /**< DATWK */
LPUART_IT_PERR = (1U << 9), /**< PERR */
LPUART_IT_FERR = (1U << 10), /**< FERR */
LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IT_ADET = (1U << 12), /**< ADET */
LPUART_IT_TC = (1U << 15), /**< TC */
} lpuart_it_t;
/**
* @brief LPUART Flags Types
*/
typedef enum {
LPUART_IF_RBR = (1U << 0), /**< RBR */
LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IF_RXTO = (1U << 3), /**< RXTO */
LPUART_IF_RXOV = (1U << 4), /**< RXOV */
LPUART_IF_TXOV = (1U << 5), /**< TXOV */
LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IF_DATWK = (1U << 8), /**< DATWK */
LPUART_IF_PERR = (1U << 9), /**< PERR */
LPUART_IF_FERR = (1U << 10), /**< FERR */
LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IF_ADET = (1U << 12), /**< ADET */
LPUART_IF_TC = (1U << 15), /**< TC */
} lpuart_flag_t;
/**
* @brief LPUART Status Types
*/
typedef enum {
LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */
LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */
LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */
LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */
LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */
LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */
LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */
} lpuart_status_t;
/**
* @}
*/
/** @defgroup LPUART_Private_Macros LPUART Private Macros
* @{
*/
#define IS_LPUART(x) ((x) == LPUART0)
#define IS_LPUART_DATA(x) ((x) <= 0x1FF)
#define IS_LPUART_BAUDRATE(x) (((x) > 0) && ((x) <= 115200))
#define IS_LPUART_WORD_LENGTH(x) (((x) == LPUART_WORD_LENGTH_5B) || \
((x) == LPUART_WORD_LENGTH_6B) || \
((x) == LPUART_WORD_LENGTH_7B) || \
((x) == LPUART_WORD_LENGTH_8B) || \
((x) == LPUART_WORD_LENGTH_9B))
#define IS_LPUART_STOPBITS(x) (((x) == LPUART_STOP_BITS_1) || \
((x) == LPUART_STOP_BITS_2))
#define IS_LPUART_PARITY(x) (((x) == LPUART_PARITY_NONE) || \
((x) == LPUART_PARITY_ODD) || \
((x) == LPUART_PARITY_EVEN))
#define IS_LPUART_MODE(x) (((x) == LPUART_MODE_UART) || \
((x) == LPUART_MODE_IrDA) || \
((x) == LPUART_MODE_RS485))
#define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\
(((x) == LPUART_HW_FLOW_CTL_NONE) || \
((x) == LPUART_HW_FLOW_CTL_RTS) || \
((x) == LPUART_HW_FLOW_CTL_CTS) || \
((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
#define IS_LPUART_DMAREQ(x) (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX))
#define IS_LPUART_RXFIFO(x) (((x) == LPUART_RXFIFO_1BYTE) || \
((x) == LPUART_RXFIFO_4BYTE) || \
((x) == LPUART_RXFIFO_8BYTE) || \
((x) == LPUART_RXFIFO_14BYTE))
#define IS_LPUART_IT(x) (((x) == LPUART_IT_RBR) || \
((x) == LPUART_IT_TBEMP) || \
((x) == LPUART_IT_CTSDET) || \
((x) == LPUART_IT_RXTO) || \
((x) == LPUART_IT_RXOV) || \
((x) == LPUART_IT_TXOV) || \
((x) == LPUART_IT_CTSWK) || \
((x) == LPUART_IT_DATWK) || \
((x) == LPUART_IT_PERR) || \
((x) == LPUART_IT_FERR) || \
((x) == LPUART_IT_BRKERR) || \
((x) == LPUART_IT_ADET) || \
((x) == LPUART_IT_TC))
#define IS_LPUART_IF(x) (((x) == LPUART_IF_RBR) || \
((x) == LPUART_IF_TBEMP) || \
((x) == LPUART_IF_CTSDET) || \
((x) == LPUART_IF_RXTO) || \
((x) == LPUART_IF_RXOV) || \
((x) == LPUART_IF_TXOV) || \
((x) == LPUART_IF_CTSWK) || \
((x) == LPUART_IF_DATWK) || \
((x) == LPUART_IF_PERR) || \
((x) == LPUART_IF_FERR) || \
((x) == LPUART_IF_BRKERR) || \
((x) == LPUART_IF_ADET) || \
((x) == LPUART_IF_TC))
#define IS_LPUART_STAT(x) (((x) == LPUART_STAT_RXEMP) || \
((x) == LPUART_STAT_RXFULL) || \
((x) == LPUART_STAT_TXEMP) || \
((x) == LPUART_STAT_TXFULL) || \
((x) == LPUART_STAT_TXIDLE) || \
((x) == LPUART_STAT_CTSSTAT) || \
((x) == LPUART_STAT_RTSSTAT))
#define LPUART_STATE_TX_MASK (1U << 4)
#define LPUART_STATE_RX_MASK (1U << 5)
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions
* @{
*/
/** @addtogroup LPUART_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void ald_lpuart_init(lpuart_handle_t *hperh);
void ald_lpuart_reset(lpuart_handle_t *hperh);
void ald_lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh);
ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh);
ald_status_t ald_lpuart_dma_stop(lpuart_handle_t *hperh);
#endif
void ald_lpuart_irq_handler(lpuart_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group3
* @{
*/
/* Peripheral Control functions */
void ald_lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status);
void ald_lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val);
void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status);
void ald_lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
void ald_lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout);
flag_status_t ald_lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag);
flag_status_t ald_lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
void ald_lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
it_status_t ald_lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group4
* @{
*/
/* Peripheral State and Errors functions */
lpuart_state_t ald_lpuart_get_state(lpuart_handle_t *hperh);
uint32_t ald_lpuart_get_error(lpuart_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LPUART_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h
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/**
*********************************************************************************
*
* @file ald_pmu.h
* @brief Header file of PMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_PMU_H__
#define __ALD_PMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_syscfg.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup PMU
* @{
*/
/** @defgroup PMU_Public_Macros PMU Public Macros
* @{
*/
#define PMU_SRAM0_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM0_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
/**
* @}
*/
/** @defgroup PMU_Public_Types PMU Public Types
* @{
*/
/**
* @brief Low power mode
*/
typedef enum {
PMU_LP_STOP1 = 0x0U, /**< Stop1 */
PMU_LP_STOP2 = 0x1U, /**< Stop2 */
PMU_LP_STANDBY = 0x2U, /**< Standby */
} pmu_lp_mode_t;
typedef enum {
PMU_SR_WUF = (1U << 0),
PMU_SR_STANDBY = (1U << 1),
} pmu_status_t;
/**
* @brief LVD voltage select
*/
typedef enum {
PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */
} pmu_lvd_voltage_sel_t;
/**
* @brief LVD trigger mode
*/
typedef enum {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */
} pmu_lvd_trigger_mode_t;
/**
* @brief LDO output voltage selest in low power mode
*/
typedef enum {
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U, /**< 1.2V */
} pmu_ldo_lpmode_output_t;
/**
* @}
*/
/**
* @defgroup PMU_Private_Macros PMU Private Macros
* @{
*/
#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY))
#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_2_3) || \
((x) == PMU_LVD_VOL_SEL_EXT))
#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
/**
* @}
*/
/** @addtogroup PMU_Public_Functions
* @{
*/
/** @addtogroup PMU_Public_Functions_Group1
* @{
*/
/* Low power mode select */
__STATIC_INLINE__ void ald_pmu_sleep()
{
__WFI();
}
__STATIC_INLINE__ void ald_pmu_sleep_deep()
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
void ald_pmu_stop1_enter(void);
void ald_pmu_stop2_enter(void);
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
flag_status_t ald_pmu_get_status(pmu_status_t sr);
void ald_pmu_clear_status(pmu_status_t sr);
/**
* @}
*/
/** @addtogroup PMU_Public_Functions_Group2
* @{
*/
/* LVD configure */
void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
void ald_lvd_irq_handler(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_PMU_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h
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/**
*********************************************************************************
*
* @file ald_rmu.h
* @brief Header file of RMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_RMU_H__
#define __ALD_RMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup RMU
* @{
*/
/** @defgroup RMU_Public_Types RMU Public Types
* @{
*/
/**
* @brief RMU BOR fliter
*/
typedef enum {
RMU_BORFLT_1 = 0x1U, /**< 1 cycle */
RMU_BORFLT_2 = 0x2U, /**< 2 cycles */
RMU_BORFLT_3 = 0x3U, /**< 3 cycles */
RMU_BORFLT_4 = 0x4U, /**< 4 cycles */
RMU_BORFLT_5 = 0x5U, /**< 5 cycles */
RMU_BORFLT_6 = 0x6U, /**< 6 cycles */
RMU_BORFLT_7 = 0x7U, /**< 7 cycles */
} rmu_bor_filter_t;
/**
* @brief RMU BOR voltage
*/
typedef enum {
RMU_VOL_1_8 = 0x0U, /**< 1.8V */
RMU_VOL_2_0 = 0x1U, /**< 2.0V */
RMU_VOL_2_2 = 0x2U, /**< 2.2V */
RMU_VOL_2_4 = 0x3U, /**< 2.4V */
RMU_VOL_2_6 = 0x4U, /**< 2.6V */
RMU_VOL_2_8 = 0x5U, /**< 2.8V */
RMU_VOL_3_0 = 0x6U, /**< 3.0V */
RMU_VOL_3_2 = 0x7U, /**< 3.2V */
RMU_VOL_3_4 = 0x8U, /**< 3.4V */
RMU_VOL_3_6 = 0x9U, /**< 3.6V */
RMU_VOL_3_8 = 0xAU, /**< 3.8V */
RMU_VOL_4_0 = 0xBU, /**< 4.0V */
RMU_VOL_4_2 = 0xCU, /**< 4.2V */
RMU_VOL_4_4 = 0xDU, /**< 4.4V */
RMU_VOL_4_6 = 0xEU, /**< 4.6V */
RMU_VOL_4_8 = 0xFU, /**< 4.8V */
} rmu_bor_vol_t;
/**
* @brief RMU reset status
*/
typedef enum {
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
RMU_RST_NMRST = (1U << 3), /**< NMRST */
RMU_RST_IWDT = (1U << 4), /**< IWDT */
RMU_RST_WWDT = (1U << 5), /**< WWDT */
RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */
RMU_RST_CHIP = (1U << 7), /**< CHIP */
RMU_RST_MCU = (1U << 8), /**< MCU */
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
RMU_RST_ALL = (0xFFFFFU), /**< ALL */
} rmu_state_t;
/**
* @brief RMU periperal select bit
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum {
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */
RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */
RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */
RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */
RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */
RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */
RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */
RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */
RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */
RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */
RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */
RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */
RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */
RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */
RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */
RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */
RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */
RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */
RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */
RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */
RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */
RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */
RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */
RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */
RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */
RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */
RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */
RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */
RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */
RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */
RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */
RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */
RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */
RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */
RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */
RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */
RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */
} rmu_peripheral_t;
/**
* @}
*/
/**
* @defgroup RMU_Private_Macros RMU Private Macros
* @{
*/
#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_2) || \
((x) == RMU_VOL_3_4) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_8) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_2) || \
((x) == RMU_VOL_4_4) || \
((x) == RMU_VOL_4_6) || \
((x) == RMU_VOL_4_8))
#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR) || \
((x) == RMU_RST_ALL))
#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_ALL))
#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
((x) == RMU_PERH_CRYPT) || \
((x) == RMU_PERH_TRNG) || \
((x) == RMU_PERH_PIS) || \
((x) == RMU_PERH_CHIP) || \
((x) == RMU_PERH_CPU) || \
((x) == RMU_PERH_TIMER0) || \
((x) == RMU_PERH_TIMER1) || \
((x) == RMU_PERH_TIMER2) || \
((x) == RMU_PERH_TIMER3) || \
((x) == RMU_PERH_TIMER4) || \
((x) == RMU_PERH_TIMER5) || \
((x) == RMU_PERH_TIMER6) || \
((x) == RMU_PERH_TIMER7) || \
((x) == RMU_PERH_UART0) || \
((x) == RMU_PERH_UART1) || \
((x) == RMU_PERH_UART2) || \
((x) == RMU_PERH_UART3) || \
((x) == RMU_PERH_USART0) || \
((x) == RMU_PERH_USART1) || \
((x) == RMU_PERH_SPI0) || \
((x) == RMU_PERH_SPI1) || \
((x) == RMU_PERH_SPI2) || \
((x) == RMU_PERH_I2C0) || \
((x) == RMU_PERH_I2C1) || \
((x) == RMU_PERH_CAN0) || \
((x) == RMU_PERH_LPTIM0) || \
((x) == RMU_PERH_LPUART0) || \
((x) == RMU_PERH_ADC0) || \
((x) == RMU_PERH_ADC1) || \
((x) == RMU_PERH_ACMP0) || \
((x) == RMU_PERH_ACMP1) || \
((x) == RMU_PERH_OPAMP) || \
((x) == RMU_PERH_DAC0) || \
((x) == RMU_PERH_WWDT) || \
((x) == RMU_PERH_LCD) || \
((x) == RMU_PERH_IWDT) || \
((x) == RMU_PERH_RTC) || \
((x) == RMU_PERH_TSENSE) || \
((x) == RMU_PERH_BKPC) || \
((x) == RMU_PERH_BKPRAM))
/**
* @}
*/
/** @addtogroup RMU_Public_Functions
* @{
*/
void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
uint32_t ald_rmu_get_reset_status(rmu_state_t state);
void ald_rmu_clear_reset_status(rmu_state_t state);
void ald_rmu_reset_periperal(rmu_peripheral_t perh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_RMU_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h
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/**
*********************************************************************************
*
* @file ald_usart.h
* @brief Header file of SMARTCARD driver module.
*
* @version V1.0
* @date 25 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SMARTCARD_H__
#define __ALD_SMARTCARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
#include "ald_usart.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SMARTCARD
* @{
*/
/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants
* @{
*/
/**
* @brief SMARTCARD error codes
*/
typedef enum {
SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} smartcard_error_t;
/**
* @brief SMARTCARD Prescaler
*/
typedef enum {
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */
} smartcard_prescaler_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct {
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
usart_parity_t parity; /**< Specifies the parity mode.
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/
usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref usart_last_bit_t */
smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock. The value given in the register (5 significant bits)
is multiplied by 2 to give the division factor of the source clock frequency. */
uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */
} smartcard_init_t;
/**
* @brief ALD state structures definition
*/
typedef enum {
SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04U, /**< Error */
} smartcard_state_t;
/**
* @brief SMARTCARD handle structure definition
*/
typedef struct smartcard_handle_s {
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */
uint16_t tx_size; /**< SmartCard Tx Transfer size */
uint16_t tx_count; /**< SmartCard Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */
uint16_t rx_size; /**< SmartCard Rx Transfer size */
uint16_t rx_count; /**< SmartCard Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
smartcard_state_t state; /**< SmartCard communication state */
uint32_t err_code; /**< SmartCard Error code */
void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */
} smartcard_handle_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros
* @{
*/
/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset
* @{
*/
#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data
* @{
*/
#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable
* @{
*/
#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable
* @{
*/
#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions
* @{
*/
/** @addtogroup SMARTCARD_Public_Functions_Group1
* @{
*/
/* Initialization functions */
ald_status_t ald_smartcard_init(smartcard_handle_t *hperh);
ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
#endif
void ald_smartcard_irq_handler(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group3
* @{
*/
/* Peripheral State and Errors functions functions */
smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh);
uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_SMARTCARD_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h
-387
View File
@@ -1,387 +0,0 @@
/**
*********************************************************************************
*
* @file ald_spi.c
* @brief Header file of SPI module driver.
*
* @version V1.0
* @date 13 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SPI_H__
#define __ALD_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Public_Types SPI Public Types
* @{
*/
/**
* @brief clock phase
*/
typedef enum {
SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */
} spi_cpha_t;
/**
* @brief clock polarity
*/
typedef enum {
SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */
} spi_cpol_t;
/**
* @brief master selection
*/
typedef enum {
SPI_MODE_SLAVER = 0U, /**< Slave mode */
SPI_MODE_MASTER = 1U, /**< Master mode */
} spi_mode_t;
/**
* @brief baud rate control
*/
typedef enum {
SPI_BAUD_2 = 0U, /**< fpclk/2 */
SPI_BAUD_4 = 1U, /**< fpclk/4 */
SPI_BAUD_8 = 2U, /**< fpclk/8 */
SPI_BAUD_16 = 3U, /**< fpclk/16 */
SPI_BAUD_32 = 4U, /**< fpclk/32 */
SPI_BAUD_64 = 5U, /**< fpclk/64 */
SPI_BAUD_128 = 6U, /**< fpclk/128 */
SPI_BAUD_256 = 7U, /**< fpclk/256 */
} spi_baud_t;
/**
* @brief frame format
*/
typedef enum {
SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */
} spi_firstbit_t;
/**
* @brief data frame format
*/
typedef enum {
SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */
} spi_datasize_t;
/**
* @brief interrupt control
*/
typedef enum {
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
} spi_it_t;
/**
* @brief interrupt flag
*/
typedef enum {
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
SPI_IF_MODF = (1U << 5), /**< mode fault */
SPI_IF_OVE = (1U << 6), /**< overrun flag */
SPI_IF_BUSY = (1U << 7), /**< busy flag */
} spi_flag_t;
/**
* @brief SPI error status
*/
typedef enum {
SPI_ERROR_NONE = 0U, /**< none */
SPI_ERROR_MODF = 1U, /**< mode fault */
SPI_ERROR_CRC = 2U, /**< crc error */
SPI_ERROR_OVE = 4U, /**< overrun error */
SPI_ERROR_DMA = 8U, /**< dma error */
SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */
} spi_error_t;
/**
* @brief SPI state structures definition
*/
typedef enum {
SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SPI_STATE_ERROR = 0x04U, /**< Error */
} spi_state_t;
/**
* @brief SPI status definition
*/
typedef enum {
SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */
SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */
SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */
SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */
SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */
SPI_STATUS_BUSY = (1U << 7), /**< Busy status */
} spi_status_t;
/**
* @brief SPI direction definition
*/
typedef enum {
SPI_DIRECTION_2LINES = 0U, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2U, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */
} spi_direction_t;
/**
* @brief SPI dma request definition
*/
typedef enum {
SPI_DMA_REQ_TX = 0U, /**< TX dma request */
SPI_DMA_REQ_RX = 1U, /**< RX dma request */
} spi_dma_req_t;
/**
* @brief SPI TXE/RXNE status definition
*/
typedef enum {
SPI_SR_TXBE = 0U, /**< SR.TXE set */
SPI_SR_RXBNE = 1U, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */
} spi_sr_status_t;
/**
* @brief SPI init structure definition
*/
typedef struct {
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
spi_baud_t baud; /**< SPI baudrate prescaler */
spi_cpha_t phase; /**< SPI clock phase */
spi_cpol_t polarity; /**< SPI clock polarity */
spi_firstbit_t first_bit; /**< SPI first bit */
type_func_t ss_en; /**< SPI ssm enable or disable */
type_func_t crc_calc; /**< SPI crc calculation */
uint16_t crc_poly; /**< SPI crc polynomial */
} spi_init_t;
/**
* @brief SPI handle structure definition
*/
typedef struct spi_handle_s {
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
uint16_t tx_size; /**< SPI Tx transfer size */
uint16_t tx_count; /**< SPI Tx transfer counter */
uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
uint16_t rx_size; /**< SPI Rx Transfer size */
uint16_t rx_count; /**< SPI Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
spi_state_t state; /**< SPI communication state */
uint32_t err_code; /**< SPI error code */
void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */
void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */
void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */
} spi_handle_t;
/**
* @}
*/
/** @defgroup SPI_Public_Macros SPI Public Macros
* @{
*/
#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define SPI_CRC_RESET(x) \
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
/**
* @}
*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#if defined(ES32F065x) || defined(ES32F033x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1))
#endif
#if defined(ES32F093x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2))
#endif
#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
((x) == SPI_CPOL_HIGH))
#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \
((x) == SPI_MODE_MASTER))
#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \
((x) == SPI_BAUD_4) || \
((x) == SPI_BAUD_8) || \
((x) == SPI_BAUD_16) || \
((x) == SPI_BAUD_32) || \
((x) == SPI_BAUD_64) || \
((x) == SPI_BAUD_128) || \
((x) == SPI_BAUD_256))
#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \
((x) == SPI_FIRSTBIT_LSB))
#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))
#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \
((x) == SPI_BIDMODE_SOLE))
#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \
((x) == SPI_DMA_REQ_RX))
#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \
((x) == SPI_SR_RXBNE) || \
((x) == SPI_SR_TXBE_RXBNE))
#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \
((x) == SPI_IT_RXBNE) || \
((x) == SPI_IT_TXBE))
#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \
((x) == SPI_IF_TXBE) || \
((x) == SPI_IF_CRCERR) || \
((x) == SPI_IF_MODF) || \
((x) == SPI_IF_OVE) || \
((x) == SPI_IF_BUSY))
#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \
((x) == SPI_STATUS_TXBE) || \
((x) == SPI_STATUS_CRCERR) || \
((x) == SPI_STATUS_MODEERR) || \
((x) == SPI_STATUS_OVERR) || \
((x) == SPI_STATUS_BUSY))
/**
* @}
*/
/** @addtogroup SPI_Public_Functions
* @{
*/
/** @addtogroup SPI_Public_Functions_Group1
* @{
*/
ald_status_t ald_spi_init(spi_handle_t *hperh);
void ald_spi_reset(spi_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group2
* @{
*/
int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data);
uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh);
ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
ald_status_t ald_spi_dma_pause(spi_handle_t *hperh);
ald_status_t ald_spi_dma_resume(spi_handle_t *hperh);
ald_status_t ald_spi_dma_stop(spi_handle_t *hperh);
#endif
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group3
* @{
*/
void ald_spi_irq_handler(spi_handle_t *hperh);
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status);
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group4
* @{
*/
spi_state_t ald_spi_get_state(spi_handle_t *hperh);
uint32_t ald_spi_get_error(spi_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h
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/**
*********************************************************************************
*
* @file ald_syscfg.h
* @brief SYSCFG module driver.
*
* @version V1.0
* @date 04 Jun 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SYSCFG_H__
#define __ALD_SYSCFG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup SYSCFG SYSCFG
* @brief SYSCFG module driver
* @{
*/
/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
* @{
*/
#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
#define BOOT_FROM_BOOT_ROM() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define BOOT_FROM_BOOT_FLASH() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define BOOT_FROM_FLASH() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions
* @{
*/
__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
{
SYSCFG_UNLOCK();
if (status) {
MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU));
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
else {
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
SYSCFG_LOCK();
return;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h
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/**
*********************************************************************************
*
* @file ald_trng.h
* @brief Header file of TRNG module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TRNG_H__
#define __ALD_TRNG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TRNG
* @{
*/
/** @defgroup TRNG_Public_Types TRNG Public Types
* @{
*/
/**
* @brief Data width
*/
typedef enum {
TRNG_DSEL_1B = 0x0U, /**< 1-bit */
TRNG_DSEL_8B = 0x1U, /**< 8-bit */
TRNG_DSEL_16B = 0x2U, /**< 16-bit */
TRNG_DSEL_32B = 0x3U, /**< 32-bit */
} trng_data_width_t;
/**
* @brief seed type
*/
typedef enum {
TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */
} trng_seed_type_t;
/**
* @brief TRNG init structure definition
*/
typedef struct {
trng_data_width_t data_width; /**< The width of data */
trng_seed_type_t seed_type; /**< The seed type */
uint32_t seed; /**< The value of seed */
uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */
uint8_t adjc; /**< Adjust parameter */
type_func_t posten; /**< Data back handle function */
} trng_init_t;
/**
* @brief TRNG state structures definition
*/
typedef enum {
TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
TRNG_STATE_ERROR = 0x4U, /**< Error */
} trng_state_t;
/**
* @brief State type
*/
typedef enum {
TRNG_STATUS_START = (1U << 0), /**< Start state */
TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */
TRNG_STATUS_SERR = (1U << 2), /**< Error state */
} trng_status_t;
/**
* @brief Interrupt type
*/
typedef enum {
TRNG_IT_START = (1U << 0), /**< Start */
TRNG_IT_DAVLD = (1U << 1), /**< Data valid */
TRNG_IT_SERR = (1U << 2), /**< Error */
} trng_it_t;
/**
* @brief Interrupt flag type
*/
typedef enum {
TRNG_IF_START = (1U << 0), /**< Start */
TRNG_IF_DAVLD = (1U << 1), /**< Data valid */
TRNG_IF_SERR = (1U << 2), /**< Error */
} trng_flag_t;
/**
* @brief TRNG Handle Structure definition
*/
typedef struct trng_handle_s {
TRNG_TypeDef *perh; /**< Register base address */
trng_init_t init; /**< TRNG required parameters */
uint32_t data; /**< result data */
lock_state_t lock; /**< Locking object */
trng_state_t state; /**< TRNG operation state */
void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */
void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */
void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */
} trng_handle_t;
/**
* @}
*/
/** @defgroup TRNG_Public_Macros TRNG Public Macros
* @{
*/
#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
/**
* @}
*/
/**
* @defgroup TRNG_Private_Macros TRNG Private Macros
* @{
*/
#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \
((x) == TRNG_DSEL_8B) || \
((x) == TRNG_DSEL_16B) || \
((x) == TRNG_DSEL_32B))
#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \
((x) == TRNG_SEED_TYPE_1) || \
((x) == TRNG_SEED_TYPE_LAST) || \
((x) == TRNG_SEED_TYPE_SEED))
#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \
((x) == TRNG_STATUS_DAVLD) || \
((x) == TRNG_STATUS_SERR))
#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \
((x) == TRNG_IT_DAVLD) || \
((x) == TRNG_IT_SERR))
#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
#define IS_TRNG_ADJC(x) ((x) < 4)
#define IS_TRNG_T_START(x) ((x) < 8)
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions
* @{
*/
/** @addtogroup TRNG_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern ald_status_t ald_trng_init(trng_handle_t *hperh);
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions_Group2
* @{
*/
/* Control functions */
extern uint32_t ald_trng_get_result(trng_handle_t *hperh);
extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state);
extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status);
extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it);
extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag);
extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag);
extern void ald_trng_irq_handler(trng_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TRNG_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h
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/**
*********************************************************************************
*
* @file ald_tsense.h
* @brief Header file of TSENSE module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TSENSE_H__
#define __ALD_TSENSE_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TSENSE
* @{
*/
/** @defgroup TSENSE_Public_Macros TSENSE Public Macros
* @{
*/
#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define TSENSE_ENABLE() \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_DISABLE() \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_REQ_ENABLE() \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_REQ_DISABLE() \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_CTN_ENABLE() \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_CTN_DISABLE() \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_RESET() \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_LTGR_WR(data) \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->LTGR, (data)); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_HTGR_WR(data) \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->HTGR, (data)); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_TBDR_WR(data) \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TBDR, (data)); \
TSENSE_LOCK(); \
} while (0)
#define TSENSE_TCALBDR_WR(data) \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TCALBDR, (data)); \
TSENSE_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup TSENSE_Public_Types TSENSE Public Types
* @{
*/
/**
* @brief Temperature update time
*/
typedef enum {
TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */
TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */
TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */
TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */
TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */
} tsense_update_cycle_t;
/**
* @brief Temperature output mode
*/
typedef enum {
TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */
TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */
TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */
TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */
TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */
} tsense_output_mode_t;
/**
* @brief Source select
*/
typedef enum {
TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */
TSENSE_SOURCE_LRC = 0x1U, /**< LRC */
} tsense_source_sel_t;
/**
* @brief Define callback function type
*/
typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
/**
* @}
*/
/**
* @defgroup TSENSE_Private_Macros TSENSE Private Macros
* @{
*/
#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \
((x) == TSENSE_SOURCE_LRC))
/**
* @}
*/
/** @addtogroup TSENSE_Public_Functions
* @{
*/
/** @addtogroup TSENSE_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void ald_tsense_init(void);
extern void ald_tsense_source_select(tsense_source_sel_t sel);
/**
* @}
*/
/** @addtogroup TSENSE_Public_Functions_Group2
* @{
*/
/* Control functions */
extern ald_status_t ald_tsense_get_value(uint16_t *tsense);
extern void ald_tsense_get_value_by_it(tsense_cbk cbk);
extern void ald_tsense_irq_handler(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TSENSE_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h
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/**
*********************************************************************************
*
* @file ald_uart.h
* @brief Header file of UART module library.
*
* @version V1.0
* @date 21 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_UART_H__
#define __ALD_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup UART
* @{
*/
/**
* @defgroup UART_Public_Macros UART Public Macros
* @{
*/
#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK))
#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK))
#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK))
#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
/**
* @}
*/
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/**
* @brief UART word length
*/
typedef enum {
UART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */
UART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */
UART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */
UART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */
} uart_word_length_t;
/**
* @brief UART stop bits
*/
typedef enum {
UART_STOP_BITS_1 = 0x0U, /**< 1-bits */
UART_STOP_BITS_2 = 0x1U, /**< 2-bits */
UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */
UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */
} uart_stop_bits_t;
/**
* @brief UART parity
*/
typedef enum {
UART_PARITY_NONE = 0x0U, /**< Not parity */
UART_PARITY_ODD = 0x1U, /**< Odd parity */
UART_PARITY_EVEN = 0x3U, /**< Even parity */
} uart_parity_t;
/**
* @brief UART mode
*/
typedef enum {
UART_MODE_UART = 0x0U, /**< UART */
UART_MODE_LIN = 0x1U, /**< LIN */
UART_MODE_IrDA = 0x2U, /**< IrDA */
UART_MODE_RS485 = 0x3U, /**< RS485 */
UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */
} uart_mode_t;
/**
* @brief UART hardware flow control
*/
typedef enum {
UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */
UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */
} uart_hw_flow_ctl_t;
/**
* @brief ALD UART state
*/
typedef enum {
UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
UART_STATE_ERROR = 0x04U, /**< Error */
} uart_state_t;
/**
* @brief UART error codes
*/
typedef enum {
UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} uart_error_t;
/**
* @brief UART init structure definition
*/
typedef struct {
uint32_t baud; /**< Specifies the uart communication baud rate */
uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
uart_parity_t parity; /**< Specifies the parity mode */
uart_mode_t mode; /**< Specifies uart mode */
uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
} uart_init_t;
/**
* @brief UART handle structure definition
*/
typedef struct uart_handle_s {
UART_TypeDef *perh; /**< UART registers base address */
uart_init_t init; /**< UART communication parameters */
uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */
uint16_t tx_size; /**< UART Tx Transfer size */
uint16_t tx_count; /**< UART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */
uint16_t rx_size; /**< UART Rx Transfer size */
uint16_t rx_count; /**< UART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
uart_state_t state; /**< UART communication state */
uart_error_t err_code; /**< UART Error code */
void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */
} uart_handle_t;
/**
* @brief UART RS485 configure structure definition
*/
typedef struct {
type_func_t normal; /**< Normal mode */
type_func_t dir; /**< Auto-direction mode */
type_func_t invert; /**< Address detection invert */
uint8_t addr; /**< Address for compare */
} uart_rs485_config_t;
/**
* @brief LIN detection break length
*/
typedef enum {
LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */
LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */
} uart_lin_break_len_t;
/**
* @brief UART TXFIFO size
*/
typedef enum {
UART_TXFIFO_EMPTY = 0x0U, /**< Empty */
UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */
UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */
UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */
} uart_txfifo_t;
/**
* @brief UART RXFIFO size
*/
typedef enum {
UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
} uart_rxfifo_t;
/**
* @brief UART auto-baud mode
*/
typedef enum {
UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */
UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */
UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */
} uart_auto_baud_mode_t;
/**
* @brief UART status types
*/
typedef enum {
UART_STATUS_DR = (1U << 0), /**< Data ready */
UART_STATUS_OE = (1U << 1), /**< Overrun error */
UART_STATUS_PE = (1U << 2), /**< Parity error */
UART_STATUS_FE = (1U << 3), /**< Framing error */
UART_STATUS_BI = (1U << 4), /**< Break interrupt */
UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */
UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */
UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */
UART_STATUS_BUSY = (1U << 8), /**< UART busy */
UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */
UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */
UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */
UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */
UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */
UART_STATUS_CTS = (1U << 15), /**< Clear to send */
} uart_status_t;
/**
* @brief UART interrupt types
*/
typedef enum {
UART_IT_RXRD = (1U << 0), /**< Receive data available */
UART_IT_TXS = (1U << 1), /**< Tx empty status */
UART_IT_RXS = (1U << 2), /**< Rx line status */
UART_IT_MDS = (1U << 3), /**< Modem status */
UART_IT_RTO = (1U << 4), /**< Receiver timeout */
UART_IT_BZ = (1U << 5), /**< Busy status */
UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IT_LINBK = (1U << 8), /**< Lin break detection */
UART_IT_TC = (1U << 9), /**< Transmission complete */
UART_IT_EOB = (1U << 10), /**< End of block */
UART_IT_CM = (1U << 11), /**< Character match */
} uart_it_t;
/**
* @brief UART flags types
*/
typedef enum {
UART_IF_RXRD = (1U << 0), /**< Receive data available */
UART_IF_TXS = (1U << 1), /**< Tx empty status */
UART_IF_RXS = (1U << 2), /**< Rx line status */
UART_IF_MDS = (1U << 3), /**< Modem status */
UART_IF_RTO = (1U << 4), /**< Receiver timeout */
UART_IF_BZ = (1U << 5), /**< Busy status */
UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IF_LINBK = (1U << 8), /**< Lin break detection */
UART_IF_TC = (1U << 9), /**< Transmission complete */
UART_IF_EOB = (1U << 10), /**< End of block */
UART_IF_CM = (1U << 11), /**< Character match */
} uart_flag_t;
/**
* @}
*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_ALL(x) (((x) == UART0) || \
((x) == UART1) || \
((x) == UART2) || \
((x) == UART3))
#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \
((x) == UART_WORD_LENGTH_6B) || \
((x) == UART_WORD_LENGTH_7B) || \
((x) == UART_WORD_LENGTH_8B))
#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \
((x) == UART_STOP_BITS_2) || \
((x) == UART_STOP_BITS_0_5) || \
((x) == UART_STOP_BITS_1_5))
#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \
((x) == UART_PARITY_ODD) || \
((x) == UART_PARITY_EVEN))
#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \
((x) == UART_MODE_LIN) || \
((x) == UART_MODE_IrDA) || \
((x) == UART_MODE_RS485) || \
((x) == UART_MODE_HDSEL))
#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
(((x) == UART_HW_FLOW_CTL_DISABLE) || \
((x) == UART_HW_FLOW_CTL_ENABLE))
#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \
((x) == LIN_BREAK_LEN_11B))
#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \
((x) == UART_TXFIFO_2BYTE) || \
((x) == UART_TXFIFO_4BYTE) || \
((x) == UART_TXFIFO_8BYTE))
#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \
((x) == UART_RXFIFO_4BYTE) || \
((x) == UART_RXFIFO_8BYTE) || \
((x) == UART_RXFIFO_14BYTE))
#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \
((x) == UART_ABRMOD_1) || \
((x) == UART_ABRMOD_0_TO_1))
#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \
((x) == UART_STATUS_OE) || \
((x) == UART_STATUS_PE) || \
((x) == UART_STATUS_FE) || \
((x) == UART_STATUS_BI) || \
((x) == UART_STATUS_TBEM) || \
((x) == UART_STATUS_TEM) || \
((x) == UART_STATUS_RFE) || \
((x) == UART_STATUS_BUSY) || \
((x) == UART_STATUS_TFNF) || \
((x) == UART_STATUS_TFEM) || \
((x) == UART_STATUS_RFNE) || \
((x) == UART_STATUS_RFF) || \
((x) == UART_STATUS_DCTS) || \
((x) == UART_STATUS_CTS))
#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \
((x) == UART_IT_TXS) || \
((x) == UART_IT_RXS) || \
((x) == UART_IT_MDS) || \
((x) == UART_IT_RTO) || \
((x) == UART_IT_BZ) || \
((x) == UART_IT_ABE) || \
((x) == UART_IT_ABTO) || \
((x) == UART_IT_LINBK) || \
((x) == UART_IT_TC) || \
((x) == UART_IT_EOB) || \
((x) == UART_IT_CM))
#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \
((x) == UART_IF_TXS) || \
((x) == UART_IF_RXS) || \
((x) == UART_IF_MDS) || \
((x) == UART_IF_RTO) || \
((x) == UART_IF_BZ) || \
((x) == UART_IF_ABE) || \
((x) == UART_IF_ABTO) || \
((x) == UART_IF_LINBK) || \
((x) == UART_IF_TC) || \
((x) == UART_IF_EOB) || \
((x) == UART_IF_CM))
#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
#define IS_UART_DATA(x) ((x) <= 0x1FF)
#define UART_STATE_TX_MASK (1U << 4)
#define UART_STATE_RX_MASK (1U << 5)
/**
* @}
*/
/** @addtogroup UART_Public_Functions
* @{
*/
/** @addtogroup UART_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void ald_uart_init(uart_handle_t *hperh);
void ald_uart_reset(uart_handle_t *hperh);
void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_uart_dma_pause(uart_handle_t *hperh);
ald_status_t ald_uart_dma_resume(uart_handle_t *hperh);
ald_status_t ald_uart_dma_stop(uart_handle_t *hperh);
#endif
void ald_uart_irq_handler(uart_handle_t *hperh);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group3
* @{
*/
/* Peripheral Control functions */
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
void ald_uart_lin_send_break(uart_handle_t *hperh);
void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status);
flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group4
* @{
*/
/* Peripheral State and Errors functions */
uart_state_t ald_uart_get_state(uart_handle_t *hperh);
uint32_t ald_uart_get_error(uart_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_UART_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h
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/**
*********************************************************************************
*
* @file ald_wdt.h
* @brief Header file of WDT module driver.
*
* @version V1.0
* @date 18 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_WDT_H__
#define __ALD_WDT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup WDT
* @{
*/
/** @defgroup WDT_Public_Types WDT Public Types
* @{
*/
/**
* @brief Wwdt no dog window
*/
typedef enum {
WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */
WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */
WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */
WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */
} wwdt_win_t;
/**
* @}
*/
/**
* @defgroup WDT_Private_Macros WDT Private Macros
* @{
*/
#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
/**
* @}
*/
/**
* @addtogroup WDT_Private_Macros WDT Private Macros
* @{
*/
#define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \
(x == WWDT_WIN_50) || \
(x == WWDT_WIN_75) || \
(x == WWDT_WIN_00))
#define IS_FUNC_STATE(x) (((x) == DISABLE) || \
((x) == ENABLE))
/**
* @}
*/
/** @addtogroup WWDT_Public_Functions
* @{
*/
void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt);
void ald_wwdt_start(void);
uint32_t ald_wwdt_get_value(void);
it_status_t ald_wwdt_get_flag_status(void);
void ald_wwdt_clear_flag_status(void);
void ald_wwdt_feed_dog(void);
/**
* @}
*/
/** @addtogroup IWDT_Public_Functions
* @{
*/
void ald_iwdt_init(uint32_t load, type_func_t interrupt);
void ald_iwdt_start(void);
uint32_t ald_iwdt_get_value(void);
it_status_t ald_iwdt_get_flag_status(void);
void ald_iwdt_clear_flag_status(void);
void ald_iwdt_feed_dog(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_WDT_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h
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/**
*********************************************************************************
*
* @file type.h
* @brief define type
*
* @version V1.0
* @date 17 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __TYPE_H__
#define __TYPE_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#if defined (__CC_ARM)
#define __INLINE__ __inline
#define __STATIC_INLINE__ static __inline
#else
#define __INLINE__ inline
#define __STATIC_INLINE__ static inline
#endif
#define __isr__
typedef enum {
RESET = 0x0U,
SET = 0x1U,
} flag_status_t, it_status_t;
typedef enum {
BIT_RESET = 0x0U,
BIT_SET = 0x1U,
} bit_status_t;
typedef enum {
DISABLE = 0x0U,
ENABLE = 0x1U,
} type_func_t;
#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE))
typedef enum {
FALSE = 0x0U,
TRUE = 0x1U,
} type_bool_t;
typedef enum {
UNLOCK = 0x0U,
LOCK = 0x1U,
} lock_state_t;
#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK))
#define BIT(x) ((1U << (x)))
#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
#define SET_BIT(reg, bit) ((reg) |= (bit))
#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
#define READ_BIT(reg, bit) ((reg) & (bit))
#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s))
#define CLEAR_REG(reg) ((reg) = (0x0))
#define WRITE_REG(reg, val) ((reg) = (val))
#define READ_REG(reg) ((reg))
#define MODIFY_REG(reg, clearmask, setmask) \
WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
#define UNUSED(x) ((void)(x))
#ifdef USE_ASSERT
#define assert_param(x) \
do { \
if (!(x)) { \
__disable_irq(); \
while (1) \
; \
} \
} while (0)
#else
#define assert_param(x)
#endif
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */
__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
{
uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
*((volatile uint32_t *)tmp) = (uint32_t)val;
}
__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
{
uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
*((volatile uint32_t *)tmp) = (uint32_t)val;
}
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TYPE_H__ */
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h
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/**
*********************************************************************************
*
* @file utils.h
* @brief This file contains the Utilities functions/types for the driver.
*
* @version V1.0
* @date 07 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __UTILS_H__
#define __UTILS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdlib.h>
#include "ald_conf.h"
#include "type.h"
#include "es32f033x.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup UTILS
* @{
*/
/** @defgroup ALD_Public_Types Public Types
* @{
*/
/**
* @brief SysTick interval
*/
extern uint32_t __systick_interval;
/**
* @brief ALD Status structures definition
*/
typedef enum {
OK = 0x0U, /**< Status: OK */
ERROR = 0x1U, /**< Status: ERROR */
BUSY = 0x2U, /**< Status: BUSY */
TIMEOUT = 0x3U, /**< Status: TIMEOUT */
} ald_status_t;
/**
* @brief SysTick interval definition
*/
typedef enum {
SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */
SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */
SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */
SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */
} systick_interval_t;
/**
* @}
*/
/** @defgroup ALD_Public_Macros Public Macros
* @{
*/
#define ALD_MAX_DELAY 0xFFFFFFFFU
#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET)
#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET)
#define RESET_HANDLE_STATE(x) ((x)->state = 0)
#define __LOCK(x) \
do { \
if ((x)->lock == LOCK) { \
return BUSY; \
} \
else { \
(x)->lock = LOCK; \
} \
} while (0)
#define __UNLOCK(x) \
do { \
(x)->lock = UNLOCK; \
} while (0)
/**
* @}
*/
/** @defgroup ALD_Private_Macros Private Macros
* @{
*/
#define MCU_UID0_ADDR 0x000403E0U
#define MCU_UID1_ADDR 0x000403E8U
#define MCU_UID2_ADDR 0x000403F0U
#define MCU_CHIPID_ADDR 0x000403F8U
#define IS_PRIO(x) ((x) < 4)
#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \
((x) == SYSTICK_INTERVAL_10MS) || \
((x) == SYSTICK_INTERVAL_100MS) || \
((x) == SYSTICK_INTERVAL_1000MS))
/**
* @}
*/
/** @addtogroup ALD_Public_Functions
* @{
*/
/** @addtogroup ALD_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void ald_cmu_init(void);
void ald_tick_init(uint32_t prio);
void ald_systick_interval_select(systick_interval_t value);
/**
* @}
*/
/** @addtogroup ALD_Public_Functions_Group2
* @{
*/
/* Peripheral Control functions */
void ald_inc_tick_weak(void);
void ald_delay_ms(__IO uint32_t delay);
uint32_t ald_get_tick(void);
void ald_suspend_tick(void);
void ald_resume_tick(void);
void ald_systick_irq_cbk(void);
void ald_inc_tick(void);
uint32_t ald_get_ald_version(void);
ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout);
void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status);
uint32_t ald_mcu_get_tick(void);
uint32_t ald_mcu_get_cpu_id(void);
void ald_mcu_get_uid(uint8_t *buf);
uint32_t ald_mcu_get_chipid(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __UTILS_H__ */

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