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Merge branch 'master' into gitee_master

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This commit is contained in:
aozima
2020-08-14 16:29:11 +08:00
parent 6bf76a375c 5b94c1482e
commit 79fd12842b
151 changed files with 34970 additions and 6369 deletions
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bsp/essemi/es8p508x/SConscript
+2 -1
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@@ -1,8 +1,9 @@
# RT-Thread SConscript bridge
import os
from building import *
objs = []
cwd = GetCurrentDir()
cwd = GetCurrentDir()
list = os.listdir(cwd)
for d in list:
bsp/imx6ul/SConstruct
+1
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@@ -20,6 +20,7 @@ env = Environment(tools = ['mingw'],
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py
+4 -1
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@@ -53,6 +53,9 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
AFLAGS += ' -D__STARTUP_CLEAR_BSS'
if BUILD == 'debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
@@ -60,7 +63,7 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -O2 -Os'
POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
# module setting
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
bsp/imxrt/imxrt1064-nxp-evk/README.md
+2 -2
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@@ -71,7 +71,7 @@
### 快速上手
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，暂不支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，以及GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
@@ -115,4 +115,4 @@ msh >
维护人:
- [王强](https://github.com/xfwangqiang), 邮箱：<164877907@qq.com>
- [王强](https://github.com/xfwangqiang, https://gitee.com/xfwangqiang), 邮箱：<164877907@qq.com>
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py
+3
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@@ -53,6 +53,9 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
AFLAGS += ' -D__STARTUP_CLEAR_BSS'
if BUILD == 'debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
bsp/nrf5x/libraries/drivers/SConscript
+4
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@@ -19,8 +19,12 @@ if GetDepend(['BSP_USING_QSPI_FLASH']):
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c']
path = [cwd]
bsp/nrf5x/libraries/drivers/drv_gpio.c
-16
View File
@@ -46,22 +46,6 @@ static const struct pin_index pins[] =
__NRF5X_PIN(29, 0, 29),
__NRF5X_PIN(30, 0, 30),
__NRF5X_PIN(31, 0, 31),
__NRF5X_PIN(32, 1, 0 ),
__NRF5X_PIN(33, 1, 1 ),
__NRF5X_PIN(34, 1, 2 ),
__NRF5X_PIN(35, 1, 3 ),
__NRF5X_PIN(36, 1, 4 ),
__NRF5X_PIN(37, 1, 5 ),
__NRF5X_PIN(38, 1, 6 ),
__NRF5X_PIN(39, 1, 7 ),
__NRF5X_PIN(40, 1, 8 ),
__NRF5X_PIN(41, 1, 9 ),
__NRF5X_PIN(42, 1, 10),
__NRF5X_PIN(43, 1, 11),
__NRF5X_PIN(44, 1, 12),
__NRF5X_PIN(45, 1, 13),
__NRF5X_PIN(46, 1, 14),
__NRF5X_PIN(47, 1, 15),
};
/* EVENTS_IN[n](n=0..7) and EVENTS_PORT */
bsp/nrf5x/libraries/drivers/drv_gpio.h
-1
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@@ -13,7 +13,6 @@
#include <board.h>
#include <rtdevice.h>
#include <nrf52840.h>
#include <hal/nrf_gpio.h>
#include <drivers/include/nrfx_gpiote.h>
bsp/nrf5x/libraries/drivers/drv_pwm.c
+432
View File
@@ -0,0 +1,432 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-26 supperthomas first version
*
*/
#include <board.h>
#include "rtdevice.h"
#include "rtservice.h"
#ifdef RT_USING_PWM
#include <nrfx_pwm.h>
struct mcu_pwm
{
struct rt_device_pwm pwm_device;
nrfx_pwm_t *pwm_handle;
nrf_pwm_values_individual_t m_demo1_seq_values;
nrf_pwm_sequence_t m_demo1_seq;
rt_uint8_t channel;
char *name;
rt_uint64_t pwm_src_clk;
uint8_t channel_0_pin;
uint8_t channel_1_pin;
uint8_t channel_2_pin;
uint8_t channel_3_pin;
};
enum
{
#ifdef BSP_USING_PWM0
PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
PWM3_INDEX,
#endif
};
#ifdef BSP_USING_PWM0
static nrfx_pwm_t m_pwm0 = NRFX_PWM_INSTANCE(0);
#define PWM0_CONFIG \
{ \
.pwm_handle = &m_pwm0, \
.name = "pwm0", \
.pwm_src_clk = 1000000, \
}
#endif
#ifdef BSP_USING_PWM1
static nrfx_pwm_t m_pwm1 = NRFX_PWM_INSTANCE(1);
#define PWM1_CONFIG \
{ \
.pwm_handle = &m_pwm1, \
.name = "pwm1", \
.pwm_src_clk = 1000000, \
}
#endif
#ifdef BSP_USING_PWM2
static nrfx_pwm_t m_pwm2 = NRFX_PWM_INSTANCE(2);
#define PWM2_CONFIG \
{ \
.pwm_handle = &m_pwm2, \
.name = "pwm2", \
.pwm_src_clk = 1000000, \
}
#endif
#ifdef BSP_USING_PWM3
static nrfx_pwm_t m_pwm3 = NRFX_PWM_INSTANCE(3);
#define PWM3_CONFIG \
{ \
.pwm_handle = &m_pwm3, \
.name = "pwm3", \
.pwm_src_clk = 1000000, \
}
#endif
static struct mcu_pwm mcu_pwm_obj[] =
{
#ifdef BSP_USING_PWM0
PWM0_CONFIG,
#endif
#ifdef BSP_USING_PWM1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CONFIG,
#endif
};
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
static struct rt_pwm_ops drv_ops =
{
drv_pwm_control
};
static rt_err_t drv_pwm_enable(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
if (!enable)
{
nrfx_pwm_stop(p_mcu->pwm_handle, true);
}
else
{
(void)nrfx_pwm_simple_playback(p_mcu->pwm_handle, &p_mcu->m_demo1_seq, 1, NRFX_PWM_FLAG_LOOP);
}
return RT_EOK;
}
uint8_t mcu_get_channel_number(uint8_t channel)
{
if (channel & 0x01)
{
return 0;
}
else if (channel & 0x02)
{
return 1;
}
else if (channel & 0x04)
{
return 2;
}
else if (channel & 0x08)
{
return 3;
}
return 0;
}
static rt_err_t drv_pwm_get(struct mcu_pwm *pwm_handle, struct rt_pwm_configuration *configuration)
{
rt_uint8_t channel_number = mcu_get_channel_number(configuration->channel);
uint8_t tick_pscond;
tick_pscond = pwm_handle->pwm_src_clk / 1000000UL;
configuration->period = pwm_handle->pwm_handle->p_registers->COUNTERTOP * 1000UL / tick_pscond;
configuration->pulse = pwm_handle->pwm_handle->p_registers->SEQ[channel_number].PTR / tick_pscond;
return RT_EOK;
}
static void nrfx_set_prioid(nrfx_pwm_t *pwm_handle, uint32_t perioid)
{
pwm_handle->p_registers->COUNTERTOP = perioid;
}
static rt_err_t drv_pwm_set(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
uint8_t tick_pscond;
tick_pscond = p_mcu->pwm_src_clk / 1000000UL;
p_mcu->pwm_handle->p_registers->COUNTERTOP = (unsigned long long)configuration->period * tick_pscond;
if (configuration->channel & 0x01)
{
p_mcu->m_demo1_seq_values.channel_0 = configuration->pulse;
}
if (configuration->channel & 0x02)
{
p_mcu->m_demo1_seq_values.channel_1 = configuration->pulse;
}
if (configuration->channel & 0x04)
{
p_mcu->m_demo1_seq_values.channel_2 = configuration->pulse;
}
if (configuration->channel & 0x08)
{
p_mcu->m_demo1_seq_values.channel_3 = configuration->pulse;
}
return RT_EOK;
}
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
void *pwm_handle = (void *)device->parent.user_data;
nrfx_pwm_t *p_handle = (nrfx_pwm_t *)pwm_handle;
struct mcu_pwm *p_mcu = rt_container_of(p_handle, struct mcu_pwm, pwm_handle);
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(p_mcu, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(p_mcu, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(p_mcu, configuration);
case PWM_CMD_GET:
return drv_pwm_get(p_mcu, configuration);
default:
return RT_EINVAL;
}
}
static rt_err_t mcu_hw_pwm_init(struct mcu_pwm *device)
{
#define NRFX_PWM_PIN_INVERTED 0x80
#define _PRIO_APP_LOWEST 7
nrfx_pwm_config_t config0 =
{
.irq_priority = _PRIO_APP_LOWEST,
.base_clock = NRF_PWM_CLK_1MHz, //default value
.count_mode = NRF_PWM_MODE_UP,
.top_value = 5000, //default vaule
.load_mode = NRF_PWM_LOAD_INDIVIDUAL,
.step_mode = NRF_PWM_STEP_AUTO
};
rt_err_t result = RT_EOK;
if (device->pwm_src_clk == 1000000)
{
config0.base_clock = NRF_PWM_CLK_1MHz;
}
else if (device->pwm_src_clk == 2000000)
{
config0.base_clock = NRF_PWM_CLK_2MHz;
}
else if (device->pwm_src_clk == 8000000)
{
config0.base_clock = NRF_PWM_CLK_8MHz;
}
else
{
config0.base_clock = NRF_PWM_CLK_1MHz;
}
if (device->channel & 0x01)
{
config0.output_pins[0] = device->channel_0_pin | NRFX_PWM_PIN_INVERTED;
}
if (device->channel & 0x02)
{
config0.output_pins[1] = device->channel_1_pin | NRFX_PWM_PIN_INVERTED;
}
if (device->channel & 0x04)
{
config0.output_pins[2] = device->channel_2_pin | NRFX_PWM_PIN_INVERTED;
}
if (device->channel & 0x08)
{
config0.output_pins[3] = device->channel_3_pin | NRFX_PWM_PIN_INVERTED;
}
device->m_demo1_seq.values.p_individual = &device->m_demo1_seq_values;
device->m_demo1_seq.length = NRF_PWM_VALUES_LENGTH(device->m_demo1_seq_values),
nrfx_pwm_init(device->pwm_handle, &config0, NULL, NULL);
return result;
}
static void pwm_get_channel(void)
{
#ifdef BSP_USING_PWM0_CH0
mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 0;
mcu_pwm_obj[PWM0_INDEX].channel_0_pin = BSP_USING_PWM0_CH0;
#endif
#ifdef BSP_USING_PWM0_CH1
mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 1;
mcu_pwm_obj[PWM0_INDEX].channel_1_pin = BSP_USING_PWM0_CH1;
#endif
#ifdef BSP_USING_PWM0_CH2
mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 2;
mcu_pwm_obj[PWM0_INDEX].channel_2_pin = BSP_USING_PWM0_CH2;
#endif
#ifdef BSP_USING_PWM0_CH3
mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 3;
mcu_pwm_obj[PWM0_INDEX].channel_3_pin = BSP_USING_PWM0_CH3;
#endif
#ifdef BSP_USING_PWM1_CH0
mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
mcu_pwm_obj[PWM1_INDEX].channel_0_pin = BSP_USING_PWM1_CH0;
#endif
#ifdef BSP_USING_PWM1_CH1
mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
mcu_pwm_obj[PWM1_INDEX].channel_1_pin = BSP_USING_PWM1_CH1;
#endif
#ifdef BSP_USING_PWM1_CH2
mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
mcu_pwm_obj[PWM1_INDEX].channel_2_pin = BSP_USING_PWM1_CH2;
#endif
#ifdef BSP_USING_PWM1_CH3
mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
mcu_pwm_obj[PWM1_INDEX].channel_3_pin = BSP_USING_PWM1_CH3;
#endif
#ifdef BSP_USING_PWM2_CH0
mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
mcu_pwm_obj[PWM2_INDEX].channel_0_pin = BSP_USING_PWM2_CH0;
#endif
#ifdef BSP_USING_PWM2_CH1
mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
mcu_pwm_obj[PWM2_INDEX].channel_1_pin = BSP_USING_PWM2_CH1;
#endif
#ifdef BSP_USING_PWM2_CH2
mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
mcu_pwm_obj[PWM2_INDEX].channel_2_pin = BSP_USING_PWM2_CH2;
#endif
#ifdef BSP_USING_PWM2_CH3
mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
mcu_pwm_obj[PWM2_INDEX].channel_3_pin = BSP_USING_PWM2_CH3;
#endif
#ifdef BSP_USING_PWM3_CH0
mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
mcu_pwm_obj[PWM3_INDEX].channel_0_pin = BSP_USING_PWM3_CH0;
#endif
#ifdef BSP_USING_PWM3_CH1
mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
mcu_pwm_obj[PWM3_INDEX].channel_1_pin = BSP_USING_PWM3_CH1;
#endif
#ifdef BSP_USING_PWM3_CH2
mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
mcu_pwm_obj[PWM3_INDEX].channel_2_pin = BSP_USING_PWM3_CH2;
#endif
#ifdef BSP_USING_PWM3_CH3
mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
mcu_pwm_obj[PWM3_INDEX].channel_3_pin = BSP_USING_PWM3_CH3;
#endif
}
static int mcu_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
pwm_get_channel();
for (i = 0; i < sizeof(mcu_pwm_obj) / sizeof(mcu_pwm_obj[0]); i++)
{
/* pwm init */
if (mcu_hw_pwm_init(&mcu_pwm_obj[i]) != RT_EOK)
{
rt_kprintf("\r\n %s init failed", mcu_pwm_obj[i].name);
result = -RT_ERROR;
goto __exit;
}
else
{
rt_kprintf("\r\n %s init success", mcu_pwm_obj[i].name);
/* register pwm device */
if (rt_device_pwm_register(&mcu_pwm_obj[i].pwm_device, mcu_pwm_obj[i].name, &drv_ops, &mcu_pwm_obj[i].pwm_handle) == RT_EOK)
{
rt_kprintf("\r\n %s register success", mcu_pwm_obj[i].name);
}
else
{
rt_kprintf("\r\n %s register failed", mcu_pwm_obj[i].name);
result = -RT_ERROR;
}
}
}
__exit:
return result;
}
INIT_DEVICE_EXPORT(mcu_pwm_init);
/* test example */
#define PWM_DEV_NAME "pwm0" /* PWM name*/
#define PWM_DEV_CHANNEL 15 /* PWM channel */
struct rt_device_pwm *pwm_dev;
static int pwm_led_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse, dir;
period = 50000; /* 50ms*/
dir = 1;
pulse = 0;
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
return RT_ERROR;
}
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
while (1)
{
rt_thread_mdelay(50);
if (dir)
{
pulse += 500;
}
else
{
pulse -= 500;
}
if (pulse >= period)
{
dir = 0;
}
if (0 == pulse)
{
dir = 1;
}
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
}
}
MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
#endif
bsp/nrf5x/nrf52832/.config
+57 -6
View File
@@ -74,7 +74,9 @@ CONFIG_RT_VER_NUM=0x40003
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
# CONFIG_RT_USING_USER_MAIN is not set
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
@@ -112,7 +114,7 @@ CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
@@ -120,6 +122,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
@@ -192,12 +195,15 @@ CONFIG_RT_USING_LIBC=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@@ -224,6 +230,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -236,9 +243,10 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@@ -257,6 +265,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
#
# security packages
@@ -265,6 +274,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@@ -299,6 +309,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
@@ -309,6 +321,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -321,6 +334,9 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# peripheral libraries and drivers
@@ -338,6 +354,13 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
CONFIG_PKG_USING_NRFX=y
CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
CONFIG_PKG_USING_NRFX_V210=y
# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set
CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@@ -355,13 +378,19 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_NORDIC_SDK is not set
# CONFIG_PKG_USING_NORDIC_SDK_V100 is not set
# CONFIG_PKG_USING_NORDIC_SDK_LATEST_VERSION is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
#
# miscellaneous packages
@@ -398,17 +427,39 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_NRF52832=y
CONFIG_SOC_NORDIC=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_JLINK_TO_USART is not set
# CONFIG_BSP_USING_QSPI_FLASH is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SOFTDEVICE is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_UART0_RX_PIN=8
CONFIG_BSP_UART0_TX_PIN=6
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
#
# On-chip flash config
#
CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
CONFIG_MCU_FLASH_SIZE_KB=1024
CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
CONFIG_MCU_SRAM_SIZE_KB=256
CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
bsp/nrf5x/nrf52832/SConstruct
+3
View File
@@ -50,5 +50,8 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
# include cmsis
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/nrf5x/nrf52832/applications/application.c
+20 -36
View File
@@ -1,48 +1,32 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-03-01 Yangfs the first version
* 2015-03-27 Bernard code cleanup.
* 2020-04-29 supperthomas first version
*
*/
/**
* @addtogroup NRF52832
*/
/*@{*/
#include <rtthread.h>
#include <rtdevice.h>
#define DK_BOARD_LED_1 17
#define DK_BOARD_LED_2 18
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <shell.h>
#endif
void rt_init_thread_entry(void* parameter)
int main(void)
{
extern rt_err_t ble_init(void);
ble_init();
int count = 1;
rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}
int rt_application_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024,
RT_THREAD_PRIORITY_MAX / 3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
/*@}*/
bsp/nrf5x/nrf52832/applications/ble_nus_app.c
-670
View File
File diff suppressed because it is too large Load Diff
bsp/nrf5x/nrf52832/applications/sdk_config.h
-3991
View File
File diff suppressed because it is too large Load Diff
bsp/nrf5x/nrf52832/applications/startup.c
-98
View File
@@ -1,98 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-03-01 Yangfs the first version
* 2015-03-27 Bernard code cleanup.
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
/**
* @addtogroup NRF52832
*/
/*@{*/
extern int rt_application_init(void);
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define NRF_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define NRF_SRAM_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define NRF_SRAM_BEGIN (&__bss_end)
#endif
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)NRF_SRAM_BEGIN, (void*)CHIP_SRAM_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_init();
#endif
/* init application */
rt_application_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
// rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
/*@}*/
bsp/nrf5x/nrf52832/board/Kconfig
+275 -3
View File
@@ -2,21 +2,293 @@ menu "Hardware Drivers Config"
config SOC_NRF52832
bool
config SOC_NRF52832
select RT_USING_COMPONENTS_INIT
# select RT_USING_USER_MAIN
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config SOC_NORDIC
bool
config SOC_NORDIC
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_JLINK_TO_USART
bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
select BSP_USING_UART
select BSP_USING_UART0
default y
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_PWM
bool "Enable PWM"
select RT_USING_PWM
default n
if BSP_USING_PWM
config NRFX_PWM_ENABLED
int
default 1
config BSP_USING_PWM0
bool "Enable PWM0 bus"
default y
if BSP_USING_PWM0
config NRFX_PWM0_ENABLED
int
default 1
config BSP_USING_PWM0_CH0
int "PWM0 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM0_CH1
int "PWM0 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM0_CH2
int "PWM0 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM0_CH3
int "PWM0 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM1
bool "Enable PWM1 bus"
default n
if BSP_USING_PWM1
config NRFX_PWM1_ENABLED
int
default 1
config BSP_USING_PWM1_CH0
int "PWM1 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM1_CH1
int "PWM1 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM1_CH2
int "PWM1 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM1_CH3
int "PWM1 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM2
bool "Enable PWM2 bus"
default n
if BSP_USING_PWM2
config NRFX_PWM2_ENABLED
int
default 1
config BSP_USING_PWM2_CH0
int "PWM2 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM2_CH1
int "PWM2 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM2_CH2
int "PWM2 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM2_CH3
int "PWM2 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM3
bool "Enable PWM3 bus"
default n
if BSP_USING_PWM3
config NRFX_PWM3_ENABLED
int
default 1
config BSP_USING_PWM3_CH0
int "PWM3 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM3_CH1
int "PWM3 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM3_CH2
int "PWM3 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM3_CH3
int "PWM3 channel 3 pin number set"
range 0 47
default 16
endif
endif
menuconfig BSP_USING_SOFTDEVICE
bool "Enable NRF SOFTDEVICE"
select PKG_USING_NRF5X_SDK
select NRFX_CLOCK_ENABLED
default n
if BSP_USING_SOFTDEVICE
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_RTC_ENABLED
int
default 1
config NRFX_RTC1_ENABLED
int
default 1
config NRF_CLOCK_ENABLED
int
default 1
config NRF_SDH_BLE_ENABLED
int
default 1
config NRF_SDH_ENABLED
int
default 1
config NRF_SDH_SOC_ENABLED
int
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default y
if BSP_USING_UART0
config BSP_UART0_RX_PIN
int "uart0 rx pin number"
range 0 31
default 8
config BSP_UART0_TX_PIN
int "uart0 tx pin number"
range 0 31
default 6
endif
config BSP_USING_UART1
bool "Enable UART1"
default n
endif
config BSP_USING_SPI
bool "Enable SPI"
select RT_USING_PIN
default y
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 bus"
default y
if BSP_USING_SPI0
config BSP_SPI0_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI0_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI0_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI0_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
config BSP_USING_SPI1
bool "Enable SPI1 bus"
default n
if BSP_USING_SPI1
config BSP_SPI1_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI1_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI1_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI1_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
config BSP_USING_SPI2
bool "Enable SPI2 bus"
default n
if BSP_USING_SPI2
config BSP_SPI2_SCK_PIN
int "SPI0 sck pin number set"
range 0 47
default 28
config BSP_SPI2_MOSI_PIN
int "SPI0 mosi pin number set"
range 0 47
default 29
config BSP_SPI2_MISO_PIN
int "SPI0 miso pin number set"
range 0 47
default 30
config BSP_SPI2_SS_PIN
int "SPI0 ss pin number set"
range 0 47
default 31
endif
endif
config BSP_USING_ON_CHIP_FLASH
select PKG_USING_FAL
bool "Enable on-chip FLASH"
default n
menu "On-chip flash config"
config MCU_FLASH_START_ADDRESS
hex "MCU FLASH START ADDRESS"
default 0x00000000
config MCU_FLASH_SIZE_KB
int "MCU FLASH SIZE, MAX size 1024 KB"
range 1 1024
default 1024
config MCU_SRAM_START_ADDRESS
hex "MCU RAM START ADDRESS"
default 0x20000000
config MCU_SRAM_SIZE_KB
int "MCU RAM SIZE, MAX size 256 KB"
range 1 256
default 256
config MCU_FLASH_PAGE_SIZE
hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
range 0x1000 0x1000
default 0x1000
endmenu
endmenu
endmenu
bsp/nrf5x/nrf52832/board/SConscript
+2 -1
View File
@@ -5,6 +5,7 @@ from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
define = ['USE_APP_CONFIG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,)
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define)
Return('group')
bsp/nrf5x/nrf52832/board/app_config.h
+4
View File
@@ -0,0 +1,4 @@
#ifndef APP_CONFIG_H
#define APP_CONFIG_H
#endif //APP_CONFIG_H
bsp/nrf5x/nrf52832/board/board.c
+94 -189
View File
@@ -1,17 +1,60 @@
#include "board.h"
#include "drv_uart.h"
#include "app_util_platform.h"
#include "nrf_drv_common.h"
#include "nrf_systick.h"
#include "nrf_rtc.h"
#include "nrf_drv_clock.h"
#include "softdevice_handler.h"
#include "nrf_drv_uart.h"
#include "nrf_gpio.h"
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-29 supperthomas first version
*
*/
#include <rtthread.h>
#include <rthw.h>
#include <nrfx_systick.h>
#include "board.h"
#include "drv_uart.h"
#ifdef BSP_USING_SOFTDEVICE
#include <nrfx_rtc.h>
#include <nrfx_clock.h>
#include "app_error.h"
#include "nrf_drv_clock.h"
const nrfx_rtc_t rtc = NRFX_RTC_INSTANCE(1); /**< Declaring an instance of nrf_drv_rtc for RTC0. */
static void rtc_handler(nrfx_rtc_int_type_t int_type)
{
if (int_type == NRFX_RTC_INT_TICK)
{
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
}
#else
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
#endif
void SysTick_Configuration(void)
{
#ifdef BSP_USING_SOFTDEVICE
nrf_drv_clock_init();
nrf_drv_clock_lfclk_request(NULL);
uint32_t err_code;
#define TICK_RATE_HZ RT_TICK_PER_SECOND
#define SYSTICK_CLOCK_HZ ( 32768UL )
@@ -19,202 +62,49 @@
/* IRQn used by the selected RTC */
#define NRF_RTC_IRQn RTC1_IRQn
/* Constants required to manipulate the NVIC. */
#define NRF_RTC_PRESCALER ( (uint32_t) (ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
/* Maximum RTC ticks */
#define NRF_RTC_MAXTICKS ((1U<<24)-1U)
#define NRF_RTC_PRESCALER ( (uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG;
config.prescaler = NRF_RTC_PRESCALER;
static volatile uint32_t m_tick_overflow_count = 0;
#define NRF_RTC_BITWIDTH 24
#define OSTick_Handler RTC1_IRQHandler
#define EXPECTED_IDLE_TIME_BEFORE_SLEEP 2
err_code = nrfx_rtc_init(&rtc, &config, rtc_handler);
// APP_ERROR_CHECK(err_code);
nrfx_rtc_tick_enable(&rtc, true);
#define COMPARE_COUNTERTIME (3UL) /**< Get Compare event COMPARE_TIME seconds after the counter starts from 0. */
//Set compare channel to trigger interrupt after COMPARE_COUNTERTIME seconds
err_code = nrfx_rtc_cc_set(&rtc, 0, COMPARE_COUNTERTIME * 8, true);
// APP_ERROR_CHECK(err_code);
void SysTick_Configuration(void)
{
nrf_drv_clock_lfclk_request(NULL);
//Power on RTC instance
nrfx_rtc_enable(&rtc);
#else
/* Set interrupt priority */
NVIC_SetPriority(SysTick_IRQn, 0xf);
/* Configure SysTick to interrupt at the requested rate. */
nrf_rtc_prescaler_set(NRF_RTC_REG, NRF_RTC_PRESCALER);
nrf_rtc_int_enable (NRF_RTC_REG, RTC_INTENSET_TICK_Msk);
nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_CLEAR);
nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_START);
nrf_rtc_event_enable(NRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk);
NVIC_SetPriority(NRF_RTC_IRQn, 0xF);
NVIC_EnableIRQ(NRF_RTC_IRQn);
}
static rt_tick_t _tick_distance(void)
{
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
uint32_t systick_counter = nrf_rtc_counter_get(NRF_RTC_REG);
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
/* check for overflow in TICK counter */
if(nrf_rtc_event_pending(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW))
{
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW);
m_tick_overflow_count++;
}
return ((m_tick_overflow_count << NRF_RTC_BITWIDTH) + systick_counter) - rt_tick_get();
}
void OSTick_Handler( void )
{
uint32_t diff;
/* enter interrupt */
rt_interrupt_enter();
diff = _tick_distance();
while((diff--) > 0)
{
if (rt_thread_self() != RT_NULL)
{
rt_tick_increase();
}
}
/* leave interrupt */
rt_interrupt_leave();
}
static void _wakeup_tick_adjust(void)
{
uint32_t diff;
uint32_t level;
level = rt_hw_interrupt_disable();
diff = _tick_distance();
rt_tick_set(rt_tick_get() + diff);
if (rt_thread_self() != RT_NULL)
{
struct rt_thread *thread;
/* check time slice */
thread = rt_thread_self();
if (thread->remaining_tick <= diff)
{
/* change to initialized tick */
thread->remaining_tick = thread->init_tick;
/* yield */
rt_thread_yield();
}
else
{
thread->remaining_tick -= diff;
}
/* check timer */
rt_timer_check();
}
rt_hw_interrupt_enable(level);
}
static void _sleep_ongo( uint32_t sleep_tick )
{
uint32_t enterTime;
uint32_t entry_tick;
/* Make sure the SysTick reload value does not overflow the counter. */
if ( sleep_tick > NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP )
{
sleep_tick = NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP;
}
rt_enter_critical();
enterTime = nrf_rtc_counter_get(NRF_RTC_REG);
{
uint32_t wakeupTime = (enterTime + sleep_tick) & NRF_RTC_MAXTICKS;
/* Stop tick events */
nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
/* Configure CTC interrupt */
nrf_rtc_cc_set(NRF_RTC_REG, 0, wakeupTime);
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
nrf_rtc_int_enable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
entry_tick = rt_tick_get();
__DSB();
if ( sleep_tick > 0 )
{
#ifdef SOFTDEVICE_PRESENT
if (softdevice_handler_is_enabled())
{
uint32_t err_code = sd_app_evt_wait();
APP_ERROR_CHECK(err_code);
}
else
nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
nrf_systick_val_clear();
nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
| NRF_SYSTICK_CSR_ENABLE);
#endif
{
/* No SD - we would just block interrupts globally.
* BASEPRI cannot be used for that because it would prevent WFE from wake up.
*/
do{
__WFE();
} while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1]));
}
}
nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
_wakeup_tick_adjust();
/* Correct the system ticks */
{
nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
nrf_rtc_int_enable (NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
/* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */
NVIC_ClearPendingIRQ(NRF_RTC_IRQn);
}
// rt_kprintf("entry tick:%u, expected:%u, current tick:%u\n", entry_tick, sleep_tick, rt_tick_get());
}
rt_exit_critical();
}
void rt_hw_system_powersave(void)
{
uint32_t sleep_tick;
sleep_tick = rt_timer_next_timeout_tick() - rt_tick_get();
if ( sleep_tick >= EXPECTED_IDLE_TIME_BEFORE_SLEEP)
{
// rt_kprintf("sleep entry:%u\n", rt_tick_get());
_sleep_ongo( sleep_tick );
}
}
void rt_hw_board_init(void)
{
rt_hw_interrupt_enable(0);
// sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
/* Activate deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
nrf_drv_clock_init();
// nrf_drv_clock_hfclk_request(0);
SysTick_Configuration();
rt_thread_idle_sethook(rt_hw_system_powersave);
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
@@ -223,5 +113,20 @@ void rt_hw_board_init(void)
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef BSP_USING_SOFTDEVICE
extern uint32_t Image$$RW_IRAM1$$Base;
uint32_t const *const m_ram_start = &Image$$RW_IRAM1$$Base;
if ((uint32_t)m_ram_start == 0x20000000)
{
rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
while (1);
}
else
{
rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
}
#endif
}
bsp/nrf5x/nrf52832/board/board.h
+18 -2
View File
@@ -2,10 +2,26 @@
#define _BOARD_H_
#include <rtthread.h>
#include <rthw.h>
#include "nrf.h"
#define CHIP_SRAM_END (0x20000000 + 64*1024)
#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
#define MCU_SRAM_END_ADDRESS (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (0x20000000 + 64*1024)
void rt_hw_board_init(void);
bsp/nrf5x/nrf52832/board/linker_scripts/link.sct
+3 -3
View File
@@ -2,13 +2,13 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x0001F000 0x00061000 { ; load region size_region
ER_IROM1 0x0001F000 0x00061000 { ; load address = execution address
LR_IROM1 0x00000000 0x100000 { ; load region size_region
ER_IROM1 0x00000000 0x100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200025F8 0x0000DA08 { ; RW data
RW_IRAM1 0x20000000 0x40000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/nrf5x/nrf52832/board/nrfx_config.h
+47
View File
@@ -0,0 +1,47 @@
/**
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_CONFIG_H__
#define NRFX_CONFIG_H__
// TODO - temporary redirection
#include <sdk_config.h>
#endif // NRFX_CONFIG_H__
bsp/nrf5x/nrf52832/board/nrfx_glue.h
+269
View File
@@ -0,0 +1,269 @@
/*
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRFX_GLUE_H__
#define NRFX_GLUE_H__
// THIS IS A TEMPLATE FILE.
// It should be copied to a suitable location within the host environment into
// which nrfx is integrated, and the following macros should be provided with
// appropriate implementations.
// And this comment should be removed from the customized file.
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "nrf.h"
/**
* @defgroup nrfx_glue nrfx_glue.h
* @{
* @ingroup nrfx
*
* @brief This file contains macros that should be implemented according to
* the needs of the host environment into which @em nrfx is integrated.
*/
// Uncomment this line to use the standard MDK way of binding IRQ handlers
// at linking time.
#include <soc/nrfx_irqs.h>
//------------------------------------------------------------------------------
/**
* @brief Macro for placing a runtime assertion.
*
* @param expression Expression to be evaluated.
*/
#define NRFX_ASSERT(expression)
/**
* @brief Macro for placing a compile time assertion.
*
* @param expression Expression to be evaluated.
*/
#define NRFX_STATIC_ASSERT(expression)
//------------------------------------------------------------------------------
/**
* @brief Macro for setting the priority of a specific IRQ.
*
* @param irq_number IRQ number.
* @param priority Priority to be set.
*/
#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) NVIC_SetPriority(irq_number, priority)
/**
* @brief Macro for enabling a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number)
/**
* @brief Macro for checking if a specific IRQ is enabled.
*
* @param irq_number IRQ number.
*
* @retval true If the IRQ is enabled.
* @retval false Otherwise.
*/
#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number)
static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
{
return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
}
/**
* @brief Macro for disabling a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number)
static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
{
NVIC_DisableIRQ(irq_number);
}
/**
* @brief Macro for setting a specific IRQ as pending.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_SET(irq_number)
/**
* @brief Macro for clearing the pending status of a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_CLEAR(irq_number)
/**
* @brief Macro for checking the pending status of a specific IRQ.
*
* @retval true If the IRQ is pending.
* @retval false Otherwise.
*/
#define NRFX_IRQ_IS_PENDING(irq_number)
/** @brief Macro for entering into a critical section. */
#define NRFX_CRITICAL_SECTION_ENTER()
/** @brief Macro for exiting from a critical section. */
#define NRFX_CRITICAL_SECTION_EXIT()
//------------------------------------------------------------------------------
/**
* @brief When set to a non-zero value, this macro specifies that
* @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
* A compilation error is generated if the DWT unit is not present
* in the SoC used.
*/
#define NRFX_DELAY_DWT_BASED 0
/**
* @brief Macro for delaying the code execution for at least the specified time.
*
* @param us_time Number of microseconds to wait.
*/
#define NRFX_DELAY_US(us_time)
//------------------------------------------------------------------------------
/** @brief Atomic 32-bit unsigned type. */
#define nrfx_atomic_t
/**
* @brief Macro for storing a value to an atomic object and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value to store.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
/**
* @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the OR operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_OR(p_data, value)
/**
* @brief Macro for running a bitwise AND operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the AND operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_AND(p_data, value)
/**
* @brief Macro for running a bitwise XOR operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the XOR operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
/**
* @brief Macro for running an addition operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the ADD operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
/**
* @brief Macro for running a subtraction operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
//------------------------------------------------------------------------------
/**
* @brief When set to a non-zero value, this macro specifies that the
* @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
* in a customized way and the default definitions from @c <nrfx_error.h>
* should not be used.
*/
#define NRFX_CUSTOM_ERROR_CODES 0
//------------------------------------------------------------------------------
/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_CHANNELS_USED 0
/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_GROUPS_USED 0
/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_CHANNELS_USED 0
/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_GROUPS_USED 0
/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
#define NRFX_EGUS_USED 0
/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
#define NRFX_TIMERS_USED 0
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRFX_GLUE_H__
bsp/nrf5x/nrf52832/board/nrfx_log.h
+135
View File
@@ -0,0 +1,135 @@
/*
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRFX_LOG_H__
#define NRFX_LOG_H__
// THIS IS A TEMPLATE FILE.
// It should be copied to a suitable location within the host environment into
// which nrfx is integrated, and the following macros should be provided with
// appropriate implementations.
// And this comment should be removed from the customized file.
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrfx_log nrfx_log.h
* @{
* @ingroup nrfx
*
* @brief This file contains macros that should be implemented according to
* the needs of the host environment into which @em nrfx is integrated.
*/
/**
* @brief Macro for logging a message with the severity level ERROR.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_ERROR(format, ...)
/**
* @brief Macro for logging a message with the severity level WARNING.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_WARNING(format, ...)
/**
* @brief Macro for logging a message with the severity level INFO.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_INFO(format, ...)
/**
* @brief Macro for logging a message with the severity level DEBUG.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_DEBUG(format, ...)
/**
* @brief Macro for logging a memory dump with the severity level ERROR.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level WARNING.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level INFO.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level DEBUG.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
/**
* @brief Macro for getting the textual representation of a given error code.
*
* @param[in] error_code Error code.
*
* @return String containing the textual representation of the error code.
*/
#define NRFX_LOG_ERROR_STRING_GET(error_code)
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRFX_LOG_H__
bsp/nrf5x/nrf52832/board/sdk_config.h
+11704
View File
File diff suppressed because it is too large Load Diff
bsp/nrf5x/nrf52832/project.uvoptx
+708 -608
View File
File diff suppressed because it is too large Load Diff
bsp/nrf5x/nrf52832/project.uvprojx
+289 -249
View File
File diff suppressed because it is too large Load Diff
bsp/nrf5x/nrf52832/rtconfig.h
+19 -1
View File
@@ -46,6 +46,9 @@
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
@@ -74,7 +77,6 @@
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
@@ -138,6 +140,8 @@
/* peripheral libraries and drivers */
#define PKG_USING_NRFX
#define PKG_USING_NRFX_V210
/* miscellaneous packages */
@@ -148,11 +152,25 @@
/* Hardware Drivers Config */
#define SOC_NRF52832
#define SOC_NORDIC
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
/* On-chip flash config */
#define MCU_FLASH_START_ADDRESS 0x00000000
#define MCU_FLASH_SIZE_KB 1024
#define MCU_SRAM_START_ADDRESS 0x20000000
#define MCU_SRAM_SIZE_KB 256
#define MCU_FLASH_PAGE_SIZE 0x1000
#endif
bsp/nrf5x/nrf52832/template.uvoptx
+2 -2
View File
@@ -120,12 +120,12 @@
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Name>-U682327541 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))</Name>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
bsp/nrf5x/nrf52832/template.uvprojx
+9 -9
View File
@@ -16,9 +16,9 @@
<TargetCommonOption>
<Device>nRF52832_xxAA</Device>
<Vendor>Nordic Semiconductor</Vendor>
<PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.24.1</PackID>
<PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.27.1</PackID>
<PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
<Cpu>IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<Cpu>IRAM(0x20000000,0x00010000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
@@ -274,8 +274,8 @@
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x1f000</StartAddress>
<Size>0x61000</Size>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@@ -299,8 +299,8 @@
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x200025f8</StartAddress>
<Size>0xda08</Size>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
@@ -315,7 +315,7 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
@@ -336,7 +336,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--reduce_paths</MiscControls>
<Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
@@ -354,7 +354,7 @@
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls>--cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74</MiscControls>
<Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
bsp/nrf5x/nrf52840/board/Kconfig
+128 -18
View File
@@ -7,6 +7,12 @@ config SOC_NRF52840
select RT_USING_USER_MAIN
default y
config SOC_NORDIC
bool
config SOC_NORDIC
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_JLINK_TO_USART
bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
@@ -55,38 +61,142 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_PWM
bool "Enable PWM"
select RT_USING_PWM
default n
if BSP_USING_PWM
config NRFX_PWM_ENABLED
int
default 1
config BSP_USING_PWM0
bool "Enable PWM0 bus"
default y
if BSP_USING_PWM0
config NRFX_PWM0_ENABLED
int
default 1
config BSP_USING_PWM0_CH0
int "PWM0 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM0_CH1
int "PWM0 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM0_CH2
int "PWM0 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM0_CH3
int "PWM0 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM1
bool "Enable PWM1 bus"
default n
if BSP_USING_PWM1
config NRFX_PWM1_ENABLED
int
default 1
config BSP_USING_PWM1_CH0
int "PWM1 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM1_CH1
int "PWM1 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM1_CH2
int "PWM1 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM1_CH3
int "PWM1 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM2
bool "Enable PWM2 bus"
default n
if BSP_USING_PWM2
config NRFX_PWM2_ENABLED
int
default 1
config BSP_USING_PWM2_CH0
int "PWM2 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM2_CH1
int "PWM2 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM2_CH2
int "PWM2 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM2_CH3
int "PWM2 channel 3 pin number set"
range 0 47
default 16
endif
config BSP_USING_PWM3
bool "Enable PWM3 bus"
default n
if BSP_USING_PWM3
config NRFX_PWM3_ENABLED
int
default 1
config BSP_USING_PWM3_CH0
int "PWM3 channel 0 pin number set"
range 0 47
default 13
config BSP_USING_PWM3_CH1
int "PWM3 channel 1 pin number set"
range 0 47
default 14
config BSP_USING_PWM3_CH2
int "PWM3 channel 2 pin number set"
range 0 47
default 15
config BSP_USING_PWM3_CH3
int "PWM3 channel 3 pin number set"
range 0 47
default 16
endif
endif
menuconfig BSP_USING_SOFTDEVICE
bool "Enable NRF SOFTDEVICE"
select PKG_USING_NRF5X_SDK
select NRFX_CLOCK_ENABLED
default n
if BSP_USING_SOFTDEVICE
config NRFX_CLOCK_ENABLED
int "NRFX_CLOCK_ENABLED"
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY"
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY"
default 7
config NRFX_RTC_ENABLED
int "NRFX_RTC_ENABLED"
config NRFX_RTC_ENABLED
int
default 1
config NRF_CLOCK_ENABLED
int "NRF_CLOCK_ENABLED"
config NRFX_RTC1_ENABLED
int
default 1
config NRF_SDH_BLE_ENABLED
int "NRF_SDH_BLE_ENABLED"
config NRF_CLOCK_ENABLED
int
default 1
config NRF_SDH_ENABLED
int "NRF_SDH_ENABLED"
config NRF_SDH_BLE_ENABLED
int
default 1
config NRF_SDH_SOC_ENABLED
int "NRF_SDH_SOC_ENABLED"
config NRF_SDH_ENABLED
int
default 1
config NRF_SDH_SOC_ENABLED
int
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
default y
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h
+12 -8
View File
@@ -433,11 +433,12 @@ extern "C"
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk))
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 1 and enable it.
@@ -458,11 +459,12 @@ extern "C"
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk))
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 2 and enable it.
@@ -483,11 +485,12 @@ extern "C"
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk))
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 3 and enable it.
@@ -508,11 +511,12 @@ extern "C"
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk))
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Enable the compare window mode.
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h
+18
View File
@@ -95,6 +95,15 @@ extern "C"
*/
#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Trigger TX and RX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk))
/**
* @brief Disable RX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
@@ -113,6 +122,15 @@ extern "C"
*/
#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable TX and RX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] qspi The pointer of the specified QSPI module.
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h
+18
View File
@@ -133,6 +133,15 @@ extern "C"
*/
#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Trigger TX and RX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
/**
* @brief Disable RX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
@@ -151,6 +160,15 @@ extern "C"
*/
#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable TX and RX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi The pointer of the specified SPI module.
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h
+18
View File
@@ -361,6 +361,15 @@ extern "C"
*/
#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
/**
* @brief Trigger TX and RX PDMA function.
* @param[in] uspi The pointer of the specified USCI_SPI module.
* @return None.
* @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define USPI_TRIGGER_TX_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] uspi The pointer of the specified USCI_SPI module.
@@ -379,6 +388,15 @@ extern "C"
*/
#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable TX and RX PDMA transfer.
* @param[in] uspi The pointer of the specified USCI_SPI module.
* @return None.
* @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk))
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void USPI_Close(USPI_T *uspi);
void USPI_ClearRxBuf(USPI_T *uspi);
bsp/nuvoton/libraries/m480/rtt_port/Kconfig
+27 -17
View File
@@ -57,7 +57,7 @@ config SOC_SERIES_M480
select RT_USING_NETDEV
config NU_EMAC_PDMA_MEMCOPY
bool "Use PDMA for data tranferring"
bool "Use PDMA for data transferring"
select BSP_USING_PDMA
depends on BSP_USING_EMAC
default y
@@ -82,14 +82,15 @@ config SOC_SERIES_M480
menuconfig BSP_USING_EADC
bool "Enable Enhanced Analog-to-Digital Converter(EADC)"
select RT_USING_ADC
config BSP_USING_EADC0
bool "Enable EADC0"
depends on BSP_USING_EADC && RT_USING_ADC
if BSP_USING_EADC
config BSP_USING_EADC0
bool "Enable EADC0"
config BSP_USING_EADC1
bool "Enable EADC1"
depends on BSP_USING_EADC && RT_USING_ADC
config BSP_USING_EADC1
bool "Enable EADC1"
endif
menuconfig BSP_USING_TMR
bool "Enable Timer Controller(TIMER)"
@@ -371,12 +372,14 @@ config SOC_SERIES_M480
config BSP_USING_UI2C0
select RT_USING_I2C
select BSP_USING_UI2C
bool "UI2C0"
help
Choose this option if you need I2C function mode.
config BSP_USING_USPI0
select RT_USING_SPI
select BSP_USING_USPI
bool "USPI0"
help
Choose this option if you need SPI function mode.
@@ -391,7 +394,7 @@ config SOC_SERIES_M480
depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA
config BSP_USING_USPI0_PDMA
bool "Use PDMA for data tranferring"
bool "Use PDMA for data transferring"
select BSP_USING_USPI_PDMA
depends on BSP_USING_USPI0
endif
@@ -405,21 +408,21 @@ config SOC_SERIES_M480
config BSP_USING_UUART1
select RT_USING_SERIAL
select BSP_USING_UUART
select BSP_USING_UUART
bool "UUART1"
help
Choose this option if you need UART function mode.
config BSP_USING_UI2C1
select RT_USING_I2C
select BSP_USING_UI2C
select BSP_USING_UI2C
bool "UI2C1"
help
Choose this option if you need I2C function mode.
config BSP_USING_USPI1
select RT_USING_SPI
select BSP_USING_USPI
select BSP_USING_USPI
bool "USPI1"
help
Choose this option if you need SPI function mode.
@@ -434,7 +437,7 @@ config SOC_SERIES_M480
depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA
config BSP_USING_USPI1_PDMA
bool "Use PDMA for data tranferring"
bool "Use PDMA for data transferring"
select BSP_USING_USPI_PDMA
depends on BSP_USING_USPI1
endif
@@ -459,6 +462,10 @@ config SOC_SERIES_M480
config NU_SDH_HOTPLUG
bool "Using HOTPLUG"
default y
config NU_SDH_MOUNT_ON_ROOT
bool "Mount on root"
endif
menuconfig BSP_USING_CAN
@@ -652,7 +659,7 @@ config SOC_SERIES_M480
select BSP_USING_SPI_PDMA
depends on BSP_USING_SPI1
endif
choice
prompt "Select SPI2 function mode"
config BSP_USING_SPI2_NONE
@@ -686,7 +693,7 @@ config SOC_SERIES_M480
bool "NONE"
help
Choose this option if you need not SPI3.
config BSP_USING_SPI3
bool "Enable SPI3"
help
@@ -724,20 +731,23 @@ config SOC_SERIES_M480
bool "Enable Quad Serial Peripheral Interface(QSPI)"
select RT_USING_SPI
select RT_USING_QSPI
select BSP_USING_SPI
if BSP_USING_QSPI
if BSP_USING_QSPI
config BSP_USING_QSPI0
bool "Enable QSPI0"
config BSP_USING_QSPI0_PDMA
bool "Enable PDMA for QSPI0"
select BSP_USING_SPI_PDMA
depends on BSP_USING_QSPI0
config BSP_USING_QSPI1
bool "Enable QSPI1"
config BSP_USING_QSPI1_PDMA
bool "Enable PDMA for QSPI1"
bool "Enable PDMA for QSPI1"
select BSP_USING_SPI_PDMA
depends on BSP_USING_QSPI1
endif
@@ -857,7 +867,7 @@ config SOC_SERIES_M480
if BSP_USING_CRC
config NU_CRC_USE_PDMA
bool "Use PDMA for data tranferring."
bool "Use PDMA for data transferring."
select BSP_USING_PDMA
default y
endif
bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
+10 -9
View File
@@ -97,7 +97,7 @@ static struct nu_can nu_can_arr[] =
},
#endif
{0}
}; /* usart nu_usart */
}; /* struct nu_can */
/* Public functions ------------------------------------------------------------*/
@@ -112,7 +112,7 @@ static const struct rt_can_ops nu_can_ops =
static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT;
/* Interrupt Handle Funtion ----------------------------------------------------*/
/* Interrupt Handle Function ----------------------------------------------------*/
#if defined(BSP_USING_CAN0)
/* CAN0 interrupt entry */
void CAN0_IRQHandler(void)
@@ -238,7 +238,7 @@ static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure
RT_ASSERT(can != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
/* Get base address of uart register */
/* Get base address of CAN register */
CAN_T *can_base = ((nu_can_t)can)->can_base;
RT_ASSERT(can_base != RT_NULL);
@@ -312,7 +312,7 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
#ifdef RT_CAN_USING_HDR
struct rt_can_filter_config *filter_cfg;
#endif
/* Get base address of uart register */
/* Get base address of CAN register */
CAN_T *can_base = ((nu_can_t)can)->can_base;
RT_ASSERT(can_base != RT_NULL);
@@ -346,7 +346,6 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
/* Enable Status Change Interrupt */
CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2);
/* Enable NVIC interrupt. */
NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
@@ -355,7 +354,6 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
/* Enable Error Status and Status Change Interrupt */
CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2);
/* Enable NVIC interrupt. */
NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
}
@@ -440,6 +438,9 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
rt_memcpy(arg, &can->status, sizeof(can->status));
}
break;
default:
return -(RT_EINVAL);
}
return RT_EOK;
@@ -449,7 +450,7 @@ static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_
{
STR_CANMSG_T tMsg;
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
/* Get base address of uart register */
/* Get base address of CAN register */
CAN_T *can_base = ((nu_can_t)can)->can_base;
RT_ASSERT(can_base != RT_NULL);
@@ -495,7 +496,7 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
{
STR_CANMSG_T tMsg;
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
/* Get base address of uart register */
/* Get base address of CAN register */
CAN_T *can_base = ((nu_can_t)can)->can_base;
RT_ASSERT(can_base != RT_NULL);
@@ -558,7 +559,7 @@ static int rt_hw_can_init(void)
RT_ASSERT(ret == RT_EOK);
}
return ret;
return (int)ret;
}
INIT_DEVICE_EXPORT(rt_hw_can_init);
#endif //#if defined(BSP_USING_CAN)
bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
+5 -5
View File
@@ -165,8 +165,8 @@ static void pm_run(struct rt_pm *pm, rt_uint8_t mode)
SYS_UnlockReg();
/* Switch run mdoe frequency using PLL + HXT if HXT is enabled.
Otherwise, the systme clock will use PLL + HIRC. */
/* Switch run mode frequency using PLL + HXT if HXT is enabled.
Otherwise, the system clock will use PLL + HIRC. */
switch (mode)
{
case PM_RUN_MODE_HIGH_SPEED:
@@ -209,7 +209,7 @@ static void hw_timer_init(void)
CLK_EnableModuleClock(PM_TIMER_MODULE);
SYS_LockReg();
/* Initialise timer and enable wakeup function. */
/* Initialize timer and enable wakeup function. */
TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1);
TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0);
TIMER_EnableInt(PM_TIMER);
@@ -262,7 +262,7 @@ static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
if (timeout == RT_TICK_MAX)
return;
/* start pm timer to compenstate the os tick in power down mode */
/* start pm timer to compensate the os tick in power down mode */
tick = pm_tick_from_os_tick(timeout);
TIMER_SET_CMP_VALUE(PM_TIMER, tick);
TIMER_Start(PM_TIMER);
@@ -277,7 +277,7 @@ static void pm_timer_stop(struct rt_pm *pm)
}
/* pm device driver initialise. */
/* pm device driver initialize. */
int rt_hw_pm_init(void)
{
rt_uint8_t timer_mask;
bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c
+6 -5
View File
@@ -21,9 +21,9 @@
#endif
/* Private define ---------------------------------------------------------------*/
#define NU_GETBYTE_OFST(addr) ((addr&0x3)*8)
#define NU_GET_WALIGN(addr) (addr&~0x3)
#define NU_GET_LSB2BIT(addr) (addr&0x3)
#define NU_GETBYTE_OFST(addr) (((addr)&0x3)*8)
#define NU_GET_WALIGN(addr) ((addr)&~0x3)
#define NU_GET_LSB2BIT(addr) ((addr)&0x3)
/* Private typedef --------------------------------------------------------------*/
/* Private functions ------------------------------------------------------------*/
@@ -159,7 +159,8 @@ int nu_fmc_erase(long addr, size_t size)
uint32_t addr_end = addr + size;
#if defined(NU_SUPPORT_NONALIGN)
uint8_t *page_sdtemp = RT_NULL, *page_edtemp = RT_NULL;
uint8_t *page_sdtemp = RT_NULL;
uint8_t *page_edtemp = RT_NULL;
addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1);
@@ -315,7 +316,7 @@ static int nu_fmc_init(void)
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
return RT_EOK;
return (int)RT_EOK;
}
INIT_APP_EXPORT(nu_fmc_init);
bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
+1 -1
View File
@@ -166,7 +166,7 @@ static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_
if ((irqindex = nu_find_irqindex(pin)) >= 0)
goto exit_nu_gpio_attach_irq;
// Find avaiable index of pin in pool.
// Find available index of pin in pool.
if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero
goto exit_nu_gpio_attach_irq;
bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h
+1 -1
View File
@@ -26,7 +26,7 @@ typedef enum
NU_PORT_CNT,
} nu_gpio_port;
#define NU_GET_PININDEX(port, pin) (port*16+pin)
#define NU_GET_PININDEX(port, pin) ((port)*16+(pin))
#define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F)
#define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F)
#define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin))
bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
+7
View File
@@ -306,6 +306,10 @@ static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_ca
} // switch (caps->sub_type)
break;
default:
result = -RT_ERROR;
break;
} // switch (caps->main_type)
return result;
@@ -449,6 +453,9 @@ static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream)
LOG_I("Start record.");
}
break;
default:
return -RT_ERROR;
}
return RT_EOK;
bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c
+48 -32
View File
@@ -12,6 +12,14 @@
#include <rtconfig.h>
#if defined(BSP_USING_QSPI)
#define LOG_TAG "drv.qspi"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_INFO
#define DBG_COLOR
#include <rtdbg.h>
#include <rthw.h>
#include <rtdef.h>
@@ -87,8 +95,8 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
struct nu_spi *spi_bus;
uint32_t u32SPIMode;
uint32_t u32BusClock;
rt_uint32_t u32SPIMode;
rt_uint32_t u32BusClock;
rt_err_t ret = RT_EOK;
RT_ASSERT(device != RT_NULL);
@@ -130,7 +138,7 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz);
if (configuration->max_hz > u32BusClock)
{
rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
configuration->max_hz = u32BusClock;
}
@@ -173,7 +181,7 @@ exit_nu_qspi_bus_configure:
}
#if defined(RT_SFUD_USING_QSPI)
static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx, int qspi_lines)
static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
{
QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
if (qspi_lines > 1)
@@ -188,6 +196,9 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx
case 4:
QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base);
break;
default:
LOG_E("Data line is not supported.\n");
break;
}
}
else
@@ -200,6 +211,9 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx
case 4:
QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base);
break;
default:
LOG_E("Data line is not supported.\n");
break;
}
}
}
@@ -218,11 +232,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
struct rt_qspi_configuration *qspi_configuration;
#if defined(RT_SFUD_USING_QSPI)
struct rt_qspi_message *qspi_message;
int last = 1;
rt_uint8_t u8last = 1;
#endif
uint8_t bytes_per_word;
rt_uint8_t bytes_per_word;
QSPI_T *qspi_base;
int len = 0;
rt_uint32_t u32len = 0;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(message != RT_NULL);
@@ -252,9 +266,9 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
/* Command stage */
if (qspi_message->instruction.content != 0)
{
last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
nu_spi_transfer((struct nu_spi *)qspi_bus,
(uint8_t *) &qspi_message->instruction.content,
(rt_uint8_t *) &qspi_message->instruction.content,
RT_NULL,
1,
1);
@@ -263,29 +277,29 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
/* Address stage */
if (qspi_message->address.size != 0)
{
uint32_t u32ReversedAddr = 0;
uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
rt_uint32_t u32ReversedAddr = 0;
rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
switch (u32AddrNumOfByte)
{
case 1:
u32ReversedAddr = (qspi_message->address.content & 0xff);
break;
case 2:
nu_set16_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
break;
case 3:
nu_set24_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
break;
case 4:
nu_set32_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content);
nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
break;
default:
RT_ASSERT(0);
break;
}
last = nu_qspi_mode_config(qspi_bus, (uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
nu_spi_transfer((struct nu_spi *)qspi_bus,
(uint8_t *) &u32ReversedAddr,
(rt_uint8_t *) &u32ReversedAddr,
RT_NULL,
u32AddrNumOfByte,
1);
@@ -294,32 +308,32 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
/* Dummy_cycles stage */
if (qspi_message->dummy_cycles != 0)
{
qspi_bus->dummy = 0xff;
qspi_bus->dummy = 0x00;
last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_bus->dummy, RT_NULL, last);
u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, u8last);
nu_spi_transfer((struct nu_spi *)qspi_bus,
(uint8_t *) &qspi_bus->dummy,
(rt_uint8_t *) &qspi_bus->dummy,
RT_NULL,
qspi_message->dummy_cycles / (8 / last),
qspi_message->dummy_cycles / (8 / u8last),
1);
}
/* Data stage */
nu_qspi_mode_config(qspi_bus, (uint8_t *) message->send_buf, (uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
#endif //#if defined(RT_SFUD_USING_QSPI)
if (message->length != 0)
{
nu_spi_transfer((struct nu_spi *)qspi_bus,
(uint8_t *) message->send_buf,
(uint8_t *) message->recv_buf,
(rt_uint8_t *) message->send_buf,
(rt_uint8_t *) message->recv_buf,
message->length,
bytes_per_word);
len = message->length;
u32len = message->length;
}
else
{
len = 1;
u32len = 1;
}
if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
@@ -334,12 +348,12 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
}
}
return len;
return u32len;
}
static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name)
static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name)
{
return rt_qspi_bus_register(&qspi_device->dev, name, &nu_qspi_poll_ops);
return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops);
}
/**
@@ -347,19 +361,21 @@ static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name)
*/
static int rt_hw_qspi_init(void)
{
int i;
rt_uint8_t i;
for (i = (QSPI_START + 1); i < QSPI_CNT; i++)
{
nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name);
#if defined(BSP_USING_QSPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
nu_qspi_arr[i].pdma_chanid_tx = -1;
nu_qspi_arr[i].pdma_chanid_rx = -1;
#endif
#if defined(BSP_USING_QSPI_PDMA)
if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
{
if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)
{
rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name);
LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name);
}
}
#endif
@@ -381,7 +397,7 @@ rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
if (qspi_device == RT_NULL)
{
rt_kprintf("no memory, qspi bus attach device failed!\n");
LOG_E("no memory, qspi bus attach device failed!\n");
result = -RT_ENOMEM;
goto __exit;
}
bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
+59 -45
View File
@@ -1,25 +1,26 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-5-31 Egbert First version
*
******************************************************************************/
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-7-21 Egbert First version
*
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_SCUART)
#include <NuMicro.h>
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.scuart"
/* Private definition
* ---------------------------------------------------------------*/
#define LOG_TAG "drv.scuart"
#define DBG_ENABLE
#define DBG_SECTION_NAME "drv.scuart"
#define DBG_LEVEL DBG_ERROR
@@ -41,7 +42,8 @@ enum
SCUART_CNT
};
/* Private typedef --------------------------------------------------------------*/
/* Private typedef
* --------------------------------------------------------------*/
struct nu_scuart
{
rt_serial_t dev;
@@ -49,34 +51,32 @@ struct nu_scuart
SC_T *scuart_base;
uint32_t scuart_rst;
IRQn_Type scuart_irq_n;
};
typedef struct nu_scuart *nu_scuart_t;
/* Private functions ------------------------------------------------------------*/
static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg);
/* Private functions
* ------------------------------------------------------------*/
static rt_err_t nu_scuart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg);
static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd,
void *arg);
static int nu_scuart_send(struct rt_serial_device *serial, char c);
static int nu_scuart_receive(struct rt_serial_device *serial);
static void nu_scuart_isr(nu_scuart_t serial);
/* Public functions ------------------------------------------------------------*/
/* Private variables ------------------------------------------------------------*/
static const struct rt_uart_ops nu_scuart_ops =
{
.configure = nu_scuart_configure,
.control = nu_scuart_control,
.putc = nu_scuart_send,
.getc = nu_scuart_receive,
.dma_transmit = RT_NULL /* not support DMA mode */
.configure = nu_scuart_configure,
.control = nu_scuart_control,
.putc = nu_scuart_send,
.getc = nu_scuart_receive,
.dma_transmit = RT_NULL /* not support DMA mode */
};
static const struct serial_configure nu_scuart_default_config =
RT_SERIAL_CONFIG_DEFAULT;
static struct nu_scuart nu_scuart_arr [] =
static struct nu_scuart nu_scuart_arr[] =
{
#if defined(BSP_USING_SCUART0)
{
@@ -108,7 +108,8 @@ static struct nu_scuart nu_scuart_arr [] =
{0}
}; /* scuart nu_scuart */
/* Interrupt Handle Funtion ----------------------------------------------------*/
/* Interrupt Handle Function
* ----------------------------------------------------*/
#if defined(BSP_USING_SCUART0)
/* SCUART0 interrupt entry */
void SC0_IRQHandler(void)
@@ -151,8 +152,6 @@ void SC2_IRQHandler(void)
}
#endif
/**
* All SCUART interrupt service routine
*/
@@ -177,9 +176,10 @@ static void nu_scuart_isr(nu_scuart_t serial)
}
/**
* Configurae scuart port
* Configure scuart port
*/
static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
static rt_err_t nu_scuart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
rt_err_t ret = RT_EOK;
uint32_t scuart_word_len = 0;
@@ -189,7 +189,7 @@ static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct seri
/* Get base address of scuart register */
SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
/* Check baudrate */
/* Check baud rate */
RT_ASSERT(cfg->baud_rate != 0);
/* Check word len */
@@ -258,11 +258,12 @@ static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct seri
/* Reset this module */
SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst);
/* Open SCUART and set SCUART Baudrate */
/* Open SCUART and set SCUART baud rate */
SCUART_Open(scuart_base, cfg->baud_rate);
/* Set line configuration. */
SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, scuart_stop_bit);
SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity,
scuart_stop_bit);
/* Enable NVIC interrupt. */
NVIC_EnableIRQ(((nu_scuart_t)serial)->scuart_irq_n);
@@ -278,14 +279,14 @@ exit_nu_scuart_configure:
/**
* SCUART interrupt control
*/
static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg)
static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd,
void *arg)
{
rt_err_t result = RT_EOK;
rt_uint32_t flag;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(arg != RT_NULL);
/* Get base address of scuart register */
SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
@@ -298,10 +299,6 @@ static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void
flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk;
SCUART_DISABLE_INT(scuart_base, flag);
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
{
LOG_E("SCUART does not support dma transmission");
}
break;
case RT_DEVICE_CTRL_SET_INT:
@@ -312,6 +309,21 @@ static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void
}
break;
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_scuart_t)serial)->scuart_irq_n);
/* Reset this module */
SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst);
/* Close SCUART port */
SCUART_Close(scuart_base);
break;
default:
result = -RT_EINVAL;
break;
}
return result;
}
@@ -327,7 +339,8 @@ static int nu_scuart_send(struct rt_serial_device *serial, char c)
SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
/* Waiting if TX-FIFO is full. */
while (SCUART_IS_TX_FULL(scuart_base));
while (SCUART_IS_TX_FULL(scuart_base))
;
/* Put char into TX-FIFO */
SCUART_WRITE(scuart_base, c);
@@ -368,10 +381,11 @@ static int rt_hw_scuart_init(void)
{
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
nu_scuart_arr[i].dev.ops = &nu_scuart_ops;
nu_scuart_arr[i].dev.ops = &nu_scuart_ops;
nu_scuart_arr[i].dev.config = nu_scuart_default_config;
ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL);
ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name,
flag, NULL);
RT_ASSERT(ret == RT_EOK);
}
bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
+57 -55
View File
@@ -25,17 +25,30 @@
#endif
/* Private define ---------------------------------------------------------------*/
// RT_DEV_NAME_PREFIX sdh
#ifndef NU_SDH_MOUNTPOINT_ROOT
#define NU_SDH_MOUNTPOINT_ROOT "/mnt"
#if defined(NU_SDH_MOUNT_ON_ROOT)
#if !defined(NU_SDH_MOUNTPOINT_SDH0)
#define NU_SDH_MOUNTPOINT_SDH0 "/"
#endif
#if !defined(NU_SDH_MOUNTPOINT_SDH1)
#define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_SDH0"/sd1"
#endif
#else
#if !defined(NU_SDH_MOUNTPOINT_ROOT)
#define NU_SDH_MOUNTPOINT_ROOT "/mnt"
#endif
#endif
#ifndef NU_SDH_MOUNTPOINT_SDH0
#if !defined(NU_SDH_MOUNTPOINT_SDH0)
#define NU_SDH_MOUNTPOINT_SDH0 NU_SDH_MOUNTPOINT_ROOT"/sd0"
#endif
#ifndef NU_SDH_MOUNTPOINT_SDH1
#if !defined(NU_SDH_MOUNTPOINT_SDH1)
#define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_ROOT"/sd1"
#endif
@@ -66,11 +79,9 @@ enum
#if defined(NU_SDH_HOTPLUG)
enum
{
NU_SDH_CARD_INSERTED_SD0 = (1 << 0),
NU_SDH_CARD_REMOVED_SD0 = (1 << 1),
NU_SDH_CARD_INSERTED_SD1 = (1 << 2),
NU_SDH_CARD_REMOVED_SD1 = (1 << 3),
NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_INSERTED_SD0 | NU_SDH_CARD_REMOVED_SD0 | NU_SDH_CARD_INSERTED_SD1 | NU_SDH_CARD_REMOVED_SD1)
NU_SDH_CARD_DETECTED_SD0 = (1 << 0),
NU_SDH_CARD_DETECTED_SD1 = (1 << 1),
NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_DETECTED_SD0 | NU_SDH_CARD_DETECTED_SD1)
};
#endif
@@ -166,40 +177,12 @@ static void nu_sdh_isr(nu_sdh_t sdh)
if (isr & SDH_INTSTS_CDIF_Msk) // card detect
{
/* SD interrupt status */
// it is work to delay 50 times for SD_CLK = 200KHz
{
int volatile i; // delay 30 fail, 50 OK
for (i = 0; i < 0x500; i++); // delay to make sure got updated value from REG_SDISR.
isr = sdh_base->INTSTS;
}
if (isr & SDH_INTSTS_CDSTS_Msk)
{
/* Card removed */
#if defined(NU_SDH_HOTPLUG)
if (sdh->base == SDH0)
rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD0);
else if (sdh->base == SDH1)
rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD1);
if (sdh->base == SDH0)
rt_event_send(&sdh_event, NU_SDH_CARD_DETECTED_SD0);
else if (sdh->base == SDH1)
rt_event_send(&sdh_event, NU_SDH_CARD_DETECTED_SD1);
#endif
sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode
rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T));
}
else
{
SDH_Open(sdh_base, CardDetect_From_GPIO);
if (!SDH_Probe(sdh_base))
{
/* Card inserted */
#if defined(NU_SDH_HOTPLUG)
if (sdh->base == SDH0)
rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD0);
else if (sdh->base == SDH1)
rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD1);
#endif
}
}
/* Clear CDIF interrupt flag */
SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CDIF_Msk);
}
@@ -210,14 +193,14 @@ static void nu_sdh_isr(nu_sdh_t sdh)
if (!(isr & SDH_INTSTS_CRC16_Msk))
{
/* CRC_16 error */
// handle CRC 16 error
// TODO: handle CRC 16 error
}
else if (!(isr & SDH_INTSTS_CRC7_Msk))
{
if (!pSD->R3Flag)
{
/* CRC_7 error */
// handle CRC 7 error
// TODO: handle CRC 7 error
}
}
/* Clear CRCIF interrupt flag */
@@ -502,6 +485,7 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
{
closedir(t);
}
#if !defined(NU_SDH_MOUNT_ON_ROOT)
else
{
@@ -523,6 +507,7 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
}
} //else
#endif
if ((ret = dfs_mount(sdh->name, sdh->mounted_point, "elm", 0, 0)) == 0)
{
@@ -567,6 +552,29 @@ exit_nu_sdh_hotplug_unmount:
return -(ret);
}
static void nu_card_detector(nu_sdh_t sdh)
{
SDH_T *sdh_base = sdh->base;
unsigned int volatile isr = sdh_base->INTSTS;
if (isr & SDH_INTSTS_CDSTS_Msk)
{
/* Card removed */
sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode
rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T));
nu_sdh_hotplug_unmount(sdh);
}
else
{
SDH_Open(sdh_base, CardDetect_From_GPIO);
if (!SDH_Probe(sdh_base))
{
/* Card inserted */
nu_sdh_hotplug_mount(sdh);
}
}
}
static void sdh_hotplugger(void *param)
{
rt_uint32_t e;
@@ -586,24 +594,18 @@ static void sdh_hotplugger(void *param)
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
RT_WAITING_FOREVER, &e) == RT_EOK)
{
/* Debouce */
/* Debounce */
rt_thread_delay(200);
switch (e)
{
#if defined(BSP_USING_SDH0)
case NU_SDH_CARD_INSERTED_SD0:
nu_sdh_hotplug_mount(&nu_sdh_arr[SDH0_IDX]);
break;
case NU_SDH_CARD_REMOVED_SD0:
nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH0_IDX]);
case NU_SDH_CARD_DETECTED_SD0:
nu_card_detector(&nu_sdh_arr[SDH0_IDX]);
break;
#endif
#if defined(BSP_USING_SDH1)
case NU_SDH_CARD_INSERTED_SD1:
nu_sdh_hotplug_mount(&nu_sdh_arr[SDH1_IDX]);
break;
case NU_SDH_CARD_REMOVED_SD1:
nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH1_IDX]);
case NU_SDH_CARD_DETECTED_SD1:
nu_card_detector(&nu_sdh_arr[SDH1_IDX]);
break;
#endif
default:
bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
+1 -2
View File
@@ -24,7 +24,6 @@
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_INFO
#define DBG_COLOR
#include <rtdbg.h>
#ifdef BSP_USING_SOFT_I2C0
@@ -58,7 +57,7 @@ struct nu_soft_i2c_config
rt_uint8_t sda;
const char *bus_name;
};
/* soft i2c dirver class */
/* soft i2c driver class */
struct nu_soft_i2c
{
struct rt_i2c_bit_ops ops;
bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c
+33 -58
View File
@@ -11,7 +11,15 @@
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_SPI) || defined(BSP_USING_QSPI)
#if defined(BSP_USING_SPI)
#define LOG_TAG "drv.spi"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_INFO
#define DBG_COLOR
#include <rtdbg.h>
#include <rthw.h>
#include <rtdevice.h>
#include <rtdef.h>
@@ -22,7 +30,7 @@
/* Private define ---------------------------------------------------------------*/
#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD
#define NU_SPI_USE_PDMA_MIN_THRESHOLD 128
#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128)
#endif
enum
@@ -52,9 +60,8 @@ static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name);
static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter);
static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter);
static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word);
static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word);
static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
@@ -63,10 +70,6 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi
void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word);
void nu_spi_drain_rxfifo(SPI_T *spi_base);
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA)
rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus);
#endif
/* Private variables ------------------------------------------------------------*/
static struct rt_spi_ops nu_spi_poll_ops =
{
@@ -193,7 +196,7 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device,
u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz);
if (configuration->max_hz > u32BusClock)
{
rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
configuration->max_hz = u32BusClock;
}
@@ -235,21 +238,14 @@ exit_nu_spi_bus_configure:
return -(ret);
}
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter)
{
struct nu_spi *spi_bus;
spi_bus = (struct nu_spi *)pvUserData;
struct nu_spi *spi_bus = (struct nu_spi *)pvUserData;
RT_ASSERT(spi_bus != RT_NULL);
/* Get base address of spi register */
SPI_T *spi_base = spi_bus->spi_base;
if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
{
SPI_DISABLE_RX_PDMA(spi_base); // Stop DMA TX transfer
}
rt_sem_release(spi_bus->m_psSemBus);
}
static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word)
{
@@ -299,24 +295,6 @@ exit_nu_pdma_spi_rx_config:
return result;
}
static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter)
{
struct nu_spi *spi_bus;
spi_bus = (struct nu_spi *)pvUserData;
RT_ASSERT(spi_bus != RT_NULL);
/* Get base address of spi register */
SPI_T *spi_base = spi_bus->spi_base;
if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
{
SPI_DISABLE_TX_PDMA(spi_base); // Stop DMA TX transfer
}
rt_sem_release(spi_bus->m_psSemBus);
}
static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word)
{
rt_err_t result = RT_EOK;
@@ -328,15 +306,6 @@ static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8
rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx;
result = nu_pdma_callback_register(spi_pdma_tx_chid,
nu_pdma_spi_tx_cb,
(void *)spi_bus,
NU_PDMA_EVENT_TRANSFER_DONE);
if (result != RT_EOK)
{
goto exit_nu_pdma_spi_tx_config;
}
if (pu8Buf == RT_NULL)
{
spi_bus->dummy = 0;
@@ -382,14 +351,14 @@ static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *sen
result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word);
RT_ASSERT(result == RT_EOK);
/* Trigger TX/RX at the same time. */
SPI_TRIGGER_TX_PDMA(spi_base);
SPI_TRIGGER_RX_PDMA(spi_base);
/* Trigger TX/RX PDMA transfer. */
SPI_TRIGGER_TX_RX_PDMA(spi_base);
/* Wait PDMA transfer done */
/* Wait RX-PDMA transfer done */
rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER);
while (SPI_IS_BUSY(spi_base));
/* Stop TX/RX DMA transfer. */
SPI_DISABLE_TX_RX_PDMA(spi_base);
return result;
}
@@ -416,7 +385,7 @@ exit_nu_hw_spi_pdma_allocate:
return -(RT_ERROR);
}
#endif /* #if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) */
#endif /* #if defined(BSP_USING_SPI_PDMA) */
void nu_spi_drain_rxfifo(SPI_T *spi_base)
{
@@ -432,11 +401,11 @@ void nu_spi_drain_rxfifo(SPI_T *spi_base)
static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word)
{
int size = 0;
uint32_t val;
// Read RX data
if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
{
uint32_t val;
// Read data from SPI RX FIFO
switch (bytes_per_word)
{
@@ -455,6 +424,9 @@ static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_wo
case 1:
*recv_addr = SPI_READ_RX(spi_base);
break;
default:
LOG_E("Data length is not supported.\n");
break;
}
size = bytes_per_word;
}
@@ -481,6 +453,9 @@ static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes
case 1:
SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr));
break;
default:
LOG_E("Data length is not supported.\n");
break;
}
return bytes_per_word;
@@ -534,7 +509,7 @@ static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus,
}
} // else
/* Wait RX or drian RX-FIFO */
/* Wait RX or drain RX-FIFO */
if (recv_addr)
{
// Wait SPI transmission done
@@ -565,8 +540,8 @@ void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int lengt
#if defined(BSP_USING_SPI_PDMA)
/* DMA transfer constrains */
if ((spi_bus->pdma_chanid_rx >= 0) &&
(!(uint32_t)tx % bytes_per_word) &&
(!(uint32_t)rx % bytes_per_word) &&
!((uint32_t)tx % bytes_per_word) &&
!((uint32_t)rx % bytes_per_word) &&
(bytes_per_word != 3) &&
(length >= NU_SPI_USE_PDMA_MIN_THRESHOLD))
nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word);
@@ -594,7 +569,7 @@ static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_m
if ((message->length % bytes_per_word) != 0)
{
/* Say bye. */
rt_kprintf("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word);
LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word);
return 0;
}
@@ -653,7 +628,7 @@ static int rt_hw_spi_init(void)
{
if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK)
{
rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name);
LOG_W("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name);
}
}
#endif
bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h
+5 -3
View File
@@ -13,11 +13,13 @@
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtconfig.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include <nu_bitutil.h>
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
#include <drv_pdma.h>
#endif
@@ -27,7 +29,7 @@ struct nu_spi
char *name;
SPI_T *spi_base;
uint32_t dummy;
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
int16_t pdma_perp_tx;
int8_t pdma_chanid_tx;
int16_t pdma_perp_rx;
@@ -42,7 +44,7 @@ typedef struct nu_spi *nu_spi_t;
void nu_spi_drain_rxfifo(SPI_T *spi_base);
void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word);
#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA)
#if defined(BSP_USING_SPI_PDMA)
rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus);
#endif
bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c
-1
View File
@@ -19,7 +19,6 @@
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_INFO
#define DBG_COLOR
#define TPWM_CHANNEL_NUM 2
#include <rtdbg.h>
bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
+37 -4
View File
@@ -291,7 +291,7 @@ static struct nu_uart nu_uart_arr [] =
{0}
}; /* uart nu_uart */
/* Interrupt Handle Funtion ----------------------------------------------------*/
/* Interrupt Handle Function ----------------------------------------------------*/
#if defined(BSP_USING_UART0)
/* UART0 interrupt entry */
void UART0_IRQHandler(void)
@@ -419,6 +419,8 @@ static void nu_uart_isr(nu_uart_t serial)
#if defined(RT_SERIAL_USING_DMA)
if (u32IntSts & UART_INTSTS_HWRLSIF_Msk)
{
/* Drain RX FIFO to remove remain FEF frames in FIFO. */
uart_base->FIFO |= UART_FIFO_RXRST_Msk;
uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk);
return;
}
@@ -434,7 +436,7 @@ static void nu_uart_isr(nu_uart_t serial)
}
/**
* Configurae uart port
* Configure uart port
*/
static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
@@ -544,6 +546,10 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
nu_pdma_uart_rx_cb,
(void *)serial,
NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
if ( result != RT_EOK )
{
goto exit_nu_pdma_uart_rx_config;
}
result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx,
8,
@@ -551,17 +557,24 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
(uint32_t)pu8Buf,
i32TriggerLen,
1000); //Idle-timeout, 1ms
if ( result != RT_EOK )
{
goto exit_nu_pdma_uart_rx_config;
}
/* Enable Receive Line interrupt & Start DMA RX transfer. */
UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
exit_nu_pdma_uart_rx_config:
return result;
}
static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
{
rt_size_t recv_len=0;
rt_size_t recv_len = 0;
rt_size_t transferred_rxbyte = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
nu_uart_t puart = (nu_uart_t)serial;
@@ -715,7 +728,6 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(arg != RT_NULL);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@@ -763,6 +775,27 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
break;
#endif
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
#endif
/* Reset this module */
SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
/* Close UART port */
UART_Close(uart_base);
break;
default:
result = -RT_EINVAL;
break;
}
return result;
}

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