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Microchip SAM MCU新增ethernet支持和驱动更新 (#5821)

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* Microchip SAM MCU BSP update and add ethernet driver

1. Update Microchip SAM MCU BSP, add I2C, GMAC, ADC driver support. 2. Add ethernet driver support of SAM MCU for RT-Thread.

* Add GMAC and I2C driver support

1. Update MCU BSP to support I2C/ADC/GMAC peripherals. 2. Add I2C and ethernet driver and LWIP support. 3. Update serial driver.

* Add I2C driver and move some files to the common folder

1. Add I2C driver. 2. Move the same drivers and demo code to same folder to reduce duplicated code.
This commit is contained in:
Kevin Liu
2022-04-19 14:32:02 +08:00
committed by GitHub
parent 991b6e78b3
commit 7847c5e98d
180 changed files with 23404 additions and 3570 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/microchip/same70/.config
+130 -14
View File
@@ -21,7 +21,9 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
@@ -93,8 +95,33 @@ CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
# CONFIG_RT_USING_MSH is not set
# CONFIG_RT_USING_DFS is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
@@ -102,7 +129,9 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
@@ -111,9 +140,11 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
# CONFIG_RT_USING_I2C_BITOPS is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
@@ -147,11 +178,20 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX_FS=y
CONFIG_RT_USING_POSIX_DEVIO=y
# CONFIG_RT_USING_POSIX_STDIO is not set
CONFIG_RT_USING_POSIX_POLL=y
CONFIG_RT_USING_POSIX_SELECT=y
CONFIG_RT_USING_POSIX_SOCKET=y
# CONFIG_RT_USING_POSIX_TERMIOS is not set
CONFIG_RT_USING_POSIX_AIO=y
# CONFIG_RT_USING_POSIX_MMAN is not set
CONFIG_RT_USING_POSIX_DELAY=y
CONFIG_RT_USING_POSIX_CLOCK=y
CONFIG_RT_USING_POSIX_TIMER=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
# CONFIG_RT_USING_MODULE is not set
#
@@ -169,9 +209,80 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_POSIX=y
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
CONFIG_RT_USING_LWIP_LOCAL_VERSION=y
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@@ -640,9 +751,14 @@ CONFIG_SOC_SAME70Q21=y
#
CONFIG_SAME70_CAN0=y
CONFIG_SAME70_ADC0=y
CONFIG_SAME70_I2C0=y
CONFIG_SAME70_GMAC=y
#
# Application Demo Config
#
CONFIG_SAM_CAN_EXAMPLE=y
CONFIG_SAM_ADC_EXAMPLE=y
CONFIG_SAM_I2C_EXAMPLE=y
CONFIG_SAM_LWIP_EXAMPLE=y
CONFIG_SOC_SAME70=y
bsp/microchip/same70/SConstruct
+19
View File
@@ -34,8 +34,27 @@ if rtconfig.PLATFORM == 'iar':
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/common'):
common_path_prefix = SDK_ROOT + '/common'
else:
common_path_prefix = os.path.dirname(SDK_ROOT) + '/common'
SDK_LIB = common_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
sam_board = 'board'
rtconfig.BSP_LIBRARY_TYPE = sam_board
# include libraries
objs.extend(SConscript(os.path.join(common_path_prefix, sam_board, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(common_path_prefix, 'applications', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/microchip/same70/applications/can_demo.c
-333
View File
@@ -1,333 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Email Notes
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
*/
#include <rtthread.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <shell.h>
#endif
#include "atmel_start.h"
#include "driver_init.h"
#include "utils.h"
#include "can_demo.h"
#ifdef SAM_CAN_EXAMPLE
static volatile enum can_async_interrupt_type can_errors;
static rt_sem_t can_txdone;
static rt_sem_t can_rxdone;
static rt_uint8_t can_stack[ 512 ];
static struct rt_thread can_thread;
/**
* @brief Callback function and should be invoked after call can_async_write.
*
* @note
*
* @param descr is CAN device description.
*
* @return None.
*/
static void can_tx_callback(struct can_async_descriptor *const descr)
{
rt_err_t result;
rt_interrupt_enter();
result = rt_sem_release(can_txdone);
if (RT_EOK != result)
{
#ifndef RT_USING_FINSH
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
#endif
}
rt_interrupt_leave();
}
/**
* @brief Callback function and should be invoked after remote device send.
*
* @note This callback function will be called in CAN interrupt function
*
* @param descr is CAN device description.
*
* @return None.
*/
static void can_rx_callback(struct can_async_descriptor *const descr)
{
rt_err_t result;
rt_interrupt_enter();
result = rt_sem_release(can_rxdone);
if (RT_EOK != result)
{
#ifndef RT_USING_FINSH
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
#endif
}
rt_interrupt_leave();
}
/**
* @brief Callback function and should be invoked after CAN device IRQ handler detects errors happened.
*
* @note This callback function will be called in CAN interrupt function
*
* @param descr is CAN device description.
*
* @return None.
*/
static void can_err_callback(struct can_async_descriptor *const descr,
enum can_async_interrupt_type type)
{
rt_err_t result;
if (type == CAN_IRQ_EW)
{
/* Error warning, Error counter has reached the error warning limit of 96,
* An error count value greater than about 96 indicates a heavily disturbed
* bus. It may be of advantage to provide means to test for this condition.
*/
}
else if (type == CAN_IRQ_EA)
{
/* Error Active State, The CAN node normally take part in bus communication
* and sends an ACTIVE ERROR FLAG when an error has been detected.
*/
}
else if (type == CAN_IRQ_EP)
{
/* Error Passive State, The Can node goes into error passive state if at least
* one of its error counters is greater than 127. It still takes part in bus
* activities, but it sends a passive error frame only, on errors.
*/
}
else if (type == CAN_IRQ_BO)
{
/* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is
* greater than or equal to 256.
*/
/* Suspend CAN task and re-initialize CAN module. */
can_errors = type;
rt_interrupt_enter();
result = rt_sem_release(can_rxdone);
if (RT_EOK != result)
{
#ifndef RT_USING_FINSH
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
#endif
}
rt_interrupt_leave();
}
else if (type == CAN_IRQ_DO)
{
/* Data Overrun in receive queue. A message was lost because the messages in
* the queue was not reading and releasing fast enough. There is not enough
* space for a new message in receive queue.
*/
/* Suggest to delete CAN task and re-initialize it. */
can_errors = type;
rt_interrupt_enter();
result = rt_sem_release(can_rxdone);
if (RT_EOK != result)
{
#ifndef RT_USING_FINSH
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
#endif
}
rt_interrupt_leave();
}
};
/**
* @brief Initialize CAN module before task run.
*
* @note This function will set CAN Tx/Rx callback function and filters.
*
* @param None.
*
* @return None.
*/
static inline void can_demo_init(void)
{
struct can_filter filter;
/**
* CAN_Node0_tx_callback callback should be invoked after call
* can_async_write, and remote device should receive message with ID=0x45A
*/
can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback);
/**
* CAN_0_rx_callback callback should be invoked after call
* can_async_set_filter and remote device send CAN Message with the same
* content as the filter.
*/
can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback);
/* Should set at least one CAN standard & message filter before enable it. */
filter.id = 0x469;
filter.mask = 0;
can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter);
/* If set second standard message filter, should increase filter index
* and filter algorithm
* For example: index should set to 1, otherwise it will replace filter 0.
* can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */
filter.id = 0x10000096;
filter.mask = 0;
can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter);
can_async_enable(&CAN_0);
}
/**
* @brief CAN task.
*
* @note This task will waiting for CAN RX semaphore and then process input.
*
* @param parameter - task input parameter.
*
* @return None.
*/
static void can_thread_entry(void* parameter)
{
int32_t ret;
rt_err_t result;
uint8_t data[64];
uint32_t count=0;
struct can_message msg;
while (1)
{
#ifndef RT_USING_FINSH
rt_kprintf("can task run count : %d\r\n",count);
#endif
count++;
result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER);
if (RT_EOK != result)
continue;
do
{
/* Process the incoming packet. */
ret = can_async_read(&CAN_0, &msg);
if (ret == ERR_NONE)
{
#ifndef RT_USING_FINSH
rt_kprintf("CAN RX Message is % frame\r\n",
msg.type == CAN_TYPE_DATA ? "data" : "remote");
rt_kprintf("CAN RX Message is % frame\r\n",
msg.type == CAN_FMT_STDID ? "Standard" : "Extended");
rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len);
rt_kprintf("CAN RX Message content: ");
for (uint8_t i = 0; i < msg.len; i++)
rt_kprintf("0x%02X ", data[i]);
rt_kprintf("\r\n");
#endif
}
} while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */
/* CAN task got CAN error message, handler CAN Error Status */
if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
{
can_async_init(&CAN_0, MCAN1);
}
}
}
/**
* @brief Call this function will to send a CAN message.
*
* @note
*
* @param msg - message to be sent, timeouts - wait timeouts for Tx completion.
*
* @return RT_OK or RT_ERROR.
*/
rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts)
{
rt_err_t result;
if (RT_NULL == msg)
{
rt_kprintf("can_send_message input message error\r\n");
return RT_ERROR;
}
can_async_write(&CAN_0, msg);
result = rt_sem_take(can_rxdone, timeouts);
return result;
}
/**
* @brief Call this function will create a CAN task.
*
* @note Should create Tx/Rx semaphore before run task.
*
* @param None.
*
* @return RT_OK or -RT_ERROR.
*/
rt_err_t can_demo_run(void)
{
rt_err_t result;
can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO);
if (RT_NULL == can_rxdone)
{
rt_kprintf("can_rx semaphore create failed\r\n");
return (-RT_ERROR);
}
can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO);
if (RT_NULL == can_txdone)
{
rt_kprintf("can_tx semaphore create failed\r\n");
return (-RT_ERROR);
}
can_demo_init();
/* initialize CAN thread */
result = rt_thread_init(&can_thread,
"can",
can_thread_entry,
RT_NULL,
(rt_uint8_t*)&can_stack[0],
sizeof(can_stack),
RT_THREAD_PRIORITY_MAX/3,
5);
if (result == RT_EOK)
{
rt_thread_startup(&can_thread);
}
return result;
}
#endif
/*@}*/
bsp/microchip/same70/applications/can_demo.h
-24
View File
@@ -1,24 +0,0 @@
/*
* Copyright (c)
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Email Notes
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
*/
#ifndef __APPLICATION_CAN_H_
#define __APPLICATION_CAN_H_
#include <rtthread.h>
/**
* @brief External function definitions
*
*/
rt_err_t can_demo_run(void);
rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
#endif // __APPLICATION_CAN_H_
bsp/microchip/same70/applications/main.c
+25 -1
View File
@@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Email Notes
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
*/
#include <rtthread.h>
@@ -22,6 +22,18 @@
#include "can_demo.h"
#endif
#ifdef SAM_I2C_EXAMPLE
#include "i2c_demo.h"
#endif
#ifdef SAM_ADC_EXAMPLE
#include "adc_demo.h"
#endif
#ifdef SAM_LWIP_EXAMPLE
#include "lwip_demo.h"
#endif
static rt_uint8_t led_stack[ 512 ];
static struct rt_thread led_thread;
@@ -63,6 +75,18 @@ int main(void)
can_demo_run();
#endif
#ifdef SAM_I2C_EXAMPLE
i2c_demo_run();
#endif
#ifdef SAM_ADC_EXAMPLE
adc_demo_run();
#endif
#ifdef SAM_LWIP_EXAMPLE
lwip_demo_run();
#endif
return 0;
}
bsp/microchip/same70/board/Kconfig
+22
View File
@@ -30,6 +30,14 @@ menu "Onboard Peripheral Drivers"
config SAME70_ADC0
bool "Enable ADC0"
default false
config SAME70_I2C0
bool "Enable I2C0"
default false
config SAME70_GMAC
bool "Enable GMAC"
default false
endmenu
menu "Application Demo Config"
@@ -47,4 +55,18 @@ menu "Application Demo Config"
help
Add ADC example task to project
config SAM_I2C_EXAMPLE
bool "Enable SAM I2C Example"
depends on SAME70_I2C0
default true
help
Add I2C example task to project
config SAM_LWIP_EXAMPLE
bool "Enable SAM LWIP Example"
depends on SAME70_GMAC
default false
help
Add GMAC LWIP example task to project
endmenu
bsp/microchip/same70/board/board.c
+3 -2
View File
@@ -25,13 +25,14 @@ static struct io_descriptor* g_stdio;
void rt_hw_console_output(const char *str)
{
io_write(g_stdio, (uint8_t *)str, strlen(str));
while (TARGET_IO.stat != 0);
}
RTM_EXPORT(rt_hw_console_output);
static inline void hw_board_init_usart(void)
{
usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
usart_sync_enable(&TARGET_IO);
usart_async_get_io_descriptor(&TARGET_IO, &g_stdio);
usart_async_enable(&TARGET_IO);
}
/**
bsp/microchip/same70/board/serial.c
-199
View File
@@ -1,199 +0,0 @@
/*
* Copyright (c)
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Email Notes
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <atmel_start.h>
/* SAM MCU serial device */
static struct rt_serial_device sam_serial;
/**
* @brief Configure serial port
*
* This function will configure UART baudrate, parity and so on.
*
* @return RT_EOK.
*/
static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct usart_sync_descriptor* desc;
RT_ASSERT(serial != RT_NULL);
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
RT_ASSERT(desc != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
usart_sync_disable(desc);
/* Set baudrate */
usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
/* Set stop bit */
if (cfg->stop_bits == STOP_BITS_1)
usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
else if (cfg->stop_bits == STOP_BITS_2)
usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
if (cfg->bit_order == BIT_ORDER_LSB)
usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
else if (cfg->bit_order == BIT_ORDER_MSB)
usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
/* Set character size */
switch (cfg->data_bits)
{
case DATA_BITS_5:
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
break;
case DATA_BITS_6:
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
break;
case DATA_BITS_7:
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
break;
case DATA_BITS_8:
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
break;
case DATA_BITS_9:
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
break;
default:
break;
}
if (cfg->parity == PARITY_NONE)
usart_sync_set_parity(desc, USART_PARITY_NONE);
else if (cfg->parity == PARITY_ODD)
usart_sync_set_parity(desc, USART_PARITY_ODD);
else if (cfg->parity == PARITY_EVEN)
usart_sync_set_parity(desc, USART_PARITY_EVEN);
usart_sync_enable(desc);
return RT_EOK;
}
/**
* @brief Control serial port
*
* This function provide UART enable/disable control.
*
* @return RT_EOK.
*/
static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct usart_sync_descriptor* desc;
RT_ASSERT(serial != RT_NULL);
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
RT_ASSERT(desc != RT_NULL);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
usart_sync_disable(desc);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
usart_sync_enable(desc);
break;
/* UART config */
case RT_DEVICE_CTRL_CONFIG :
break;
}
return RT_EOK;
}
/**
* @brief Serial sends a char
*
* This function will send a char to the UART
*
* @return 1.
*/
static int serial_putc(struct rt_serial_device *serial, char c)
{
struct usart_sync_descriptor* desc;
RT_ASSERT(serial != RT_NULL);
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
RT_ASSERT(desc != RT_NULL);
io_write(&desc->io, (const uint8_t *)&c, 1);
return 1;
}
/**
* @brief Serial gets a char
*
* This function will get a char from the UART
*
* @return received char character or -1 if no char received.
*/
static int serial_getc(struct rt_serial_device *serial)
{
char c;
int ch;
struct usart_sync_descriptor* desc;
RT_ASSERT(serial != RT_NULL);
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
RT_ASSERT(desc != RT_NULL);
ch = -1;
if (usart_sync_is_rx_not_empty(desc))
{
io_read(&desc->io, (uint8_t *)&c, 1);;
ch = c & 0xff;
}
return ch;
}
static const struct rt_uart_ops sam_serial_ops =
{
serial_configure,
serial_control,
serial_putc,
serial_getc,
};
/**
* @brief Initialize the UART
*
* This function initialize the UART
*
* @return None.
*/
int rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
sam_serial.ops = &sam_serial_ops;
sam_serial.config = config;
sam_serial.serial_rx = RT_NULL;
sam_serial.serial_rx = RT_NULL;
rt_hw_serial_register(&sam_serial, "uart0",
RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
return 0;
}
/*@}*/
bsp/microchip/same70/board/serial.h
-22
View File
@@ -1,22 +0,0 @@
/*
* Copyright (c)
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Email Notes
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
*/
#ifndef __BOARD_SERIAL_H_
#define __BOARD_SERIAL_H_
#include <rtthread.h>
/**
* @brief External function definitions
*
*/
int rt_hw_uart_init(void);
#endif // __BOARD_SERIAL_H_
bsp/microchip/same70/bsp/AtmelStart.gpdsc
+40 -9
View File
@@ -42,14 +42,19 @@
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
<files>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/mac_async.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_mac_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
@@ -58,17 +63,23 @@
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_mac_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_mac_async.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
@@ -85,6 +96,7 @@
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gmac/hpl_gmac_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_acc_e70b.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e70b.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_afec_e70b.h"/>
@@ -123,56 +135,75 @@
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_utmi_e70b.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e70b.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_xdmac_e70b.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="led_switcher_main.c"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/led_switcher.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/ethernet_phy.rst"/>
<file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ieee8023_mii_standard_register.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/afec/hpl_afec.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m7_base.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gmac/hpl_gmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mcan/hpl_mcan.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/mcan/hpl_mcan.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pio/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_pmc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_pmc.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_sleep.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick_ARMv7_base.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/twihs/hpl_twihs.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/usart/hpl_usart.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/usart/hpl_usart_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/xdmac/hpl_xdmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_afec_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mcan_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_pmc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_ARMv7_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_twihs_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_usart_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_xdmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/ieee8023_mii_standard_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/afec"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mcan"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pio"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pmc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/twihs"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/usart"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/xdmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="ethernet_phy"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
bsp/microchip/same70/bsp/SConscript
+9 -1
View File
@@ -14,14 +14,19 @@ CPPDEFINES += [rtconfig.DEVICE_TYPE]
src = Glob('hal/src/*.c')
src += Glob('hal/utils/src/*.c')
src += Glob('hpl/afec/*.c')
src += Glob('hpl/core/*.c')
src += Glob('hpl/gmac/*.c')
src += Glob('hpl/mcan/*.c')
src += Glob('hpl/pmc/*.c')
src += Glob('hpl/systick/*.c')
src += Glob('hpl/twihs/*.c')
src += Glob('hpl/usart/*.c')
src += Glob('hpl/xdmac/*.c')
src += Glob('ethernet_phy/*.c')
src += [cwd + '/atmel_start.c']
src += [cwd + '/driver_init.c']
src += [cwd + '/ethernet_phy_main.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
@@ -38,6 +43,7 @@ path = [
cwd,
cwd + '/CMSIS/Core/Include',
cwd + '/config',
cwd + '/ethernet_phy',
cwd + '/hal/include',
cwd + '/hal/utils/include',
cwd + '/hpl/core',
@@ -47,7 +53,9 @@ path = [
cwd + '/hpl/systick',
cwd + '/hpl/usart',
cwd + '/hri',
cwd + '/same70b/include',]
cwd + '/same70b/include',
cwd + '/../board',
cwd + '/../../common/applications']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
bsp/microchip/same70/bsp/atmel_start.c
+1
View File
@@ -6,4 +6,5 @@
void atmel_start_init(void)
{
system_init();
ethernet_phys_init();
}
bsp/microchip/same70/bsp/atmel_start.h
+1
View File
@@ -6,6 +6,7 @@ extern "C" {
#endif
#include "driver_init.h"
#include "ethernet_phy_main.h"
/**
* Initializes MCU, drivers and middleware in the project
bsp/microchip/same70/bsp/atmel_start_config.atstart
+414 -19
View File
@@ -17,21 +17,168 @@ board:
identifier: SAME70Xplained
device: ATSAME70Q21B-AN
details: null
application:
definition: 'Atmel:Application_Examples:0.0.1::Application:LED_switcher:'
configuration: null
middlewares: {}
application: null
middlewares:
MACIF_PHY:
user_label: MACIF_PHY
configuration:
ieee8023_mii_control_autoneg_en: true
ieee8023_mii_control_duplex_mode: full duplex
ieee8023_mii_control_isolate_en: false
ieee8023_mii_control_loopback_en: false
ieee8023_mii_control_powerdown_en: false
ieee8023_mii_control_reg0_setting: true
ieee8023_mii_control_speed_lsb: 100 Mb/s
ieee8023_mii_phy_address: 0
definition: Atmel:Ethernet_PHY:0.0.1::Generic_Ethernet_PHY_Driver
functionality: Ethernet_PHY
api: Ethernet:GenericPHY:Driver
dependencies:
Communication IO: MACIF
drivers:
ADC_0:
user_label: ADC_0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::AFEC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
functionality: ADC
api: HAL:Driver:ADC_Sync
configuration:
afec_advanced_settings: true
afec_channel0_enable: false
afec_channel10_enable: true
afec_channel11_enable: false
afec_channel1_enable: false
afec_channel2_enable: false
afec_channel3_enable: false
afec_channel4_enable: false
afec_channel5_enable: false
afec_channel6_enable: false
afec_channel7_enable: false
afec_channel8_enable: false
afec_channel9_enable: false
afec_channel_diff0: false
afec_channel_diff1: false
afec_channel_diff10: false
afec_channel_diff11: false
afec_channel_diff2: false
afec_channel_diff3: false
afec_channel_diff4: false
afec_channel_diff5: false
afec_channel_diff6: false
afec_channel_diff7: false
afec_channel_diff8: false
afec_channel_diff9: false
afec_channel_dual0: false
afec_channel_dual1: false
afec_channel_dual10: true
afec_channel_dual11: false
afec_channel_dual2: false
afec_channel_dual3: false
afec_channel_dual4: false
afec_channel_dual5: false
afec_channel_dual6: false
afec_channel_dual7: false
afec_channel_dual8: false
afec_channel_dual9: false
afec_channel_ecorr0: false
afec_channel_ecorr1: false
afec_channel_ecorr10: true
afec_channel_ecorr11: false
afec_channel_ecorr2: false
afec_channel_ecorr3: false
afec_channel_ecorr4: false
afec_channel_ecorr5: false
afec_channel_ecorr6: false
afec_channel_ecorr7: false
afec_channel_ecorr8: false
afec_channel_ecorr9: false
afec_channel_gain0: '1'
afec_channel_gain1: '1'
afec_channel_gain10: '1'
afec_channel_gain11: '1'
afec_channel_gain2: '1'
afec_channel_gain3: '1'
afec_channel_gain4: '1'
afec_channel_gain5: '1'
afec_channel_gain6: '1'
afec_channel_gain7: '1'
afec_channel_gain8: '1'
afec_channel_gain9: '1'
afec_channel_offset0: 512
afec_channel_offset1: 512
afec_channel_offset10: 512
afec_channel_offset11: 512
afec_channel_offset2: 512
afec_channel_offset3: 512
afec_channel_offset4: 512
afec_channel_offset5: 512
afec_channel_offset6: 512
afec_channel_offset7: 512
afec_channel_offset8: 512
afec_channel_offset9: 512
afec_cmpmode: The converted data is lower than the low threshold of the window.
afec_cmpsel: Channel 0
afec_compare_all_channels: false
afec_comparison_settings: false
afec_cosr_csel: false
afec_fast_wakeup_mode: false
afec_freerunning_mode: false
afec_gaincorr: 0
afec_highthres: 0
afec_ibctl: 1
afec_lowthres: 0
afec_offsetcorr: 0
afec_prescaler: 49
afec_resolution: 16-bit
afec_sign_mode: 'Single-Ended channels: Unsigned. Differential channels: Signed.'
afec_sleep_mode: false
afec_startup_time: 64 periods of AFE clock
afec_stm: true
afec_tag: true
afec_tracktim: 15
afec_transfer: 2
afec_trigger_enable: false
afec_trigger_selection: AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1
afec_usch0: None
afec_usch1: None
afec_usch10: None
afec_usch11: None
afec_usch2: None
afec_usch3: None
afec_usch4: None
afec_usch5: None
afec_usch6: None
afec_usch7: None
afec_usch8: None
afec_usch9: None
afec_useq: false
optional_signals:
- identifier: ADC_0:AD/10
pad: PB0
mode: Enabled
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::AFEC0.AD.10
name: AFEC0/AD/10
label: AD/10
variant: null
clocks:
domain_group:
nodes:
- name: AFEC
input: Master Clock (MCK)
external: false
external_frequency: 0
configuration:
afec_clock_source: Master Clock (MCK)
PMC:
user_label: PMC
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::PMC::driver_config_definition::PMC::HAL:HPL:PMC
functionality: System
api: HAL:HPL:PMC
configuration:
$input: 240000000
$input_id: UDPLL with Divider (MCKR UPLLDIV2)
RESERVED_InputFreq: 240000000
RESERVED_InputFreq_id: UDPLL with Divider (MCKR UPLLDIV2)
$input: 12000000
$input_id: Main Clock (MAINCK)
RESERVED_InputFreq: 12000000
RESERVED_InputFreq_id: Main Clock (MAINCK)
_$freq_output_32kHz External Crystal Oscillator (XOSC32K): 0
_$freq_output_32kHz High Accuracy Internal Oscillator (OSC32K): 0
_$freq_output_Embedded 4/8/12MHz RC Oscillator (OSC12M): '12000000'
@@ -165,27 +312,58 @@ drivers:
external: false
external_frequency: 0
configuration: {}
DELAY_0:
user_label: DELAY_0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
functionality: Delay
api: HAL:Driver:Delay
I2C_0:
user_label: I2C_0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::TWIHS0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
functionality: I2C
api: HAL:Driver:I2C_Master_Sync
configuration:
systick_arch_tickint: false
optional_signals: []
i2c_master_advanced: true
i2c_master_baud_rate: 100000
i2c_master_digital_filter_enable: true
i2c_master_filter_threshold: '2'
i2c_master_packet_error_check: false
i2c_master_pad_filter_enable: true
i2c_master_smbus_clock_prescaler: Divide by 2
i2c_master_smbus_enable: false
i2c_master_thigh_max: 0
i2c_master_tlow_mext: 0
i2c_master_tlow_sext: 0
optional_signals:
- identifier: I2C_0:TWCK/0
pad: PA4
mode: Enabled
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::TWIHS0.TWCK.0
name: TWIHS0/TWCK/0
label: TWCK/0
- identifier: I2C_0:TWD/0
pad: PA3
mode: Enabled
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::TWIHS0.TWD.0
name: TWIHS0/TWD/0
label: TWD/0
variant: null
clocks:
domain_group: null
domain_group:
nodes:
- name: TWIHS
input: Master Clock (MCK)
external: false
external_frequency: 0
configuration:
twihs_clock_source: Master Clock (MCK)
TARGET_IO:
user_label: TARGET_IO
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::USART1::driver_config_definition::UART::HAL:Driver:USART.Sync
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::USART1::driver_config_definition::UART::HAL:Driver:USART.Async
functionality: USART
api: HAL:Driver:USART_Sync
api: HAL:Driver:USART_Async
configuration:
usart_9bits_enable: false
usart__inack: The NACK is not generated
usart__oversampling_mode: 16 Oversampling
usart_advanced: false
usart_advanced: true
usart_arch_fractional: 0
usart_arch_msbf: LSB is transmitted first
usart_baud_rate: 115200
@@ -479,6 +657,145 @@ drivers:
variant: null
clocks:
domain_group: null
MACIF:
user_label: MACIF
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::GMAC::driver_config_definition::GMAC::HAL:Driver:GMAC.Async
functionality: Ethernet_MAC
api: HAL:Driver:GMAC_Async
configuration:
gmac_arch_adv_cfg: true
gmac_arch_cltto: Clause 22 Operation
gmac_arch_dcfgr_ddrp: false
gmac_arch_dcfgr_drbs: 8
gmac_arch_dcfgr_esma: false
gmac_arch_dcfgr_espa: false
gmac_arch_dcfgr_fbldo: Always use INCR4 AHB bursts
gmac_arch_dcfgr_rxbms: 4 Kbytes
gmac_arch_dcfgr_txcoen: true
gmac_arch_dcfgr_txpbms: 4 Kbytes
gmac_arch_dma_cfg: true
gmac_arch_ipgs_fl_div: 1
gmac_arch_ipgs_fl_mul: 1
gmac_arch_mii_cfg: true
gmac_arch_ncfgr_caf: false
gmac_arch_ncfgr_clk: '64'
gmac_arch_ncfgr_dcpf: false
gmac_arch_ncfgr_df: true
gmac_arch_ncfgr_dnvlan: false
gmac_arch_ncfgr_efrhd: false
gmac_arch_ncfgr_ipgsen: false
gmac_arch_ncfgr_irxer: false
gmac_arch_ncfgr_irxfcs: false
gmac_arch_ncfgr_jframe: false
gmac_arch_ncfgr_lferd: false
gmac_arch_ncfgr_maxfs: true
gmac_arch_ncfgr_mtihen: false
gmac_arch_ncfgr_nbc: false
gmac_arch_ncfgr_pen: false
gmac_arch_ncfgr_rfcs: false
gmac_arch_ncfgr_rty: false
gmac_arch_ncfgr_rxbp: false
gmac_arch_ncfgr_rxbufo: 0
gmac_arch_ncfgr_rxcoen: false
gmac_arch_ncfgr_spd: true
gmac_arch_ncfgr_unihen: false
gmac_arch_ncr_bp: false
gmac_arch_ncr_enpbpr: false
gmac_arch_ncr_lbl: false
gmac_arch_ncr_mpe: true
gmac_arch_ncr_txpbpf: false
gmac_arch_ncr_westat: false
gmac_arch_rpsf_en: false
gmac_arch_rpsf_wm: 100
gmac_arch_rxdescr_num: 16
gmac_arch_svlan_enable: true
gmac_arch_svlan_type: 33024
gmac_arch_tpsf_en: false
gmac_arch_tpsf_wm: 100
gmac_arch_txbuf_size: 1500
gmac_arch_txdescr_num: 8
gmac_arch_ur_rmii: RMII
optional_signals:
- identifier: MACIF:GMDC
pad: PD8
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GMDC
name: GMAC/GMDC
label: GMDC
- identifier: MACIF:GMDIO
pad: PD9
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GMDIO
name: GMAC/GMDIO
label: GMDIO
- identifier: MACIF:GRX/0
pad: PD5
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GRX.0
name: GMAC/GRX/0
label: GRX/0
- identifier: MACIF:GRX/1
pad: PD6
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GRX.1
name: GMAC/GRX/1
label: GRX/1
- identifier: MACIF:GRXDV
pad: PD4
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GRXDV
name: GMAC/GRXDV
label: GRXDV
- identifier: MACIF:GRXER
pad: PD7
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GRXER
name: GMAC/GRXER
label: GRXER
- identifier: MACIF:GTX/0
pad: PD2
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GTX.0
name: GMAC/GTX/0
label: GTX/0
- identifier: MACIF:GTX/1
pad: PD3
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GTX.1
name: GMAC/GTX/1
label: GTX/1
- identifier: MACIF:GTXCK
pad: PD0
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GTXCK
name: GMAC/GTXCK
label: GTXCK
- identifier: MACIF:GTXEN
pad: PD1
mode: Enable
configuration: null
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::GMAC.GTXEN
name: GMAC/GTXEN
label: GTXEN
variant: null
clocks:
domain_group:
nodes:
- name: GMAC
input: Master Clock (MCK)
external: false
external_frequency: 0
configuration:
gmac_clock_source: Master Clock (MCK)
CAN_0:
user_label: CAN_0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::MCAN1::driver_config_definition::CAN::HAL:Driver:CAN.Async
@@ -543,12 +860,24 @@ drivers:
configuration:
mcan_clock_source: Programmable Clock Controller 5 (PMC_PCK5)
pads:
PD0:
name: PD0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD0
mode: Peripheral IO
user_label: PD0
configuration: null
PC12:
name: PC12
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC12
mode: Peripheral IO
user_label: PC12
configuration: null
PB0:
name: PB0
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PB0
mode: Analog
user_label: PB0
configuration: null
PA21:
name: PA21
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PA21
@@ -562,6 +891,12 @@ pads:
user_label: SW0
configuration:
pad_pull_config: Pull-up
PA4:
name: PA4
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PA4
mode: Peripheral IO
user_label: PA4
configuration: null
LED0:
name: PC8
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC8
@@ -569,6 +904,12 @@ pads:
user_label: LED0
configuration:
pad_initial_level: High
PA3:
name: PA3
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PA3
mode: Peripheral IO
user_label: PA3
configuration: null
PC14:
name: PC14
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC14
@@ -581,5 +922,59 @@ pads:
mode: Peripheral IO
user_label: PB4
configuration: null
PD9:
name: PD9
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD9
mode: Peripheral IO
user_label: PD9
configuration: null
PD8:
name: PD8
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD8
mode: Peripheral IO
user_label: PD8
configuration: null
PD7:
name: PD7
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD7
mode: Peripheral IO
user_label: PD7
configuration: null
PD6:
name: PD6
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD6
mode: Peripheral IO
user_label: PD6
configuration: null
PD5:
name: PD5
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD5
mode: Peripheral IO
user_label: PD5
configuration: null
PD4:
name: PD4
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD4
mode: Peripheral IO
user_label: PD4
configuration: null
PD3:
name: PD3
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD3
mode: Peripheral IO
user_label: PD3
configuration: null
PD2:
name: PD2
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD2
mode: Peripheral IO
user_label: PD2
configuration: null
PD1:
name: PD1
definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PD1
mode: Peripheral IO
user_label: PD1
configuration: null
toolchain_options: []
static_files: []
bsp/microchip/same70/bsp/atmel_start_pins.h
+13
View File
@@ -17,11 +17,24 @@
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define PA3 GPIO(GPIO_PORTA, 3)
#define PA4 GPIO(GPIO_PORTA, 4)
#define SW0 GPIO(GPIO_PORTA, 11)
#define PA21 GPIO(GPIO_PORTA, 21)
#define PB0 GPIO(GPIO_PORTB, 0)
#define PB4 GPIO(GPIO_PORTB, 4)
#define LED0 GPIO(GPIO_PORTC, 8)
#define PC12 GPIO(GPIO_PORTC, 12)
#define PC14 GPIO(GPIO_PORTC, 14)
#define PD0 GPIO(GPIO_PORTD, 0)
#define PD1 GPIO(GPIO_PORTD, 1)
#define PD2 GPIO(GPIO_PORTD, 2)
#define PD3 GPIO(GPIO_PORTD, 3)
#define PD4 GPIO(GPIO_PORTD, 4)
#define PD5 GPIO(GPIO_PORTD, 5)
#define PD6 GPIO(GPIO_PORTD, 6)
#define PD7 GPIO(GPIO_PORTD, 7)
#define PD8 GPIO(GPIO_PORTD, 8)
#define PD9 GPIO(GPIO_PORTD, 9)
#endif // ATMEL_START_PINS_H_INCLUDED
bsp/microchip/same70/bsp/config/hpl_afec_config.h
+1042
View File
File diff suppressed because it is too large Load Diff
bsp/microchip/same70/bsp/config/hpl_gmac_config.h
+492
View File
@@ -0,0 +1,492 @@
/* Auto-generated config file hpl_gmac_config.h */
#ifndef HPL_GMAC_CONFIG_H
#define HPL_GMAC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <h> Network Control configuration
// <q> Enable LoopBack Local
// <i> Connects GTX to GRX, GTXEN to GRXDV and forces full duplex mode.
// <id> gmac_arch_ncr_lbl
#ifndef CONF_GMAC_NCR_LBL
#define CONF_GMAC_NCR_LBL 0
#endif
// <q> Management Port Enable
// <i> Enable the Management port
// <id> gmac_arch_ncr_mpe
#ifndef CONF_GMAC_NCR_MPE
#define CONF_GMAC_NCR_MPE 1
#endif
// <q> Enable write for Static Register
// <i> Make the statistics registers writable for functional test proposes.
// <id> gmac_arch_ncr_westat
#ifndef CONF_GMAC_NCR_WESTAT
#define CONF_GMAC_NCR_WESTAT 0
#endif
// <q> Enable Back pressure
// <i> If set in 10M or 100M half duplex mode, forces collisions on all received frames.
// <id> gmac_arch_ncr_bp
#ifndef CONF_GMAC_NCR_BP
#define CONF_GMAC_NCR_BP 0
#endif
// <q> Enable PFC Priority-based Pause Reception
// <i> Enables PFC negotiation and recognition of priority-based pause frames.
// <id> gmac_arch_ncr_enpbpr
#ifndef CONF_GMAC_NCR_ENPBPR
#define CONF_GMAC_NCR_ENPBPR 0
#endif
// <q> Enable PFC Priority-based Pause Frame
// <i> Takes the values stored in the Transmit PFC Pause Register.
// <id> gmac_arch_ncr_txpbpf
#ifndef CONF_GMAC_NCR_TXPBPF
#define CONF_GMAC_NCR_TXPBPF 0
#endif
// </h>
// <h> Network Configuration
// <q> 100Mbps Speed
// <i> Set to one to indicate 100 Mbps operation, zero for 10 Mbps.
// <id> gmac_arch_ncfgr_spd
#ifndef CONF_GMAC_NCFGR_SPD
#define CONF_GMAC_NCFGR_SPD 1
#endif
// <q> Enable Full Duplex
// <i> Enable Full duplex
// <id> gmac_arch_ncfgr_df
#ifndef CONF_GMAC_NCFGR_FD
#define CONF_GMAC_NCFGR_FD 1
#endif
// <q> Discard Non-VLAN Frames
// <i> Discard Non-VLAN Frames
// <id> gmac_arch_ncfgr_dnvlan
#ifndef CONF_GMAC_NCFGR_DNVLAN
#define CONF_GMAC_NCFGR_DNVLAN 0
#endif
// <q> Enable Jumbo Frame
// <i> Enable jumbo frames up to 10240 bytes to be accepted.
// <id> gmac_arch_ncfgr_jframe
#ifndef CONF_GMAC_NCFGR_JFRAME
#define CONF_GMAC_NCFGR_JFRAME 0
#endif
// <q> Copy All Frames
// <i> All valid frames will be accepted
// <id> gmac_arch_ncfgr_caf
#ifndef CONF_GMAC_NCFGR_CAF
#define CONF_GMAC_NCFGR_CAF 0
#endif
// <q> No broadcast
// <i> Frames addressed to the broadcast address of all ones will not be accepted.
// <id> gmac_arch_ncfgr_nbc
#ifndef CONF_GMAC_NCFGR_NBC
#define CONF_GMAC_NCFGR_NBC 0
#endif
// <q> Multicast Hash Enable
// <i> Multicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register.
// <id> gmac_arch_ncfgr_mtihen
#ifndef CONF_GMAC_NCFGR_MTIHEN
#define CONF_GMAC_NCFGR_MTIHEN 0
#endif
// <q> Unicast Hash Enable
// <i> Unicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register.
// <id> gmac_arch_ncfgr_unihen
#ifndef CONF_GMAC_NCFGR_UNIHEN
#define CONF_GMAC_NCFGR_UNIHEN 0
#endif
// <q> 1536 Maximum Frame Size
// <i> Accept frames up to 1536 bytes in length.
// <id> gmac_arch_ncfgr_maxfs
#ifndef CONF_GMAC_NCFGR_MAXFS
#define CONF_GMAC_NCFGR_MAXFS 1
#endif
// <q> Retry Test
// <i> Must be set to zero for normal operation. If set to one the backoff
// <i> between collisions will always be one slot time. Setting this bit to
// <i> one helps test the too many retries condition. Also used in the pause
// <i> frame tests to reduce the pause counter's decrement time from 512 bit
// <i> times, to every GRXCK cycle.
// <id> gmac_arch_ncfgr_rty
#ifndef CONF_GMAC_NCFGR_RTY
#define CONF_GMAC_NCFGR_RTY 0
#endif
// <q> Pause Enable
// <i> When set, transmission will pause if a non-zero 802.3 classic pause
// <i> frame is received and PFC has not been negotiated
// <id> gmac_arch_ncfgr_pen
#ifndef CONF_GMAC_NCFGR_PEN
#define CONF_GMAC_NCFGR_PEN 0
#endif
// <o> Receive Buffer Offset <0-3>
// <i> Indicates the number of bytes by which the received data is offset from
// <i> the start of the receive buffer.
// <id> gmac_arch_ncfgr_rxbufo
#ifndef CONF_GMAC_NCFGR_RXBUFO
#define CONF_GMAC_NCFGR_RXBUFO 0
#endif
// <q> Length Field Error Frame Discard
// <i> Setting this bit causes frames with a measured length shorter than the
// <i> extracted length field (as indicated by bytes 13 and 14 in a non-VLAN
// <i> tagged frame) to be discarded. This only applies to frames with a length
// <i> field less than 0x0600.
// <id> gmac_arch_ncfgr_lferd
#ifndef CONF_GMAC_NCFGR_LFERD
#define CONF_GMAC_NCFGR_LFERD 0
#endif
// <q> Remove FCS
// <i> Setting this bit will cause received frames to be written to memory
// <i> without their frame check sequence (last 4 bytes). The frame length
// <i> indicated will be reduced by four bytes in this mode.
// <id> gmac_arch_ncfgr_rfcs
#ifndef CONF_GMAC_NCFGR_RFCS
#define CONF_GMAC_NCFGR_RFCS 0
#endif
// <o> MDC Clock Division
// <i> Set according to MCK speed. These three bits determine the number MCK
// <i> will be divided by to generate Management Data Clock (MDC). For
// <i> conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
// <i> (MDC is only active during MDIO read and write operations).
// <0=> 8
// <1=> 16
// <2=> 32
// <3=> 48
// <4=> 64
// <5=> 96
// <id> gmac_arch_ncfgr_clk
#ifndef CONF_GMAC_NCFGR_CLK
#define CONF_GMAC_NCFGR_CLK 4
#endif
/**
* For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
**/
#ifndef CONF_GMAC_MCK_FREQUENCY
#if CONF_GMAC_NCFGR_CLK == 0
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 8)
#elif CONF_GMAC_NCFGR_CLK == 1
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 16)
#elif CONF_GMAC_NCFGR_CLK == 2
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 32)
#elif CONF_GMAC_NCFGR_CLK == 3
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 48)
#elif CONF_GMAC_NCFGR_CLK == 4
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 64)
#elif CONF_GMAC_NCFGR_CLK == 5
#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 96)
#endif
#endif
#if CONF_GMAC_MCK_FREQUENCY > 2500000
#warning For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
#endif
// <q> Disable Copy of Pause Frames
// <i> Set to one to prevent valid pause frames being copied to memory. When
// <i> set, pause frames are not copied to memory regardless of the state of
// <i> the Copy All Frames bit, whether a hash match is found or whether a
// <i> type ID match is identified. If a destination address match is found,
// <i> the pause frame will be copied to memory. Note that valid pause frames
// <i> received will still increment pause statistics and pause the
// <i> transmission of frames as required.
// <id> gmac_arch_ncfgr_dcpf
#ifndef CONF_GMAC_NCFGR_DCPF
#define CONF_GMAC_NCFGR_DCPF 0
#endif
// <q> Receive Checksum Offload Enable
// <i> When set, the receive checksum engine is enabled. Frames with bad IP,
// <i> TCP or UDP checksums are discarded.
// <id> gmac_arch_ncfgr_rxcoen
#ifndef CONF_GMAC_NCFGR_RXCOEN
#define CONF_GMAC_NCFGR_RXCOEN 0
#endif
// <q> Enable Frames Received in Half Duplex
// <i> Enable frames to be received in half-duplex mode while transmittinga.
// <id> gmac_arch_ncfgr_efrhd
#ifndef CONF_GMAC_NCFGR_EFRHD
#define CONF_GMAC_NCFGR_EFRHD 0
#endif
// <q> Ignore RX FCS
// <i> When set, frames with FCS/CRC errors will not be rejected. FCS error
// <i> statistics will still be collected for frames with bad FCS and FCS
// <i> status will be recorded in frame's DMA descriptor. For normal operation
// <i> this bit must be set to zero.
// <id> gmac_arch_ncfgr_irxfcs
#ifndef CONF_GMAC_NCFGR_IRXFCS
#define CONF_GMAC_NCFGR_IRXFCS 0
#endif
// <q> IP Stretch Enable
// <i> When set, the transmit IPG can be increased above 96 bit times depending
// <i> on the previous frame length using the IPG Stretch Register.
// <id> gmac_arch_ncfgr_ipgsen
#ifndef CONF_GMAC_NCFGR_IPGSEN
#define CONF_GMAC_NCFGR_IPGSEN 0
#endif
// <q> Receive Bad Preamble
// <i> When set, frames with non-standard preamble are not rejected.
// <id> gmac_arch_ncfgr_rxbp
#ifndef CONF_GMAC_NCFGR_RXBP
#define CONF_GMAC_NCFGR_RXBP 0
#endif
// <q> Ignore IPG GRXER
// <i> When set, GRXER has no effect on the GMAC's operation when GRXDV is low.
// <id> gmac_arch_ncfgr_irxer
#ifndef CONF_GMAC_NCFGR_IRXER
#define CONF_GMAC_NCFGR_IRXER 0
#endif
// </h>
// <e> MII Configuration
// <id> gmac_arch_mii_cfg
#ifndef CONF_GMAC_MII_CFG
#define CONF_GMAC_MII_CFG 1
#endif
// <o> MII Mode
// <i> Select MII or RMII mode
// <0=> RMII
// <1=> MII
// <id> gmac_arch_ur_rmii
#ifndef CONF_GMAC_UR_RMII
#define CONF_GMAC_UR_RMII 0
#endif
// <o> PHY Clause Operation
// <i> Chose which Clause operation will be used
// <0=>Clause 45 Operation
// <1=>Clause 22 Operation
// <id> gmac_arch_cltto
#ifndef CONF_GMAC_CLTTO
#define CONF_GMAC_CLTTO 1
#endif
// </e>
// <e> Stacked VLAN Processing
// <i> When enabled, the first VLAN tag in a received frame will only be
// <i> accepted if the VLAN type field is equal to the User defined VLAN Type,
// <i> OR equal to the standard VLAN type (0x8100). Note that the second VLAN
// <i> tag of a Stacked VLAN packet will only be matched correctly if its
// <i> VLAN_TYPE field equals 0x8100.
// <id> gmac_arch_svlan_enable
#ifndef CONF_GMAC_SVLAN_ENABLE
#define CONF_GMAC_SVLAN_ENABLE 1
#endif
// <o> User Defined VLAN Type <0x0-0xFFFF>
// <i> User defined VLAN TYPE
// <id> gmac_arch_svlan_type
#ifndef CONF_GMAC_SVLAN_TYPE
#define CONF_GMAC_SVLAN_TYPE 0x8100
#endif
// </e>
// <e> DMA Configuration
// <i> The GMAC DMA controller is connected to the MAC FIFO interface and
// <i> provides a scatter-gather type capability for packet data storage.
// <i> The DMA implements packet buffering where dual-port memories are used
// <i> to buffer multiple frames.
// <id> gmac_arch_dma_cfg
#ifndef CONF_GMAC_DMA_CFG
#define CONF_GMAC_DMA_CFG 1
#endif
// <o> Fixed Burst Length for DMA Data Operations
// <i> Selects the burst length to attempt to use on the AHB when transferring
// <i> frame data. Not used for DMA management operations and only used where
// <i> space and data size allow. Otherwise SINGLE type AHB transfers are used.
// <1=> Always use SINGLE AHB bursts
// <4=> Always use INCR4 AHB bursts
// <8=> Always use INCR8 AHB bursts
// <16=> Always use INCR16 AHB bursts
// <id> gmac_arch_dcfgr_fbldo
#ifndef CONF_GMAC_DCFGR_FBLDO
#define CONF_GMAC_DCFGR_FBLDO 4
#endif
// <q> Endian Swap Mode Enable for Management Descriptor Accesses
// <i> When set, selects swapped endianism for AHB transfers. When clear,
// <i> selects little endian mode.
// <id> gmac_arch_dcfgr_esma
#ifndef CONF_GMAC_DCFGR_ESMA
#define CONF_GMAC_DCFGR_ESMA 0
#endif
// <q> Endian Swap Mode Enable for Packet Data Accesses
// <i> When set, selects swapped endianism for AHB transfers. When clear,
// <i> selects little endian mode.
// <id> gmac_arch_dcfgr_espa
#ifndef CONF_GMAC_DCFGR_ESPA
#define CONF_GMAC_DCFGR_ESPA 0
#endif
// <o> Receiver Packet Buffer Memory Size Select
// <i> Select the receive packet buffer size
// <0=> 0.5 Kbytes
// <1=> 1 Kbytes
// <2=> 2 Kbytes
// <3=> 4 Kbytes
// <id> gmac_arch_dcfgr_rxbms
#ifndef CONF_GMAC_DCFGR_RXBMS
#define CONF_GMAC_DCFGR_RXBMS 3
#endif
// <o> Transmitter Packet Buffer Memory Size Select
// <i> Select the Transmitter packet buffer size
// <0=> 2 Kbytes
// <1=> 4 Kbytes
// <id> gmac_arch_dcfgr_txpbms
#ifndef CONF_GMAC_DCFGR_TXPBMS
#define CONF_GMAC_DCFGR_TXPBMS 1
#endif
// <q> Transmitter Checksum Generation Offload Enable
// <i> Transmitter IP, TCP and UDP checksum generation offload enable. When
// <i> set, the transmitter checksum generation engine is enabled to calculate
// <i> and substitute checksums for transmit frames. When clear, frame data is
// <i> unaffected
// <id> gmac_arch_dcfgr_txcoen
#ifndef CONF_GMAC_DCFGR_TXCOEN
#define CONF_GMAC_DCFGR_TXCOEN 1
#endif
// <o> DMA Receive Buffer Size <1-255>
// <i> DMA receive buffer size in AHB system memory. The value defined by these
// <i> bits determines the size of buffer to use in main AHB system memory when
// <i> writing received data. The value is defined in multiples of 64 bytes,
// <i> thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02
// <i> corresponds to 128 bytes etc.
// <id> gmac_arch_dcfgr_drbs
#ifndef CONF_GMAC_DCFGR_DRBS
#define CONF_GMAC_DCFGR_DRBS 8
#endif
// <q> DMA Discard Received Packets
// <i> When set, the GMAC DMA will automatically discard receive packets from
// <i> the receiver packet buffer memory when no AHB resource is available.
// <i> When low, the received packets will remain to be stored in the SRAM
// <i> based packet buffer until AHB buffer resource next becomes available.
// <i> Note: packet buffer full store and forward mode should be enabled.
// <id> gmac_arch_dcfgr_ddrp
#ifndef CONF_GMAC_DCFGR_DDRP
#define CONF_GMAC_DCFGR_DDRP 0
#endif
// </e>
// <e> Advanced configuration
// <id> gmac_arch_adv_cfg
#ifndef CONF_GMAC_ADV_CFG
#define CONF_GMAC_ADV_CFG 1
#endif
// <o> Number of Transmit Buffer Descriptor <1-255>
// <i> Number of Transmit Buffer Descriptor
// <id> gmac_arch_txdescr_num
#ifndef CONF_GMAC_TXDESCR_NUM
#define CONF_GMAC_TXDESCR_NUM 8
#endif
// <o> Number of Receive Buffer Descriptor <1-255>
// <i> Number of Receive Buffer Descriptor
// <id> gmac_arch_rxdescr_num
#ifndef CONF_GMAC_RXDESCR_NUM
#define CONF_GMAC_RXDESCR_NUM 16
#endif
// <o> Byte size of Transmit Buffer <64-10240>
// <i> Byte size of buffer for each transmit buffer descriptor.
// <id> gmac_arch_txbuf_size
#ifndef CONF_GMAC_TXBUF_SIZE
#define CONF_GMAC_TXBUF_SIZE 1500
#endif
/*
* Receive buffer size is defined by DMA Configuration Register GMAC_DCFGR,
* DRBS: DMA Receive Buffer Size.The value is defined in multiples of 64 bytes,
* thus CONF_GMAC_DCFGR_DRBS = 0x01 corresponds to buffers of 64 bytes,
* 0x02 corresponds to 128 bytes etc.
*/
#ifndef CONF_GMAC_RXBUF_SIZE
#define CONF_GMAC_RXBUF_SIZE (CONF_GMAC_DCFGR_DRBS * 64)
#endif
// <e> Enable Transmit Partial Store and Forward
// <i> This allows for a reduced latency but there are performance implications.
// <id> gmac_arch_tpsf_en
#ifndef CONF_GMAC_TPSF_EN
#define CONF_GMAC_TPSF_EN 0
#endif
// <o> Watermark <20-4095>
// <i> Byte size of buffer for each transmit buffer descriptor.
// <id> gmac_arch_tpsf_wm
#ifndef CONF_GMAC_TPSF_WM
#define CONF_GMAC_TPSF_WM 100
#endif
// </e>
// <e> Enable Receive Partial Store and Forward
// <i> This allows for a reduced latency but there are performance implications.
// <id> gmac_arch_rpsf_en
#ifndef CONF_GMAC_RPSF_EN
#define CONF_GMAC_RPSF_EN 0
#endif
// <o> Watermark <20-4095>
// <i> Byte size of buffer for each transmite buffer descriptor.
// <id> gmac_arch_rpsf_wm
#ifndef CONF_GMAC_RPSF_WM
#define CONF_GMAC_RPSF_WM 100
#endif
// <o> IPG Stretch Multiple <0-15>
// <i> This value will multiplied with the previously transmitted frame length
// <i> (including preamble)
// <id> gmac_arch_ipgs_fl_mul
#ifndef CONF_GMAC_IPGS_FL_MUL
#define CONF_GMAC_IPGS_FL_MUL 1
#endif
// <o> IPG Stretch Divide <1-16>
// <i> Divide the frame length. If the resulting number is greater than 96 and
// <i> IP Stretch Enabled then the resulting number is used for the transmit
// <i> inter-packet-gap
// <id> gmac_arch_ipgs_fl_div
#ifndef CONF_GMAC_IPGS_FL_DIV
#define CONF_GMAC_IPGS_FL_DIV 1
#endif
// </e>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GMAC_CONFIG_H
bsp/microchip/same70/bsp/config/hpl_systick_ARMv7_config.h
-18
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@@ -1,18 +0,0 @@
/* Auto-generated config file hpl_systick_ARMv7_config.h */
#ifndef HPL_SYSTICK_ARMV7_CONFIG_H
#define HPL_SYSTICK_ARMV7_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Advanced settings
// <q> SysTick exception request
// <i> Indicates whether the generation of SysTick exception is enabled or not
// <id> systick_arch_tickint
#ifndef CONF_SYSTICK_TICKINT
#define CONF_SYSTICK_TICKINT 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_SYSTICK_ARMV7_CONFIG_H
bsp/microchip/same70/bsp/config/hpl_twihs_config.h
+213
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@@ -0,0 +1,213 @@
/* Auto-generated config file hpl_twihs_config.h */
#ifndef HPL_TWIHS_CONFIG_H
#define HPL_TWIHS_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
/* TWI0 peripheral clock frequency */
#ifndef CONF_TWIHS0_FREQUENCY
#define CONF_TWIHS0_FREQUENCY (CONF_TWIHS0_FREQUENCY)
#endif
// <h> Standard configuration
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_TWIHS0_BAUD
#define CONF_TWIHS0_BAUD 100000
#endif
// </h>
// <e> Advanced configuration
// <id> i2c_master_advanced
#ifndef CONF_TWIHS0_ADVANCED_CONFIG
#define CONF_TWIHS0_ADVANCED_CONFIG 1
#endif
// <q> SMBus Mode Enabled
// <i> Determine if the SMBus mode enabled
// <id> i2c_master_smbus_enable
#ifndef CONF_TWIHS0_SMBEN
#define CONF_TWIHS0_SMBEN 0
#endif
// <q> Packet Error Checking
// <i> SMBus PEC (CRC) generation and check enabled
// <id> i2c_master_packet_error_check
#ifndef CONF_TWIHS0_PECEN
#define CONF_TWIHS0_PECEN 0
#endif
// <o> SMBus Clock Prescaler
// <0=> Divide by 2
// <1=> Divide by 4
// <2=> Divide by 8
// <3=> Divide by 16
// <4=> Divide by 32
// <5=> Divide by 64
// <6=> Divide by 128
// <7=> Divide by 256
// <8=> Divide by 512
// <9=> Divide by 1024
// <10=> Divide by 2048
// <11=> Divide by 4096
// <12=> Divide by 8192
// <13=> Divide by 16384
// <14=> Divide by 32768
// <15=> Divide by 65536
// <i> Used to specify how to prescale the TLOWS, TLOWM and THMAX counters in SMBTR
// <id> i2c_master_smbus_clock_prescaler
#ifndef CONF_TWIHS0_SMBTR_PRESC
#define CONF_TWIHS0_SMBTR_PRESC 0
#endif
// <o> Master Clock Stretch Maximum Cycles <0-255>
// <i> Clock cycles in master maximum clock stretch count. Prescaled by PRESC.
// <i> Used to time TLOW:MEXT. If 0, timeout check disabled.
// <id> i2c_master_tlow_mext
#ifndef CONF_TWIHS0_SMBTR_TLOWM
#define CONF_TWIHS0_SMBTR_TLOWM 0
#endif
// <o> Slave Clock Stretch Maximum Cycles <0-255>
// <i> Clock cycles in slave maximum clock stretch count. Prescaled by PRESC.
// <i> Used to time TLOW:SEXT. If 0, timeout check disabled.
// <id> i2c_master_tlow_sext
#ifndef CONF_TWIHS0_SMBTR_TLOWS
#define CONF_TWIHS0_SMBTR_TLOWS 0
#endif
// <o> Clock High Maximum Cycles <0-255>
// <i> Clock cycles in clock high maximum count. Prescaled by PRESC. Used for
// <i> bus free detection. Used to time THIGH:MAX.
// <id> i2c_master_thigh_max
#ifndef CONF_TWIHS0_SMBTR_THMAX
#define CONF_TWIHS0_SMBTR_THMAX 0
#endif
// <q> RX Digital Filter Enable
// <i> TWIHS input filtering is active (only in Standard and Fast modes)
// <id> i2c_master_digital_filter_enable
#ifndef CONF_TWIHS0_FILTR_FILT
#define CONF_TWIHS0_FILTR_FILT 1
#endif
// <q> PAD Filter Enable
// <i> PAD analog filter is enabled (The analog filter must be enabled if High-speed mode is enabled)
// <id> i2c_master_pad_filter_enable
#ifndef CONF_TWIHS0_FILTR_PADFEN
#define CONF_TWIHS0_FILTR_PADFEN 1
#endif
// <o> Digital Filter Threshold
// <0=> Disabled
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <6=> 7
// <i> Maximum pulse width of spikes to be suppressed by the input filter, defined in peripheral clock cycles.
// <id> i2c_master_filter_threshold
#ifndef CONF_TWIHS0_FILTR_THRES
#define CONF_TWIHS0_FILTR_THRES 2
#endif
// </e>
/* Configuration for CR (Control Register) */
#ifndef CONF_TWIHS0_CR_REG
#define CONF_TWIHS0_CR_REG \
(TWIHS_CR_SVDIS | (CONF_TWIHS0_SMBEN << TWIHS_CR_SMBEN_Pos) | (CONF_TWIHS0_PECEN << TWIHS_CR_PECEN_Pos))
#endif
/* Configuration for SMBTR(TWI SMBus Timing Register Register) */
#ifndef CONF_TWIHS0_SMBTR_REG
#define CONF_TWIHS0_SMBTR_REG \
((CONF_TWIHS0_SMBTR_PRESC << TWIHS_SMBTR_PRESC_Pos) | (CONF_TWIHS0_SMBTR_TLOWM << TWIHS_SMBTR_TLOWM_Pos) \
| (CONF_TWIHS0_SMBTR_TLOWS << TWIHS_SMBTR_TLOWS_Pos) | (CONF_TWIHS0_SMBTR_THMAX << TWIHS_SMBTR_THMAX_Pos))
#endif
/* Configuration for FILTR(TWI Filter Register Register) */
#ifndef CONF_TWIHS0_FILTR_REG
#define CONF_TWIHS0_FILTR_REG \
((CONF_TWIHS0_FILTR_FILT << TWIHS_FILTR_FILT_Pos) | (CONF_TWIHS0_FILTR_PADFEN << TWIHS_FILTR_PADFEN_Pos) \
| (CONF_TWIHS0_FILTR_THRES << TWIHS_FILTR_THRES_Pos))
#endif
/* The peripheral clock is the source clock for the bit rate generation when
* CONF_TWIHS0_CWGR_BRSRCCLK == 0
* 1 (CLDIV * CKDIV_val + 3)
* Tlow = --------------- = ------------------------------
* baudrate * 2 PeripheralFrequency(HZ)
*/
#define CONF_TWIHS0_CWGR_CLDIV_CALC(freq, baud, ckdiv) (((freq / (baud * 2)) - 3) / ckdiv)
/* Find a valid CWGR_CKDIV value and Check if the CONF_TWIHS0_CKDIV will overflow */
#ifndef CONF_TWIHS0_CWGR_CKDIV
#if CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 1) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 0
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 2) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 1
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 4) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 2
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 8) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 3
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 16) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 4
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 32) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 5
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 64) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 6
#elif CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, 128) <= 255
#define CONF_TWIHS0_CWGR_CKDIV 7
#else
#error Failed to generate TWI0 I2C baudrate, please check settings.
#endif
#endif /* end ifndef CONF_TWIHS0_CWGR_CKDIV */
/* TWIHS_CWGR_CKDIV Result value for calc CWGR_CLDIV and CWGR_CHDIV */
#if CONF_TWIHS0_CWGR_CKDIV == 0
#define CONF_TWIHS0_CWGR_CKDIV_val 1
#elif CONF_TWIHS0_CWGR_CKDIV == 1
#define CONF_TWIHS0_CWGR_CKDIV_val 2
#elif CONF_TWIHS0_CWGR_CKDIV == 2
#define CONF_TWIHS0_CWGR_CKDIV_val 4
#elif CONF_TWIHS0_CWGR_CKDIV == 3
#define CONF_TWIHS0_CWGR_CKDIV_val 8
#elif CONF_TWIHS0_CWGR_CKDIV == 4
#define CONF_TWIHS0_CWGR_CKDIV_val 16
#elif CONF_TWIHS0_CWGR_CKDIV == 5
#define CONF_TWIHS0_CWGR_CKDIV_val 32
#elif CONF_TWIHS0_CWGR_CKDIV == 6
#define CONF_TWIHS0_CWGR_CKDIV_val 64
#elif CONF_TWIHS0_CWGR_CKDIV == 7
#define CONF_TWIHS0_CWGR_CKDIV_val 128
#endif
/* Clock Waveform Generator Register Clock Divider */
#ifndef CONF_TWIHS0_CWGR_CLDIV
#define CONF_TWIHS0_CWGR_CLDIV \
(CONF_TWIHS0_CWGR_CLDIV_CALC(CONF_TWIHS0_FREQUENCY, CONF_TWIHS0_BAUD, CONF_TWIHS0_CWGR_CKDIV_val))
#endif
/* CHDIV same as CLDIV for generator a 50 duty cycle clock */
#ifndef CONF_TWIHS0_CWGR_CHDIV
#define CONF_TWIHS0_CWGR_CHDIV CONF_TWIHS0_CWGR_CLDIV
#endif /* endif CONF_TWIHS0_CWGR_BRSRCCLK == 1 */
/* Configuration for CWGR(TWI Clock Waveform Generator Register) */
#ifndef CONF_TWIHS0_CWGR_REG
#define CONF_TWIHS0_CWGR_REG \
(TWIHS_CWGR_CKDIV(CONF_TWIHS0_CWGR_CKDIV) | TWIHS_CWGR_CHDIV(CONF_TWIHS0_CWGR_CHDIV) \
| TWIHS_CWGR_CLDIV(CONF_TWIHS0_CWGR_CLDIV))
#endif
// <<< end of configuration section >>>
#endif // HPL_TWIHS_CONFIG_H
bsp/microchip/same70/bsp/config/ieee8023_mii_standard_config.h
+106
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@@ -0,0 +1,106 @@
/* Auto-generated config file ieee8023_mii_standard_config.h */
#ifndef IEEE8023_MII_STANDARD_CONFIG_H
#define IEEE8023_MII_STANDARD_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic configuration
// <o> PHY Address <0-31>
// <i> The PHY Address is five bits, allowing 32 unique PHY addresses. A PHY
// <i> that is connected to the station management entity via the mechanical
// <i> interface defined in IEEE 802.3 22.6 shall always respond to
// <i> transactions addressed to PHY Address zero b00000. A station management
// <i> entity that is attached to multiple PHYs must have prior knowledge of
// <i> the appropriate PHY Address for each PHY.
// <id> ieee8023_mii_phy_address
#ifndef CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS
#define CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS 0
#endif
// </h>
// <e> Control Register (Register 0) Settings
// <i> The MII Management Interface Control Register (Register 0) Setting.
// <i> Full details about the can be found in Clause 22.2.4 of the IEEE 802.3
// <i> Specification.
// <id> ieee8023_mii_control_reg0_setting
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING 1
#endif
// <q> Loopback Enable
// <i> Set PHY be placed in a loopback mode of operation.
// <id> ieee8023_mii_control_loopback_en
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN 0
#endif
// <o> Speed Selection
// <i> These bits select the PHY speed.
// <0x0=> 10 Mb/s
// <0x1=> 100 Mb/s
// <0x2=> 1000 Mb/s
// <id> ieee8023_mii_control_speed_lsb
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED 1
#endif
// <q> Auto-Negotiation Enable
// <i> Indicates whether the Auto-Negotiation enable or not
// <id> ieee8023_mii_control_autoneg_en
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN 1
#endif
// <q> Power Down Enable
// <i> Set PHY in a low-power consumption state, The specific behavior of a
// <i> PHY in the power-down state is implementation specific. While in the
// <i> power-down state, the PHY shall respond to management transactions.
// <i> During the transition to the power-down state and while in the
// <i> power-down state, the PHY shall not generate spurious signals on the
// <i> MII or GMII.
// <id> ieee8023_mii_control_powerdown_en
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN 0
#endif
// <q> Isolate Enable
// <i> Set PHY forced to electrically isolate its data paths from the MII or
// <i> GMII. When the PHY is isolated from the MII or GMII it shall not
// <i> respond to the TXD data bundle, TX_EN, TX_ER and GTX_CLK inputs, and it
// <i> shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD
// <i> data bundle, COL, and CRS outputs. When the PHY is isolated from the
// <i> MII or GMII it shall respond to management transactions.
// <id> ieee8023_mii_control_isolate_en
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN 0
#endif
// <o> Duplex Mode Selection
// <i> The duplex mode can be selected via either the Auto-Negotiation enable,
// <i> or manual duplex selection. Manual duplex selection is allowed when
// <i> Auto-Negotiation is disabled. When Auto-Negotiation is enabled, this
// <i> setting has no effect on the link configuration.
// <0x0=> half duplex
// <0x1=> full duplex
// <id> ieee8023_mii_control_duplex_mode
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE 1
#endif
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0 \
(CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN ? MDIO_REG0_BIT_RESET : 0) \
| ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x1) ? MDIO_REG0_BIT_SPEED_SELECT_LSB : 0) \
| ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x2) ? MDIO_REG0_BIT_SPEED_SELECT_MSB : 0) \
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN ? MDIO_REG0_BIT_AUTONEG : 0) \
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN ? MDIO_REG0_BIT_POWER_DOWN : 0) \
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN ? MDIO_REG0_BIT_ISOLATE : 0) \
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE ? MDIO_REG0_BIT_DUPLEX_MODE : 0)
#endif
// </e>
// <<< end of configuration section >>>
#endif // IEEE8023_MII_STANDARD_CONFIG_H
bsp/microchip/same70/bsp/config/peripheral_clk_config.h
+54
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@@ -4,6 +4,24 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> AFEC Clock Settings
// <y> AFEC Clock source
// <CONF_SRC_MCK"> Master Clock (MCK)
// <i> This defines the clock source for the AFEC
// <id> afec_clock_source
#ifndef CONF_AFEC0_SRC
#define CONF_AFEC0_SRC CONF_SRC_MCK
#endif
// </h>
/**
* \def AFEC FREQUENCY
* \brief AFEC's Clock frequency
*/
#ifndef CONF_AFEC0_FREQUENCY
#define CONF_AFEC0_FREQUENCY 150000000
#endif
/**
* \def CONF_HCLK_FREQUENCY
* \brief HCLK's Clock frequency
@@ -46,6 +64,24 @@
*/
#define CONF_PCK6_FREQUENCY 1714285
// <h> TWIHS Clock Settings
// <y> TWIHS Clock source
// <CONF_SRC_MCK"> Master Clock (MCK)
// <i> This defines the clock source for the TWIHS
// <id> twihs_clock_source
#ifndef CONF_TWIHS0_SRC
#define CONF_TWIHS0_SRC CONF_SRC_MCK
#endif
// </h>
/**
* \def TWIHS FREQUENCY
* \brief TWIHS's Clock frequency
*/
#ifndef CONF_TWIHS0_FREQUENCY
#define CONF_TWIHS0_FREQUENCY 150000000
#endif
// <h> USART Clock Settings
// <o> USART Clock source
@@ -76,6 +112,24 @@
#define CONF_USART1_FREQUENCY 150000000
#endif
// <h> GMAC Clock Settings
// <y> GMAC Clock source
// <CONF_SRC_MCK"> Master Clock (MCK)
// <i> Select the clock source for GMAC
// <id> gmac_clock_source
#ifndef CONF_GMAC_SRC
#define CONF_GMAC_SRC CONF_SRC_MCK
#endif
// </h>
/**
* \def GMAC FREQUENCY
* \brief GMAC Clock frequency
*/
#ifndef CONF_GMAC_FREQUENCY
#define CONF_GMAC_FREQUENCY 150000000
#endif
// <h> MCAN Clock Settings
// <y> MCAN Clock source
// <CONF_SRC_PCK5"> Programmable Clock Controller 5 (PMC_PCK5)
bsp/microchip/same70/bsp/documentation/ethernet_phy.rst
+56
View File
@@ -0,0 +1,56 @@
======================================
Generic IEEE 802.3 Ethernet PHY Driver
======================================
This software component supply a generic IEEE802.3 Ethernet PHY driver.
The PHY chip should be compliant IEEE 802.3 Ethernet Standard that
supports MDC/MDIO management interface for PHY register configuration.
The management interface specified here provides a simple, two-wire, serial
interface to connect a management entity and a managed PHY for the purposes of
controlling the PHY and gathering status from the PHY. This interface is
referred to as the MII Management Interface.
The management interface consists of a pair of signals that physically
transport the management information across the MII or GMII, a frame format
and a protocol specification for exchanging management frames, and a register
set that can be read and written using these frames. The register definition
specifies a basic register set with an extension mechanism. The MII uses two
basic registers. The GMII also uses the same two basic registers and adds a
third basic register.
The MII basic register set consists of two registers referred to as the Control
register (Register 0) and the Status register (Register 1). All PHYs that
provide an MII shall incorporate the basic register set. All PHYs that provide
a GMII shall incorporate an extended basic register set consisting of the
Control register (Register 0), Status register (Register 1), and Extended
Status register (Register 15). The status and control functions defined here
are considered basic and fundamental to 100 Mb/s and 1000 Mb/s PHYs.
Registers 2 through 14 are part of the extended register set. The format of
Registers 4 through 10 are defined for the specific Auto-Negotiation protocol
used (Clause 28 or Clause 37). The format of these registers is selected by
the bit settings of Registers 1 and 15.
More information please refer to IEEE Std 802.3 Chapter 22.2.4
Features
--------
* Initialization the Ethernet PHY driver with Ethernet MAC communication
* Setting PHY address
* Reading/Writing register from PHY device
* Setting/Clearing register bit from PHY device
* Enabling/Disabling Power Down
* Restart Auto Negotiation
* Enabling/Disabling Loop Back
* Getting Link Status
* Reset PHY device
Dependencies
------------
* An instance of the Ethernet MAC driver is used by this driver.
Limitations
-----------
N/A
bsp/microchip/same70/bsp/driver_init.c
+111 -12
View File
@@ -13,16 +13,77 @@
#include <utils.h>
#include <hpl_usart_base.h>
struct can_async_descriptor CAN_0;
/*! The buffer size for USART */
#define TARGET_IO_BUFFER_SIZE 16
struct usart_sync_descriptor TARGET_IO;
struct usart_async_descriptor TARGET_IO;
struct can_async_descriptor CAN_0;
void delay_driver_init(void)
static uint8_t TARGET_IO_buffer[TARGET_IO_BUFFER_SIZE];
struct adc_sync_descriptor ADC_0;
struct i2c_m_sync_desc I2C_0;
struct mac_async_descriptor MACIF;
void ADC_0_PORT_init(void)
{
delay_init(SysTick);
gpio_set_pin_function(PB0, GPIO_PIN_FUNCTION_OFF);
}
void TARGET_IO_PORT_init(void)
void ADC_0_CLOCK_init(void)
{
_pmc_enable_periph_clock(ID_AFEC0);
}
void ADC_0_init(void)
{
ADC_0_CLOCK_init();
ADC_0_PORT_init();
adc_sync_init(&ADC_0, AFEC0, (void *)NULL);
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_function(PA4, MUX_PA4A_TWIHS0_TWCK0);
gpio_set_pin_function(PA3, MUX_PA3A_TWIHS0_TWD0);
}
void I2C_0_CLOCK_init(void)
{
_pmc_enable_periph_clock(ID_TWIHS0);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, TWIHS0);
I2C_0_PORT_init();
}
/**
* \brief USART Clock initialization function
*
* Enables register interface and peripheral clock
*/
void TARGET_IO_CLOCK_init()
{
_pmc_enable_periph_clock(ID_USART1);
}
/**
* \brief USART pinmux initialization function
*
* Set each required pin to USART functionality
*/
void TARGET_IO_PORT_init()
{
gpio_set_pin_function(PA21, MUX_PA21A_USART1_RXD1);
@@ -30,16 +91,52 @@ void TARGET_IO_PORT_init(void)
gpio_set_pin_function(PB4, MUX_PB4D_USART1_TXD1);
}
void TARGET_IO_CLOCK_init(void)
{
_pmc_enable_periph_clock(ID_USART1);
}
/**
* \brief USART initialization function
*
* Enables USART peripheral, clocks and initializes USART driver
*/
void TARGET_IO_init(void)
{
TARGET_IO_CLOCK_init();
TARGET_IO_PORT_init();
usart_sync_init(&TARGET_IO, USART1, _usart_get_usart_sync());
usart_async_init(&TARGET_IO, USART1, TARGET_IO_buffer, TARGET_IO_BUFFER_SIZE, _usart_get_usart_async());
}
void MACIF_PORT_init(void)
{
gpio_set_pin_function(PD8, MUX_PD8A_GMAC_GMDC);
gpio_set_pin_function(PD9, MUX_PD9A_GMAC_GMDIO);
gpio_set_pin_function(PD5, MUX_PD5A_GMAC_GRX0);
gpio_set_pin_function(PD6, MUX_PD6A_GMAC_GRX1);
gpio_set_pin_function(PD4, MUX_PD4A_GMAC_GRXDV);
gpio_set_pin_function(PD7, MUX_PD7A_GMAC_GRXER);
gpio_set_pin_function(PD2, MUX_PD2A_GMAC_GTX0);
gpio_set_pin_function(PD3, MUX_PD3A_GMAC_GTX1);
gpio_set_pin_function(PD0, MUX_PD0A_GMAC_GTXCK);
gpio_set_pin_function(PD1, MUX_PD1A_GMAC_GTXEN);
}
void MACIF_CLOCK_init(void)
{
_pmc_enable_periph_clock(ID_GMAC);
}
void MACIF_init(void)
{
MACIF_CLOCK_init();
mac_async_init(&MACIF, GMAC);
MACIF_PORT_init();
}
/**
@@ -116,9 +213,11 @@ void system_init(void)
gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF);
delay_driver_init();
ADC_0_init();
I2C_0_init();
TARGET_IO_init();
MACIF_init();
CAN_0_init();
}
bsp/microchip/same70/bsp/driver_init.h
+24 -5
View File
@@ -21,21 +21,40 @@ extern "C" {
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_delay.h>
#include <hal_adc_sync.h>
#include <hal_usart_sync.h>
#include <hal_i2c_m_sync.h>
#include <hal_usart_async.h>
#include <hal_mac_async.h>
#include <hal_can_async.h>
extern struct usart_sync_descriptor TARGET_IO;
extern struct can_async_descriptor CAN_0;
extern struct adc_sync_descriptor ADC_0;
void delay_driver_init(void);
#define CONF_ADC_0_CHANNEL_10 10
extern struct i2c_m_sync_desc I2C_0;
extern struct usart_async_descriptor TARGET_IO;
extern struct mac_async_descriptor MACIF;
extern struct can_async_descriptor CAN_0;
void ADC_0_PORT_init(void);
void ADC_0_CLOCK_init(void);
void ADC_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
void TARGET_IO_PORT_init(void);
void TARGET_IO_CLOCK_init(void);
void TARGET_IO_init(void);
void MACIF_CLOCK_init(void);
void MACIF_init(void);
void MACIF_PORT_init(void);
void CAN_0_PORT_init(void);
void CAN_0_CLOCK_init(void);
void CAN_0_init(void);
bsp/microchip/same70/bsp/ethernet_phy/ethernet_phy.c
+184
View File
@@ -0,0 +1,184 @@
/**
* \file
*
* \brief Ethernet PHY functionality implementation.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <ethernet_phy.h>
#include <utils_assert.h>
/**
* \brief Perform a HW initialization to the PHY
*/
int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
uint16_t addr)
{
ASSERT(descr && mac && (addr <= 0x1F));
descr->mac = mac;
descr->addr = addr;
return ERR_NONE;
}
/**
* \brief Set PHY address
*/
int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr)
{
ASSERT(descr && (addr <= 0x1F));
descr->addr = addr;
return ERR_NONE;
}
/**
* \brief Read PHY Register value.
*/
int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val)
{
ASSERT(descr && descr->mac && (reg <= 0x1F) && val);
return mac_async_read_phy_reg(descr->mac, descr->addr, reg, val);
}
/**
* \brief Write PHY Register value.
*/
int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val)
{
ASSERT(descr && descr->mac && (reg <= 0x1F));
return mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
}
/**
* \brief Setting bit for a PHY Register
*/
int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
{
int32_t rst;
uint16_t val;
ASSERT(descr && descr->mac && (reg <= 0x1F));
rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
if (rst == ERR_NONE) {
val |= ofst;
rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
}
return rst;
}
/**
* \brief Clear bit for a PHY Register
*/
int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
{
int32_t rst;
uint16_t val;
ASSERT(descr && (reg <= 0x1F));
rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
if (rst == ERR_NONE) {
val &= ~ofst;
rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
}
return rst;
}
/**
* \brief Set PHY low-power consumption state.
*/
int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state)
{
ASSERT(descr);
if (state) {
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
} else {
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
}
}
/**
* \brief Set PHY electrically isolate state.
*/
int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state)
{
ASSERT(descr);
if (state) {
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
} else {
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
}
}
/**
* \brief Restart an auto negotiation of the PHY.
*/
int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr)
{
ASSERT(descr);
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESTART_AUTONEG);
}
/**
* \brief Set PHY placed in a loopback mode of operation.
*/
int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state)
{
ASSERT(descr);
if (state) {
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
} else {
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
}
}
/**
* \brief Get PHY link status
*/
int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status)
{
int32_t rst;
uint16_t val;
ASSERT(descr && descr->mac && status);
rst = mac_async_read_phy_reg(descr->mac, descr->addr, MDIO_REG1_BMSR, &val);
if (rst == ERR_NONE) {
*status = (val & MDIO_REG1_BIT_LINK_STATUS) ? true : false;
}
return rst;
}
/**
* \brief Reset PHY.
*/
int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr)
{
ASSERT(descr);
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESET);
}
bsp/microchip/same70/bsp/ethernet_phy/ethernet_phy.h
+230
View File
@@ -0,0 +1,230 @@
/**
* \file
*
* \brief Ethernet PHY functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef ETHERNET_PHY_H_INCLUDED
#define ETHERNET_PHY_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "compiler.h"
#include "hal_mac_async.h"
#include "ieee8023_mii_standard_register.h"
struct ethernet_phy_descriptor {
struct mac_async_descriptor *mac; /* MAC descriptor handler */
uint16_t addr; /* PHY address, defined by IEEE802.3
section 22.2.4.5.5 */
};
/**
* \brief Perform a HW initialization to the PHY
*
* This should be called only once to initialize the PHY pre-settings.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] mac MAC descriptor, the descriptor should be initialized.
* \param[in] addr Ethernet PHY 5 bits address.
*
* \return Operation result
* \retval ERR_NONE initializing successful.
*/
int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
uint16_t addr);
/**
* \brief Set PHY address
*
* Set PHY management PHY address which defined by IEEE802.3 section 22.2.4.5.5
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] addr PHY address
*
* \return Operation result
* \retval ERR_NONE Set address successful.
*/
int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr);
/**
* \brief Read PHY Register value.
*
* Read PHY Register value from PHY.
*
* \note For conformance with the 802.3 specification, MDC must not exceed
* 2.5 MHz (MDC is only active during MDIO read and write operations).
* The function execution time depend on MDC frequency.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] reg Register address
* \param[out] val Register value
*
* \return Operation result.
* \retval ERR_NONE Read register successful.
*/
int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val);
/**
* \brief Write PHY Register value.
*
* Read PHY Register value from PHY.
*
* \note For conformance with the 802.3 specification, MDC must not exceed
* 2.5 MHz (MDC is only active during MDIO read and write operations).
* The function execution time depend on MDC frequency.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] reg Register address
* \param[out] val Register value
*
* \return Operation result.
* \retval ERR_NONE Write register successful.
*/
int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val);
/**
* \brief Setting bit for a PHY Register
*
* Bit setting for a PHY Register.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] reg Register address.
* \param[in] ofst Register bit mask.
*
* \return Operation result.
* \retval ERR_NONE Set register bit successful.
*/
int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
/**
* \brief Clear bit for a PHY Register
*
* Clear bit for a PHY Register.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] reg Register address.
* \param[in] ofst Register bit mask.
*
* \return Operation result.
* \retval ERR_NONE Clear register bit successful.
*/
int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
/**
* \brief Set PHY low-power consumption state.
*
* The specific behavior of a PHY in the power-down state is implementation
* specific. While in the power-down state, the PHY shall respond to management
* transactions. During the transition to the power-down state and while in the
* power-down state, the PHY shall not generate spurious signals on the MII or
* GMII.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] state The state of the power-down mode.
*
* \return Operation result.
* \retval ERR_NONE Power-Down has been config successful.
*/
int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state);
/**
* \brief Set PHY electrically isolate state.
*
* When the PHY is isolated from the MII or RMII it shall not respond to the
* data bundle.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] state The state of the isolate mode.
*
* \return Operation result.
* \retval ERR_NONE Isolate has been config successful.
*/
int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state);
/**
* \brief Restart an auto negotiation of the PHY.
*
* Restart Auto_Negotantion process
*
* \param[in] descr Ethernet PHY descriptor.
*
* \return Operation result
* \retval ERR_NONE Auto-Negotiation has been initiated.
*/
int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr);
/**
* \brief Set PHY placed in a loopback mode of operation.
*
* When in loopback mode, the PHY shall accept data from the MII/RMII transmit
* data path and return it to the MII/RMII receive data path.
*
* \param[in] descr Ethernet PHY descriptor.
* \param[in] state State of the loopback mode.
*
* \return Operation result
* \retval ERR_NONE Loopback has been set successful.
*/
int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state);
/**
* \brief Get PHY link status
*
* Get PHY link status
*
* \param[in] descr Ethernet PHY descriptor.
* \param[out] status Pointer to the Link Status.
*
* \return ERR_NONE if successfully
*/
int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status);
/**
* \brief Reset PHY.
*
* Resetting PHY, this action set all the status and control register to their
* default states. As a consequence this action may change the internal state
* of the PHY and the state of the physical link associated with the PHY. The
* reset process shall be completed within 0.5 second.
*
* \param[in] descr Ethernet PHY descriptor.
*
* \return ERR_NONE if successfully
*/
int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr);
#ifdef __cplusplus
}
#endif
#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */
bsp/microchip/same70/bsp/ethernet_phy/ieee8023_mii_standard_register.h
+137
View File
@@ -0,0 +1,137 @@
/**
* \file
*
* \brief IEEE802.3 MII Management Standard Register Set
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef ETHERNET_MII_REGISTER_H_INCLUDED
#define ETHERNET_MII_REGISTER_H_INCLUDED
/* IEEE 802.3 Clause22.2.4 defined Standard Registers.
* The MII basic register set consists of two registers referred to as the
* Control register (Register 0) and the Status register (Register 1). All
* PHYs that provide an MII shall incorporate the basic register set. All PHYs
* that provide a GMII shall incorporate an extended basic register set
* consisting of the Control register (Register 0), Status register
* (Register 1), and Extended Status register (Register 15). The status and
* control functions defined here are considered basic and fundamental to
* 100 Mb/s and 1000 Mb/s PHYs. Registers 2 through 14 are part of the
* extended register set. The format of Registers 4 through 10 are defined for
* the specific Auto-Negotiation protocol used (Clause 28 or Clause 37). The
* format of these registers is selected by the bit settings of Registers 1
* and 15.
**/
#define MDIO_REG0_BMCR 0x00 /* Basic Control */
#define MDIO_REG1_BMSR 0x01 /* Basic Status */
#define MDIO_REG2_PHYID1 0x02 /* PHY Idendifier 1 */
#define MDIO_REG3_PHYID2 0x03 /* PHY Idendifier 2 */
#define MDIO_REG4_ANA 0x04 /* Auto_Negotiation Advertisement */
#define MDIO_REG5_ANLPA 0x05 /* Auto_negotiation Link Partner Base Page Ability */
#define MDIO_REG6_ANE 0x06 /* Auto-negotiation Expansion */
#define MDIO_REG7_ANNPT 0x07 /* Auto-negotiation Next Page Transmit */
#define MDIO_REG8_ANLPRNP 0x08 /* Auto-Negotiation Link Partner Received Next Page */
#define MDIO_REG9_MSC 0x09 /* MASTER-SLAVE Control Register */
#define MDIO_REG10_MSS 0x0A /* MASTER-SLAVE Status Register */
#define MDIO_REG11_PSEC 0x0B /* PSE Control Register */
#define MDIO_REG12_PSES 0x0C /* PSE Status Register */
#define MDIO_REG13_MMDAC 0x0D /* MMD Access Control Register */
#define MDIO_REG14_MMDAAD 0x0E /* MMD Access Address Data Register */
#define MDIO_REG15_EXTS 0x0F /* Extended Status */
/* Register 16 to 31 are Reserved for Vendor Specific */
/* Bit definitions: MDIO_REG0_BMCR 0x00 Basic Control */
#define MDIO_REG0_BIT_RESET (1 << 15) /* 1 = Software Reset; 0 = Normal Operation */
#define MDIO_REG0_BIT_LOOPBACK (1 << 14) /* 1 = loopback Enabled; 0 = Normal Operation */
#define MDIO_REG0_BIT_SPEED_SELECT_LSB (1 << 13) /* 1 = 100Mbps; 0=10Mbps */
#define MDIO_REG0_BIT_AUTONEG (1 << 12) /* 1 = Auto-negotiation Enable */
#define MDIO_REG0_BIT_POWER_DOWN (1 << 11) /* 1 = Power down 0=Normal operation */
#define MDIO_REG0_BIT_ISOLATE (1 << 10) /* 1 = Isolates 0 = Normal operation */
#define MDIO_REG0_BIT_RESTART_AUTONEG (1 << 9) /* 1 = Restart auto-negotiation 0 = Normal operation */
#define MDIO_REG0_BIT_DUPLEX_MODE (1 << 8) /* 1 = Full duplex operation 0 = Normal operation */
#define MDIO_REG0_BIT_COLLISION_TEST (1 << 7) /* 1 = Enable COL test; 0 = Disable COL test */
#define MDIO_REG0_BIT_SPEED_SELECT_MSB (1 << 6) /* 1 with LSB0 = 1000Mbps */
#define MDIO_REG0_BIT_UNIDIR_ENABLE (1 << 5) /* Unidirectional Enable */
/* Reserved 4 to 0 Read as 0, ignore on write */
/* Bit definitions: MDIO_BMSR 0x01 Basic Status */
#define MDIO_REG1_BIT_100BASE_T4 (1 << 15) /* 100BASE-T4 Capable */
#define MDIO_REG1_BIT_100BASE_TX_FD (1 << 14) /* 100BASE-TX Full Duplex Capable */
#define MDIO_REG1_BIT_100BASE_TX_HD (1 << 13) /* 100BASE-TX Half Duplex Capable */
#define MDIO_REG1_BIT_10BASE_T_FD (1 << 12) /* 10BASE-T Full Duplex Capable */
#define MDIO_REG1_BIT_10BASE_T_HD (1 << 11) /* 10BASE-T Half Duplex Capable */
#define MDIO_REG1_BIT_100BASE_T2_FD (1 << 10) /* 1000BASE-T2 Full Duplex Capable */
#define MDIO_REG1_BIT_100BASE_T2_HD (1 << 9) /* 1000BASE-T2 Half Duplex Capable */
#define MDIO_REG1_BIT_EXTEND_STATUS (1 << 8) /* 1 = Extend Status Information In Reg 15 */
#define MDIO_REG1_BIT_UNIDIR_ABILITY (1 << 7) /* Unidirectional ability */
#define MDIO_REG1_BIT_MF_PREAMB_SUPPR (1 << 6) /* MII Frame Preamble Suppression */
#define MDIO_REG1_BIT_AUTONEG_COMP (1 << 5) /* Auto-negotiation Complete */
#define MDIO_REG1_BIT_REMOTE_FAULT (1 << 4) /* Remote Fault */
#define MDIO_REG1_BIT_AUTONEG_ABILITY (1 << 3) /* Auto Configuration Ability */
#define MDIO_REG1_BIT_LINK_STATUS (1 << 2) /* Link Status */
#define MDIO_REG1_BIT_JABBER_DETECT (1 << 1) /* Jabber Detect */
#define MDIO_REG1_BIT_EXTEND_CAPAB (1 << 0) /* Extended Capability */
/* Bit definitions: MDIO_PHYID1 0x02 PHY Idendifier 1 */
/* Bit definitions: MDIO_PHYID2 0x03 PHY Idendifier 2 */
#define MDIO_LSB_MASK 0x3F
#define MDIO_OUI_MSB 0x0022
#define MDIO_OUI_LSB 0x1572
/* Bit definitions: MDIO_REG4_ANA 0x04 Auto-Negotiation advertisement */
#define MDIO_REG4_BIT_NEXTPAGE (15 << 0) /* Next Page */
#define MDIO_REG4_BIT_REMOTE_FAULT (13 << 0) /* Remote Fault */
#define MDIO_REG4_BIT_EXT_NEXTPAGE (12 << 0) /* Extended Next Page */
/* Bit definitions: MDIO_ANAR 0x04 Auto_Negotiation Advertisement */
/* Bit definitions: MDIO_ANLPAR 0x05 Auto_negotiation Link Partner Ability */
#define MDIO_NP (1 << 15) /* Next page Indication */
#define MDIO_RF (1 << 13) /* Remote Fault */
#define MDIO_PAUSE_MASK (3 << 10) /* 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) */
/* 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) */
#define MDIO_100T4 (1 << 9) /* 100BASE-T4 Support */
#define MDIO_100TX_FDX (1 << 8) /* 100BASE-TX Full Duplex Support */
#define MDIO_100TX_HDX (1 << 7) /* 100BASE-TX Half Duplex Support */
#define MDIO_10_FDX (1 << 6) /* 10BASE-T Full Duplex Support */
#define MDIO_10_HDX (1 << 5) /* 10BASE-T Half Duplex Support */
#define MDIO_AN_IEEE_802_3 0x0001 /* [00001] = IEEE 802.3 */
/* Bit definitions: MDIO_ANER 0x06 Auto-negotiation Expansion */
#define MDIO_PDF (1 << 4) /* Local Device Parallel Detection Fault */
#define MDIO_LP_NP_ABLE (1 << 3) /* Link Partner Next Page Able */
#define MDIO_NP_ABLE (1 << 2) /* Local Device Next Page Able */
#define MDIO_PAGE_RX (1 << 1) /* New Page Received */
#define MDIO_LP_AN_ABLE (1 << 0) /* Link Partner Auto-negotiation Able */
/* Bit definitions: MDIO_PCR1 0x1E PHY Control 1 */
#define MDIO_OMI_10BASE_T_HD 0x0001
#define MDIO_OMI_100BASE_TX_HD 0x0002
#define MDIO_OMI_10BASE_T_FD 0x0005
#endif /* #ifndef ETHERNET_MII_REGISTER_H_INCLUDED */
bsp/microchip/same70/bsp/ethernet_phy_main.c
+43
View File
@@ -0,0 +1,43 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file or main.c
* to avoid loosing it when reconfiguring.
*/
#include <atmel_start.h>
#include <ieee8023_mii_standard_config.h>
#include <ethernet_phy_main.h>
struct ethernet_phy_descriptor MACIF_PHY_desc;
void MACIF_PHY_init(void)
{
mac_async_enable(&MACIF);
ethernet_phy_init(&MACIF_PHY_desc, &MACIF, CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS);
#if CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING == 1
ethernet_phy_write_reg(&MACIF_PHY_desc, MDIO_REG0_BMCR, CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0);
#endif /* CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING */
}
void MACIF_PHY_example(void)
{
bool link_state;
int32_t rst;
/* Restart an auto-negotiation */
rst = ethernet_phy_restart_autoneg(&MACIF_PHY_desc);
while (rst != ERR_NONE) {
}
/* Wait for PHY link up */
do {
rst = ethernet_phy_get_link_status(&MACIF_PHY_desc, &link_state);
} while (rst == ERR_NONE && link_state == true);
}
void ethernet_phys_init(void)
{
MACIF_PHY_init();
}
bsp/microchip/same70/bsp/ethernet_phy_main.h
+30
View File
@@ -0,0 +1,30 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file or main.c
* to avoid loosing it when reconfiguring.
*/
#ifndef ETHERNET_PHY_MAIN_H
#define ETHERNET_PHY_MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ethernet_phy.h>
extern struct ethernet_phy_descriptor MACIF_PHY_desc;
void ethernet_phys_init(void);
void MACIF_PHY_example(void);
/**
* \brief Ethernet PHY devices
*/
void ethernet_phys_init(void);
#ifdef __cplusplus
}
#endif
#endif /* ETHERNET_PHY_MAIN_H */
bsp/microchip/same70/bsp/examples/driver_examples.c
+47 -5
View File
@@ -10,21 +10,63 @@
#include "driver_init.h"
#include "utils.h"
void delay_example(void)
/**
* Example of using ADC_0 to generate waveform.
*/
void ADC_0_example(void)
{
delay_ms(5000);
uint8_t buffer_ch10[2];
adc_sync_enable_channel(&ADC_0, CONF_ADC_0_CHANNEL_10);
while (1) {
adc_sync_read_channel(&ADC_0, CONF_ADC_0_CHANNEL_10, buffer_ch10, 2);
}
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
/**
* Example of using TARGET_IO to write "Hello World" using the IO abstraction.
*
* Since the driver is asynchronous we need to use statically allocated memory for string
* because driver initiates transfer and then returns before the transmission is completed.
*
* Once transfer has been completed the tx_cb function will be called.
*/
static uint8_t example_TARGET_IO[12] = "Hello World!";
static void tx_cb_TARGET_IO(const struct usart_async_descriptor *const io_descr)
{
/* Transfer completed */
}
void TARGET_IO_example(void)
{
struct io_descriptor *io;
usart_sync_get_io_descriptor(&TARGET_IO, &io);
usart_sync_enable(&TARGET_IO);
io_write(io, (uint8_t *)"Hello World!", 12);
usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, tx_cb_TARGET_IO);
/*usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, rx_cb);
usart_async_register_callback(&TARGET_IO, USART_ASYNC_ERROR_CB, err_cb);*/
usart_async_get_io_descriptor(&TARGET_IO, &io);
usart_async_enable(&TARGET_IO);
io_write(io, example_TARGET_IO, 12);
}
void MACIF_example(void)
{
mac_async_enable(&MACIF);
mac_async_write(&MACIF, (uint8_t *)"Hello World!", 12);
}
void CAN_0_tx_callback(struct can_async_descriptor *const descr)
bsp/microchip/same70/bsp/examples/driver_examples.h
+5 -1
View File
@@ -16,10 +16,14 @@
extern "C" {
#endif
void delay_example(void);
void ADC_0_example(void);
void I2C_0_example(void);
void TARGET_IO_example(void);
void MACIF_example(void);
void CAN_0_example(void);
#ifdef __cplusplus
bsp/microchip/same70/bsp/hal/documentation/adc_sync.rst
+74
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@@ -0,0 +1,74 @@
======================
ADC Synchronous driver
======================
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
A reference signal with a known voltage level is quantified into equally
sized chunks, each representing a digital value from 0 to the highest number
possible with the bit resolution supported by the ADC. The input voltage
measured by the ADC is compared against these chunks and the chunk with the
closest voltage level defines the digital value that can be used to represent
the analog input voltage level.
Usually an ADC can operate in either differential or single-ended mode.
In differential mode two signals (V+ and V-) are compared against each other
and the resulting digital value represents the relative voltage level between
V+ and V-. This means that if the input voltage level on V+ is lower than on
V- the digital value is negative, which also means that in differential
mode one bit is lost to the sign. In single-ended mode only V+ is compared
against the reference voltage, and the resulting digital value can only be
positive, but the full bit-range of the ADC can be used.
Usually multiple resolutions are supported by the ADC, lower resolution can
reduce the conversion time, but lose accuracy.
Some ADCs has a gain stage on the input lines which can be used to increase the
dynamic range. The default gain value is usually x1, which means that the
conversion range is from 0V to the reference voltage.
Applications can change the gain stage, to increase or reduce the conversion
range.
The window mode allows the conversion result to be compared to a set of
predefined threshold values. Applications can use callback function to monitor
if the conversion result exceeds predefined threshold value.
Usually multiple reference voltages are supported by the ADC, both internal and
external with difference voltage levels. The reference voltage have an impact
on the accuracy, and should be selected to cover the full range of the analog
input signal and never less than the expected maximum input voltage.
There are two conversion modes supported by ADC, single shot and free running.
In single shot mode the ADC only make one conversion when triggered by the
application, in free running mode it continues to make conversion from it
is triggered until it is stopped by the application. When window monitoring,
the ADC should be set to free running mode.
Features
--------
* Initialization and de-initialization
* Support multiple Conversion Mode, Single or Free run
* Start ADC Conversion
* Read Conversion Result
Applications
------------
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
Dependencies
------------
* ADC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A
bsp/microchip/same70/bsp/hal/documentation/i2c_master_sync.rst
+87
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@@ -0,0 +1,87 @@
=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A
bsp/microchip/same70/bsp/hal/documentation/mac_async.rst
+43
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@@ -0,0 +1,43 @@
================================
Ethernet MAC Asynchronous Driver
================================
The Ethernet MAC driver implements a 10/100 Mbps Ethernet MAC compatible with
the IEEE 802.3 standard.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Data transfer: transmission, reception
* Enabling/disabling Interrupt
* Notifications about transfer completion and frame received via callbacks
* Address Filter for Specific 48-bit Addresses and Type ID
* Address Filter for Unicast and Multicase Addresses
* Reading/writing PHY registers
Applications
------------
Co-works with thirdpart TCP/IP stacks. E.g., Lwip, Cyclone IP stack.
Dependencies
------------
MAC capable hardware compatible with the IEEE 802.3 standard.
Concurrency
-----------
N/A
Limitations
-----------
N/A
Known issues and workarounds
----------------------------
N/A
bsp/microchip/same70/bsp/hal/documentation/usart_sync.rst → bsp/microchip/same70/bsp/hal/documentation/usart_async.rst
+17 -3
View File
@@ -1,9 +1,20 @@
The USART Synchronous Driver
============================
The USART Asynchronous Driver
=============================
The universal synchronous and asynchronous receiver and transmitter
(USART) is usually used to transfer data from one device to the other.
The USART driver use a ring buffer to store received data. When the USART
raise the data received interrupt, this data will be stored in the ring buffer
at the next free location. When the ring buffer is full, the next reception
will overwrite the oldest data stored in the ring buffer. There is one
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
is called SERCOM0_USART_BUFFER_SIZE.
On the other hand, when sending data over USART, the data is not copied to an
internal buffer, but the data buffer supplied by the user is used. The callback
will only be generated at the end of the buffer and not for each byte.
User can set action for flow control pins by function usart_set_flow_control,
if the flow control is enabled. All the available states are defined in union
usart_flow_control_state.
@@ -24,6 +35,8 @@ Features
* Data order
* Flow control
* Data transfer: transmission, reception
* Notifications about transfer done or error case via callbacks
* Status information with busy state and transfer count
Applications
------------
@@ -34,7 +47,8 @@ between devices.
Dependencies
------------
USART capable hardware.
USART capable hardware, with interrupt on each character is sent or
received.
Concurrency
-----------
bsp/microchip/same70/bsp/hal/include/hal_adc_sync.h
+277
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@@ -0,0 +1,277 @@
/**
* \file
*
* \brief ADC functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ADC_SYNC_H_INCLUDED
#define _HAL_ADC_SYNC_H_INCLUDED
#include <hpl_adc_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_adc_sync
*
* @{
*/
/**
* \brief ADC descriptor
*
* The ADC descriptor forward declaration.
*/
struct adc_sync_descriptor;
/**
* \brief ADC descriptor
*/
struct adc_sync_descriptor {
/** ADC device */
struct _adc_sync_device device;
};
/**
* \brief Initialize ADC
*
* This function initializes the given ADC descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr An ADC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Initialization status.
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize ADC
*
* This function deinitializes the given ADC descriptor.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr An ADC descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
/**
* \brief Enable ADC
*
* Use this function to set the ADC peripheral to enabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Disable ADC
*
* Use this function to set the ADC peripheral to disabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Read data from ADC
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] buf A buffer to read data to
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length);
/**
* \brief Set ADC reference source
*
* This function sets ADC reference source.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] reference A reference source to set
*
* \return Status of the ADC reference source setting.
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
/**
* \brief Set ADC resolution
*
* This function sets ADC resolution.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] resolution A resolution to set
*
* \return Status of the ADC resolution setting.
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* This function sets ADC positive and negative input sources.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*
* \return Status of the ADC channels setting.
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set ADC conversion mode
*
* This function sets ADC conversion mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A conversion mode to set
*
* \return Status of the ADC conversion mode setting.
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
/**
* \brief Set ADC differential mode
*
* This function sets ADC differential mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*
* \return Status of the ADC differential mode setting.
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set ADC channel gain
*
* This function sets ADC channel gain.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] gain A gain to set
*
* \return Status of the ADC gain setting.
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
const adc_gain_t gain);
/**
* \brief Set ADC window mode
*
* This function sets ADC window mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A window mode to set
*
* \return Status of the ADC window mode setting.
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
/**
* \brief Set ADC thresholds
*
* This function sets ADC positive and negative thresholds.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*
* \return Status of the ADC thresholds setting.
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* This function retrieves ADC threshold state.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[out] state The threshold state
*
* \return The state of ADC thresholds state retrieving.
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
adc_threshold_status_t *const state);
/**
* \brief Check if conversion is complete
*
* This function checks if the ADC has finished the conversion.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return The status of ADC conversion completion checking.
* \retval 1 The conversion is complete
* \retval 0 The conversion is not complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t adc_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#include <hpl_missing_features.h>
#endif /* _HAL_ADC_SYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hal_i2c_m_sync.h
+244
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/**
* \file
*
* \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
#define _HAL_I2C_M_SYNC_H_INCLUDED
#include <hpl_i2c_m_sync.h>
#include <hal_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_i2c_master_sync
*
* @{
*/
#define I2C_M_MAX_RETRY 1
/**
* \brief I2C descriptor structure, embed i2c_device & i2c_interface
*/
struct i2c_m_sync_desc {
struct _i2c_m_sync_device device;
struct io_descriptor io;
uint16_t slave_addr;
};
/**
* \brief Initialize synchronous I2C interface
*
* This function initializes the given I/O descriptor to be used as a
* synchronous I2C interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
* \retval -1 The passed parameters were invalid or the interface is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
/**
* \brief Deinitialize I2C interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Uninitialization status.
* \retval -1 The passed parameters were invalid or the interface is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
/**
* \brief Set the slave device address
*
* This function sets the next transfer target slave I2C device address.
* It takes no effect to any already started access.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] addr The slave address to access
* \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
*
* \return Masked slave address. The mask is a maximum 10-bit address, and 10th
* bit is set if a 10-bit address is used
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
/**
* \brief Set baudrate
*
* This function sets the I2C device to the specified baudrate.
* It only takes effect when the hardware is disabled.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] clkrate Unused parameter. Should always be 0
* \param[in] baudrate The baudrate value set to master
*
* \return Whether successfully set the baudrate
* \retval -1 The passed parameters were invalid or the device is already enabled
* \retval 0 The baudrate set is completed successfully
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Sync version of enable hardware
*
* This function enables the I2C device, and then waits for this enabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully enable the device
* \retval -1 The passed parameters were invalid or the device enable failed
* \retval 0 The hardware enabling is completed successfully
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of disable hardware
*
* This function disables the I2C device and then waits for this disabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully disable the device
* \retval -1 The passed parameters were invalid or the device disable failed
* \retval 0 The hardware disabling is completed successfully
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of write command to I2C slave
*
* This function will write the value to a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer holding data to write to the I2C slave device
* \param[in] length The length (in bytes) to write to the I2C slave device
*
* \return Whether successfully write to the device
* \retval <0 The passed parameters were invalid or write fail
* \retval 0 Writing to register is completed successfully
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of read register value from I2C slave
*
* This function will read a byte value from a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer to hold the read data from the I2C slave device
* \param[in] length The length (in bytes) to read from the I2C slave device
*
* \return Whether successfully read from the device
* \retval <0 The passed parameters were invalid or read fail
* \retval 0 Reading from register is completed successfully
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of transfer message to/from the I2C slave
*
* This function will transfer a message between the I2C slave and the master. This function will wait for the operation
* to be done.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] msg An i2c_m_msg struct
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
/**
* \brief Sync version of send stop condition on the i2c bus
*
* This function will create a stop condition on the i2c bus to release the bus
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
/**
* \brief Return I/O descriptor for this I2C instance
*
* This function will return a I/O instance for this I2C driver instance
*
* \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
* \param[in] io_descriptor A pointer to an I/O descriptor pointer type
*
* \return Error code
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t i2c_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
bsp/microchip/same70/bsp/hal/include/hal_mac_async.h
+260
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/**
* \file
*
* \brief MAC functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HAL_MAC_ASYNC_H_INCLUDED
#define HAL_MAC_ASYNC_H_INCLUDED
#include <hpl_mac_async.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_mac_async
*
*@{
*/
/**
* \brief MAC descriptor
*
* The MAC descriptor forward declaration.
*/
struct mac_async_descriptor;
/**
* \brief MAC callback type
*
* \param[in] descr A MAC descriptor
*/
typedef void (*mac_async_cb_t)(struct mac_async_descriptor *const descr);
/**
* \brief MAC callbacks
*/
struct mac_async_callbacks {
mac_async_cb_t receive;
mac_async_cb_t transmit;
};
/**
* \brief MAC descriptor
*/
struct mac_async_descriptor {
struct _mac_async_device dev; /*!< MAC HPL device descriptor */
struct mac_async_callbacks cb; /*!< MAC Callback handlers */
};
/**
* Callback for MAC interrupt
*/
typedef void (*mac_cb)(struct mac_async_descriptor *const descr);
/**
* \brief Initialize the MAC driver
*
* \param[in] descr A MAC descriptor to init.
* \param[in] hw Hardware instance pointer.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_init(struct mac_async_descriptor *const descr, void *const dev);
/**
* \brief Deinitialize the MAC driver
*
* \param[in] descr A MAC descriptor to deinitialize.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_deinit(struct mac_async_descriptor *const descr);
/** \brief Enable the MAC
*
* \param[in] descr Pointer to the HAL MAC descriptor.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_enable(struct mac_async_descriptor *const descr);
/**
* \brief Disable the MAC
*
* \param[in] descr Pointer to the HAL MAC descriptor
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_disable(struct mac_async_descriptor *const descr);
/**
* \brief Write raw data to MAC
*
* Write the raw data to the MAC that will be transmitted
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] buf Pointer to the data buffer.
* \param[in] len Length of the data buffer.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_write(struct mac_async_descriptor *const descr, uint8_t *buf, uint32_t len);
/**
* \brief Read raw data from MAC
*
* Read received raw data from MAC
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] buffer Pointer to the data buffer. If the pointer is NULL, then the
* frame will be discarded.
* \param[in] length The max. length of the data buffer to be read. If the length is zero,
* then the frame will be discard
*
* \return Number of bytes that received
*/
uint32_t mac_async_read(struct mac_async_descriptor *const descr, uint8_t *buf, uint32_t len);
/**
* \brief Get next valid package length
*
* Get next valid package length from the MAC. The application can use this function
* to fetch the length of the next package, malloc a buffer with this
* length, and then invoke mac_async_read to read out the package data.
*
* \param[in] descr Pointer to the HAL MAC descriptor.
*
* \return The number of bytes in the next package that can be read.
*/
uint32_t mac_async_read_len(struct mac_async_descriptor *const descr);
/**
* \brief Enable the MAC IRQ
*
* \param[in] descr Pointer to the HAL MAC descriptor
*/
void mac_async_enable_irq(struct mac_async_descriptor *const descr);
/**
* \brief Disable the MAC IRQ
*
* \param[in] descr Pointer to the HAL MAC descriptor
*/
void mac_async_disable_irq(struct mac_async_descriptor *const descr);
/**
* \brief Register the MAC callback function
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] type Callback function type.
* \param[in] func A callback function. Passing NULL will de-register any
* registered callback.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_register_callback(struct mac_async_descriptor *const descr, const enum mac_async_cb_type type,
const FUNC_PTR func);
/**
* \brief Set MAC filter
*
* Set MAC filter. Ethernet frames matching the filter, will be received.
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] index MAC filter index. Start from 0. The maximum value depends on
* the hardware specifications.
* \param[in] filter Pointer to the filter descriptor.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_set_filter(struct mac_async_descriptor *const descr, uint8_t index, struct mac_async_filter *filter);
/**
* \brief Set MAC filter (expanded).
*
* Set MAC filter. The Ethernet frames matching the filter, will be received.
*
* \param[in] descr Pointer to the HAL MAC descriptor
* \param[in] mac MAC address
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_set_filter_ex(struct mac_async_descriptor *const descr, uint8_t mac[6]);
/**
* \brief Write PHY register
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] addr PHY address.
* \param[in] reg Register address.
* \param[in] val Register value.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_write_phy_reg(struct mac_async_descriptor *const descr, uint16_t addr, uint16_t reg, uint16_t val);
/**
* \brief Read PHY register
*
* \param[in] descr Pointer to the HAL MAC descriptor.
* \param[in] addr PHY address.
* \param[in] reg Register address.
* \param[in] val Register value.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t mac_async_read_phy_reg(struct mac_async_descriptor *const descr, uint16_t addr, uint16_t reg, uint16_t *val);
/**
* \brief Get the MAC driver version
*/
uint32_t mac_async_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_MAC_ASYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hal_usart_async.h
+339
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/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_USART_ASYNC_H_INCLUDED
#define _HAL_USART_ASYNC_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_async.h>
#include <utils_ringbuffer.h>
/**
* \addtogroup doc_driver_hal_usart_async
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor
*
* The USART descriptor forward declaration.
*/
struct usart_async_descriptor;
/**
* \brief USART callback type
*/
typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr);
/**
* \brief USART callback types
*/
enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB };
/**
* \brief USART callbacks
*/
struct usart_async_callbacks {
usart_cb_t tx_done;
usart_cb_t rx_done;
usart_cb_t error;
};
/** \brief USART status
* Status descriptor holds the current status of transfer.
*/
struct usart_async_status {
/** Status flags */
uint32_t flags;
/** Number of characters transmitted */
uint16_t txcnt;
/** Number of characters receviced */
uint16_t rxcnt;
};
/**
* \brief Asynchronous USART descriptor structure
*/
struct usart_async_descriptor {
struct io_descriptor io;
struct _usart_async_device device;
struct usart_async_callbacks usart_cb;
volatile uint32_t stat;
struct ringbuffer rx;
uint16_t tx_por;
uint8_t * tx_buffer;
uint16_t tx_buffer_length;
};
/** USART write busy */
#define USART_ASYNC_STATUS_BUSY 0x0001
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used as USART
* interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via the USART
* \param[in] hw The pointer to the hardware instance
* \param[in] rx_buffer An RX buffer
* \param[in] rx_buffer_length The length of the buffer above
* \param[in] func The pointer to a set of function pointers
*
* \return Initialization status.
* \retval -1 Passed parameters were invalid or the interface is already
* initialized
* \retval 0 The initialization is completed successfully
*/
int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer,
const uint16_t rx_buffer_length, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware
* is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_async_deinit(struct usart_async_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_async_enable(struct usart_async_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_async_disable(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of I/O descriptor retrieving.
*/
int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Register USART callback
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] type Callback type
* \param[in] cb A callback function
*
* \return The status of callback assignment.
* \retval -1 Passed parameters were invalid or the interface is not initialized
* \retval 0 A callback is registered successfully
*/
int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
const enum usart_async_callback_type type, usart_cb_t cb);
/**
* \brief Specify action for flow control pins
*
* This function sets action (or state) for flow control pins if
* the flow control is enabled.
* It sets state of flow control pins only if automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr,
const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the flow control pins
* if the flow control is enabled.
*
* The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of the USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current interface status
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] status The state of USART
*
* \return The status of USART status retrieving.
*/
int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status);
/**
* \brief flush USART ringbuf
*
* This function flush USART RX ringbuf.
*
* \param[in] descr The pointer to USART descriptor
*
* \return ERR_NONE
*/
int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_async_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_USART_ASYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hal_usart_sync.h
-247
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@@ -1,247 +0,0 @@
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SYNC_USART_H_INCLUDED
#define _HAL_SYNC_USART_H_INCLUDED
#include "hal_io.h"
#include <hpl_usart_sync.h>
/**
* \addtogroup doc_driver_hal_usart_sync
*
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Synchronous USART descriptor
*/
struct usart_sync_descriptor {
struct io_descriptor io;
struct _usart_sync_device device;
};
/**
* \brief Initialize USART interface
*
* This function initializes the given I/O descriptor to be used
* as USART interface descriptor.
* It checks if the given hardware is not initialized and
* if the given hardware is permitted to be initialized.
*
* \param[out] descr A USART descriptor which is used to communicate via USART
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to as set of functions pointers
*
* \return Initialization status.
*/
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize USART interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and
* if the given hardware is permitted to be deinitialized.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return De-initialization status.
*/
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
/**
* \brief Enable USART interface
*
* Enables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Enabling status.
*/
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
/**
* \brief Disable USART interface
*
* Disables the USART interface
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return Disabling status.
*/
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve I/O descriptor
*
* This function retrieves the I/O descriptor of the given USART descriptor.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] io An I/O descriptor to retrieve
*
* \return The status of the I/O descriptor retrieving.
*/
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
/**
* \brief Specify action for flow control pins
*
* This function sets the action (or state) for the flow control pins
* if the flow control is enabled.
* It sets the state of flow control pins only if the automatic support of
* the flow control is not supported by the hardware.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] state A state to set the flow control pins
*
* \return The status of flow control action setup.
*/
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
const union usart_flow_control_state state);
/**
* \brief Set USART baud rate
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] baud_rate A baud rate to set
*
* \return The status of baud rate setting.
*/
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
/**
* \brief Set USART data order
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] data_order A data order to set
*
* \return The status of data order setting.
*/
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
/**
* \brief Set USART mode
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] mode A mode to set
*
* \return The status of mode setting.
*/
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
/**
* \brief Set USART parity
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] parity A parity to set
*
* \return The status of parity setting.
*/
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
/**
* \brief Set USART stop bits
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] stop_bits Stop bits to set
*
* \return The status of stop bits setting.
*/
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
/**
* \brief Set USART character size
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[in] size A character size to set
*
* \return The status of character size setting.
*/
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins
* if the flow control is enabled.
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
* if the flow control is done by the hardware
* and the pins state cannot be read out.
*
* \param[in] descr A USART descriptor which is used to communicate via USART
* \param[out] state The state of flow control pins
*
* \return The status of flow control state reading.
*/
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
union usart_flow_control_state *const state);
/**
* \brief Check if the USART transmitter is empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART TX empty checking.
* \retval 0 The USART transmitter is not empty
* \retval 1 The USART transmitter is empty
*/
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Check if the USART receiver is not empty
*
* \param[in] descr A USART descriptor which is used to communicate via USART
*
* \return The status of USART RX empty checking.
* \retval 1 The USART receiver is not empty
* \retval 0 The USART receiver is empty
*/
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t usart_sync_get_version(void);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_SYNC_USART_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_adc_async.h
+264
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/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_ASYNC_H_INCLUDED
#define _HPL_ADC_ASYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_async_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_adc_sync.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_async_device;
/**
* \brief ADC callback types
*/
enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_async_callbacks {
void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
};
/**
* \brief ADC channel interrupt callbacks
*/
struct _adc_async_ch_callbacks {
void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_async_device {
struct _adc_async_callbacks adc_async_cb;
struct _adc_async_ch_callbacks adc_async_ch_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_deinit(struct _adc_async_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_convert(struct _adc_async_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* The result value
*/
uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
/**
* \brief Set lower threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
/**
* \brief Enable/disable ADC channel interrupt
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
const enum _adc_async_callback_type type, const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_ASYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_adc_sync.h
+271
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@@ -0,0 +1,271 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_SYNC_H_INCLUDED
#define _HPL_ADC_SYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_adc_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC reference source
*/
typedef uint8_t adc_reference_t;
/**
* \brief ADC resolution
*/
typedef uint8_t adc_resolution_t;
/**
* \brief ADC positive input for channel
*/
typedef uint8_t adc_pos_input_t;
/**
* \brief ADC negative input for channel
*/
typedef uint8_t adc_neg_input_t;
/**
* \brief ADC threshold
*/
typedef uint16_t adc_threshold_t;
/**
* \brief ADC gain
*/
typedef uint8_t adc_gain_t;
/**
* \brief ADC conversion mode
*/
enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
/**
* \brief ADC differential mode
*/
enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
/**
* \brief ADC window mode
*/
typedef uint8_t adc_window_mode_t;
/**
* \brief ADC threshold status
*/
typedef bool adc_threshold_status_t;
/**
* \brief ADC sync descriptor device structure
*/
struct _adc_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_deinit(struct _adc_sync_device *const device);
/**
* \brief Enable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Disable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_convert(struct _adc_sync_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The result value of channel
*/
uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
/**
* \brief Set threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_SYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_i2c_m_async.h
+205
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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
#define _HPL_I2C_M_ASYNC_H_INCLUDED
#include "hpl_i2c_m_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c master callback names
*/
enum _i2c_m_async_callback_type {
I2C_M_ASYNC_DEVICE_ERROR,
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
I2C_M_ASYNC_DEVICE_RX_COMPLETE
};
struct _i2c_m_async_device;
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
/**
* \brief i2c callback pointers structure
*/
struct _i2c_m_async_callback {
_i2c_error_cb_t error;
_i2c_complete_cb_t tx_complete;
_i2c_complete_cb_t rx_complete;
};
/**
* \brief i2c device structure
*/
struct _i2c_m_async_device {
struct _i2c_m_service service;
void * hw;
struct _i2c_m_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C in interrupt mode
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c interrupt device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C in interrupt mode
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Register callback to I2C
*
* This function does low level I2C callback register.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] cb_type The callback type request
* \param[in] func The callback function pointer
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
FUNC_PTR func);
/**
* \brief Generate stop condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Operation status
* \retval 0 Operation executed successfully
* \retval <0 Operation failed
*/
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Returns the number of bytes left or not used in the I2C message buffer
*
* This function will return the number of bytes left (not written to the bus) or still free
* (not received from the bus) in the message buffer, depending on direction of transmission.
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Number of bytes or error code
* \retval >0 Positive number indicating bytes left
* \retval 0 Buffer is full/empty depending on direction
* \retval <0 Error code
*/
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable/disable I2C master interrupt
*
* param[in] device The pointer to I2C master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
#endif
bsp/microchip/same70/bsp/hal/include/hpl_i2c_m_sync.h
+185
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/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
#define _HPL_I2C_M_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c flags
*/
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_BUSY 0x0100
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
#define I2C_M_FAIL 0x1000
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* \brief i2c Return codes
*/
#define I2C_OK 0 /* Operation successful */
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
#define I2C_ERR_BUS -5 /* Bus error */
#define I2C_ERR_BUSY -6 /* Device busy */
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
/**
* \brief i2c I2C Modes
*/
#define I2C_STANDARD_MODE 0x00
#define I2C_FASTMODE 0x01
#define I2C_HIGHSPEED_MODE 0x02
/**
* \brief i2c master message structure
*/
struct _i2c_m_msg {
uint16_t addr;
volatile uint16_t flags;
int32_t len;
uint8_t * buffer;
};
/**
* \brief i2c master service
*/
struct _i2c_m_service {
struct _i2c_m_msg msg;
uint16_t mode;
uint16_t trise;
};
/**
* \brief i2c sync master device structure
*/
struct _i2c_m_sync_device {
struct _i2c_m_service service;
void * hw;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Send send condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_dev The pointer to i2c device struct
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
#ifdef __cplusplus
}
#endif
#endif
bsp/microchip/same70/bsp/hal/include/hpl_i2c_s_async.h
+184
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/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
#define _HPL_I2C_S_ASYNC_H_INCLUDED
#include "hpl_i2c_s_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c callback types
*/
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
/**
* \brief Forward declaration of I2C Slave device
*/
struct _i2c_s_async_device;
/**
* \brief i2c slave callback function type
*/
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
/**
* \brief i2c slave callback pointers structure
*/
struct _i2c_s_async_callback {
void (*error)(struct _i2c_s_async_device *const device);
void (*tx)(struct _i2c_s_async_device *const device);
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
};
/**
* \brief i2c slave device structure
*/
struct _i2c_s_async_device {
void * hw;
struct _i2c_s_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize asynchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c interrupt device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
/**
* \brief Deinitialize asynchronous I2C in interrupt mode
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
/**
* \brief Abort data transmission
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
/**
* \brief Enable/disable I2C slave interrupt
*
* param[in] device The pointer to I2C slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
const bool disable);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_i2c_s_sync.h
+184
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/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
#define _HPL_I2C_S_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I2C Slave status type
*/
typedef uint32_t i2c_s_status_t;
/**
* \brief i2c slave device structure
*/
struct _i2c_s_sync_device {
void *hw;
};
#include <compiler.h>
/**
* \name HPL functions
*/
/**
* \brief Initialize synchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
/**
* \brief Deinitialize synchronous I2C slave
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
/**
* \brief Clear the Data Ready interrupt flag
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
/**
* \brief Read a byte from the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Data received via I2C interface.
*/
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if I2C is ready to send next byte
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the ready check.
* \retval true if the I2C is ready to send next byte
* \retval false if the I2C is not ready to send next byte
*/
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if there is data received by I2C
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the data received check.
* \retval true if the I2C has received a byte
* \retval false if the I2C has not received a byte
*/
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_mac_async.h
+280
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@@ -0,0 +1,280 @@
/**
* \file
*
* \brief MAC functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HPL_MAC_ASYNC_H_INCLUDED
#define HPL_MAC_ASYNC_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include <utils.h>
#include <hpl_irq.h>
/**
* \addtogroup hpl__mac__async__group MAC HPL APIs
*
*@{
*/
/**
* \brief MAC device descriptor Forward declaration
*/
struct _mac_async_device;
/**
* \brief MAC callback type
*
* \param[in] dev An MAC device descriptor
*/
typedef void (*_mac_async_cb_t)(struct _mac_async_device *const dev);
/**
* \brief MAC callbacks
*/
struct _mac_async_callbacks {
_mac_async_cb_t transmited; /*!< Frame received */
_mac_async_cb_t received; /*!< Frame transmited */
};
/**
* \brief MAC device descriptor
*/
struct _mac_async_device {
void * hw; /*!< Hardware module instance handler */
struct _mac_async_callbacks cb; /*!< Callback handler */
struct _irq_descriptor irq; /*!< IRQ handler */
};
/**
* \brief MAC callback types
*/
enum mac_async_cb_type {
MAC_ASYNC_RECEIVE_CB, /*!< One or more frame been received */
MAC_ASYNC_TRANSMIT_CB /*!< One or more frame been transmited */
};
struct mac_async_filter {
uint8_t mac[6]; /*!< Destination address */
uint8_t tid[2]; /*!< Type ID, 0x0600 IP package */
bool tid_enable; /*!< Enable TID matching */
};
/**
* \brief Initialize the MAC driver
*
* Initialize the MAC driver
*
* \param[in] dev A MAC device descriptor to deinit
* \param[in] hw Hardware module instance
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_init(struct _mac_async_device *const dev, void *const hw);
/**
* \brief Deinitialize the MAC driver
*
* Deinitialize the MAC driver
*
* \param[in] descr A MAC device descriptor to deinit
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_deinit(struct _mac_async_device *const dev);
/** \brief Enable the MAC
*
* Enable the MAC
*
* \param[in] dev Pointer to the HPL MAC device descriptor
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_enable(struct _mac_async_device *const dev);
/**
* \brief Disable the MAC
*
* Disable the MAC
*
* \param[in] dev Pointer to the HPL MAC device descriptor
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_disable(struct _mac_async_device *const dev);
/**
* \brief Write raw data to MAC
*
* Write raw data to MAC that will be transmitted.
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] buffer Pointer to the data buffer
* \param[in] length Length of the data buffer
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_write(struct _mac_async_device *const dev, uint8_t *buf, uint32_t len);
/**
* \brief Read received raw data from MAC
*
* Read received raw data from MAC
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] buffer Pointer to the data buffer. if pointer is null, then the
* frame will be discard.
* \param[in] length Max Length of the data buffer to be read. if len is zero,
* then the frame will be discard
*
* \return Number of bytes that have been received
*/
uint32_t _mac_async_read(struct _mac_async_device *const dev, uint8_t *buf, uint32_t len);
/**
* \brief Get next valid package length
*
* Get next valid package length from MAC. Application can use this function
* to fetch the length of the next package, malloc the a buffer whit this
* length, and then invoke mac_async_read to read out the package data.
*
* \param[in] dev Pointer to the HPL MAC device descriptor.
*
* \return Number of bytes that next package can be read.
*/
uint32_t _mac_async_read_len(struct _mac_async_device *const dev);
/**
* \brief Enable the MAC IRQ
*
* Enable the MAC IRQ
*
* \param[in] dev Pointer to the HPL MAC device descriptor
*/
void _mac_async_enable_irq(struct _mac_async_device *const dev);
/**
* \brief Disable the MAC IRQ
*
* Disable the MAC IRQ
*
* \param[in] dev Pointer to the HPL MAC device descriptor
*/
void _mac_async_disable_irq(struct _mac_async_device *const dev);
/**
* \brief Register the MAC callback
*
* Register the MAC callback
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] type Callback function type.
* \param[in] func A callback function, passing NULL will de-register
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_register_callback(struct _mac_async_device *const dev, const enum mac_async_cb_type type,
const FUNC_PTR func);
/**
* \brief Set MAC filter
*
* Set MAC filter, ethernet frames which match the filter will be received.
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] index Mac filter index, start from 0, max value depends on
* hardware specificaions.
* \param[in] filter Pointer to the filter descriptor.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_set_filter(struct _mac_async_device *const dev, uint8_t index, struct mac_async_filter *filter);
/**
* \brief Set MAC filter (expaneded)
*
* Set MAC filter, ethernet frames which match the filter will be received.
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] mac Mac address
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_set_filter_ex(struct _mac_async_device *const dev, uint8_t mac[6]);
/**
* \brief Write PHY register
*
* Write PHY register
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] addr PHY address.
* \param[in] reg Register address.
* \param[in] data Register value.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_write_phy_reg(struct _mac_async_device *const dev, uint16_t addr, uint16_t reg, uint16_t data);
/**
* \brief Read PHY register
*
* Read PHY register
*
* \param[in] dev Pointer to the HPL MAC device descriptor
* \param[in] addr PHY address.
* \param[in] reg Register address.
* \param[in] data Register value.
*
* \return Operation status.
* \retval ERR_NONE Success.
*/
int32_t _mac_async_read_phy_reg(struct _mac_async_device *const dev, uint16_t addr, uint16_t reg, uint16_t *val);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* HPL_MAC_ASYNC_H_INCLUDED */
bsp/microchip/same70/bsp/hal/include/hpl_time_measure.h
-94
View File
@@ -1,94 +0,0 @@
/**
* \file
*
* \brief Time measure related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIME_MEASURE_H_INCLUDED
#define _HPL_TIME_MEASURE_H_INCLUDED
/**
* \addtogroup HPL Time measure
*
* \section hpl_time_measure_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief System time type
*/
typedef uint32_t system_time_t;
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize system time module
*
* \param[in] hw The pointer to hardware instance to initialize
*/
void _system_time_init(void *const hw);
/**
* \brief Deinitialize system time module
*
* \param[in] hw The pointer to hardware instance to initialize
*/
void _system_time_deinit(void *const hw);
/**
* \brief Get system time
*
* \param[in] hw The pointer to hardware instance to initialize
*/
system_time_t _system_time_get(const void *const hw);
/**
* \brief Get maximum possible system time
*
* \param[in] hw The pointer to hardware instance to initialize
*/
system_time_t _system_time_get_max_time_value(const void *const hw);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIME_MEASURE_H_INCLUDED */
bsp/microchip/same70/bsp/hal/src/hal_adc_sync.c
+244
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@@ -0,0 +1,244 @@
/**
* \file
*
* \brief ADC functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \brief Indicates HAL being compiled. Must be defined before including.
*/
#define _COMPILING_HAL
#include "hal_adc_sync.h"
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Maximum amount of ADC interface instances
*/
#define MAX_ADC_AMOUNT ADC_INST_NUM
/**
* \brief Initialize ADC
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
{
ASSERT(descr && hw);
return _adc_sync_init(&descr->device, hw);
}
/**
* \brief Deinitialize ADC
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
{
ASSERT(descr);
_adc_sync_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Enable ADC
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_enable_channel(&descr->device, channel);
return ERR_NONE;
}
/**
* \brief Disable ADC
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_disable_channel(&descr->device, channel);
return ERR_NONE;
}
/*
* \brief Read data from ADC
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length)
{
uint8_t data_size;
uint16_t offset = 0;
ASSERT(descr && buffer && length);
data_size = _adc_sync_get_data_size(&descr->device);
ASSERT(!(length % data_size));
do {
uint16_t result;
_adc_sync_convert(&descr->device);
while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
;
result = _adc_sync_read_channel_data(&descr->device, channel);
buffer[offset] = result;
if (1 < data_size) {
buffer[offset + 1] = result >> 8;
}
offset += data_size;
} while (offset < length);
return offset;
}
/**
* \brief Set ADC reference source
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
{
ASSERT(descr);
_adc_sync_set_reference_source(&descr->device, reference);
return ERR_NONE;
}
/**
* \brief Set ADC resolution
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
{
ASSERT(descr);
_adc_sync_set_resolution(&descr->device, resolution);
return ERR_NONE;
}
/**
* \brief Set ADC input source of a channel
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
return ERR_NONE;
}
/**
* \brief Set ADC thresholds
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold)
{
ASSERT(descr);
_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
return ERR_NONE;
}
/**
* \brief Set ADC gain
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
{
ASSERT(descr);
_adc_sync_set_channel_gain(&descr->device, channel, gain);
return ERR_NONE;
}
/**
* \brief Set ADC conversion mode
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
{
ASSERT(descr);
_adc_sync_set_conversion_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Set ADC differential mode
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode)
{
ASSERT(descr);
_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
return ERR_NONE;
}
/**
* \brief Set ADC window mode
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
{
ASSERT(descr);
_adc_sync_set_window_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Retrieve threshold state
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
{
ASSERT(descr && state);
_adc_sync_get_threshold_state(&descr->device, state);
return ERR_NONE;
}
/**
* \brief Check if conversion is complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
return _adc_sync_is_channel_conversion_done(&descr->device, channel);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t adc_sync_get_version(void)
{
return DRIVER_VERSION;
}
//@}
bsp/microchip/same70/bsp/hal/src/hal_i2c_m_sync.c
+258
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@@ -0,0 +1,258 @@
/**
* \file
*
* \brief I/O I2C related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hal_i2c_m_sync.h>
#include <utils.h>
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Sync version of I2C I/O read
*/
static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n)
{
struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = n;
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = buf;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret) {
return ret;
}
return n;
}
/**
* \brief Sync version of I2C I/O write
*/
static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
{
struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = n;
msg.flags = I2C_M_STOP;
msg.buffer = (uint8_t *)buf;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret) {
return ret;
}
return n;
}
/**
* \brief Sync version of i2c initialize
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
{
int32_t init_status;
ASSERT(i2c);
init_status = _i2c_m_sync_init(&i2c->device, hw);
if (init_status) {
return init_status;
}
/* Init I/O */
i2c->io.read = i2c_m_sync_read;
i2c->io.write = i2c_m_sync_write;
return ERR_NONE;
}
/**
* \brief deinitialize
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c)
{
int32_t status;
ASSERT(i2c);
status = _i2c_m_sync_deinit(&i2c->device);
if (status) {
return status;
}
i2c->io.read = NULL;
i2c->io.write = NULL;
return ERR_NONE;
}
/**
* \brief Sync version of i2c enable
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
{
return _i2c_m_sync_enable(&i2c->device);
}
/**
* \brief Sync version of i2c disable
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c)
{
return _i2c_m_sync_disable(&i2c->device);
}
/**
* \brief Sync version of i2c set slave address
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
{
return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
}
/**
* \brief Sync version of i2c set baudrate
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate)
{
return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate);
}
/**
* \brief Sync version of i2c write command
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
{
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = 1;
msg.flags = 0;
msg.buffer = &reg;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
msg.flags = I2C_M_STOP;
msg.buffer = buffer;
msg.len = length;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
return ERR_NONE;
}
/**
* \brief Sync version of i2c read command
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
{
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = 1;
msg.flags = 0;
msg.buffer = &reg;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = buffer;
msg.len = length;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
return ERR_NONE;
}
/**
* \brief Sync version of i2c transfer command
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg)
{
return _i2c_m_sync_transfer(&i2c->device, msg);
}
/**
* \brief Sync version of i2c send stop condition command
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c)
{
return _i2c_m_sync_send_stop(&i2c->device);
}
/**
* \brief Retrieve I/O descriptor
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
{
*io = &i2c->io;
return ERR_NONE;
}
/**
* \brief Retrieve the current driver version
*/
uint32_t i2c_m_sync_get_version(void)
{
return DRIVER_VERSION;
}

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