mirror of
https://github.com/RT-Thread/rt-thread.git
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Microchip SAM MCU新增ethernet支持和驱动更新 (#5821)
* Microchip SAM MCU BSP update and add ethernet driver 1. Update Microchip SAM MCU BSP, add I2C, GMAC, ADC driver support. 2. Add ethernet driver support of SAM MCU for RT-Thread. * Add GMAC and I2C driver support 1. Update MCU BSP to support I2C/ADC/GMAC peripherals. 2. Add I2C and ethernet driver and LWIP support. 3. Update serial driver. * Add I2C driver and move some files to the common folder 1. Add I2C driver. 2. Move the same drivers and demo code to same folder to reduce duplicated code.
This commit is contained in:
Kevin Liu
@@ -183,6 +183,9 @@ About RT-Thread env tools, click [Here](https://github.com/RT-Thread/rt-thread/b
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* Debugging message output.
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# 4. Reconfigure MCU BSP
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@@ -0,0 +1,23 @@
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import rtconfig
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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#remove other no use files
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if GetDepend('SAM_CAN_EXAMPLE') == False:
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SrcRemove(src, ['can_demo.c'])
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if GetDepend('SAM_I2C_EXAMPLE') == False:
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SrcRemove(src, ['i2c_demo.c'])
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if GetDepend('SAM_ADC_EXAMPLE') == False:
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SrcRemove(src, ['adc_demo.c'])
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if GetDepend('SAM_LWIP_EXAMPLE') == False:
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SrcRemove(src, ['lwip_demo.c'])
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,74 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Email Notes
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* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#include <rtthread.h>
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#include <atmel_start.h>
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#include "adc_demo.h"
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#ifdef SAM_ADC_EXAMPLE
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#if defined(SOC_SAMC21)
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#define ADC_RESOLUTION_12BIT ADC_CTRLC_RESSEL_12BIT_Val
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#define ADC_RESOLUTION_16BIT ADC_CTRLC_RESSEL_16BIT_Val
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#elif defined(SOC_SAME54)
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#define ADC_RESOLUTION_12BIT ADC_CTRLB_RESSEL_12BIT_Val
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#define ADC_RESOLUTION_16BIT ADC_CTRLB_RESSEL_16BIT_Val
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#elif defined(SOC_SAME70)
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#define ADC_RESOLUTION_12BIT AFEC_EMR_RES_NO_AVERAGE_Val
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#define ADC_RESOLUTION_16BIT AFEC_EMR_RES_OSR256_Val
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#else
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#error "ADC undefined SOC Platform"
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#endif
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/**
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* @brief Call this function will run ADC test code.
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*
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* @note Test code will try to read ADC conversion result.
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*
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* @param None.
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*
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* @return RT_OK or -RT_ERROR.
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*/
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rt_err_t adc_demo_run(void)
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{
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rt_uint8_t buffer[2];
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/* enable ADC driver module */
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adc_sync_enable_channel(&ADC_0, 0);
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adc_sync_read_channel(&ADC_0, 0, buffer, 2);
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#ifndef RT_USING_FINSH
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rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
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#endif
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/* ADC 16-bit resolution */
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adc_sync_disable_channel(&ADC_0, 0);
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adc_sync_set_resolution(&ADC_0, ADC_RESOLUTION_16BIT);
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adc_sync_enable_channel(&ADC_0, 0);
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#ifndef RT_USING_FINSH
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rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
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#endif
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/* ADC 12-bit resolution */
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adc_sync_disable_channel(&ADC_0, 0);
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adc_sync_set_resolution(&ADC_0, ADC_RESOLUTION_12BIT);
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adc_sync_enable_channel(&ADC_0, 0);
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#ifndef RT_USING_FINSH
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rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
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#endif
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return RT_EOK;
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}
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#endif
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/*@}*/
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@@ -5,11 +5,11 @@
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*
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* Change Logs:
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* Date Author Email Notes
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* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#ifndef __BOARD_SERIAL_H_
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#define __BOARD_SERIAL_H_
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#ifndef __APPLICATION_ADC_H_
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#define __APPLICATION_ADC_H_
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#include <rtthread.h>
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@@ -17,6 +17,6 @@
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* @brief External function definitions
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*
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*/
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int rt_hw_uart_init(void);
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rt_err_t adc_demo_run(void);
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#endif // __BOARD_SERIAL_H_
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#endif // __APPLICATION_I2C_H_
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+10
-7
@@ -5,16 +5,11 @@
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*
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* Change Logs:
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* Date Author Email Notes
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* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#include <rtthread.h>
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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#include <shell.h>
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#endif
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#include "atmel_start.h"
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#include "driver_init.h"
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#include "utils.h"
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@@ -23,6 +18,14 @@
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#ifdef SAM_CAN_EXAMPLE
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#if defined(SOC_SAMC21) || defined(SOC_SAME54)
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#define CAN_HARDWARE (void *)CAN1
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#elif defined(SOC_SAME70)
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#define CAN_HARDWARE (void *)MCAN1
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#else
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#error "CAN undefined SOC Platform"
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#endif
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static volatile enum can_async_interrupt_type can_errors;
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static rt_sem_t can_txdone;
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static rt_sem_t can_rxdone;
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@@ -251,7 +254,7 @@ static void can_thread_entry(void* parameter)
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/* CAN task got CAN error message, handler CAN Error Status */
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if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
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{
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can_async_init(&CAN_0, MCAN1);
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can_async_init(&CAN_0, CAN_HARDWARE);
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}
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}
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}
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@@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Email Notes
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* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#include <rtthread.h>
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#include <atmel_start.h>
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#include "i2c_demo.h"
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#ifdef SAM_I2C_EXAMPLE
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#define I2C_AT24MAC_PGMAXSZ (16+1)
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#define CONF_AT24MAC_ADDRESS 0x57
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/**
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* @brief Call this function will run I2C test code.
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*
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* @note Test code will try to read/write external EEPROM.
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*
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* @param None.
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*
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* @return RT_OK or -RT_ERROR.
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*/
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rt_err_t i2c_demo_run(void)
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{
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rt_uint8_t addr = 0x20;
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rt_int32_t len;
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rt_uint8_t i2ctx[I2C_AT24MAC_PGMAXSZ];
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rt_uint8_t i2crx[I2C_AT24MAC_PGMAXSZ];
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for (len = 1; len < I2C_AT24MAC_PGMAXSZ; len++)
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{
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i2ctx[len] = (rt_uint8_t)(len + 0x20);
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}
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/* enable I2C master and set slave address before use I2C driver module */
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i2c_m_sync_enable(&I2C_0);
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i2c_m_sync_set_slaveaddr(&I2C_0, CONF_AT24MAC_ADDRESS, I2C_M_SEVEN);
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/* write 16bytes data to address 0x20 - I2C slave address + random address + write data[0]...[n] */
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i2ctx[0] = addr; /* Refer to AT24MAC data sheet, first byte is page address. */
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io_write(&(I2C_0.io), i2ctx, I2C_AT24MAC_PGMAXSZ);
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/* Refer to data sheet, for random read, should send read address first. */
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io_write(&(I2C_0.io), &addr, 1);
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/* Then start I2C read after send I2C slave address first */
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io_read(&(I2C_0.io), &i2crx[1], 16);
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#ifndef RT_USING_FINSH
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rt_kprintf("i2crx[0]=0x%02X i2crx[15]=0x%02X\r\n", i2crx[0], i2crx[15]);
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#endif
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return RT_EOK;
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}
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#endif
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/*@}*/
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c)
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Email Notes
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* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#ifndef __APPLICATION_I2C_H_
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#define __APPLICATION_I2C_H_
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#include <rtthread.h>
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/**
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* @brief External function definitions
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*
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*/
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rt_err_t i2c_demo_run(void);
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#endif // __APPLICATION_I2C_H_
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,22 @@
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/*
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* Copyright (c)
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Email Notes
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* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#ifndef __APPLICATION_LWIP_H_
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#define __APPLICATION_LWIP_H_
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#include <rtthread.h>
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/**
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* @brief External function definitions
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*
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*/
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rt_err_t lwip_demo_run(void);
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#endif // __APPLICATION_LWIP_H_
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@@ -0,0 +1,21 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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#remove other no use files
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if GetDepend('SAM_I2C_EXAMPLE') == False:
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SrcRemove(src, ['sam_i2c.c'])
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if GetDepend('SAM_LWIP_EXAMPLE') == False:
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SrcRemove(src, ['sam_gmac.c'])
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# You can select chips from the list above
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CPPDEFINES = []
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
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Return('group')
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
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/*
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* Copyright (c)
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*
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* SPDX-License-Identifier: Apache-2.0
|
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*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
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* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
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*/
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#ifndef __BOARD_SAM_GMAC_H_
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#define __BOARD_SAM_GMAC_H_
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#include <rtthread.h>
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/**
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* @brief GMAC duplex type
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*/
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typedef enum
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{
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GMAC_HALF_DUPLEX = 0x00, /*!< half duplex */
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GMAC_FULL_DUPLEX = 0x01 /*!< full duplex */
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} gmac_duplex_type;
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/**
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* @brief GMAC speed type
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*/
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typedef enum
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{
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GMAC_SPEED_10MBPS = 0x00, /*!< 10 mbps */
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GMAC_SPEED_100MBPS = 0x01 /*!< 100 mbps */
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} gmac_speed_type;
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#define CONF_AT24MAC_ADDRESS 0x57
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#endif // __BOARD_SAM_GMAC_H_
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@@ -0,0 +1,122 @@
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/*
|
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* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <atmel_start.h>
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#ifdef SAM_I2C_EXAMPLE
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struct sam_i2c_bus
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{
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struct rt_i2c_bus_device parent;
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struct i2c_m_sync_desc *i2c_desc;
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char *device_name;
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};
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#define I2CBUS_NAME "i2c0"
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static struct sam_i2c_bus sam_i2c0 =
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{
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.i2c_desc = &I2C_0,
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.device_name = I2CBUS_NAME,
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};
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static rt_size_t sam_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_size_t sam_i2c_slave_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_err_t sam_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t, rt_uint32_t);
|
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static const struct rt_i2c_bus_device_ops sam_i2c_ops =
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{
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.master_xfer = sam_i2c_master_xfer,
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.slave_xfer = sam_i2c_slave_xfer,
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.i2c_bus_control = sam_i2c_bus_control,
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};
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static inline void sam_i2c_update_control(struct rt_i2c_msg *src,
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struct _i2c_m_msg *dest)
|
||||
{
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||||
dest->len = (int32_t)src->len;
|
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dest->addr = src->addr;
|
||||
dest->buffer = src->buf;
|
||||
|
||||
/* Get I2C message R/W attribute first */
|
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dest->flags = dest->flags & 0x0001;
|
||||
|
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if (dest->flags & RT_I2C_ADDR_10BIT)
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dest->flags |= I2C_M_TEN;
|
||||
else
|
||||
dest->flags |= I2C_M_SEVEN;
|
||||
}
|
||||
|
||||
static rt_size_t sam_i2c_master_xfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num)
|
||||
{
|
||||
struct sam_i2c_bus *sam_i2c = (struct sam_i2c_bus *)bus;
|
||||
struct _i2c_m_msg i2c_msg;
|
||||
rt_size_t i;
|
||||
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
sam_i2c_update_control(&msgs[i], &i2c_msg);
|
||||
if (i2c_m_sync_transfer(sam_i2c->i2c_desc, &i2c_msg) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static rt_size_t sam_i2c_slave_xfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_err_t sam_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
||||
rt_uint32_t cmd,
|
||||
rt_uint32_t arg)
|
||||
{
|
||||
return RT_ERROR;
|
||||
struct sam_i2c_bus *sam_i2c = (struct sam_i2c_bus *)bus;
|
||||
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_I2C_DEV_CTRL_CLK:
|
||||
i2c_m_sync_set_baudrate(sam_i2c->i2c_desc, 0, arg);
|
||||
break;
|
||||
default:
|
||||
return -RT_EIO;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
rt_i2c_bus_device_register(&sam_i2c0.parent, sam_i2c0.device_name);
|
||||
return 0;
|
||||
}
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
INIT_BOARD_EXPORT(rt_hw_i2c_init);
|
||||
#endif
|
||||
#endif
|
||||
/*@}*/
|
||||
@@ -5,11 +5,11 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
* 2022-04-11 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_SERIAL_H_
|
||||
#define __BOARD_SERIAL_H_
|
||||
#ifndef __BOARD_SAM_I2C_H_
|
||||
#define __BOARD_SAM_I2C_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
@@ -17,6 +17,6 @@
|
||||
* @brief External function definitions
|
||||
*
|
||||
*/
|
||||
int rt_hw_uart_init(void);
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif // __BOARD_SERIAL_H_
|
||||
#endif // __BOARD_SAM_I2C_H_
|
||||
@@ -16,6 +16,34 @@
|
||||
/* SAM MCU serial device */
|
||||
static struct rt_serial_device sam_serial;
|
||||
|
||||
static void serial_rxcallback(const struct usart_async_descriptor *const io_descr)
|
||||
{
|
||||
(void)io_descr;
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
/* Notify Serial driver to process RX data */
|
||||
rt_hw_serial_isr(&sam_serial, RT_SERIAL_EVENT_RX_IND);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static void serial_txcallback(const struct usart_async_descriptor *const io_descr)
|
||||
{
|
||||
(void)io_descr;
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
/* Notify Serial driver to process TX done event */
|
||||
rt_hw_serial_isr(&sam_serial, RT_SERIAL_EVENT_TX_DONE);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure serial port
|
||||
*
|
||||
@@ -25,61 +53,61 @@ static struct rt_serial_device sam_serial;
|
||||
*/
|
||||
static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
struct usart_async_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
desc = (struct usart_async_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
usart_sync_disable(desc);
|
||||
usart_async_disable(desc);
|
||||
|
||||
/* Set baudrate */
|
||||
usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
|
||||
usart_async_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
|
||||
|
||||
/* Set stop bit */
|
||||
if (cfg->stop_bits == STOP_BITS_1)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
|
||||
usart_async_set_stopbits(desc, USART_STOP_BITS_ONE);
|
||||
else if (cfg->stop_bits == STOP_BITS_2)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
|
||||
usart_async_set_stopbits(desc, USART_STOP_BITS_TWO);
|
||||
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
|
||||
usart_async_set_data_order(desc, USART_DATA_ORDER_LSB);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
|
||||
usart_async_set_data_order(desc, USART_DATA_ORDER_MSB);
|
||||
|
||||
/* Set character size */
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_5:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
|
||||
usart_async_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
|
||||
break;
|
||||
case DATA_BITS_6:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
|
||||
usart_async_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
|
||||
usart_async_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
|
||||
usart_async_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
|
||||
break;
|
||||
case DATA_BITS_9:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
|
||||
usart_async_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
usart_sync_set_parity(desc, USART_PARITY_NONE);
|
||||
usart_async_set_parity(desc, USART_PARITY_NONE);
|
||||
else if (cfg->parity == PARITY_ODD)
|
||||
usart_sync_set_parity(desc, USART_PARITY_ODD);
|
||||
usart_async_set_parity(desc, USART_PARITY_ODD);
|
||||
else if (cfg->parity == PARITY_EVEN)
|
||||
usart_sync_set_parity(desc, USART_PARITY_EVEN);
|
||||
usart_async_set_parity(desc, USART_PARITY_EVEN);
|
||||
|
||||
usart_sync_enable(desc);
|
||||
usart_async_enable(desc);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
@@ -93,10 +121,10 @@ static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_
|
||||
*/
|
||||
static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
struct usart_async_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
desc = (struct usart_async_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
@@ -104,11 +132,11 @@ static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *a
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
usart_sync_disable(desc);
|
||||
usart_async_disable(desc);
|
||||
break;
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
usart_sync_enable(desc);
|
||||
usart_async_enable(desc);
|
||||
break;
|
||||
/* UART config */
|
||||
case RT_DEVICE_CTRL_CONFIG :
|
||||
@@ -127,14 +155,15 @@ static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *a
|
||||
*/
|
||||
static int serial_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
struct usart_async_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
desc = (struct usart_async_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
io_write(&desc->io, (const uint8_t *)&c, 1);
|
||||
while (usart_async_is_tx_empty(desc) == 0);
|
||||
_usart_async_write_byte(&TARGET_IO.device, (uint8_t)c);
|
||||
|
||||
return 1;
|
||||
}
|
||||
@@ -150,17 +179,17 @@ static int serial_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
char c;
|
||||
int ch;
|
||||
struct usart_sync_descriptor* desc;
|
||||
struct usart_async_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
desc = (struct usart_async_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
ch = -1;
|
||||
if (usart_sync_is_rx_not_empty(desc))
|
||||
if (usart_async_is_rx_not_empty(desc))
|
||||
{
|
||||
io_read(&desc->io, (uint8_t *)&c, 1);;
|
||||
io_read(&desc->io, (uint8_t *)&c, 1);
|
||||
ch = c & 0xff;
|
||||
}
|
||||
|
||||
@@ -190,8 +219,12 @@ int rt_hw_uart_init(void)
|
||||
sam_serial.config = config;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
rt_hw_serial_register(&sam_serial, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
|
||||
rt_hw_serial_register(&sam_serial, RT_CONSOLE_DEVICE_NAME,
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
|
||||
RT_DEVICE_FLAG_INT_TX, (void *)&TARGET_IO);
|
||||
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, serial_txcallback);
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, serial_rxcallback);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 299 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 201 KiB After Width: | Height: | Size: 86 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 26 KiB After Width: | Height: | Size: 44 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 21 KiB |
@@ -93,8 +93,32 @@ CONFIG_RT_USING_USER_MAIN=y
|
||||
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
# CONFIG_RT_USING_LEGACY is not set
|
||||
# CONFIG_RT_USING_MSH is not set
|
||||
# CONFIG_RT_USING_DFS is not set
|
||||
CONFIG_RT_USING_MSH=y
|
||||
CONFIG_RT_USING_FINSH=y
|
||||
CONFIG_FINSH_USING_MSH=y
|
||||
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||
CONFIG_FINSH_USING_HISTORY=y
|
||||
CONFIG_FINSH_HISTORY_LINES=5
|
||||
CONFIG_FINSH_USING_SYMTAB=y
|
||||
CONFIG_FINSH_CMD_SIZE=80
|
||||
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
|
||||
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||
# CONFIG_FINSH_USING_AUTH is not set
|
||||
CONFIG_FINSH_ARG_MAX=10
|
||||
CONFIG_RT_USING_DFS=y
|
||||
CONFIG_DFS_USING_POSIX=y
|
||||
CONFIG_DFS_USING_WORKDIR=y
|
||||
CONFIG_DFS_FILESYSTEMS_MAX=4
|
||||
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
|
||||
CONFIG_DFS_FD_MAX=16
|
||||
# CONFIG_RT_USING_DFS_MNTTABLE is not set
|
||||
# CONFIG_RT_USING_DFS_ELMFAT is not set
|
||||
CONFIG_RT_USING_DFS_DEVFS=y
|
||||
# CONFIG_RT_USING_DFS_ROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_RAMFS is not set
|
||||
# CONFIG_RT_USING_FAL is not set
|
||||
# CONFIG_RT_USING_LWP is not set
|
||||
|
||||
@@ -102,7 +126,9 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
# Device Drivers
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE_IPC=y
|
||||
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
|
||||
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
|
||||
CONFIG_RT_USING_SERIAL=y
|
||||
CONFIG_RT_USING_SERIAL_V1=y
|
||||
# CONFIG_RT_USING_SERIAL_V2 is not set
|
||||
@@ -111,7 +137,9 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
|
||||
# CONFIG_RT_USING_CAN is not set
|
||||
# CONFIG_RT_USING_HWTIMER is not set
|
||||
# CONFIG_RT_USING_CPUTIME is not set
|
||||
# CONFIG_RT_USING_I2C is not set
|
||||
CONFIG_RT_USING_I2C=y
|
||||
# CONFIG_RT_I2C_DEBUG is not set
|
||||
# CONFIG_RT_USING_I2C_BITOPS is not set
|
||||
# CONFIG_RT_USING_PHY is not set
|
||||
# CONFIG_RT_USING_PIN is not set
|
||||
# CONFIG_RT_USING_ADC is not set
|
||||
@@ -639,10 +667,12 @@ CONFIG_SOC_SAMC21J18=y
|
||||
#
|
||||
CONFIG_SAMC21_CAN0=y
|
||||
CONFIG_SAMC21_ADC0=y
|
||||
CONFIG_SAMC21_I2C0=y
|
||||
|
||||
#
|
||||
# Application Demo Config
|
||||
#
|
||||
CONFIG_SAM_CAN_EXAMPLE=y
|
||||
CONFIG_SAM_ADC_EXAMPLE=y
|
||||
CONFIG_SAM_I2C_EXAMPLE=y
|
||||
CONFIG_SOC_SAMC21=y
|
||||
|
||||
@@ -34,8 +34,27 @@ if rtconfig.PLATFORM == 'iar':
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/common'):
|
||||
common_path_prefix = SDK_ROOT + '/common'
|
||||
else:
|
||||
common_path_prefix = os.path.dirname(SDK_ROOT) + '/common'
|
||||
|
||||
SDK_LIB = common_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
sam_board = 'board'
|
||||
rtconfig.BSP_LIBRARY_TYPE = sam_board
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(common_path_prefix, sam_board, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(common_path_prefix, 'applications', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -5,7 +5,7 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
@@ -22,6 +22,14 @@
|
||||
#include "can_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef SAM_I2C_EXAMPLE
|
||||
#include "i2c_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef SAM_ADC_EXAMPLE
|
||||
#include "adc_demo.h"
|
||||
#endif
|
||||
|
||||
static rt_uint8_t led_stack[ 512 ];
|
||||
static struct rt_thread led_thread;
|
||||
|
||||
@@ -63,6 +71,14 @@ int main(void)
|
||||
can_demo_run();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_I2C_EXAMPLE
|
||||
i2c_demo_run();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_ADC_EXAMPLE
|
||||
adc_demo_run();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -32,6 +32,11 @@ menu "Onboard Peripheral Drivers"
|
||||
config SAMC21_ADC0
|
||||
bool "Enable ADC0"
|
||||
default false
|
||||
|
||||
config SAMC21_I2C0
|
||||
bool "Enable I2C0"
|
||||
default false
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Application Demo Config"
|
||||
@@ -49,4 +54,10 @@ menu "Application Demo Config"
|
||||
help
|
||||
Add ADC example task to project
|
||||
|
||||
config SAM_I2C_EXAMPLE
|
||||
bool "Enable SAM I2C Example"
|
||||
depends on SAMC21_I2C0
|
||||
default true
|
||||
help
|
||||
Add I2C example task to project
|
||||
endmenu
|
||||
|
||||
@@ -25,13 +25,14 @@ static struct io_descriptor* g_stdio;
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
io_write(g_stdio, (uint8_t *)str, strlen(str));
|
||||
while (TARGET_IO.stat != 0);
|
||||
}
|
||||
RTM_EXPORT(rt_hw_console_output);
|
||||
|
||||
static inline void hw_board_init_usart(void)
|
||||
{
|
||||
usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
|
||||
usart_sync_enable(&TARGET_IO);
|
||||
usart_async_get_io_descriptor(&TARGET_IO, &g_stdio);
|
||||
usart_async_enable(&TARGET_IO);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -1,199 +0,0 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <atmel_start.h>
|
||||
|
||||
/* SAM MCU serial device */
|
||||
static struct rt_serial_device sam_serial;
|
||||
|
||||
/**
|
||||
* @brief Configure serial port
|
||||
*
|
||||
* This function will configure UART baudrate, parity and so on.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
usart_sync_disable(desc);
|
||||
|
||||
/* Set baudrate */
|
||||
usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
|
||||
|
||||
/* Set stop bit */
|
||||
if (cfg->stop_bits == STOP_BITS_1)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
|
||||
else if (cfg->stop_bits == STOP_BITS_2)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
|
||||
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
|
||||
|
||||
/* Set character size */
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_5:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
|
||||
break;
|
||||
case DATA_BITS_6:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
|
||||
break;
|
||||
case DATA_BITS_9:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
usart_sync_set_parity(desc, USART_PARITY_NONE);
|
||||
else if (cfg->parity == PARITY_ODD)
|
||||
usart_sync_set_parity(desc, USART_PARITY_ODD);
|
||||
else if (cfg->parity == PARITY_EVEN)
|
||||
usart_sync_set_parity(desc, USART_PARITY_EVEN);
|
||||
|
||||
usart_sync_enable(desc);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control serial port
|
||||
*
|
||||
* This function provide UART enable/disable control.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
usart_sync_disable(desc);
|
||||
break;
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
usart_sync_enable(desc);
|
||||
break;
|
||||
/* UART config */
|
||||
case RT_DEVICE_CTRL_CONFIG :
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial sends a char
|
||||
*
|
||||
* This function will send a char to the UART
|
||||
*
|
||||
* @return 1.
|
||||
*/
|
||||
static int serial_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
io_write(&desc->io, (const uint8_t *)&c, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial gets a char
|
||||
*
|
||||
* This function will get a char from the UART
|
||||
*
|
||||
* @return received char character or -1 if no char received.
|
||||
*/
|
||||
static int serial_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
char c;
|
||||
int ch;
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
ch = -1;
|
||||
if (usart_sync_is_rx_not_empty(desc))
|
||||
{
|
||||
io_read(&desc->io, (uint8_t *)&c, 1);;
|
||||
ch = c & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops sam_serial_ops =
|
||||
{
|
||||
serial_configure,
|
||||
serial_control,
|
||||
serial_putc,
|
||||
serial_getc,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART
|
||||
*
|
||||
* This function initialize the UART
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
sam_serial.ops = &sam_serial_ops;
|
||||
sam_serial.config = config;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
rt_hw_serial_register(&sam_serial, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -42,17 +42,21 @@
|
||||
<description>Atmel Start Framework</description>
|
||||
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||
<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/flash.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_flash.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
|
||||
@@ -78,6 +82,7 @@
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_flash.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||
@@ -90,9 +95,11 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
|
||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/divas/hpl_divas.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_c21.h"/>
|
||||
@@ -138,7 +145,10 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="config/hpl_divas_config.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
@@ -148,8 +158,11 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
|
||||
@@ -168,6 +181,7 @@
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
@@ -183,6 +197,7 @@
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/divas"/>
|
||||
|
||||
@@ -11,8 +11,10 @@ CPPDEFINES = []
|
||||
CPPDEFINES += [rtconfig.DEVICE_TYPE]
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Glob('hal/src/*.c')
|
||||
src += Glob('hal/utils/src/*.c')
|
||||
src += Glob('hpl/adc/*.c')
|
||||
src += Glob('hpl/can/*.c')
|
||||
src += Glob('hpl/core/*.c')
|
||||
src += Glob('hpl/divas/*.c')
|
||||
@@ -45,12 +47,15 @@ path = [
|
||||
cwd + '/config',
|
||||
cwd + '/hal/include',
|
||||
cwd + '/hal/utils/include',
|
||||
cwd + '/hpl/adc',
|
||||
cwd + '/hpl/can',
|
||||
cwd + '/hpl/core',
|
||||
cwd + '/hpl/gclk',
|
||||
cwd + '/hpl/pm',
|
||||
cwd + '/hpl/port',
|
||||
cwd + '/hri',
|
||||
cwd + '/../board',
|
||||
cwd + '/../../common/applications',
|
||||
cwd + '/samc21/include']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -22,6 +22,64 @@ application:
|
||||
configuration: null
|
||||
middlewares: {}
|
||||
drivers:
|
||||
ADC_0:
|
||||
user_label: ADC_0
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
|
||||
functionality: ADC
|
||||
api: HAL:Driver:ADC_Sync
|
||||
configuration:
|
||||
adc_advanced_settings: true
|
||||
adc_arch_adjres: 0
|
||||
adc_arch_corren: false
|
||||
adc_arch_dbgrun: false
|
||||
adc_arch_dualsel: BOTH
|
||||
adc_arch_event_settings: false
|
||||
adc_arch_flushei: false
|
||||
adc_arch_flushinv: false
|
||||
adc_arch_gaincorr: 0
|
||||
adc_arch_leftadj: false
|
||||
adc_arch_offcomp: false
|
||||
adc_arch_offsetcorr: 0
|
||||
adc_arch_ondemand: false
|
||||
adc_arch_r2r: false
|
||||
adc_arch_refcomp: false
|
||||
adc_arch_resrdyeo: false
|
||||
adc_arch_runstdby: false
|
||||
adc_arch_samplen: 0
|
||||
adc_arch_samplenum: 1 sample
|
||||
adc_arch_seqen: 0
|
||||
adc_arch_slaveen: false
|
||||
adc_arch_startei: false
|
||||
adc_arch_startinv: false
|
||||
adc_arch_winlt: 0
|
||||
adc_arch_winmode: No window mode
|
||||
adc_arch_winmoneo: false
|
||||
adc_arch_winut: 0
|
||||
adc_differential_mode: false
|
||||
adc_freerunning_mode: false
|
||||
adc_pinmux_negative: I/O ground
|
||||
adc_pinmux_positive: ADC AIN0 pin
|
||||
adc_prescaler: Peripheral clock divided by 2
|
||||
adc_reference: Internal bandgap reference
|
||||
adc_resolution: 16-bit (averaging must be enabled)
|
||||
optional_signals:
|
||||
- identifier: ADC_0:AIN/10
|
||||
pad: PA10
|
||||
mode: Enabled
|
||||
configuration: null
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::ADC0.AIN.10
|
||||
name: ADC0/AIN/10
|
||||
label: AIN/10
|
||||
variant: null
|
||||
clocks:
|
||||
domain_group:
|
||||
nodes:
|
||||
- name: ADC
|
||||
input: Generic clock generator 0
|
||||
external: false
|
||||
external_frequency: 0
|
||||
configuration:
|
||||
adc_gclk_selection: Generic clock generator 0
|
||||
DMAC:
|
||||
user_label: DMAC
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
|
||||
@@ -589,13 +647,53 @@ drivers:
|
||||
variant: null
|
||||
clocks:
|
||||
domain_group: null
|
||||
I2C_0:
|
||||
user_label: I2C_0
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
|
||||
functionality: I2C
|
||||
api: HAL:Driver:I2C_Master_Sync
|
||||
configuration:
|
||||
i2c_master_advanced: true
|
||||
i2c_master_arch_dbgstop: Keep running
|
||||
i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
|
||||
i2c_master_arch_lowtout: true
|
||||
i2c_master_arch_mexttoen: true
|
||||
i2c_master_arch_runstdby: false
|
||||
i2c_master_arch_sdahold: 300-600ns hold time
|
||||
i2c_master_arch_sexttoen: false
|
||||
i2c_master_arch_trise: 215
|
||||
i2c_master_baud_rate: 100000
|
||||
optional_signals: []
|
||||
variant:
|
||||
specification: SDA=0, SCL=1
|
||||
required_signals:
|
||||
- name: SERCOM0/PAD/0
|
||||
pad: PA08
|
||||
label: SDA
|
||||
- name: SERCOM0/PAD/1
|
||||
pad: PA09
|
||||
label: SCL
|
||||
clocks:
|
||||
domain_group:
|
||||
nodes:
|
||||
- name: Core
|
||||
input: Generic clock generator 0
|
||||
external: false
|
||||
external_frequency: 0
|
||||
- name: Slow
|
||||
input: Generic clock generator 1
|
||||
external: false
|
||||
external_frequency: 0
|
||||
configuration:
|
||||
core_gclk_selection: Generic clock generator 0
|
||||
slow_gclk_selection: Generic clock generator 1
|
||||
TARGET_IO:
|
||||
user_label: TARGET_IO
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Sync
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Async
|
||||
functionality: USART
|
||||
api: HAL:Driver:USART_Sync
|
||||
api: HAL:Driver:USART_Async
|
||||
configuration:
|
||||
usart_advanced: false
|
||||
usart_advanced: true
|
||||
usart_arch_clock_mode: USART with internal clock
|
||||
usart_arch_cloden: false
|
||||
usart_arch_dbgstop: Keep running
|
||||
@@ -703,6 +801,24 @@ drivers:
|
||||
configuration:
|
||||
can_gclk_selection: Generic clock generator 0
|
||||
pads:
|
||||
PA08:
|
||||
name: PA08
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA08
|
||||
mode: I2C
|
||||
user_label: PA08
|
||||
configuration: null
|
||||
PA09:
|
||||
name: PA09
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA09
|
||||
mode: I2C
|
||||
user_label: PA09
|
||||
configuration: null
|
||||
PA10:
|
||||
name: PA10
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA10
|
||||
mode: Analog
|
||||
user_label: PA10
|
||||
configuration: null
|
||||
PB10:
|
||||
name: PB10
|
||||
definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10
|
||||
|
||||
@@ -22,6 +22,9 @@
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
|
||||
#define PA08 GPIO(GPIO_PORTA, 8)
|
||||
#define PA09 GPIO(GPIO_PORTA, 9)
|
||||
#define PA10 GPIO(GPIO_PORTA, 10)
|
||||
#define LED0 GPIO(GPIO_PORTA, 15)
|
||||
#define PA24 GPIO(GPIO_PORTA, 24)
|
||||
#define PA25 GPIO(GPIO_PORTA, 25)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -6,6 +6,141 @@
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
|
||||
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_0_I2CM_ENABLE
|
||||
#define CONF_SERCOM_0_I2CM_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic
|
||||
|
||||
// <o> I2C Bus clock speed (Hz) <1-400000>
|
||||
// <i> I2C Bus clock (SCL) speed measured in Hz
|
||||
// <id> i2c_master_baud_rate
|
||||
#ifndef CONF_SERCOM_0_I2CM_BAUD
|
||||
#define CONF_SERCOM_0_I2CM_BAUD 100000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced
|
||||
// <id> i2c_master_advanced
|
||||
#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <o> TRise (ns) <0-300>
|
||||
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
|
||||
// <i> Standard Fast Mode: typical 215ns, max 300ns
|
||||
// <i> Fast Mode +: typical 60ns, max 100ns
|
||||
// <i> High Speed Mode: typical 20ns, max 40ns
|
||||
// <id> i2c_master_arch_trise
|
||||
|
||||
#ifndef CONF_SERCOM_0_I2CM_TRISE
|
||||
#define CONF_SERCOM_0_I2CM_TRISE 215
|
||||
#endif
|
||||
|
||||
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
|
||||
// <i> This enables the master SCL low extend time-out
|
||||
// <id> i2c_master_arch_mexttoen
|
||||
#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
|
||||
#define CONF_SERCOM_0_I2CM_MEXTTOEN 1
|
||||
#endif
|
||||
|
||||
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
|
||||
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
|
||||
// <id> i2c_master_arch_sexttoen
|
||||
#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
|
||||
#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
|
||||
#endif
|
||||
|
||||
// <q> SCL Low Time-Out (LOWTOUT)
|
||||
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
|
||||
// <id> i2c_master_arch_lowtout
|
||||
#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
|
||||
#define CONF_SERCOM_0_I2CM_LOWTOUT 1
|
||||
#endif
|
||||
|
||||
// <o> Inactive Time-Out (INACTOUT)
|
||||
// <0x0=>Disabled
|
||||
// <0x1=>5-6 SCL cycle time-out(50-60us)
|
||||
// <0x2=>10-11 SCL cycle time-out(100-110us)
|
||||
// <0x3=>20-21 SCL cycle time-out(200-210us)
|
||||
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
|
||||
// <id> i2c_master_arch_inactout
|
||||
#ifndef CONF_SERCOM_0_I2CM_INACTOUT
|
||||
#define CONF_SERCOM_0_I2CM_INACTOUT 0x3
|
||||
#endif
|
||||
|
||||
// <o> SDA Hold Time (SDAHOLD)
|
||||
// <0=>Disabled
|
||||
// <1=>50-100ns hold time
|
||||
// <2=>300-600ns hold time
|
||||
// <3=>400-800ns hold time
|
||||
// <i> Defines the SDA hold time with respect to the negative edge of SCL
|
||||
// <id> i2c_master_arch_sdahold
|
||||
#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
|
||||
#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Determine if the module shall run in standby sleep mode
|
||||
// <id> i2c_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
|
||||
#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> i2c_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
|
||||
#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_SERCOM_0_I2CM_SPEED
|
||||
#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
|
||||
#endif
|
||||
#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
|
||||
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
|
||||
#undef CONF_SERCOM_0_I2CM_TRISE
|
||||
#define CONF_SERCOM_0_I2CM_TRISE 215U
|
||||
#endif
|
||||
|
||||
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
|
||||
// BAUD + BAUDLOW = --------------------------------------------------------------------
|
||||
// i2c_scl_freq
|
||||
// BAUD: register value low [7:0]
|
||||
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
|
||||
#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \
|
||||
(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U) \
|
||||
- (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U) \
|
||||
/ 1000U)) \
|
||||
* 10U \
|
||||
+ 5U) \
|
||||
/ (CONF_SERCOM_0_I2CM_BAUD * 10U))
|
||||
#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
|
||||
#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
|
||||
#warning Requested I2C baudrate too low, please check
|
||||
#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
|
||||
#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
|
||||
#warning Requested I2C baudrate too high, please check
|
||||
#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
|
||||
#else
|
||||
#define CONF_SERCOM_0_I2CM_BAUD_RATE \
|
||||
((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \
|
||||
? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
|
||||
: (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef CONF_SERCOM_4_USART_ENABLE
|
||||
#define CONF_SERCOM_4_USART_ENABLE 1
|
||||
#endif
|
||||
@@ -69,7 +204,7 @@
|
||||
// <e> Advanced configuration
|
||||
// <id> usart_advanced
|
||||
#ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0
|
||||
#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
|
||||
@@ -4,6 +4,38 @@
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <y> ADC Clock Source
|
||||
// <id> adc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <i> Select the clock source for ADC.
|
||||
#ifndef CONF_GCLK_ADC0_SRC
|
||||
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_ADC0_FREQUENCY
|
||||
* \brief ADC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_ADC0_FREQUENCY
|
||||
#define CONF_GCLK_ADC0_FREQUENCY 40001536
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
@@ -31,6 +63,70 @@
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM0_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
|
||||
* \brief SERCOM0's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 40001536
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
|
||||
* \brief SERCOM0's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 4000000
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM4_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
|
||||
@@ -11,11 +11,43 @@
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
struct can_async_descriptor CAN_0;
|
||||
#include <hpl_adc_base.h>
|
||||
|
||||
/*! The buffer size for USART */
|
||||
#define TARGET_IO_BUFFER_SIZE 16
|
||||
|
||||
struct usart_async_descriptor TARGET_IO;
|
||||
struct can_async_descriptor CAN_0;
|
||||
|
||||
static uint8_t TARGET_IO_buffer[TARGET_IO_BUFFER_SIZE];
|
||||
|
||||
struct adc_sync_descriptor ADC_0;
|
||||
|
||||
struct flash_descriptor FLASH_0;
|
||||
|
||||
struct usart_sync_descriptor TARGET_IO;
|
||||
struct i2c_m_sync_desc I2C_0;
|
||||
|
||||
void ADC_0_PORT_init(void)
|
||||
{
|
||||
|
||||
// Disable digital pin circuitry
|
||||
gpio_set_pin_direction(PA10, GPIO_DIRECTION_OFF);
|
||||
|
||||
gpio_set_pin_function(PA10, PINMUX_PA10B_ADC0_AIN10);
|
||||
}
|
||||
|
||||
void ADC_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_APBCMASK_ADC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
}
|
||||
|
||||
void ADC_0_init(void)
|
||||
{
|
||||
ADC_0_CLOCK_init();
|
||||
ADC_0_PORT_init();
|
||||
adc_sync_init(&ADC_0, ADC0, _adc_get_adc_sync());
|
||||
}
|
||||
|
||||
void FLASH_0_CLOCK_init(void)
|
||||
{
|
||||
@@ -29,7 +61,63 @@ void FLASH_0_init(void)
|
||||
flash_init(&FLASH_0, NVMCTRL);
|
||||
}
|
||||
|
||||
void TARGET_IO_PORT_init(void)
|
||||
void I2C_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_pull_mode(PA08,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PA08, PINMUX_PA08C_SERCOM0_PAD0);
|
||||
|
||||
gpio_set_pin_pull_mode(PA09,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PA09, PINMUX_PA09C_SERCOM0_PAD1);
|
||||
}
|
||||
|
||||
void I2C_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_mclk_set_APBCMASK_SERCOM0_bit(MCLK);
|
||||
}
|
||||
|
||||
void I2C_0_init(void)
|
||||
{
|
||||
I2C_0_CLOCK_init();
|
||||
i2c_m_sync_init(&I2C_0, SERCOM0);
|
||||
I2C_0_PORT_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief USART Clock initialization function
|
||||
*
|
||||
* Enables register interface and peripheral clock
|
||||
*/
|
||||
void TARGET_IO_CLOCK_init()
|
||||
{
|
||||
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_mclk_set_APBCMASK_SERCOM4_bit(MCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief USART pinmux initialization function
|
||||
*
|
||||
* Set each required pin to USART functionality
|
||||
*/
|
||||
void TARGET_IO_PORT_init()
|
||||
{
|
||||
|
||||
gpio_set_pin_function(PB10, PINMUX_PB10D_SERCOM4_PAD2);
|
||||
@@ -37,17 +125,15 @@ void TARGET_IO_PORT_init(void)
|
||||
gpio_set_pin_function(PB11, PINMUX_PB11D_SERCOM4_PAD3);
|
||||
}
|
||||
|
||||
void TARGET_IO_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_mclk_set_APBCMASK_SERCOM4_bit(MCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief USART initialization function
|
||||
*
|
||||
* Enables USART peripheral, clocks and initializes USART driver
|
||||
*/
|
||||
void TARGET_IO_init(void)
|
||||
{
|
||||
TARGET_IO_CLOCK_init();
|
||||
usart_sync_init(&TARGET_IO, SERCOM4, (void *)NULL);
|
||||
usart_async_init(&TARGET_IO, SERCOM4, TARGET_IO_buffer, TARGET_IO_BUFFER_SIZE, (void *)NULL);
|
||||
TARGET_IO_PORT_init();
|
||||
}
|
||||
|
||||
@@ -89,8 +175,11 @@ void system_init(void)
|
||||
|
||||
gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
ADC_0_init();
|
||||
|
||||
FLASH_0_init();
|
||||
|
||||
I2C_0_init();
|
||||
TARGET_IO_init();
|
||||
CAN_0_init();
|
||||
}
|
||||
|
||||
@@ -21,19 +21,33 @@ extern "C" {
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_adc_sync.h>
|
||||
|
||||
#include <hal_flash.h>
|
||||
|
||||
#include <hal_usart_sync.h>
|
||||
#include <hal_i2c_m_sync.h>
|
||||
#include <hal_usart_async.h>
|
||||
#include <hal_can_async.h>
|
||||
|
||||
extern struct adc_sync_descriptor ADC_0;
|
||||
|
||||
extern struct flash_descriptor FLASH_0;
|
||||
|
||||
extern struct usart_sync_descriptor TARGET_IO;
|
||||
extern struct can_async_descriptor CAN_0;
|
||||
extern struct i2c_m_sync_desc I2C_0;
|
||||
extern struct usart_async_descriptor TARGET_IO;
|
||||
extern struct can_async_descriptor CAN_0;
|
||||
|
||||
void ADC_0_PORT_init(void);
|
||||
void ADC_0_CLOCK_init(void);
|
||||
void ADC_0_init(void);
|
||||
|
||||
void FLASH_0_init(void);
|
||||
void FLASH_0_CLOCK_init(void);
|
||||
|
||||
void I2C_0_CLOCK_init(void);
|
||||
void I2C_0_init(void);
|
||||
void I2C_0_PORT_init(void);
|
||||
|
||||
void TARGET_IO_PORT_init(void);
|
||||
void TARGET_IO_CLOCK_init(void);
|
||||
void TARGET_IO_init(void);
|
||||
|
||||
@@ -10,6 +10,20 @@
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using ADC_0 to generate waveform.
|
||||
*/
|
||||
void ADC_0_example(void)
|
||||
{
|
||||
uint8_t buffer[2];
|
||||
|
||||
adc_sync_enable_channel(&ADC_0, 0);
|
||||
|
||||
while (1) {
|
||||
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t src_data[128];
|
||||
static uint8_t chk_data[128];
|
||||
/**
|
||||
@@ -70,16 +84,43 @@ void RWW_FLASH_0_example(void)
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_0_example(void)
|
||||
{
|
||||
struct io_descriptor *I2C_0_io;
|
||||
|
||||
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
|
||||
i2c_m_sync_enable(&I2C_0);
|
||||
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
|
||||
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using TARGET_IO to write "Hello World" using the IO abstraction.
|
||||
*
|
||||
* Since the driver is asynchronous we need to use statically allocated memory for string
|
||||
* because driver initiates transfer and then returns before the transmission is completed.
|
||||
*
|
||||
* Once transfer has been completed the tx_cb function will be called.
|
||||
*/
|
||||
|
||||
static uint8_t example_TARGET_IO[12] = "Hello World!";
|
||||
|
||||
static void tx_cb_TARGET_IO(const struct usart_async_descriptor *const io_descr)
|
||||
{
|
||||
/* Transfer completed */
|
||||
}
|
||||
|
||||
void TARGET_IO_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
usart_sync_get_io_descriptor(&TARGET_IO, &io);
|
||||
usart_sync_enable(&TARGET_IO);
|
||||
|
||||
io_write(io, (uint8_t *)"Hello World!", 12);
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, tx_cb_TARGET_IO);
|
||||
/*usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, rx_cb);
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_ERROR_CB, err_cb);*/
|
||||
usart_async_get_io_descriptor(&TARGET_IO, &io);
|
||||
usart_async_enable(&TARGET_IO);
|
||||
|
||||
io_write(io, example_TARGET_IO, 12);
|
||||
}
|
||||
|
||||
void CAN_0_tx_callback(struct can_async_descriptor *const descr)
|
||||
|
||||
@@ -12,9 +12,13 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ADC_0_example(void);
|
||||
|
||||
void FLASH_0_example(void);
|
||||
void RWW_FLASH_0_example(void);
|
||||
|
||||
void I2C_0_example(void);
|
||||
|
||||
void TARGET_IO_example(void);
|
||||
|
||||
void CAN_0_example(void);
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
======================
|
||||
ADC Synchronous driver
|
||||
======================
|
||||
|
||||
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
|
||||
A reference signal with a known voltage level is quantified into equally
|
||||
sized chunks, each representing a digital value from 0 to the highest number
|
||||
possible with the bit resolution supported by the ADC. The input voltage
|
||||
measured by the ADC is compared against these chunks and the chunk with the
|
||||
closest voltage level defines the digital value that can be used to represent
|
||||
the analog input voltage level.
|
||||
|
||||
Usually an ADC can operate in either differential or single-ended mode.
|
||||
In differential mode two signals (V+ and V-) are compared against each other
|
||||
and the resulting digital value represents the relative voltage level between
|
||||
V+ and V-. This means that if the input voltage level on V+ is lower than on
|
||||
V- the digital value is negative, which also means that in differential
|
||||
mode one bit is lost to the sign. In single-ended mode only V+ is compared
|
||||
against the reference voltage, and the resulting digital value can only be
|
||||
positive, but the full bit-range of the ADC can be used.
|
||||
|
||||
Usually multiple resolutions are supported by the ADC, lower resolution can
|
||||
reduce the conversion time, but lose accuracy.
|
||||
|
||||
Some ADCs has a gain stage on the input lines which can be used to increase the
|
||||
dynamic range. The default gain value is usually x1, which means that the
|
||||
conversion range is from 0V to the reference voltage.
|
||||
Applications can change the gain stage, to increase or reduce the conversion
|
||||
range.
|
||||
|
||||
The window mode allows the conversion result to be compared to a set of
|
||||
predefined threshold values. Applications can use callback function to monitor
|
||||
if the conversion result exceeds predefined threshold value.
|
||||
|
||||
Usually multiple reference voltages are supported by the ADC, both internal and
|
||||
external with difference voltage levels. The reference voltage have an impact
|
||||
on the accuracy, and should be selected to cover the full range of the analog
|
||||
input signal and never less than the expected maximum input voltage.
|
||||
|
||||
There are two conversion modes supported by ADC, single shot and free running.
|
||||
In single shot mode the ADC only make one conversion when triggered by the
|
||||
application, in free running mode it continues to make conversion from it
|
||||
is triggered until it is stopped by the application. When window monitoring,
|
||||
the ADC should be set to free running mode.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Support multiple Conversion Mode, Single or Free run
|
||||
* Start ADC Conversion
|
||||
* Read Conversion Result
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
|
||||
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
|
||||
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* ADC hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
N/A
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
=============================
|
||||
I2C Master synchronous driver
|
||||
=============================
|
||||
|
||||
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
|
||||
for on-board low-speed bi-directional communication between controllers and
|
||||
peripherals. The master device is responsible for initiating and controlling
|
||||
all transfers on the I2C bus. Only one master device can be active on the I2C
|
||||
bus at the time, but the master role can be transferred between devices on the
|
||||
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
|
||||
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
|
||||
resistors.
|
||||
|
||||
The stop condition is automatically controlled by the driver if the I/O write and
|
||||
read functions are used, but can be manually controlled by using the
|
||||
i2c_m_sync_transfer function.
|
||||
|
||||
Often a master accesses different information in the slave by accessing
|
||||
different registers in the slave. This is done by first sending a message to
|
||||
the target slave containing the register address, followed by a repeated start
|
||||
condition (no stop condition between) ending with transferring register data.
|
||||
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
|
||||
function, but limited to 8-bit register addresses.
|
||||
|
||||
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
|
||||
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
|
||||
stick within the SCL clock frequency range supported by the selected mode.
|
||||
The requested SCL clock frequency is not validated by the
|
||||
i2c_m_sync_set_baudrate function against the selected I2C mode.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* I2C Master support
|
||||
* Initialization and de-initialization
|
||||
* Enabling and disabling
|
||||
* Run-time bus speed configuration
|
||||
* Write and read I2C messages
|
||||
* Slave register access functions (limited to 8-bit address)
|
||||
* Manual or automatic stop condition generation
|
||||
* 10- and 7- bit addressing
|
||||
* I2C Modes supported
|
||||
+----------------------+-------------------+
|
||||
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
|
||||
+----------------------+-------------------+
|
||||
|* Fastmode+ | (SCL: 1 - 1000kHz)|
|
||||
+----------------------+-------------------+
|
||||
|* Highspeed mode | (SCL: 1 - 3400kHz)|
|
||||
+----------------------+-------------------+
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
|
||||
* Data communication between micro controllers
|
||||
* Controlling displays
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
* I2C Master capable hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
General
|
||||
^^^^^^^
|
||||
|
||||
* System Managmenet Bus (SMBus) not supported.
|
||||
* Power Management Bus (PMBus) not supported.
|
||||
|
||||
Clock considerations
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
||||
|
||||
+17
-3
@@ -1,9 +1,20 @@
|
||||
The USART Synchronous Driver
|
||||
============================
|
||||
The USART Asynchronous Driver
|
||||
=============================
|
||||
|
||||
The universal synchronous and asynchronous receiver and transmitter
|
||||
(USART) is usually used to transfer data from one device to the other.
|
||||
|
||||
The USART driver use a ring buffer to store received data. When the USART
|
||||
raise the data received interrupt, this data will be stored in the ring buffer
|
||||
at the next free location. When the ring buffer is full, the next reception
|
||||
will overwrite the oldest data stored in the ring buffer. There is one
|
||||
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
|
||||
is called SERCOM0_USART_BUFFER_SIZE.
|
||||
|
||||
On the other hand, when sending data over USART, the data is not copied to an
|
||||
internal buffer, but the data buffer supplied by the user is used. The callback
|
||||
will only be generated at the end of the buffer and not for each byte.
|
||||
|
||||
User can set action for flow control pins by function usart_set_flow_control,
|
||||
if the flow control is enabled. All the available states are defined in union
|
||||
usart_flow_control_state.
|
||||
@@ -24,6 +35,8 @@ Features
|
||||
* Data order
|
||||
* Flow control
|
||||
* Data transfer: transmission, reception
|
||||
* Notifications about transfer done or error case via callbacks
|
||||
* Status information with busy state and transfer count
|
||||
|
||||
Applications
|
||||
------------
|
||||
@@ -34,7 +47,8 @@ between devices.
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
USART capable hardware.
|
||||
USART capable hardware, with interrupt on each character is sent or
|
||||
received.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,116 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Ringbuffer declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _UTILS_RINGBUFFER_H_INCLUDED
|
||||
#define _UTILS_RINGBUFFER_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_utils_ringbuffer
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "compiler.h"
|
||||
#include "utils_assert.h"
|
||||
|
||||
/**
|
||||
* \brief Ring buffer element type
|
||||
*/
|
||||
struct ringbuffer {
|
||||
uint8_t *buf; /** Buffer base address */
|
||||
uint32_t size; /** Buffer size */
|
||||
uint32_t read_index; /** Buffer read index */
|
||||
uint32_t write_index; /** Buffer write index */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Ring buffer init
|
||||
*
|
||||
* \param[in] rb The pointer to a ring buffer structure instance
|
||||
* \param[in] buf Space to store the data
|
||||
* \param[in] size The buffer length, must be aligned with power of 2
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size);
|
||||
|
||||
/**
|
||||
* \brief Get one byte from ring buffer, the user needs to handle the concurrent
|
||||
* access on buffer via put/get/flush
|
||||
*
|
||||
* \param[in] rb The pointer to a ring buffer structure instance
|
||||
* \param[in] data One byte space to store the read data
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data);
|
||||
|
||||
/**
|
||||
* \brief Put one byte to ring buffer, the user needs to handle the concurrent access
|
||||
* on buffer via put/get/flush
|
||||
*
|
||||
* \param[in] rb The pointer to a ring buffer structure instance
|
||||
* \param[in] data One byte data to be put into ring buffer
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Return the element number of ring buffer
|
||||
*
|
||||
* \param[in] rb The pointer to a ring buffer structure instance
|
||||
*
|
||||
* \return The number of elements in ring buffer [0, rb->size]
|
||||
*/
|
||||
uint32_t ringbuffer_num(const struct ringbuffer *const rb);
|
||||
|
||||
/**
|
||||
* \brief Flush ring buffer, the user needs to handle the concurrent access on buffer
|
||||
* via put/get/flush
|
||||
*
|
||||
* \param[in] rb The pointer to a ring buffer structure instance
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
uint32_t ringbuffer_flush(struct ringbuffer *const rb);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _UTILS_RINGBUFFER_H_INCLUDED */
|
||||
@@ -0,0 +1,118 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Ringbuffer functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#include "utils_ringbuffer.h"
|
||||
|
||||
/**
|
||||
* \brief Ringbuffer init
|
||||
*/
|
||||
int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size)
|
||||
{
|
||||
ASSERT(rb && buf && size);
|
||||
|
||||
/*
|
||||
* buf size must be aligned to power of 2
|
||||
*/
|
||||
if ((size & (size - 1)) != 0) {
|
||||
return ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
/* size - 1 is faster in calculation */
|
||||
rb->size = size - 1;
|
||||
rb->read_index = 0;
|
||||
rb->write_index = rb->read_index;
|
||||
rb->buf = (uint8_t *)buf;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get one byte from ringbuffer
|
||||
*
|
||||
*/
|
||||
int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data)
|
||||
{
|
||||
ASSERT(rb && data);
|
||||
|
||||
if (rb->write_index != rb->read_index) {
|
||||
*data = rb->buf[rb->read_index & rb->size];
|
||||
rb->read_index++;
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
return ERR_NOT_FOUND;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Put one byte to ringbuffer
|
||||
*
|
||||
*/
|
||||
int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data)
|
||||
{
|
||||
ASSERT(rb);
|
||||
|
||||
rb->buf[rb->write_index & rb->size] = data;
|
||||
|
||||
/*
|
||||
* buffer full strategy: new data will overwrite the oldest data in
|
||||
* the buffer
|
||||
*/
|
||||
if ((rb->write_index - rb->read_index) > rb->size) {
|
||||
rb->read_index = rb->write_index - rb->size;
|
||||
}
|
||||
|
||||
rb->write_index++;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Return the element number of ringbuffer
|
||||
*/
|
||||
uint32_t ringbuffer_num(const struct ringbuffer *const rb)
|
||||
{
|
||||
ASSERT(rb);
|
||||
|
||||
return rb->write_index - rb->read_index;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Flush ringbuffer
|
||||
*/
|
||||
uint32_t ringbuffer_flush(struct ringbuffer *const rb)
|
||||
{
|
||||
ASSERT(rb);
|
||||
|
||||
rb->read_index = rb->write_index;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
+14
-36
@@ -1,9 +1,9 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Time measure related functionality declaration.
|
||||
* \brief ADC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@@ -31,64 +31,42 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_TIME_MEASURE_H_INCLUDED
|
||||
#define _HPL_TIME_MEASURE_H_INCLUDED
|
||||
#ifndef _HPL_ADC_ADC_H_INCLUDED
|
||||
#define _HPL_ADC_ADC_H_INCLUDED
|
||||
|
||||
#include <hpl_adc_sync.h>
|
||||
#include <hpl_adc_async.h>
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Time measure
|
||||
* \addtogroup HPL ADC
|
||||
*
|
||||
* \section hpl_time_measure_rev Revision History
|
||||
* \section hpl_adc_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief System time type
|
||||
*/
|
||||
typedef uint32_t system_time_t;
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initialize system time module
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance to initialize
|
||||
*/
|
||||
void _system_time_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize system time module
|
||||
* \brief Retrieve ADC helper functions
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance to initialize
|
||||
* \return A pointer to set of ADC helper functions
|
||||
*/
|
||||
void _system_time_deinit(void *const hw);
|
||||
void *_adc_get_adc_sync(void);
|
||||
void *_adc_get_adc_async(void);
|
||||
|
||||
/**
|
||||
* \brief Get system time
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance to initialize
|
||||
*/
|
||||
system_time_t _system_time_get(const void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Get maximum possible system time
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance to initialize
|
||||
*/
|
||||
system_time_t _system_time_get_max_time_value(const void *const hw);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_TIME_MEASURE_H_INCLUDED */
|
||||
#endif /* _HPL_USART_UART_H_INCLUDED */
|
||||
@@ -156,6 +156,8 @@ static struct usart_configuration _usarts[] = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct _usart_async_device *_sercom4_dev = NULL;
|
||||
|
||||
static uint8_t _get_sercom_index(const void *const hw);
|
||||
static uint8_t _sercom_get_irq_num(const void *const hw);
|
||||
static void _sercom_init_irq_param(const void *const hw, void *dev);
|
||||
@@ -549,6 +551,40 @@ void _usart_async_set_irq_state(struct _usart_async_device *const device, const
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Sercom interrupt handler
|
||||
*
|
||||
* \param[in] p The pointer to interrupt parameter
|
||||
*/
|
||||
static void _sercom_usart_interrupt_handler(struct _usart_async_device *device)
|
||||
{
|
||||
void *hw = device->hw;
|
||||
|
||||
if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) {
|
||||
hri_sercomusart_clear_INTEN_DRE_bit(hw);
|
||||
device->usart_cb.tx_byte_sent(device);
|
||||
} else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) {
|
||||
hri_sercomusart_clear_INTEN_TXC_bit(hw);
|
||||
device->usart_cb.tx_done_cb(device);
|
||||
} else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) {
|
||||
if (hri_sercomusart_read_STATUS_reg(hw)
|
||||
& (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF
|
||||
| SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) {
|
||||
hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK);
|
||||
return;
|
||||
}
|
||||
|
||||
device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw));
|
||||
} else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) {
|
||||
uint32_t status;
|
||||
|
||||
hri_sercomusart_clear_interrupt_ERROR_bit(hw);
|
||||
device->usart_cb.error_cb(device);
|
||||
status = hri_sercomusart_read_STATUS_reg(hw);
|
||||
hri_sercomusart_clear_STATUS_reg(hw, status);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Retrieve ordinal number of the given sercom hardware instance
|
||||
*
|
||||
@@ -576,6 +612,10 @@ static uint8_t _get_sercom_index(const void *const hw)
|
||||
*/
|
||||
static void _sercom_init_irq_param(const void *const hw, void *dev)
|
||||
{
|
||||
|
||||
if (hw == SERCOM4) {
|
||||
_sercom4_dev = (struct _usart_async_device *)dev;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -2407,6 +2447,11 @@ static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_a
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void SERCOM4_Handler(void)
|
||||
{
|
||||
_sercom_usart_interrupt_handler(_sercom4_dev);
|
||||
}
|
||||
|
||||
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
|
||||
{
|
||||
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
<path>$PROJ_DIR$\examples</path>
|
||||
<path>$PROJ_DIR$\hal\include</path>
|
||||
<path>$PROJ_DIR$\hal\utils\include</path>
|
||||
<path>$PROJ_DIR$\hpl\adc</path>
|
||||
<path>$PROJ_DIR$\hpl\can</path>
|
||||
<path>$PROJ_DIR$\hpl\core</path>
|
||||
<path>$PROJ_DIR$\hpl\divas</path>
|
||||
@@ -34,6 +35,7 @@
|
||||
<path>$PROJ_DIR$\examples</path>
|
||||
<path>$PROJ_DIR$\hal\include</path>
|
||||
<path>$PROJ_DIR$\hal\utils\include</path>
|
||||
<path>$PROJ_DIR$\hpl\adc</path>
|
||||
<path>$PROJ_DIR$\hpl\can</path>
|
||||
<path>$PROJ_DIR$\hpl\core</path>
|
||||
<path>$PROJ_DIR$\hpl\divas</path>
|
||||
@@ -101,6 +103,7 @@
|
||||
</group>
|
||||
|
||||
<group name="config">
|
||||
<path>config/hpl_adc_config.h</path>
|
||||
<path>config/hpl_can_config.h</path>
|
||||
<path>config/hpl_divas_config.h</path>
|
||||
<path>config/hpl_dmac_config.h</path>
|
||||
@@ -120,15 +123,20 @@
|
||||
</group>
|
||||
|
||||
<group name="hal/include">
|
||||
<path>hal/include/hal_adc_sync.h</path>
|
||||
<path>hal/include/hal_atomic.h</path>
|
||||
<path>hal/include/hal_can_async.h</path>
|
||||
<path>hal/include/hal_delay.h</path>
|
||||
<path>hal/include/hal_flash.h</path>
|
||||
<path>hal/include/hal_gpio.h</path>
|
||||
<path>hal/include/hal_i2c_m_sync.h</path>
|
||||
<path>hal/include/hal_init.h</path>
|
||||
<path>hal/include/hal_io.h</path>
|
||||
<path>hal/include/hal_sleep.h</path>
|
||||
<path>hal/include/hal_usart_sync.h</path>
|
||||
<path>hal/include/hal_usart_async.h</path>
|
||||
<path>hal/include/hpl_adc_async.h</path>
|
||||
<path>hal/include/hpl_adc_dma.h</path>
|
||||
<path>hal/include/hpl_adc_sync.h</path>
|
||||
<path>hal/include/hpl_can.h</path>
|
||||
<path>hal/include/hpl_can_async.h</path>
|
||||
<path>hal/include/hpl_core.h</path>
|
||||
@@ -161,15 +169,17 @@
|
||||
</group>
|
||||
|
||||
<group name="hal/src">
|
||||
<path>hal/src/hal_adc_sync.c</path>
|
||||
<path>hal/src/hal_atomic.c</path>
|
||||
<path>hal/src/hal_can_async.c</path>
|
||||
<path>hal/src/hal_delay.c</path>
|
||||
<path>hal/src/hal_flash.c</path>
|
||||
<path>hal/src/hal_gpio.c</path>
|
||||
<path>hal/src/hal_i2c_m_sync.c</path>
|
||||
<path>hal/src/hal_init.c</path>
|
||||
<path>hal/src/hal_io.c</path>
|
||||
<path>hal/src/hal_sleep.c</path>
|
||||
<path>hal/src/hal_usart_sync.c</path>
|
||||
<path>hal/src/hal_usart_async.c</path>
|
||||
</group>
|
||||
|
||||
<group name="hal/utils/include">
|
||||
@@ -183,12 +193,19 @@
|
||||
<path>hal/utils/include/utils_increment_macro.h</path>
|
||||
<path>hal/utils/include/utils_list.h</path>
|
||||
<path>hal/utils/include/utils_repeat_macro.h</path>
|
||||
<path>hal/utils/include/utils_ringbuffer.h</path>
|
||||
</group>
|
||||
|
||||
<group name="hal/utils/src">
|
||||
<path>hal/utils/src/utils_assert.c</path>
|
||||
<path>hal/utils/src/utils_event.c</path>
|
||||
<path>hal/utils/src/utils_list.c</path>
|
||||
<path>hal/utils/src/utils_ringbuffer.c</path>
|
||||
</group>
|
||||
|
||||
<group name="hpl/adc">
|
||||
<path>hpl/adc/hpl_adc.c</path>
|
||||
<path>hpl/adc/hpl_adc_base.h</path>
|
||||
</group>
|
||||
|
||||
<group name="hpl/can">
|
||||
|
||||
@@ -58,6 +58,31 @@ SECTIONS
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for utest */
|
||||
. = ALIGN(4);
|
||||
__rt_utest_tc_tab_start = .;
|
||||
KEEP(*(UtestTcTab))
|
||||
__rt_utest_tc_tab_end = .;
|
||||
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
|
||||
@@ -54,14 +54,38 @@
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_DEVFS
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
|
||||
/* Using USB */
|
||||
|
||||
@@ -170,11 +194,13 @@
|
||||
|
||||
#define SAMC21_CAN0
|
||||
#define SAMC21_ADC0
|
||||
#define SAMC21_I2C0
|
||||
|
||||
/* Application Demo Config */
|
||||
|
||||
#define SAM_CAN_EXAMPLE
|
||||
#define SAM_ADC_EXAMPLE
|
||||
#define SAM_I2C_EXAMPLE
|
||||
#define SOC_SAMC21
|
||||
|
||||
#endif
|
||||
|
||||
+129
-14
@@ -21,7 +21,9 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
|
||||
CONFIG_RT_USING_IDLE_HOOK=y
|
||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||
# CONFIG_RT_USING_TIMER_SOFT is not set
|
||||
CONFIG_RT_USING_TIMER_SOFT=y
|
||||
CONFIG_RT_TIMER_THREAD_PRIO=4
|
||||
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
|
||||
|
||||
#
|
||||
# kservice optimization
|
||||
@@ -93,8 +95,33 @@ CONFIG_RT_USING_USER_MAIN=y
|
||||
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
# CONFIG_RT_USING_LEGACY is not set
|
||||
# CONFIG_RT_USING_MSH is not set
|
||||
# CONFIG_RT_USING_DFS is not set
|
||||
CONFIG_RT_USING_MSH=y
|
||||
CONFIG_RT_USING_FINSH=y
|
||||
CONFIG_FINSH_USING_MSH=y
|
||||
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||
CONFIG_FINSH_USING_HISTORY=y
|
||||
CONFIG_FINSH_HISTORY_LINES=5
|
||||
CONFIG_FINSH_USING_SYMTAB=y
|
||||
CONFIG_FINSH_CMD_SIZE=80
|
||||
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
|
||||
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||
# CONFIG_FINSH_USING_AUTH is not set
|
||||
CONFIG_FINSH_ARG_MAX=10
|
||||
CONFIG_RT_USING_DFS=y
|
||||
CONFIG_DFS_USING_POSIX=y
|
||||
CONFIG_DFS_USING_WORKDIR=y
|
||||
CONFIG_DFS_FILESYSTEMS_MAX=4
|
||||
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
|
||||
CONFIG_DFS_FD_MAX=16
|
||||
# CONFIG_RT_USING_DFS_MNTTABLE is not set
|
||||
# CONFIG_RT_USING_DFS_ELMFAT is not set
|
||||
CONFIG_RT_USING_DFS_DEVFS=y
|
||||
# CONFIG_RT_USING_DFS_ROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_RAMFS is not set
|
||||
# CONFIG_RT_USING_DFS_NFS is not set
|
||||
# CONFIG_RT_USING_FAL is not set
|
||||
# CONFIG_RT_USING_LWP is not set
|
||||
|
||||
@@ -102,7 +129,9 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
# Device Drivers
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE_IPC=y
|
||||
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
|
||||
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
|
||||
CONFIG_RT_USING_SERIAL=y
|
||||
CONFIG_RT_USING_SERIAL_V1=y
|
||||
# CONFIG_RT_USING_SERIAL_V2 is not set
|
||||
@@ -111,9 +140,11 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
|
||||
# CONFIG_RT_USING_CAN is not set
|
||||
# CONFIG_RT_USING_HWTIMER is not set
|
||||
# CONFIG_RT_USING_CPUTIME is not set
|
||||
# CONFIG_RT_USING_I2C is not set
|
||||
CONFIG_RT_USING_I2C=y
|
||||
# CONFIG_RT_I2C_DEBUG is not set
|
||||
# CONFIG_RT_USING_I2C_BITOPS is not set
|
||||
# CONFIG_RT_USING_PHY is not set
|
||||
CONFIG_RT_USING_PIN=y
|
||||
# CONFIG_RT_USING_PIN is not set
|
||||
# CONFIG_RT_USING_ADC is not set
|
||||
# CONFIG_RT_USING_DAC is not set
|
||||
# CONFIG_RT_USING_PWM is not set
|
||||
@@ -147,11 +178,20 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||
#
|
||||
# POSIX (Portable Operating System Interface) layer
|
||||
#
|
||||
# CONFIG_RT_USING_POSIX_FS is not set
|
||||
# CONFIG_RT_USING_POSIX_DELAY is not set
|
||||
# CONFIG_RT_USING_POSIX_CLOCK is not set
|
||||
# CONFIG_RT_USING_POSIX_TIMER is not set
|
||||
# CONFIG_RT_USING_PTHREADS is not set
|
||||
CONFIG_RT_USING_POSIX_FS=y
|
||||
CONFIG_RT_USING_POSIX_DEVIO=y
|
||||
# CONFIG_RT_USING_POSIX_STDIO is not set
|
||||
CONFIG_RT_USING_POSIX_POLL=y
|
||||
CONFIG_RT_USING_POSIX_SELECT=y
|
||||
CONFIG_RT_USING_POSIX_SOCKET=y
|
||||
# CONFIG_RT_USING_POSIX_TERMIOS is not set
|
||||
CONFIG_RT_USING_POSIX_AIO=y
|
||||
# CONFIG_RT_USING_POSIX_MMAN is not set
|
||||
CONFIG_RT_USING_POSIX_DELAY=y
|
||||
CONFIG_RT_USING_POSIX_CLOCK=y
|
||||
CONFIG_RT_USING_POSIX_TIMER=y
|
||||
CONFIG_RT_USING_PTHREADS=y
|
||||
CONFIG_PTHREAD_NUM_MAX=8
|
||||
# CONFIG_RT_USING_MODULE is not set
|
||||
|
||||
#
|
||||
@@ -169,9 +209,80 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||
#
|
||||
# Network
|
||||
#
|
||||
# CONFIG_RT_USING_SAL is not set
|
||||
# CONFIG_RT_USING_NETDEV is not set
|
||||
# CONFIG_RT_USING_LWIP is not set
|
||||
CONFIG_RT_USING_SAL=y
|
||||
CONFIG_SAL_INTERNET_CHECK=y
|
||||
|
||||
#
|
||||
# protocol stack implement
|
||||
#
|
||||
CONFIG_SAL_USING_LWIP=y
|
||||
CONFIG_SAL_USING_POSIX=y
|
||||
CONFIG_RT_USING_NETDEV=y
|
||||
CONFIG_NETDEV_USING_IFCONFIG=y
|
||||
CONFIG_NETDEV_USING_PING=y
|
||||
CONFIG_NETDEV_USING_NETSTAT=y
|
||||
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
|
||||
# CONFIG_NETDEV_USING_IPV6 is not set
|
||||
CONFIG_NETDEV_IPV4=1
|
||||
CONFIG_NETDEV_IPV6=0
|
||||
# CONFIG_NETDEV_IPV6_SCOPES is not set
|
||||
CONFIG_RT_USING_LWIP=y
|
||||
CONFIG_RT_USING_LWIP_LOCAL_VERSION=y
|
||||
# CONFIG_RT_USING_LWIP141 is not set
|
||||
# CONFIG_RT_USING_LWIP203 is not set
|
||||
CONFIG_RT_USING_LWIP212=y
|
||||
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
|
||||
# CONFIG_RT_USING_LWIP_IPV6 is not set
|
||||
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
|
||||
CONFIG_RT_LWIP_IGMP=y
|
||||
CONFIG_RT_LWIP_ICMP=y
|
||||
# CONFIG_RT_LWIP_SNMP is not set
|
||||
CONFIG_RT_LWIP_DNS=y
|
||||
CONFIG_RT_LWIP_DHCP=y
|
||||
CONFIG_IP_SOF_BROADCAST=1
|
||||
CONFIG_IP_SOF_BROADCAST_RECV=1
|
||||
|
||||
#
|
||||
# Static IPv4 Address
|
||||
#
|
||||
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
|
||||
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
|
||||
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
|
||||
CONFIG_RT_LWIP_UDP=y
|
||||
CONFIG_RT_LWIP_TCP=y
|
||||
CONFIG_RT_LWIP_RAW=y
|
||||
# CONFIG_RT_LWIP_PPP is not set
|
||||
CONFIG_RT_MEMP_NUM_NETCONN=8
|
||||
CONFIG_RT_LWIP_PBUF_NUM=16
|
||||
CONFIG_RT_LWIP_RAW_PCB_NUM=4
|
||||
CONFIG_RT_LWIP_UDP_PCB_NUM=4
|
||||
CONFIG_RT_LWIP_TCP_PCB_NUM=4
|
||||
CONFIG_RT_LWIP_TCP_SEG_NUM=40
|
||||
CONFIG_RT_LWIP_TCP_SND_BUF=8196
|
||||
CONFIG_RT_LWIP_TCP_WND=8196
|
||||
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
|
||||
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
|
||||
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
|
||||
# CONFIG_LWIP_NO_RX_THREAD is not set
|
||||
# CONFIG_LWIP_NO_TX_THREAD is not set
|
||||
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
|
||||
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
|
||||
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
|
||||
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
|
||||
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
|
||||
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
|
||||
CONFIG_SO_REUSE=1
|
||||
CONFIG_LWIP_SO_RCVTIMEO=1
|
||||
CONFIG_LWIP_SO_SNDTIMEO=1
|
||||
CONFIG_LWIP_SO_RCVBUF=1
|
||||
CONFIG_LWIP_SO_LINGER=0
|
||||
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
|
||||
CONFIG_LWIP_NETIF_LOOPBACK=0
|
||||
# CONFIG_RT_LWIP_STATS is not set
|
||||
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
|
||||
CONFIG_RT_LWIP_USING_PING=y
|
||||
# CONFIG_LWIP_USING_DHCPD is not set
|
||||
# CONFIG_RT_LWIP_DEBUG is not set
|
||||
# CONFIG_RT_USING_AT is not set
|
||||
|
||||
#
|
||||
@@ -640,10 +751,14 @@ CONFIG_SOC_SAME54P20=y
|
||||
#
|
||||
CONFIG_SAME5X_CAN0=y
|
||||
CONFIG_SAME5X_ADC0=y
|
||||
CONFIG_SAME5X_I2C0=y
|
||||
CONFIG_SAME5X_GMAC=y
|
||||
|
||||
#
|
||||
# Application Demo Config
|
||||
#
|
||||
CONFIG_SAM_CAN_EXAMPLE=y
|
||||
CONFIG_SAM_ADC_EXAMPLE=y
|
||||
CONFIG_SAM_I2C_EXAMPLE=y
|
||||
CONFIG_SAM_LWIP_EXAMPLE=y
|
||||
CONFIG_SOC_SAME54=y
|
||||
|
||||
@@ -34,8 +34,27 @@ if rtconfig.PLATFORM == 'iar':
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/common'):
|
||||
common_path_prefix = SDK_ROOT + '/common'
|
||||
else:
|
||||
common_path_prefix = os.path.dirname(SDK_ROOT) + '/common'
|
||||
|
||||
SDK_LIB = common_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
sam_board = 'board'
|
||||
rtconfig.BSP_LIBRARY_TYPE = sam_board
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(common_path_prefix, sam_board, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(common_path_prefix, 'applications', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#ifndef __APPLICATION_CAN_H_
|
||||
#define __APPLICATION_CAN_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @brief External function definitions
|
||||
*
|
||||
*/
|
||||
rt_err_t can_demo_run(void);
|
||||
|
||||
rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
|
||||
|
||||
#endif // __APPLICATION_CAN_H_
|
||||
@@ -5,7 +5,7 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
* 2022-04-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
@@ -22,6 +22,18 @@
|
||||
#include "can_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef SAM_I2C_EXAMPLE
|
||||
#include "i2c_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef SAM_ADC_EXAMPLE
|
||||
#include "adc_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef SAM_LWIP_EXAMPLE
|
||||
#include "lwip_demo.h"
|
||||
#endif
|
||||
|
||||
static rt_uint8_t led_stack[ 512 ];
|
||||
static struct rt_thread led_thread;
|
||||
|
||||
@@ -63,6 +75,18 @@ int main(void)
|
||||
can_demo_run();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_I2C_EXAMPLE
|
||||
i2c_demo_run();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_ADC_EXAMPLE
|
||||
adc_demo_run();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_LWIP_EXAMPLE
|
||||
lwip_demo_run();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -32,6 +32,14 @@ menu "Onboard Peripheral Drivers"
|
||||
config SAME5X_ADC0
|
||||
bool "Enable ADC0"
|
||||
default false
|
||||
|
||||
config SAME5X_I2C0
|
||||
bool "Enable I2C0"
|
||||
default false
|
||||
|
||||
config SAME5X_GMAC
|
||||
bool "Enable GMAC"
|
||||
default false
|
||||
endmenu
|
||||
|
||||
menu "Application Demo Config"
|
||||
@@ -49,4 +57,18 @@ menu "Application Demo Config"
|
||||
help
|
||||
Add ADC example task to project
|
||||
|
||||
config SAM_I2C_EXAMPLE
|
||||
bool "Enable SAM I2C Example"
|
||||
depends on SAME5X_I2C0
|
||||
default true
|
||||
help
|
||||
Add I2C example task to project
|
||||
|
||||
config SAM_LWIP_EXAMPLE
|
||||
bool "Enable SAM LWIP Example"
|
||||
depends on SAME5X_GMAC
|
||||
default false
|
||||
help
|
||||
Add GMAC LWIP example task to project
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -21,17 +21,20 @@ extern int rt_hw_uart_init(void);
|
||||
#endif
|
||||
|
||||
static struct io_descriptor* g_stdio;
|
||||
static uint8_t board_info[16] = "Microchip SAME54";
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
io_write(g_stdio, (uint8_t *)str, strlen(str));
|
||||
while (TARGET_IO.stat != 0);
|
||||
}
|
||||
RTM_EXPORT(rt_hw_console_output);
|
||||
|
||||
static inline void hw_board_init_usart(void)
|
||||
{
|
||||
usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
|
||||
usart_sync_enable(&TARGET_IO);
|
||||
usart_async_get_io_descriptor(&TARGET_IO, &g_stdio);
|
||||
usart_async_enable(&TARGET_IO);
|
||||
io_write(g_stdio, board_info, 16);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -1,199 +0,0 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <atmel_start.h>
|
||||
|
||||
/* SAM MCU serial device */
|
||||
static struct rt_serial_device sam_serial;
|
||||
|
||||
/**
|
||||
* @brief Configure serial port
|
||||
*
|
||||
* This function will configure UART baudrate, parity and so on.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
usart_sync_disable(desc);
|
||||
|
||||
/* Set baudrate */
|
||||
usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
|
||||
|
||||
/* Set stop bit */
|
||||
if (cfg->stop_bits == STOP_BITS_1)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
|
||||
else if (cfg->stop_bits == STOP_BITS_2)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
|
||||
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
|
||||
|
||||
/* Set character size */
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_5:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
|
||||
break;
|
||||
case DATA_BITS_6:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
|
||||
break;
|
||||
case DATA_BITS_9:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
usart_sync_set_parity(desc, USART_PARITY_NONE);
|
||||
else if (cfg->parity == PARITY_ODD)
|
||||
usart_sync_set_parity(desc, USART_PARITY_ODD);
|
||||
else if (cfg->parity == PARITY_EVEN)
|
||||
usart_sync_set_parity(desc, USART_PARITY_EVEN);
|
||||
|
||||
usart_sync_enable(desc);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control serial port
|
||||
*
|
||||
* This function provide UART enable/disable control.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
usart_sync_disable(desc);
|
||||
break;
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
usart_sync_enable(desc);
|
||||
break;
|
||||
/* UART config */
|
||||
case RT_DEVICE_CTRL_CONFIG :
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial sends a char
|
||||
*
|
||||
* This function will send a char to the UART
|
||||
*
|
||||
* @return 1.
|
||||
*/
|
||||
static int serial_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
io_write(&desc->io, (const uint8_t *)&c, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial gets a char
|
||||
*
|
||||
* This function will get a char from the UART
|
||||
*
|
||||
* @return received char character or -1 if no char received.
|
||||
*/
|
||||
static int serial_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
char c;
|
||||
int ch;
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
ch = -1;
|
||||
if (usart_sync_is_rx_not_empty(desc))
|
||||
{
|
||||
io_read(&desc->io, (uint8_t *)&c, 1);;
|
||||
ch = c & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops sam_serial_ops =
|
||||
{
|
||||
serial_configure,
|
||||
serial_control,
|
||||
serial_putc,
|
||||
serial_getc,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART
|
||||
*
|
||||
* This function initialize the UART
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
sam_serial.ops = &sam_serial_ops;
|
||||
sam_serial.config = config;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
rt_hw_serial_register(&sam_serial, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -42,18 +42,24 @@
|
||||
<description>Atmel Start Framework</description>
|
||||
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||
<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/aes_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/mac_async.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_aes_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_mac_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
|
||||
@@ -69,6 +75,7 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_mac_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
|
||||
@@ -81,8 +88,10 @@
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_mac_async.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
|
||||
@@ -93,9 +102,11 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
|
||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
|
||||
@@ -136,6 +147,10 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/ethernet_phy.rst"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ieee8023_mii_standard_register.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/aes_demo.rst"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||
@@ -143,7 +158,10 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
@@ -153,8 +171,11 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/aes/hpl_aes.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
|
||||
@@ -165,6 +186,7 @@
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gmac/hpl_gmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
|
||||
@@ -173,24 +195,30 @@
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_aes_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/ieee8023_mii_standard_config.h"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/aes"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
|
||||
@@ -206,6 +234,9 @@
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="ethernet_phy"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
@@ -11,14 +11,17 @@ CPPDEFINES = []
|
||||
CPPDEFINES += [rtconfig.DEVICE_TYPE]
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Glob('hal/src/*.c')
|
||||
src += Glob('hal/utils/src/*.c')
|
||||
src += Glob('hpl/adc/*.c')
|
||||
src += Glob('hpl/aes/*.c')
|
||||
src += Glob('hpl/can/*.c')
|
||||
src += Glob('hpl/cmcc/*.c')
|
||||
src += Glob('hpl/core/*.c')
|
||||
src += Glob('hpl/dmac/*.c')
|
||||
src += Glob('hpl/gclk/*.c')
|
||||
src += Glob('hpl/gmac/*.c')
|
||||
src += Glob('hpl/mclk/*.c')
|
||||
src += Glob('hpl/osc32kctrl/*.c')
|
||||
src += Glob('hpl/oscctrl/*.c')
|
||||
@@ -26,8 +29,10 @@ src += Glob('hpl/pm/*.c')
|
||||
src += Glob('hpl/port/*.c')
|
||||
src += Glob('hpl/ramecc/*.c')
|
||||
src += Glob('hpl/sercom/*.c')
|
||||
src += Glob('ethernet_phy/*.c')
|
||||
src += [cwd + '/atmel_start.c']
|
||||
src += [cwd + '/driver_init.c']
|
||||
src += [cwd + '/ethernet_phy_main.c']
|
||||
|
||||
#add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
@@ -44,15 +49,19 @@ path = [
|
||||
cwd,
|
||||
cwd + '/CMSIS/Core/Include',
|
||||
cwd + '/config',
|
||||
cwd + '/ethernet_phy',
|
||||
cwd + '/hal/include',
|
||||
cwd + '/hal/utils/include',
|
||||
cwd + '/hpl/adc',
|
||||
cwd + '/hpl/can',
|
||||
cwd + '/hpl/core',
|
||||
cwd + '/hpl/gclk',
|
||||
cwd + '/hpl/pm',
|
||||
cwd + '/hpl/port',
|
||||
cwd + '/hri',
|
||||
cwd + '/include',]
|
||||
cwd + '/include',
|
||||
cwd + '/../board',
|
||||
cwd + '/../../common/applications']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -6,4 +6,5 @@
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
ethernet_phys_init();
|
||||
}
|
||||
|
||||
@@ -6,6 +6,7 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#include "driver_init.h"
|
||||
#include "ethernet_phy_main.h"
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -27,10 +27,23 @@
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define PA02 GPIO(GPIO_PORTA, 2)
|
||||
#define PA12 GPIO(GPIO_PORTA, 12)
|
||||
#define PA13 GPIO(GPIO_PORTA, 13)
|
||||
#define PA14 GPIO(GPIO_PORTA, 14)
|
||||
#define PA15 GPIO(GPIO_PORTA, 15)
|
||||
#define PA17 GPIO(GPIO_PORTA, 17)
|
||||
#define PA18 GPIO(GPIO_PORTA, 18)
|
||||
#define PA19 GPIO(GPIO_PORTA, 19)
|
||||
#define PB12 GPIO(GPIO_PORTB, 12)
|
||||
#define PB13 GPIO(GPIO_PORTB, 13)
|
||||
#define PB24 GPIO(GPIO_PORTB, 24)
|
||||
#define PB25 GPIO(GPIO_PORTB, 25)
|
||||
#define PC11 GPIO(GPIO_PORTC, 11)
|
||||
#define PC12 GPIO(GPIO_PORTC, 12)
|
||||
#define LED0 GPIO(GPIO_PORTC, 18)
|
||||
#define PC20 GPIO(GPIO_PORTC, 20)
|
||||
#define PD08 GPIO(GPIO_PORTD, 8)
|
||||
#define PD09 GPIO(GPIO_PORTD, 9)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -69,7 +69,7 @@
|
||||
// <e> Advanced configuration
|
||||
// <id> usart_advanced
|
||||
#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
|
||||
#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
@@ -273,6 +273,141 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
|
||||
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
|
||||
#endif
|
||||
|
||||
#ifndef CONF_SERCOM_7_I2CM_ENABLE
|
||||
#define CONF_SERCOM_7_I2CM_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <h> Basic
|
||||
|
||||
// <o> I2C Bus clock speed (Hz) <1-400000>
|
||||
// <i> I2C Bus clock (SCL) speed measured in Hz
|
||||
// <id> i2c_master_baud_rate
|
||||
#ifndef CONF_SERCOM_7_I2CM_BAUD
|
||||
#define CONF_SERCOM_7_I2CM_BAUD 100000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced
|
||||
// <id> i2c_master_advanced
|
||||
#ifndef CONF_SERCOM_7_I2CM_ADVANCED_CONFIG
|
||||
#define CONF_SERCOM_7_I2CM_ADVANCED_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <o> TRise (ns) <0-300>
|
||||
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
|
||||
// <i> Standard Fast Mode: typical 215ns, max 300ns
|
||||
// <i> Fast Mode +: typical 60ns, max 100ns
|
||||
// <i> High Speed Mode: typical 20ns, max 40ns
|
||||
// <id> i2c_master_arch_trise
|
||||
|
||||
#ifndef CONF_SERCOM_7_I2CM_TRISE
|
||||
#define CONF_SERCOM_7_I2CM_TRISE 215
|
||||
#endif
|
||||
|
||||
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
|
||||
// <i> This enables the master SCL low extend time-out
|
||||
// <id> i2c_master_arch_mexttoen
|
||||
#ifndef CONF_SERCOM_7_I2CM_MEXTTOEN
|
||||
#define CONF_SERCOM_7_I2CM_MEXTTOEN 1
|
||||
#endif
|
||||
|
||||
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
|
||||
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
|
||||
// <id> i2c_master_arch_sexttoen
|
||||
#ifndef CONF_SERCOM_7_I2CM_SEXTTOEN
|
||||
#define CONF_SERCOM_7_I2CM_SEXTTOEN 0
|
||||
#endif
|
||||
|
||||
// <q> SCL Low Time-Out (LOWTOUT)
|
||||
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
|
||||
// <id> i2c_master_arch_lowtout
|
||||
#ifndef CONF_SERCOM_7_I2CM_LOWTOUT
|
||||
#define CONF_SERCOM_7_I2CM_LOWTOUT 1
|
||||
#endif
|
||||
|
||||
// <o> Inactive Time-Out (INACTOUT)
|
||||
// <0x0=>Disabled
|
||||
// <0x1=>5-6 SCL cycle time-out(50-60us)
|
||||
// <0x2=>10-11 SCL cycle time-out(100-110us)
|
||||
// <0x3=>20-21 SCL cycle time-out(200-210us)
|
||||
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
|
||||
// <id> i2c_master_arch_inactout
|
||||
#ifndef CONF_SERCOM_7_I2CM_INACTOUT
|
||||
#define CONF_SERCOM_7_I2CM_INACTOUT 0x3
|
||||
#endif
|
||||
|
||||
// <o> SDA Hold Time (SDAHOLD)
|
||||
// <0=>Disabled
|
||||
// <1=>50-100ns hold time
|
||||
// <2=>300-600ns hold time
|
||||
// <3=>400-800ns hold time
|
||||
// <i> Defines the SDA hold time with respect to the negative edge of SCL
|
||||
// <id> i2c_master_arch_sdahold
|
||||
#ifndef CONF_SERCOM_7_I2CM_SDAHOLD
|
||||
#define CONF_SERCOM_7_I2CM_SDAHOLD 0x2
|
||||
#endif
|
||||
|
||||
// <q> Run in stand-by
|
||||
// <i> Determine if the module shall run in standby sleep mode
|
||||
// <id> i2c_master_arch_runstdby
|
||||
#ifndef CONF_SERCOM_7_I2CM_RUNSTDBY
|
||||
#define CONF_SERCOM_7_I2CM_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Debug Stop Mode
|
||||
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
|
||||
// <0=>Keep running
|
||||
// <1=>Halt
|
||||
// <id> i2c_master_arch_dbgstop
|
||||
#ifndef CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE
|
||||
#define CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
#ifndef CONF_SERCOM_7_I2CM_SPEED
|
||||
#define CONF_SERCOM_7_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
|
||||
#endif
|
||||
#if CONF_SERCOM_7_I2CM_TRISE < 215 || CONF_SERCOM_7_I2CM_TRISE > 300
|
||||
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
|
||||
#undef CONF_SERCOM_7_I2CM_TRISE
|
||||
#define CONF_SERCOM_7_I2CM_TRISE 215U
|
||||
#endif
|
||||
|
||||
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
|
||||
// BAUD + BAUDLOW = --------------------------------------------------------------------
|
||||
// i2c_scl_freq
|
||||
// BAUD: register value low [7:0]
|
||||
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
|
||||
#define CONF_SERCOM_7_I2CM_BAUD_BAUDLOW \
|
||||
(((CONF_GCLK_SERCOM7_CORE_FREQUENCY - (CONF_SERCOM_7_I2CM_BAUD * 10U) \
|
||||
- (CONF_SERCOM_7_I2CM_TRISE * (CONF_SERCOM_7_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM7_CORE_FREQUENCY / 10000U) \
|
||||
/ 1000U)) \
|
||||
* 10U \
|
||||
+ 5U) \
|
||||
/ (CONF_SERCOM_7_I2CM_BAUD * 10U))
|
||||
#ifndef CONF_SERCOM_7_I2CM_BAUD_RATE
|
||||
#if CONF_SERCOM_7_I2CM_BAUD_BAUDLOW > (0xFF * 2)
|
||||
#warning Requested I2C baudrate too low, please check
|
||||
#define CONF_SERCOM_7_I2CM_BAUD_RATE 0xFF
|
||||
#elif CONF_SERCOM_7_I2CM_BAUD_BAUDLOW <= 1
|
||||
#warning Requested I2C baudrate too high, please check
|
||||
#define CONF_SERCOM_7_I2CM_BAUD_RATE 1
|
||||
#else
|
||||
#define CONF_SERCOM_7_I2CM_BAUD_RATE \
|
||||
((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW & 0x1) \
|
||||
? (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
|
||||
: (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SERCOM_CONFIG_H
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
/* Auto-generated config file ieee8023_mii_standard_config.h */
|
||||
#ifndef IEEE8023_MII_STANDARD_CONFIG_H
|
||||
#define IEEE8023_MII_STANDARD_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic configuration
|
||||
|
||||
// <o> PHY Address <0-31>
|
||||
// <i> The PHY Address is five bits, allowing 32 unique PHY addresses. A PHY
|
||||
// <i> that is connected to the station management entity via the mechanical
|
||||
// <i> interface defined in IEEE 802.3 22.6 shall always respond to
|
||||
// <i> transactions addressed to PHY Address zero b00000. A station management
|
||||
// <i> entity that is attached to multiple PHYs must have prior knowledge of
|
||||
// <i> the appropriate PHY Address for each PHY.
|
||||
// <id> ieee8023_mii_phy_address
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Control Register (Register 0) Settings
|
||||
// <i> The MII Management Interface Control Register (Register 0) Setting.
|
||||
// <i> Full details about the can be found in Clause 22.2.4 of the IEEE 802.3
|
||||
// <i> Specification.
|
||||
// <id> ieee8023_mii_control_reg0_setting
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING 1
|
||||
#endif
|
||||
|
||||
// <q> Loopback Enable
|
||||
// <i> Set PHY be placed in a loopback mode of operation.
|
||||
// <id> ieee8023_mii_control_loopback_en
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN 0
|
||||
#endif
|
||||
|
||||
// <o> Speed Selection
|
||||
// <i> These bits select the PHY speed.
|
||||
// <0x0=> 10 Mb/s
|
||||
// <0x1=> 100 Mb/s
|
||||
// <0x2=> 1000 Mb/s
|
||||
// <id> ieee8023_mii_control_speed_lsb
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED 1
|
||||
#endif
|
||||
|
||||
// <q> Auto-Negotiation Enable
|
||||
// <i> Indicates whether the Auto-Negotiation enable or not
|
||||
// <id> ieee8023_mii_control_autoneg_en
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN 1
|
||||
#endif
|
||||
|
||||
// <q> Power Down Enable
|
||||
// <i> Set PHY in a low-power consumption state, The specific behavior of a
|
||||
// <i> PHY in the power-down state is implementation specific. While in the
|
||||
// <i> power-down state, the PHY shall respond to management transactions.
|
||||
// <i> During the transition to the power-down state and while in the
|
||||
// <i> power-down state, the PHY shall not generate spurious signals on the
|
||||
// <i> MII or GMII.
|
||||
// <id> ieee8023_mii_control_powerdown_en
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN 0
|
||||
#endif
|
||||
|
||||
// <q> Isolate Enable
|
||||
// <i> Set PHY forced to electrically isolate its data paths from the MII or
|
||||
// <i> GMII. When the PHY is isolated from the MII or GMII it shall not
|
||||
// <i> respond to the TXD data bundle, TX_EN, TX_ER and GTX_CLK inputs, and it
|
||||
// <i> shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD
|
||||
// <i> data bundle, COL, and CRS outputs. When the PHY is isolated from the
|
||||
// <i> MII or GMII it shall respond to management transactions.
|
||||
// <id> ieee8023_mii_control_isolate_en
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN 0
|
||||
#endif
|
||||
|
||||
// <o> Duplex Mode Selection
|
||||
// <i> The duplex mode can be selected via either the Auto-Negotiation enable,
|
||||
// <i> or manual duplex selection. Manual duplex selection is allowed when
|
||||
// <i> Auto-Negotiation is disabled. When Auto-Negotiation is enabled, this
|
||||
// <i> setting has no effect on the link configuration.
|
||||
// <0x0=> half duplex
|
||||
// <0x1=> full duplex
|
||||
// <id> ieee8023_mii_control_duplex_mode
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE 1
|
||||
#endif
|
||||
|
||||
#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0
|
||||
#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0 \
|
||||
(CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN ? MDIO_REG0_BIT_RESET : 0) \
|
||||
| ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x1) ? MDIO_REG0_BIT_SPEED_SELECT_LSB : 0) \
|
||||
| ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x2) ? MDIO_REG0_BIT_SPEED_SELECT_MSB : 0) \
|
||||
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN ? MDIO_REG0_BIT_AUTONEG : 0) \
|
||||
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN ? MDIO_REG0_BIT_POWER_DOWN : 0) \
|
||||
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN ? MDIO_REG0_BIT_ISOLATE : 0) \
|
||||
| (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE ? MDIO_REG0_BIT_DUPLEX_MODE : 0)
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // IEEE8023_MII_STANDARD_CONFIG_H
|
||||
@@ -4,6 +4,46 @@
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <y> ADC Clock Source
|
||||
// <id> adc_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for ADC.
|
||||
#ifndef CONF_GCLK_ADC0_SRC
|
||||
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_ADC0_FREQUENCY
|
||||
* \brief ADC0's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_ADC0_FREQUENCY
|
||||
#define CONF_GCLK_ADC0_FREQUENCY 120000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
@@ -92,6 +132,86 @@
|
||||
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 3000000
|
||||
#endif
|
||||
|
||||
// <y> Core Clock Source
|
||||
// <id> core_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for CORE.
|
||||
#ifndef CONF_GCLK_SERCOM7_CORE_SRC
|
||||
#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
// <y> Slow Clock Source
|
||||
// <id> slow_gclk_selection
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the slow clock source.
|
||||
#ifndef CONF_GCLK_SERCOM7_SLOW_SRC
|
||||
#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM7_CORE_FREQUENCY
|
||||
* \brief SERCOM7's Core Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 40000000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY
|
||||
* \brief SERCOM7's Slow Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY
|
||||
#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 3000000
|
||||
#endif
|
||||
|
||||
// <y> CAN1 Clock Source
|
||||
// <id> can_gclk_selection
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
======================================
|
||||
Generic IEEE 802.3 Ethernet PHY Driver
|
||||
======================================
|
||||
|
||||
This software component supply a generic IEEE802.3 Ethernet PHY driver.
|
||||
The PHY chip should be compliant IEEE 802.3 Ethernet Standard that
|
||||
supports MDC/MDIO management interface for PHY register configuration.
|
||||
|
||||
The management interface specified here provides a simple, two-wire, serial
|
||||
interface to connect a management entity and a managed PHY for the purposes of
|
||||
controlling the PHY and gathering status from the PHY. This interface is
|
||||
referred to as the MII Management Interface.
|
||||
|
||||
The management interface consists of a pair of signals that physically
|
||||
transport the management information across the MII or GMII, a frame format
|
||||
and a protocol specification for exchanging management frames, and a register
|
||||
set that can be read and written using these frames. The register definition
|
||||
specifies a basic register set with an extension mechanism. The MII uses two
|
||||
basic registers. The GMII also uses the same two basic registers and adds a
|
||||
third basic register.
|
||||
|
||||
The MII basic register set consists of two registers referred to as the Control
|
||||
register (Register 0) and the Status register (Register 1). All PHYs that
|
||||
provide an MII shall incorporate the basic register set. All PHYs that provide
|
||||
a GMII shall incorporate an extended basic register set consisting of the
|
||||
Control register (Register 0), Status register (Register 1), and Extended
|
||||
Status register (Register 15). The status and control functions defined here
|
||||
are considered basic and fundamental to 100 Mb/s and 1000 Mb/s PHYs.
|
||||
Registers 2 through 14 are part of the extended register set. The format of
|
||||
Registers 4 through 10 are defined for the specific Auto-Negotiation protocol
|
||||
used (Clause 28 or Clause 37). The format of these registers is selected by
|
||||
the bit settings of Registers 1 and 15.
|
||||
More information please refer to IEEE Std 802.3 Chapter 22.2.4
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization the Ethernet PHY driver with Ethernet MAC communication
|
||||
* Setting PHY address
|
||||
* Reading/Writing register from PHY device
|
||||
* Setting/Clearing register bit from PHY device
|
||||
* Enabling/Disabling Power Down
|
||||
* Restart Auto Negotiation
|
||||
* Enabling/Disabling Loop Back
|
||||
* Getting Link Status
|
||||
* Reset PHY device
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
* An instance of the Ethernet MAC driver is used by this driver.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
N/A
|
||||
File diff suppressed because it is too large
Load Diff
@@ -21,20 +21,42 @@ extern "C" {
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_adc_sync.h>
|
||||
#include <hal_aes_sync.h>
|
||||
|
||||
#include <hal_usart_sync.h>
|
||||
#include <hal_usart_async.h>
|
||||
|
||||
#include <hal_i2c_m_sync.h>
|
||||
#include <hal_can_async.h>
|
||||
|
||||
extern struct aes_sync_descriptor CRYPTOGRAPHY_0;
|
||||
#include <hal_mac_async.h>
|
||||
|
||||
extern struct usart_sync_descriptor TARGET_IO;
|
||||
extern struct can_async_descriptor CAN_0;
|
||||
extern struct adc_sync_descriptor ADC_0;
|
||||
extern struct aes_sync_descriptor CRYPTOGRAPHY_0;
|
||||
extern struct usart_async_descriptor TARGET_IO;
|
||||
|
||||
extern struct i2c_m_sync_desc I2C_0;
|
||||
extern struct can_async_descriptor CAN_0;
|
||||
|
||||
extern struct mac_async_descriptor MACIF;
|
||||
|
||||
void ADC_0_PORT_init(void);
|
||||
void ADC_0_CLOCK_init(void);
|
||||
void ADC_0_init(void);
|
||||
|
||||
void TARGET_IO_PORT_init(void);
|
||||
void TARGET_IO_CLOCK_init(void);
|
||||
void TARGET_IO_init(void);
|
||||
|
||||
void I2C_0_CLOCK_init(void);
|
||||
void I2C_0_init(void);
|
||||
void I2C_0_PORT_init(void);
|
||||
|
||||
void MACIF_CLOCK_init(void);
|
||||
void MACIF_init(void);
|
||||
void MACIF_PORT_init(void);
|
||||
void MACIF_example(void);
|
||||
|
||||
/**
|
||||
* \brief Perform system initialization, initialize pins and clocks for
|
||||
* peripherals
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Ethernet PHY functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <ethernet_phy.h>
|
||||
#include <utils_assert.h>
|
||||
/**
|
||||
* \brief Perform a HW initialization to the PHY
|
||||
*/
|
||||
int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
|
||||
uint16_t addr)
|
||||
{
|
||||
ASSERT(descr && mac && (addr <= 0x1F));
|
||||
|
||||
descr->mac = mac;
|
||||
descr->addr = addr;
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set PHY address
|
||||
*/
|
||||
int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr)
|
||||
{
|
||||
ASSERT(descr && (addr <= 0x1F));
|
||||
|
||||
descr->addr = addr;
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Read PHY Register value.
|
||||
*/
|
||||
int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val)
|
||||
{
|
||||
ASSERT(descr && descr->mac && (reg <= 0x1F) && val);
|
||||
|
||||
return mac_async_read_phy_reg(descr->mac, descr->addr, reg, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Write PHY Register value.
|
||||
*/
|
||||
int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val)
|
||||
{
|
||||
ASSERT(descr && descr->mac && (reg <= 0x1F));
|
||||
return mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Setting bit for a PHY Register
|
||||
*/
|
||||
int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
|
||||
{
|
||||
int32_t rst;
|
||||
uint16_t val;
|
||||
|
||||
ASSERT(descr && descr->mac && (reg <= 0x1F));
|
||||
|
||||
rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
|
||||
if (rst == ERR_NONE) {
|
||||
val |= ofst;
|
||||
rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
|
||||
}
|
||||
return rst;
|
||||
}
|
||||
/**
|
||||
* \brief Clear bit for a PHY Register
|
||||
*/
|
||||
int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
|
||||
{
|
||||
int32_t rst;
|
||||
uint16_t val;
|
||||
|
||||
ASSERT(descr && (reg <= 0x1F));
|
||||
|
||||
rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
|
||||
if (rst == ERR_NONE) {
|
||||
val &= ~ofst;
|
||||
rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
|
||||
}
|
||||
return rst;
|
||||
}
|
||||
/**
|
||||
* \brief Set PHY low-power consumption state.
|
||||
*/
|
||||
int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state)
|
||||
{
|
||||
ASSERT(descr);
|
||||
if (state) {
|
||||
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
|
||||
} else {
|
||||
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set PHY electrically isolate state.
|
||||
*/
|
||||
int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state)
|
||||
{
|
||||
ASSERT(descr);
|
||||
if (state) {
|
||||
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
|
||||
} else {
|
||||
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Restart an auto negotiation of the PHY.
|
||||
*/
|
||||
int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESTART_AUTONEG);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set PHY placed in a loopback mode of operation.
|
||||
*/
|
||||
int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state)
|
||||
{
|
||||
ASSERT(descr);
|
||||
if (state) {
|
||||
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
|
||||
} else {
|
||||
return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get PHY link status
|
||||
*/
|
||||
int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status)
|
||||
{
|
||||
int32_t rst;
|
||||
uint16_t val;
|
||||
|
||||
ASSERT(descr && descr->mac && status);
|
||||
rst = mac_async_read_phy_reg(descr->mac, descr->addr, MDIO_REG1_BMSR, &val);
|
||||
if (rst == ERR_NONE) {
|
||||
*status = (val & MDIO_REG1_BIT_LINK_STATUS) ? true : false;
|
||||
}
|
||||
return rst;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Reset PHY.
|
||||
*/
|
||||
int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESET);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,137 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief IEEE802.3 MII Management Standard Register Set
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ETHERNET_MII_REGISTER_H_INCLUDED
|
||||
#define ETHERNET_MII_REGISTER_H_INCLUDED
|
||||
|
||||
/* IEEE 802.3 Clause22.2.4 defined Standard Registers.
|
||||
* The MII basic register set consists of two registers referred to as the
|
||||
* Control register (Register 0) and the Status register (Register 1). All
|
||||
* PHYs that provide an MII shall incorporate the basic register set. All PHYs
|
||||
* that provide a GMII shall incorporate an extended basic register set
|
||||
* consisting of the Control register (Register 0), Status register
|
||||
* (Register 1), and Extended Status register (Register 15). The status and
|
||||
* control functions defined here are considered basic and fundamental to
|
||||
* 100 Mb/s and 1000 Mb/s PHYs. Registers 2 through 14 are part of the
|
||||
* extended register set. The format of Registers 4 through 10 are defined for
|
||||
* the specific Auto-Negotiation protocol used (Clause 28 or Clause 37). The
|
||||
* format of these registers is selected by the bit settings of Registers 1
|
||||
* and 15.
|
||||
**/
|
||||
#define MDIO_REG0_BMCR 0x00 /* Basic Control */
|
||||
#define MDIO_REG1_BMSR 0x01 /* Basic Status */
|
||||
#define MDIO_REG2_PHYID1 0x02 /* PHY Idendifier 1 */
|
||||
#define MDIO_REG3_PHYID2 0x03 /* PHY Idendifier 2 */
|
||||
#define MDIO_REG4_ANA 0x04 /* Auto_Negotiation Advertisement */
|
||||
#define MDIO_REG5_ANLPA 0x05 /* Auto_negotiation Link Partner Base Page Ability */
|
||||
#define MDIO_REG6_ANE 0x06 /* Auto-negotiation Expansion */
|
||||
#define MDIO_REG7_ANNPT 0x07 /* Auto-negotiation Next Page Transmit */
|
||||
#define MDIO_REG8_ANLPRNP 0x08 /* Auto-Negotiation Link Partner Received Next Page */
|
||||
#define MDIO_REG9_MSC 0x09 /* MASTER-SLAVE Control Register */
|
||||
#define MDIO_REG10_MSS 0x0A /* MASTER-SLAVE Status Register */
|
||||
#define MDIO_REG11_PSEC 0x0B /* PSE Control Register */
|
||||
#define MDIO_REG12_PSES 0x0C /* PSE Status Register */
|
||||
#define MDIO_REG13_MMDAC 0x0D /* MMD Access Control Register */
|
||||
#define MDIO_REG14_MMDAAD 0x0E /* MMD Access Address Data Register */
|
||||
#define MDIO_REG15_EXTS 0x0F /* Extended Status */
|
||||
/* Register 16 to 31 are Reserved for Vendor Specific */
|
||||
|
||||
/* Bit definitions: MDIO_REG0_BMCR 0x00 Basic Control */
|
||||
#define MDIO_REG0_BIT_RESET (1 << 15) /* 1 = Software Reset; 0 = Normal Operation */
|
||||
#define MDIO_REG0_BIT_LOOPBACK (1 << 14) /* 1 = loopback Enabled; 0 = Normal Operation */
|
||||
#define MDIO_REG0_BIT_SPEED_SELECT_LSB (1 << 13) /* 1 = 100Mbps; 0=10Mbps */
|
||||
#define MDIO_REG0_BIT_AUTONEG (1 << 12) /* 1 = Auto-negotiation Enable */
|
||||
#define MDIO_REG0_BIT_POWER_DOWN (1 << 11) /* 1 = Power down 0=Normal operation */
|
||||
#define MDIO_REG0_BIT_ISOLATE (1 << 10) /* 1 = Isolates 0 = Normal operation */
|
||||
#define MDIO_REG0_BIT_RESTART_AUTONEG (1 << 9) /* 1 = Restart auto-negotiation 0 = Normal operation */
|
||||
#define MDIO_REG0_BIT_DUPLEX_MODE (1 << 8) /* 1 = Full duplex operation 0 = Normal operation */
|
||||
#define MDIO_REG0_BIT_COLLISION_TEST (1 << 7) /* 1 = Enable COL test; 0 = Disable COL test */
|
||||
#define MDIO_REG0_BIT_SPEED_SELECT_MSB (1 << 6) /* 1 with LSB0 = 1000Mbps */
|
||||
#define MDIO_REG0_BIT_UNIDIR_ENABLE (1 << 5) /* Unidirectional Enable */
|
||||
/* Reserved 4 to 0 Read as 0, ignore on write */
|
||||
|
||||
/* Bit definitions: MDIO_BMSR 0x01 Basic Status */
|
||||
#define MDIO_REG1_BIT_100BASE_T4 (1 << 15) /* 100BASE-T4 Capable */
|
||||
#define MDIO_REG1_BIT_100BASE_TX_FD (1 << 14) /* 100BASE-TX Full Duplex Capable */
|
||||
#define MDIO_REG1_BIT_100BASE_TX_HD (1 << 13) /* 100BASE-TX Half Duplex Capable */
|
||||
#define MDIO_REG1_BIT_10BASE_T_FD (1 << 12) /* 10BASE-T Full Duplex Capable */
|
||||
#define MDIO_REG1_BIT_10BASE_T_HD (1 << 11) /* 10BASE-T Half Duplex Capable */
|
||||
#define MDIO_REG1_BIT_100BASE_T2_FD (1 << 10) /* 1000BASE-T2 Full Duplex Capable */
|
||||
#define MDIO_REG1_BIT_100BASE_T2_HD (1 << 9) /* 1000BASE-T2 Half Duplex Capable */
|
||||
#define MDIO_REG1_BIT_EXTEND_STATUS (1 << 8) /* 1 = Extend Status Information In Reg 15 */
|
||||
#define MDIO_REG1_BIT_UNIDIR_ABILITY (1 << 7) /* Unidirectional ability */
|
||||
#define MDIO_REG1_BIT_MF_PREAMB_SUPPR (1 << 6) /* MII Frame Preamble Suppression */
|
||||
#define MDIO_REG1_BIT_AUTONEG_COMP (1 << 5) /* Auto-negotiation Complete */
|
||||
#define MDIO_REG1_BIT_REMOTE_FAULT (1 << 4) /* Remote Fault */
|
||||
#define MDIO_REG1_BIT_AUTONEG_ABILITY (1 << 3) /* Auto Configuration Ability */
|
||||
#define MDIO_REG1_BIT_LINK_STATUS (1 << 2) /* Link Status */
|
||||
#define MDIO_REG1_BIT_JABBER_DETECT (1 << 1) /* Jabber Detect */
|
||||
#define MDIO_REG1_BIT_EXTEND_CAPAB (1 << 0) /* Extended Capability */
|
||||
|
||||
/* Bit definitions: MDIO_PHYID1 0x02 PHY Idendifier 1 */
|
||||
/* Bit definitions: MDIO_PHYID2 0x03 PHY Idendifier 2 */
|
||||
#define MDIO_LSB_MASK 0x3F
|
||||
#define MDIO_OUI_MSB 0x0022
|
||||
#define MDIO_OUI_LSB 0x1572
|
||||
|
||||
/* Bit definitions: MDIO_REG4_ANA 0x04 Auto-Negotiation advertisement */
|
||||
#define MDIO_REG4_BIT_NEXTPAGE (15 << 0) /* Next Page */
|
||||
#define MDIO_REG4_BIT_REMOTE_FAULT (13 << 0) /* Remote Fault */
|
||||
#define MDIO_REG4_BIT_EXT_NEXTPAGE (12 << 0) /* Extended Next Page */
|
||||
|
||||
/* Bit definitions: MDIO_ANAR 0x04 Auto_Negotiation Advertisement */
|
||||
/* Bit definitions: MDIO_ANLPAR 0x05 Auto_negotiation Link Partner Ability */
|
||||
#define MDIO_NP (1 << 15) /* Next page Indication */
|
||||
#define MDIO_RF (1 << 13) /* Remote Fault */
|
||||
#define MDIO_PAUSE_MASK (3 << 10) /* 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) */
|
||||
/* 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) */
|
||||
#define MDIO_100T4 (1 << 9) /* 100BASE-T4 Support */
|
||||
#define MDIO_100TX_FDX (1 << 8) /* 100BASE-TX Full Duplex Support */
|
||||
#define MDIO_100TX_HDX (1 << 7) /* 100BASE-TX Half Duplex Support */
|
||||
#define MDIO_10_FDX (1 << 6) /* 10BASE-T Full Duplex Support */
|
||||
#define MDIO_10_HDX (1 << 5) /* 10BASE-T Half Duplex Support */
|
||||
#define MDIO_AN_IEEE_802_3 0x0001 /* [00001] = IEEE 802.3 */
|
||||
|
||||
/* Bit definitions: MDIO_ANER 0x06 Auto-negotiation Expansion */
|
||||
#define MDIO_PDF (1 << 4) /* Local Device Parallel Detection Fault */
|
||||
#define MDIO_LP_NP_ABLE (1 << 3) /* Link Partner Next Page Able */
|
||||
#define MDIO_NP_ABLE (1 << 2) /* Local Device Next Page Able */
|
||||
#define MDIO_PAGE_RX (1 << 1) /* New Page Received */
|
||||
#define MDIO_LP_AN_ABLE (1 << 0) /* Link Partner Auto-negotiation Able */
|
||||
|
||||
/* Bit definitions: MDIO_PCR1 0x1E PHY Control 1 */
|
||||
#define MDIO_OMI_10BASE_T_HD 0x0001
|
||||
#define MDIO_OMI_100BASE_TX_HD 0x0002
|
||||
#define MDIO_OMI_10BASE_T_FD 0x0005
|
||||
|
||||
#endif /* #ifndef ETHERNET_MII_REGISTER_H_INCLUDED */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file or main.c
|
||||
* to avoid loosing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include <atmel_start.h>
|
||||
#include <ieee8023_mii_standard_config.h>
|
||||
#include <ethernet_phy_main.h>
|
||||
|
||||
struct ethernet_phy_descriptor MACIF_PHY_desc;
|
||||
|
||||
void MACIF_PHY_init(void)
|
||||
{
|
||||
mac_async_enable(&MACIF);
|
||||
ethernet_phy_init(&MACIF_PHY_desc, &MACIF, CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS);
|
||||
#if CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING == 1
|
||||
ethernet_phy_write_reg(&MACIF_PHY_desc, MDIO_REG0_BMCR, CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0);
|
||||
#endif /* CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING */
|
||||
}
|
||||
|
||||
void MACIF_PHY_example(void)
|
||||
{
|
||||
bool link_state;
|
||||
int32_t rst;
|
||||
/* Restart an auto-negotiation */
|
||||
rst = ethernet_phy_restart_autoneg(&MACIF_PHY_desc);
|
||||
while (rst != ERR_NONE) {
|
||||
}
|
||||
|
||||
/* Wait for PHY link up */
|
||||
do {
|
||||
rst = ethernet_phy_get_link_status(&MACIF_PHY_desc, &link_state);
|
||||
} while (rst == ERR_NONE && link_state == true);
|
||||
}
|
||||
|
||||
void ethernet_phys_init(void)
|
||||
{
|
||||
|
||||
MACIF_PHY_init();
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file or main.c
|
||||
* to avoid loosing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ETHERNET_PHY_MAIN_H
|
||||
#define ETHERNET_PHY_MAIN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <ethernet_phy.h>
|
||||
|
||||
extern struct ethernet_phy_descriptor MACIF_PHY_desc;
|
||||
|
||||
void ethernet_phys_init(void);
|
||||
void MACIF_PHY_example(void);
|
||||
|
||||
/**
|
||||
* \brief Ethernet PHY devices
|
||||
*/
|
||||
void ethernet_phys_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ETHERNET_PHY_MAIN_H */
|
||||
@@ -10,6 +10,20 @@
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using ADC_0 to generate waveform.
|
||||
*/
|
||||
void ADC_0_example(void)
|
||||
{
|
||||
uint8_t buffer[2];
|
||||
|
||||
adc_sync_enable_channel(&ADC_0, 0);
|
||||
|
||||
while (1) {
|
||||
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t aes_plain_text[16]
|
||||
= {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a};
|
||||
static uint8_t aes_key[16]
|
||||
@@ -34,14 +48,41 @@ void CRYPTOGRAPHY_0_example(void)
|
||||
|
||||
/**
|
||||
* Example of using TARGET_IO to write "Hello World" using the IO abstraction.
|
||||
*
|
||||
* Since the driver is asynchronous we need to use statically allocated memory for string
|
||||
* because driver initiates transfer and then returns before the transmission is completed.
|
||||
*
|
||||
* Once transfer has been completed the tx_cb function will be called.
|
||||
*/
|
||||
|
||||
static uint8_t example_TARGET_IO[12] = "Hello World!";
|
||||
|
||||
static void tx_cb_TARGET_IO(const struct usart_async_descriptor *const io_descr)
|
||||
{
|
||||
/* Transfer completed */
|
||||
}
|
||||
|
||||
void TARGET_IO_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
usart_sync_get_io_descriptor(&TARGET_IO, &io);
|
||||
usart_sync_enable(&TARGET_IO);
|
||||
|
||||
io_write(io, (uint8_t *)"Hello World!", 12);
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, tx_cb_TARGET_IO);
|
||||
/*usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, rx_cb);
|
||||
usart_async_register_callback(&TARGET_IO, USART_ASYNC_ERROR_CB, err_cb);*/
|
||||
usart_async_get_io_descriptor(&TARGET_IO, &io);
|
||||
usart_async_enable(&TARGET_IO);
|
||||
|
||||
io_write(io, example_TARGET_IO, 12);
|
||||
}
|
||||
|
||||
void I2C_0_example(void)
|
||||
{
|
||||
struct io_descriptor *I2C_0_io;
|
||||
|
||||
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
|
||||
i2c_m_sync_enable(&I2C_0);
|
||||
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
|
||||
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
void CAN_0_tx_callback(struct can_async_descriptor *const descr)
|
||||
|
||||
@@ -12,10 +12,14 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ADC_0_example(void);
|
||||
|
||||
void CRYPTOGRAPHY_0_example(void);
|
||||
|
||||
void TARGET_IO_example(void);
|
||||
|
||||
void I2C_0_example(void);
|
||||
|
||||
void CAN_0_example(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -60,6 +60,31 @@ SECTIONS
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for utest */
|
||||
. = ALIGN(4);
|
||||
__rt_utest_tc_tab_start = .;
|
||||
KEEP(*(UtestTcTab))
|
||||
__rt_utest_tc_tab_end = .;
|
||||
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
======================
|
||||
ADC Synchronous driver
|
||||
======================
|
||||
|
||||
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
|
||||
A reference signal with a known voltage level is quantified into equally
|
||||
sized chunks, each representing a digital value from 0 to the highest number
|
||||
possible with the bit resolution supported by the ADC. The input voltage
|
||||
measured by the ADC is compared against these chunks and the chunk with the
|
||||
closest voltage level defines the digital value that can be used to represent
|
||||
the analog input voltage level.
|
||||
|
||||
Usually an ADC can operate in either differential or single-ended mode.
|
||||
In differential mode two signals (V+ and V-) are compared against each other
|
||||
and the resulting digital value represents the relative voltage level between
|
||||
V+ and V-. This means that if the input voltage level on V+ is lower than on
|
||||
V- the digital value is negative, which also means that in differential
|
||||
mode one bit is lost to the sign. In single-ended mode only V+ is compared
|
||||
against the reference voltage, and the resulting digital value can only be
|
||||
positive, but the full bit-range of the ADC can be used.
|
||||
|
||||
Usually multiple resolutions are supported by the ADC, lower resolution can
|
||||
reduce the conversion time, but lose accuracy.
|
||||
|
||||
Some ADCs has a gain stage on the input lines which can be used to increase the
|
||||
dynamic range. The default gain value is usually x1, which means that the
|
||||
conversion range is from 0V to the reference voltage.
|
||||
Applications can change the gain stage, to increase or reduce the conversion
|
||||
range.
|
||||
|
||||
The window mode allows the conversion result to be compared to a set of
|
||||
predefined threshold values. Applications can use callback function to monitor
|
||||
if the conversion result exceeds predefined threshold value.
|
||||
|
||||
Usually multiple reference voltages are supported by the ADC, both internal and
|
||||
external with difference voltage levels. The reference voltage have an impact
|
||||
on the accuracy, and should be selected to cover the full range of the analog
|
||||
input signal and never less than the expected maximum input voltage.
|
||||
|
||||
There are two conversion modes supported by ADC, single shot and free running.
|
||||
In single shot mode the ADC only make one conversion when triggered by the
|
||||
application, in free running mode it continues to make conversion from it
|
||||
is triggered until it is stopped by the application. When window monitoring,
|
||||
the ADC should be set to free running mode.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Support multiple Conversion Mode, Single or Free run
|
||||
* Start ADC Conversion
|
||||
* Read Conversion Result
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
|
||||
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
|
||||
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* ADC hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
N/A
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
N/A
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
=============================
|
||||
I2C Master synchronous driver
|
||||
=============================
|
||||
|
||||
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
|
||||
for on-board low-speed bi-directional communication between controllers and
|
||||
peripherals. The master device is responsible for initiating and controlling
|
||||
all transfers on the I2C bus. Only one master device can be active on the I2C
|
||||
bus at the time, but the master role can be transferred between devices on the
|
||||
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
|
||||
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
|
||||
resistors.
|
||||
|
||||
The stop condition is automatically controlled by the driver if the I/O write and
|
||||
read functions are used, but can be manually controlled by using the
|
||||
i2c_m_sync_transfer function.
|
||||
|
||||
Often a master accesses different information in the slave by accessing
|
||||
different registers in the slave. This is done by first sending a message to
|
||||
the target slave containing the register address, followed by a repeated start
|
||||
condition (no stop condition between) ending with transferring register data.
|
||||
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
|
||||
function, but limited to 8-bit register addresses.
|
||||
|
||||
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
|
||||
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
|
||||
stick within the SCL clock frequency range supported by the selected mode.
|
||||
The requested SCL clock frequency is not validated by the
|
||||
i2c_m_sync_set_baudrate function against the selected I2C mode.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* I2C Master support
|
||||
* Initialization and de-initialization
|
||||
* Enabling and disabling
|
||||
* Run-time bus speed configuration
|
||||
* Write and read I2C messages
|
||||
* Slave register access functions (limited to 8-bit address)
|
||||
* Manual or automatic stop condition generation
|
||||
* 10- and 7- bit addressing
|
||||
* I2C Modes supported
|
||||
+----------------------+-------------------+
|
||||
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
|
||||
+----------------------+-------------------+
|
||||
|* Fastmode+ | (SCL: 1 - 1000kHz)|
|
||||
+----------------------+-------------------+
|
||||
|* Highspeed mode | (SCL: 1 - 3400kHz)|
|
||||
+----------------------+-------------------+
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
|
||||
* Data communication between micro controllers
|
||||
* Controlling displays
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
* I2C Master capable hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
General
|
||||
^^^^^^^
|
||||
|
||||
* System Managmenet Bus (SMBus) not supported.
|
||||
* Power Management Bus (PMBus) not supported.
|
||||
|
||||
Clock considerations
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
================================
|
||||
Ethernet MAC Asynchronous Driver
|
||||
================================
|
||||
|
||||
The Ethernet MAC driver implements a 10/100 Mbps Ethernet MAC compatible with
|
||||
the IEEE 802.3 standard.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Data transfer: transmission, reception
|
||||
* Enabling/disabling Interrupt
|
||||
* Notifications about transfer completion and frame received via callbacks
|
||||
* Address Filter for Specific 48-bit Addresses and Type ID
|
||||
* Address Filter for Unicast and Multicase Addresses
|
||||
* Reading/writing PHY registers
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
Co-works with thirdpart TCP/IP stacks. E.g., Lwip, Cyclone IP stack.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
MAC capable hardware compatible with the IEEE 802.3 standard.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
+17
-3
@@ -1,9 +1,20 @@
|
||||
The USART Synchronous Driver
|
||||
============================
|
||||
The USART Asynchronous Driver
|
||||
=============================
|
||||
|
||||
The universal synchronous and asynchronous receiver and transmitter
|
||||
(USART) is usually used to transfer data from one device to the other.
|
||||
|
||||
The USART driver use a ring buffer to store received data. When the USART
|
||||
raise the data received interrupt, this data will be stored in the ring buffer
|
||||
at the next free location. When the ring buffer is full, the next reception
|
||||
will overwrite the oldest data stored in the ring buffer. There is one
|
||||
USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
|
||||
is called SERCOM0_USART_BUFFER_SIZE.
|
||||
|
||||
On the other hand, when sending data over USART, the data is not copied to an
|
||||
internal buffer, but the data buffer supplied by the user is used. The callback
|
||||
will only be generated at the end of the buffer and not for each byte.
|
||||
|
||||
User can set action for flow control pins by function usart_set_flow_control,
|
||||
if the flow control is enabled. All the available states are defined in union
|
||||
usart_flow_control_state.
|
||||
@@ -24,6 +35,8 @@ Features
|
||||
* Data order
|
||||
* Flow control
|
||||
* Data transfer: transmission, reception
|
||||
* Notifications about transfer done or error case via callbacks
|
||||
* Status information with busy state and transfer count
|
||||
|
||||
Applications
|
||||
------------
|
||||
@@ -34,7 +47,8 @@ between devices.
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
USART capable hardware.
|
||||
USART capable hardware, with interrupt on each character is sent or
|
||||
received.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user