mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-08-18 20:48:41 +08:00
[BSP] add some bsp drivers for F448, F472 and add bsp test codes
This commit is contained in:
Jamie
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Load Diff
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@@ -64,5 +64,15 @@
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<type>2</type>
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<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/platform</name>
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<type>2</type>
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<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/tests</name>
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<type>2</type>
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<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
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</link>
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</linkedResources>
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</projectDescription>
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@@ -50,35 +50,43 @@ EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下：
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| USB 转串口 | 支持 | 使用 UART2 |
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| LED | 支持 | LED1~4 |
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| **片上外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
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| CAN | 支持 | CAN1、CAN2 |
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| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
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| Hwtimer | 支持 | Hwtimer1~5 |
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| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
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| UART | 支持 | UART1~6<br>UART2为console使用 |
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| **板载外设** | **支持情况** | **备注** |
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|:-------- |:--------:|:--------:|
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| USB 转串口 | 支持 | 使用 UART2 |
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| LED | 支持 | LED1~4 |
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| **片上外设** | **支持情况** | **备注** |
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|:------------- |:--------:|:------------------------------------------:|
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| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
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| DAC | 支持 | |
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| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
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| CAN | 支持 | CAN1、CAN2 |
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| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
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| PM | 支持 | |
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| Lptimer | 支持 | |
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| Hwtimer | 支持 | Hwtimer1~5 |
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| Pulse_encoder | 支持 | |
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| PWM | 支持 | |
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| RTC | 支持 | 闹钟精度为1分钟 |
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| WDT | 支持 | |
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| I2C | 支持 | 软件、硬件 I2C |
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| QSPI | 支持 | |
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| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
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| UART | 支持 | UART1~6<br>UART2为console使用 |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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@@ -120,9 +128,13 @@ msh >
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4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
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## 注意事项
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无
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| 板载外设 | 模式 | 注意事项 |
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| ---- | ---- | ------------------------------------------------------------------------------------------------------ |
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| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
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## 联系人信息
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维护人:
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- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>
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- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
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@@ -56,7 +56,13 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
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objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
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# include platform
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platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
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objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
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# include tests
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test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
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objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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@@ -42,12 +42,17 @@ menu "Onboard Peripheral Drivers"
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select RT_USING_MTD_NOR
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default n
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config BSP_USING_EXT_IO
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bool
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default y
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endmenu
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menu "On-chip Peripheral Drivers"
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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select BSP_USING_TCA9539
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default y
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menuconfig BSP_USING_UART
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@@ -212,12 +217,12 @@ menu "On-chip Peripheral Drivers"
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if BSP_USING_I2C1_SW
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config BSP_I2C1_SCL_PIN
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int "i2c1 scl pin number"
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range 1 176
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default 51
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range 1 80
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default 10
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config BSP_I2C1_SDA_PIN
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int "I2C1 sda pin number"
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range 1 176
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default 90
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range 1 80
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default 9
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endif
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endif
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@@ -368,23 +373,20 @@ menu "On-chip Peripheral Drivers"
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config BSP_USING_DAC1
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bool "using dac1"
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default n
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config BSP_USING_DAC2
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bool "using dac2"
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default n
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endif
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menuconfig BSP_USING_CAN
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bool "Enable CAN"
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menuconfig BSP_USING_MCAN
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bool "Enable MCAN"
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default n
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select RT_USING_CAN
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select RT_CAN_USING_HDR
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select BSP_USING_TCA9539
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if BSP_USING_CAN
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config BSP_USING_CAN1
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bool "using can1"
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if BSP_USING_MCAN
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config BSP_USING_MCAN1
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bool "using mcan1"
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default n
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config BSP_USING_CAN2
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bool "using can2"
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config BSP_USING_MCAN2
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bool "using mcan2"
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default n
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endif
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@@ -418,10 +420,13 @@ menu "On-chip Peripheral Drivers"
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default BSP_RTC_USING_XTAL32
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config BSP_RTC_USING_XTAL32
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bool "RTC USING XTAL32"
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bool "RTC Using XTAL32"
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config BSP_RTC_USING_LRC
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bool "RTC USING LRC"
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bool "RTC Using LRC"
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config BSP_RTC_USING_XTAL_DIV
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bool "RTC Using XTAL Division"
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endchoice
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endif
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@@ -12,12 +12,6 @@ board.c
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board_config.c
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''')
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if GetDepend(['BSP_USING_TCA9539']):
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src += Glob('ports/tca9539.c')
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if GetDepend(['BSP_USING_SPI_FLASH']):
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src += Glob('ports/drv_spi_flash.c')
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path = [cwd]
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path += [cwd + '/ports']
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path += [cwd + '/config']
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@@ -25,11 +19,11 @@ path += [cwd + '/config']
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startup_path_prefix = SDK_LIB
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if rtconfig.PLATFORM in ['gcc']:
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src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
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src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
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elif rtconfig.PLATFORM in ['armcc', 'armclang']:
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src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
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src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
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elif rtconfig.PLATFORM in ['iccarm']:
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src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
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src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
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CPPDEFINES = ['HC32F448', '__DEBUG']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
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@@ -7,6 +7,7 @@
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* Change Logs:
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* Date Author Notes
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* 2024-02-20 CDT first version
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* 2024-06-07 CDT Add XTAL divider config code for RTC
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*/
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#include "board.h"
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@@ -41,6 +42,9 @@ void SystemClock_Config(void)
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#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
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stc_clock_xtal32_init_t stcXtal32Init;
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#endif
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#if defined(BSP_RTC_USING_XTAL_DIV)
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stc_clock_xtaldiv_init_t stcXtaldivInit;
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#endif
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/* PCLK0, HCLK Max 200MHz */
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/* PCLK1, PCLK4 Max 100MHz */
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@@ -87,17 +91,27 @@ void SystemClock_Config(void)
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stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
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(void)CLK_Xtal32Init(&stcXtal32Init);
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#endif
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#if defined(BSP_RTC_USING_XTAL_DIV)
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/* Xtal Div config */
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(void)CLK_XtalDivStructInit(&stcXtaldivInit);
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/* 8000000Hz / 32768Hz = 0x7A12 / 0x80 */
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stcXtaldivInit.u32Num = 0x7A12UL;
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stcXtaldivInit.u32Den = 0x80UL;
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stcXtaldivInit.u32State = CLK_XTALDIV_ON;
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(void)CLK_XtalDivInit(&stcXtaldivInit);
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#endif
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}
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/** Peripheral Clock Configuration
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*/
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void PeripheralClock_Config(void)
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{
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#if defined(BSP_USING_CAN1)
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CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
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#if defined(BSP_USING_MCAN1)
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CLK_SetCANClockSrc(CLK_MCAN1, CLK_MCANCLK_SYSCLK_DIV5);
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#endif
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#if defined(BSP_USING_CAN2)
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CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
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#if defined(BSP_USING_MCAN2)
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CLK_SetCANClockSrc(CLK_MCAN2, CLK_MCANCLK_SYSCLK_DIV5);
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#endif
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#if defined(RT_USING_ADC)
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@@ -11,7 +11,7 @@
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#include <rtdevice.h>
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#include "board_config.h"
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#include "tca9539.h"
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#include "tca9539_port.h"
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/**
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* The below functions will initialize HC32 board.
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@@ -130,7 +130,7 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
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switch ((rt_uint32_t)DACx)
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{
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#if defined(BSP_USING_DAC1)
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case (rt_uint32_t)CM_DAC1:
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case (rt_uint32_t)CM_DAC:
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(void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
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(void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
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break;
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@@ -144,34 +144,35 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
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}
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#endif
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#if defined(RT_USING_CAN)
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void CanPhyEnable(void)
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{
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#if defined(BSP_USING_CAN1)
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#if defined(BSP_USING_MCAN1)
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TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
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TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
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#endif
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#if defined(BSP_USING_CAN2)
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#if defined(BSP_USING_MCAN2)
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TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
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TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
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#endif
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}
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rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
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rt_err_t rt_hw_board_can_init(CM_MCAN_TypeDef *MCANx)
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{
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rt_err_t result = RT_EOK;
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switch ((rt_uint32_t)CANx)
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switch ((rt_uint32_t)MCANx)
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{
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#if defined(BSP_USING_CAN1)
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case (rt_uint32_t)CM_CAN1:
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GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
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GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
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#if defined(BSP_USING_MCAN1)
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case (rt_uint32_t)CM_MCAN1:
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GPIO_SetFunc(MCAN1_TX_PORT, MCAN1_TX_PIN, MCAN1_TX_PIN_FUNC);
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GPIO_SetFunc(MCAN1_RX_PORT, MCAN1_RX_PIN, MCAN1_RX_PIN_FUNC);
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break;
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#endif
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#if defined(BSP_USING_CAN2)
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case (rt_uint32_t)CM_CAN2:
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GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
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GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
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#if defined(BSP_USING_MCAN2)
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case (rt_uint32_t)CM_MCAN2:
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GPIO_SetFunc(MCAN2_TX_PORT, MCAN2_TX_PIN, MCAN2_TX_PIN_FUNC);
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GPIO_SetFunc(MCAN2_RX_PORT, MCAN2_RX_PIN, MCAN2_RX_PIN_FUNC);
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break;
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#endif
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default:
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@@ -183,7 +184,6 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
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}
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#endif
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#if defined (RT_USING_SPI)
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rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
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{
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@@ -333,103 +333,7 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
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#endif
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#ifdef RT_USING_PM
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#define EFM_ERASE_TIME_MAX_IN_MILLISECOND (20)
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#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
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static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk)
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{
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CLK_Xtal32Cmd(ENABLE);
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rt_tick_t tick_start = rt_tick_get_millisecond();
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rt_err_t rt_stat = RT_EOK;
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//wait flash idle
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while (SET != EFM_GetStatus(EFM_FLAG_RDY))
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{
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if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND)
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{
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rt_stat = RT_ERROR;
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break;
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}
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}
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RT_ASSERT(rt_stat == RT_EOK);
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if (b_disable_unused_clk)
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{
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uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW);
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switch (cur_clk_src)
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{
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case CLK_SYSCLK_SRC_HRC:
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CLK_PLLCmd(DISABLE);
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CLK_MrcCmd(DISABLE);
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CLK_LrcCmd(DISABLE);
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CLK_XtalCmd(DISABLE);
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PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE);
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break;
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case CLK_SYSCLK_SRC_MRC:
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CLK_PLLCmd(DISABLE);
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CLK_HrcCmd(DISABLE);
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CLK_LrcCmd(DISABLE);
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CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_XTAL:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_XTAL32:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_PLL:
|
||||
if (CLK_PLL_SRC_XTAL == PLL_SRC)
|
||||
{
|
||||
CLK_HrcCmd(DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLK_XtalCmd(DISABLE);
|
||||
}
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sleep_deep_init(void)
|
||||
{
|
||||
#if (PM_SLEEP_DEEP_CFG_CLK == PWC_STOP_CLK_KEEP)
|
||||
_pm_sleep_common_init(RT_TRUE);
|
||||
#else
|
||||
_pm_sleep_common_init(RT_FALSE);
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sleep_shutdown_init(void)
|
||||
{
|
||||
_pm_sleep_common_init(RT_TRUE);
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
switch (run_mode)
|
||||
|
||||
@@ -78,17 +78,17 @@
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC2_CH_PIN (GPIO_PIN_01)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
|
||||
#define ADC2_CH_PIN (GPIO_PIN_04)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC3)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_E)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */
|
||||
#define ADC3_CH_PIN (GPIO_PIN_03)
|
||||
#endif
|
||||
|
||||
@@ -101,24 +101,24 @@
|
||||
#endif
|
||||
|
||||
/*********** CAN configure *********/
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define CAN1_TX_PORT (GPIO_PORT_C)
|
||||
#define CAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define MCAN1_TX_PORT (GPIO_PORT_C)
|
||||
#define MCAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define CAN1_RX_PORT (GPIO_PORT_D)
|
||||
#define CAN1_RX_PIN (GPIO_PIN_00)
|
||||
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#define MCAN1_RX_PORT (GPIO_PORT_D)
|
||||
#define MCAN1_RX_PIN (GPIO_PIN_00)
|
||||
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_CAN2)
|
||||
#define CAN2_TX_PORT (GPIO_PORT_H)
|
||||
#define CAN2_TX_PIN (GPIO_PIN_02)
|
||||
#define CAN2_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define MCAN2_TX_PORT (GPIO_PORT_H)
|
||||
#define MCAN2_TX_PIN (GPIO_PIN_02)
|
||||
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define CAN2_RX_PORT (GPIO_PORT_E)
|
||||
#define CAN2_RX_PIN (GPIO_PIN_04)
|
||||
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#define MCAN2_RX_PORT (GPIO_PORT_E)
|
||||
#define MCAN2_RX_PIN (GPIO_PIN_04)
|
||||
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
/************************* SPI port ***********************/
|
||||
@@ -296,11 +296,11 @@
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
|
||||
|
||||
@@ -1,5 +1,4 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
@@ -32,7 +31,7 @@ extern "C" {
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
@@ -75,7 +74,7 @@ extern "C" {
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
@@ -118,7 +117,7 @@ extern "C" {
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
|
||||
@@ -19,117 +19,352 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
// The arguments of RT command RT_CAN_CMD_SET_CANFD
|
||||
#define MCAN_FD_CLASSICAL 0 /* CAN classical */
|
||||
#define MCAN_FD_ISO_FD_NO_BRS 1 /* ISO CAN FD without BRS */
|
||||
#define MCAN_FD_ISO_FD_BRS 2 /* ISO CAN FD with BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_NO_BRS 3 /* non-ISO CAN FD without BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_BRS 4 /* non-ISO CAN FD with BRS */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN2_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
#define MCAN_FD_ARG_MIN MCAN_FD_ISO_FD_NO_BRS
|
||||
#define MCAN_FD_ARG_MAX MCAN_FD_NON_ISO_FD_BRS
|
||||
|
||||
/* Bit time config
|
||||
Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
|
||||
|
||||
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
/* The default configuration for MCANs. Users can modify the configurations based on the application.
|
||||
For the message RAM:
|
||||
1. MCAN1 and MCAN2 share 2048 bytes message RAM
|
||||
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
|
||||
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
|
||||
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
|
||||
and pay attention the total size of meesage RAM that to be allocated.
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
|
||||
#define MCAN_TOTAL_FILTER_NUM (26U)
|
||||
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (6U)
|
||||
#define MCAN_RX_FIFO_NUM (6U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
|
||||
#else
|
||||
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
|
||||
#define MCAN_TOTAL_FILTER_NUM (32U)
|
||||
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (26U)
|
||||
#define MCAN_RX_FIFO_NUM (26U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_MCAN1
|
||||
#define MCAN1_NAME ("can1")
|
||||
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN1_FD_SEL MCAN_FD_SEL
|
||||
|
||||
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN1 */
|
||||
|
||||
#ifdef BSP_USING_MCAN2
|
||||
#define MCAN2_NAME ("can2")
|
||||
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN2_FD_SEL MCAN_FD_SEL
|
||||
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN2 */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for CAN FD.
|
||||
Nominal bit rate for CAN FD arbitration phase and data bit rate for CAN FD data phase.
|
||||
BitRate(bps) = MCANClock(Hz) / (Prescaler * (TimeSeg1 + TimeSeg2))
|
||||
SamplePoint(%) = TimeSeg1 / (TimeSeg1 + TimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
NOTE:
|
||||
1. It is better to limit u32NominalPrescaler and u32DataPrescaler between 1 and 2.
|
||||
1. The unit of u32SspOffset is MCANClock.
|
||||
2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF).
|
||||
The u32TdcFilter can be get from PSR.TDCV.
|
||||
*/
|
||||
#define MCAN_FD_CFG_500K_1M \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 32, \
|
||||
.u32TdcFilter = 32 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
#define MCAN_FD_CFG_500K_2M \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
#define MCAN_FD_CFG_500K_4M \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
#define MCAN_FD_CFG_500K_5M \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
#define MCAN_FD_CFG_500K_8M \
|
||||
{ \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
#define MCAN_FD_CFG_1M_1M \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 2*32, \
|
||||
.u32TdcFilter = 2*32 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
#define MCAN_FD_CFG_1M_2M \
|
||||
{ \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
#define MCAN_FD_CFG_1M_4M \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
#define MCAN_FD_CFG_1M_5M \
|
||||
{ \
|
||||
.u32Prescaler = 200, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for classical CAN.
|
||||
BitRate(bps) = MCANClock(Hz) / (u32NominalPrescaler * (u32NominalTimeSeg1 + u32NominalTimeSeg2))
|
||||
SamplePoint(%) = u32NominalTimeSeg1 / (u32NominalTimeSeg1 + u32NominalTimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
*/
|
||||
#define MCAN_CC_CFG_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_800K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 20, \
|
||||
.u32NominalTimeSeg2 = 5, \
|
||||
.u32NominalSyncJumpWidth = 5, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_500K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_250K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_125K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 8, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_100K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 10, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_50K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 20, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_20K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 50, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_10K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 100, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE MCANFD_NOMINAL_BAUD_1M
|
||||
#define MCAN1_DATA_BAUD_RATE MCANFD_DATA_BAUD_4M
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE MCANFD_NOMINAL_BAUD_1M
|
||||
#define MCAN2_DATA_BAUD_RATE MCANFD_DATA_BAUD_4M
|
||||
|
||||
#else
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN1_DATA_BAUD_RATE 0
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN2_DATA_BAUD_RATE 0
|
||||
|
||||
#endif /* #ifdef RT_CAN_USING_CANFD */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -27,15 +26,6 @@ extern "C" {
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -193,6 +193,16 @@ extern "C" {
|
||||
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
|
||||
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
|
||||
#define QSPI_DMA_INSTANCE CM_DMA2
|
||||
#define QSPI_DMA_CHANNEL DMA_CH0
|
||||
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
|
||||
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#endif
|
||||
|
||||
/* DMA2 ch1 */
|
||||
|
||||
@@ -158,6 +158,11 @@ extern "C" {
|
||||
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_QSPI)
|
||||
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
|
||||
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#if defined(BSP_USING_TMRA_1)
|
||||
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
@@ -183,16 +188,71 @@ extern "C" {
|
||||
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_5 */
|
||||
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define BSP_CAN1_IRQ_NUM MCAN1_INT0_IRQn
|
||||
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_CAN1 */
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
|
||||
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn
|
||||
#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN1 */
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
|
||||
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn
|
||||
#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN2 */
|
||||
|
||||
#if defined(RT_USING_ALARM)
|
||||
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
|
||||
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* RT_USING_ALARM */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -174,224 +174,6 @@ extern "C" {
|
||||
}
|
||||
#endif /* PWM_TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_6
|
||||
#ifndef PWM_TMRA_6_CONFIG
|
||||
#define PWM_TMRA_6_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a6", \
|
||||
.instance = CM_TMRA_6, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_6_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_6 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_7
|
||||
#ifndef PWM_TMRA_7_CONFIG
|
||||
#define PWM_TMRA_7_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a7", \
|
||||
.instance = CM_TMRA_7, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_7_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_7 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_8
|
||||
#ifndef PWM_TMRA_8_CONFIG
|
||||
#define PWM_TMRA_8_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a8", \
|
||||
.instance = CM_TMRA_8, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_8_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_8 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_9
|
||||
#ifndef PWM_TMRA_9_CONFIG
|
||||
#define PWM_TMRA_9_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a9", \
|
||||
.instance = CM_TMRA_9, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_9_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_9 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_10
|
||||
#ifndef PWM_TMRA_10_CONFIG
|
||||
#define PWM_TMRA_10_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a10", \
|
||||
.instance = CM_TMRA_10, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_10_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_10 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_11
|
||||
#ifndef PWM_TMRA_11_CONFIG
|
||||
#define PWM_TMRA_11_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a11", \
|
||||
.instance = CM_TMRA_11, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_11_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_11 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_12
|
||||
#ifndef PWM_TMRA_12_CONFIG
|
||||
#define PWM_TMRA_12_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a12", \
|
||||
.instance = CM_TMRA_12, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_12_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_12 */
|
||||
|
||||
#endif /* BSP_USING_PWM_TMRA */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR4
|
||||
|
||||
@@ -65,8 +65,13 @@ extern "C" {
|
||||
} \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
|
||||
/* unit: half-word, DMA data width of QSPI transmitting is 16bit */
|
||||
#ifndef QSPI_DMA_TX_BUFSIZE
|
||||
#define QSPI_DMA_TX_BUFSIZE 256
|
||||
#endif /* QSPI_DMA_TX_BUFSIZE */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
||||
@@ -103,7 +103,7 @@ extern "C"
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to 0U.
|
||||
*/
|
||||
#define BSP_EV_HC32F4XX (BSP_EV_HC32F448_LQFP80)
|
||||
#define BSP_EV_HC32F4XX (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -1,122 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <drv_spi.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
#include <finsh.h>
|
||||
#include <dfs_fs.h>
|
||||
#include <fal.h>
|
||||
|
||||
#ifdef BSP_USING_SPI_FLASH
|
||||
|
||||
#include "dev_spi_flash.h"
|
||||
#ifdef RT_USING_SFUD
|
||||
#include "dev_spi_flash_sfud.h"
|
||||
#endif
|
||||
|
||||
#define SPI_BUS_NAME "spi1"
|
||||
#define SPI_FLASH_DEVICE_NAME "spi10"
|
||||
#define SPI_FLASH_CHIP "w25q64"
|
||||
#define SPI_FLASH_SS_PIN GET_PIN(C, 7)
|
||||
/* Partition Name */
|
||||
#define FS_PARTITION_NAME "filesystem"
|
||||
|
||||
#ifdef RT_USING_SFUD
|
||||
static void rt_hw_spi_flash_reset(char *spi_dev_name)
|
||||
{
|
||||
struct rt_spi_device *spi_dev_w25;
|
||||
rt_uint8_t w25_en_reset = 0x66;
|
||||
rt_uint8_t w25_reset_dev = 0x99;
|
||||
|
||||
spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
|
||||
if (!spi_dev_w25)
|
||||
{
|
||||
rt_kprintf("Can't find %s device!\n", spi_dev_name);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
|
||||
rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
|
||||
DDL_DelayMS(1U);
|
||||
rt_kprintf("Reset ext flash!\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int rt_hw_spi_flash_with_sfud_init(void)
|
||||
{
|
||||
rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PIN);
|
||||
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
|
||||
|
||||
static int rt_hw_fs_init(void)
|
||||
{
|
||||
struct rt_device *mtd_dev = RT_NULL;
|
||||
|
||||
/* 初始化 fal */
|
||||
fal_init();
|
||||
/* 生成 mtd 设备 */
|
||||
mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
|
||||
if (!mtd_dev)
|
||||
{
|
||||
LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 格式化文件系统 */
|
||||
if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to initialize filesystem!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to Format fs!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
INIT_APP_EXPORT(rt_hw_fs_init);
|
||||
|
||||
#endif /* RT_USING_SFUD */
|
||||
|
||||
#endif /* BSP_USING_SPI_FLASH */
|
||||
@@ -1,20 +0,0 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
src += Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
LOCAL_CFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM in ['armcc']:
|
||||
LOCAL_CFLAGS += ' --c99'
|
||||
|
||||
group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||
|
||||
Return('group')
|
||||
@@ -1,85 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <fal.h>
|
||||
|
||||
#include <sfud.h>
|
||||
#ifdef RT_USING_SFUD
|
||||
#include <dev_spi_flash_sfud.h>
|
||||
#endif
|
||||
|
||||
#ifndef FAL_USING_NOR_FLASH_DEV_NAME
|
||||
#define FAL_USING_NOR_FLASH_DEV_NAME "w25q64"
|
||||
#endif
|
||||
|
||||
static int init(void);
|
||||
static int read(long offset, rt_uint8_t *buf, rt_size_t size);
|
||||
static int write(long offset, const rt_uint8_t *buf, rt_size_t size);
|
||||
static int erase(long offset, rt_size_t size);
|
||||
|
||||
static sfud_flash_t sfud_dev = NULL;
|
||||
struct fal_flash_dev ext_nor_flash0 =
|
||||
{
|
||||
.name = FAL_USING_NOR_FLASH_DEV_NAME,
|
||||
.addr = 0,
|
||||
.len = 8 * 1024 * 1024,
|
||||
.blk_size = 4096,
|
||||
.ops = {init, read, write, erase},
|
||||
.write_gran = 1
|
||||
};
|
||||
|
||||
static int init(void)
|
||||
{
|
||||
/* RT-Thread RTOS platform */
|
||||
sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
|
||||
if (NULL == sfud_dev)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* update the flash chip information */
|
||||
ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
|
||||
ext_nor_flash0.len = sfud_dev->chip.capacity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read(long offset, rt_uint8_t *buf, rt_size_t size)
|
||||
{
|
||||
RT_ASSERT(sfud_dev);
|
||||
RT_ASSERT(sfud_dev->init_ok);
|
||||
sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int write(long offset, const rt_uint8_t *buf, rt_size_t size)
|
||||
{
|
||||
RT_ASSERT(sfud_dev);
|
||||
RT_ASSERT(sfud_dev->init_ok);
|
||||
if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int erase(long offset, rt_size_t size)
|
||||
{
|
||||
RT_ASSERT(sfud_dev);
|
||||
RT_ASSERT(sfud_dev->init_ok);
|
||||
if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
@@ -1,320 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtdbg.h>
|
||||
|
||||
#ifdef BSP_USING_TCA9539
|
||||
|
||||
#include "tca9539.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Define for TCA9539 */
|
||||
#define BSP_TCA9539_I2C_BUS_NAME "i2c1"
|
||||
#define BSP_TCA9539_DEV_ADDR (0x74U)
|
||||
|
||||
#define TCA9539_RST_PIN (32) /* PB15 */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @brief BSP TCA9539 write data.
|
||||
* @param [in] bus: Pointer to the i2c bus device.
|
||||
* @param [in] reg: Register to be written.
|
||||
* @param [in] data: The pointer to the buffer contains the data to be written.
|
||||
* @param [in] len: Buffer size in byte.
|
||||
* @retval rt_err_t:
|
||||
* - RT_EOK
|
||||
* - -RT_ERROR
|
||||
*/
|
||||
static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
|
||||
{
|
||||
struct rt_i2c_msg msgs;
|
||||
rt_uint8_t buf[6];
|
||||
|
||||
buf[0] = reg;
|
||||
if (len > 0)
|
||||
{
|
||||
if (len < 6)
|
||||
{
|
||||
rt_memcpy(buf + 1, data, len);
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
msgs.addr = BSP_TCA9539_DEV_ADDR;
|
||||
msgs.flags = RT_I2C_WR;
|
||||
msgs.buf = buf;
|
||||
msgs.len = len + 1;
|
||||
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP TCA9539 Read data.
|
||||
* @param [in] bus: Pointer to the i2c bus device.
|
||||
* @param [in] reg: Register to be read.
|
||||
* @param [out] data: The pointer to the buffer contains the data to be read.
|
||||
* @param [in] len: Buffer size in byte.
|
||||
* @retval rt_err_t:
|
||||
* - RT_EOK
|
||||
* - -RT_ERROR
|
||||
*/
|
||||
static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
|
||||
{
|
||||
struct rt_i2c_msg msgs;
|
||||
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
msgs.addr = BSP_TCA9539_DEV_ADDR;
|
||||
msgs.flags = RT_I2C_RD;
|
||||
msgs.buf = data;
|
||||
msgs.len = len;
|
||||
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset TCA9539.
|
||||
* @param [in] None
|
||||
* @retval None
|
||||
*/
|
||||
static void TCA9539_Reset(void)
|
||||
{
|
||||
rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
|
||||
/* Reset the device */
|
||||
rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(3U);
|
||||
rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write TCA9539 pin output value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8PinState Pin state to be written.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Pin_State_Definition
|
||||
* @retval rt_err_t:
|
||||
* - RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (0U == u8PinState)
|
||||
{
|
||||
u8TempData[1] &= (uint8_t)(~u8Pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
u8TempData[1] |= u8Pin;
|
||||
}
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read TCA9539 pin input value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8PinState Pin state to be written.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Pin_State_Definition
|
||||
* @retval rt_err_t:
|
||||
* - RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (0U != (u8TempData[1] & u8Pin))
|
||||
{
|
||||
*pu8PinState = TCA9539_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pu8PinState = TCA9539_PIN_RESET;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle TCA9539 pin output value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
u8TempData[1] ^= u8Pin;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configuration TCA9539 pin.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8Dir Pin output direction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Direction_Definition
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (TCA9539_DIR_OUT == u8Dir)
|
||||
{
|
||||
u8TempData[1] &= (uint8_t)(~u8Pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
u8TempData[1] |= u8Pin;
|
||||
}
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize TCA9539.
|
||||
* @param [in] None
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
int TCA9539_Init(void)
|
||||
{
|
||||
char name[RT_NAME_MAX];
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
TCA9539_Reset();
|
||||
rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
|
||||
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
|
||||
if (i2c_bus == RT_NULL)
|
||||
{
|
||||
rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
/* All Pins are input as default */
|
||||
u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
|
||||
u8TempData[1] = 0xFFU;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_PREV_EXPORT(TCA9539_Init);
|
||||
|
||||
#endif /* BSP_USING_TCA9539 */
|
||||
@@ -1,133 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_H__
|
||||
#define __TCA9539_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_REG_INPUT_PORT0 (0x00U)
|
||||
#define TCA9539_REG_INPUT_PORT1 (0x01U)
|
||||
#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
|
||||
#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
|
||||
#define TCA9539_REG_INVERT_PORT0 (0x04U)
|
||||
#define TCA9539_REG_INVERT_PORT1 (0x05U)
|
||||
#define TCA9539_REG_CONFIG_PORT0 (0x06U)
|
||||
#define TCA9539_REG_CONFIG_PORT1 (0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Port_Definition TCA9539 Port Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PORT0 (0x00U)
|
||||
#define TCA9539_IO_PORT1 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PIN0 (0x01U)
|
||||
#define TCA9539_IO_PIN1 (0x02U)
|
||||
#define TCA9539_IO_PIN2 (0x04U)
|
||||
#define TCA9539_IO_PIN3 (0x08U)
|
||||
#define TCA9539_IO_PIN4 (0x10U)
|
||||
#define TCA9539_IO_PIN5 (0x20U)
|
||||
#define TCA9539_IO_PIN6 (0x40U)
|
||||
#define TCA9539_IO_PIN7 (0x80U)
|
||||
#define TCA9539_IO_PIN_ALL (0xFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_DIR_OUT (0x00U)
|
||||
#define TCA9539_DIR_IN (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_PIN_RESET (0x00U)
|
||||
#define TCA9539_PIN_SET (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
|
||||
#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
|
||||
#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
|
||||
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */
|
||||
#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
|
||||
#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN1_STB_PIN (EIO_CAN1_STB)
|
||||
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN2_STB_PIN (EIO_CAN2_STB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
int TCA9539_Init(void);
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_PORT_H__
|
||||
#define __TCA9539_PORT_H__
|
||||
|
||||
#include "tca9539.h"
|
||||
|
||||
/**
|
||||
* @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
|
||||
#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
|
||||
#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
|
||||
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */
|
||||
#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
|
||||
#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN1_STB_PIN (EIO_CAN1_STB)
|
||||
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN2_STB_PIN (EIO_CAN2_STB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
@@ -41,7 +41,7 @@
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -80,7 +80,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>OCProductVersion</name>
|
||||
<state>8.40.1.21529</state>
|
||||
<state>7.70.1.11471</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDynDriverList</name>
|
||||
@@ -88,7 +88,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>OCLastSavedByProductVersion</name>
|
||||
<state>8.50.9.33458</state>
|
||||
<state>8.40.2.22864</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UseFlashLoader</name>
|
||||
@@ -112,7 +112,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board</state>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
@@ -1007,7 +1007,7 @@
|
||||
<name>STLINK_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>7</version>
|
||||
<version>6</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>0</debug>
|
||||
<option>
|
||||
@@ -1033,7 +1033,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockAuto</name>
|
||||
<state>0</state>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockEdit</name>
|
||||
@@ -1123,7 +1123,7 @@
|
||||
<option>
|
||||
<name>CCSTLinkProbeList</name>
|
||||
<version>1</version>
|
||||
<state>2</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
@@ -1379,7 +1379,7 @@
|
||||
<option>
|
||||
<name>CCXds100ProbeList</name>
|
||||
<version>0</version>
|
||||
<state>3</state>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCXds100SWOPortRadio</name>
|
||||
@@ -1445,11 +1445,11 @@
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
@@ -1529,7 +1529,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
@@ -1565,15 +1565,15 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>OCProductVersion</name>
|
||||
<state>8.40.1.21529</state>
|
||||
<state>7.70.1.11471</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDynDriverList</name>
|
||||
<state>CMSISDAP_ID</state>
|
||||
<state>ARMSIM_ID</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCLastSavedByProductVersion</name>
|
||||
<state>8.40.1.21529</state>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UseFlashLoader</name>
|
||||
@@ -1597,7 +1597,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board</state>
|
||||
<state>$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F448xC.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
@@ -2492,7 +2492,7 @@
|
||||
<name>STLINK_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>7</version>
|
||||
<version>6</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>0</debug>
|
||||
<option>
|
||||
@@ -2518,7 +2518,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockAuto</name>
|
||||
<state>0</state>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockEdit</name>
|
||||
@@ -2608,7 +2608,7 @@
|
||||
<option>
|
||||
<name>CCSTLinkProbeList</name>
|
||||
<version>1</version>
|
||||
<state>2</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
@@ -2930,11 +2930,11 @@
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
|
||||
@@ -319,27 +319,31 @@
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state />
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\tests</state>
|
||||
<state>$PROJ_DIR$\..\platform\tca9539</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
@@ -1310,27 +1314,31 @@
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state />
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\epoll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Device\HDSC\hc32f4xx\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\tests</state>
|
||||
<state>$PROJ_DIR$\..\platform\tca9539</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\eventfd</state>
|
||||
<state>$PROJ_DIR$\..\..\..\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Include</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\inc</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
|
||||
<state>$PROJ_DIR$\board\config</state>
|
||||
<state>$PROJ_DIR$\..\libraries\hc32_drivers</state>
|
||||
<state>$PROJ_DIR$\board\ports</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\board</state>
|
||||
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
@@ -1985,10 +1993,10 @@
|
||||
<group>
|
||||
<name>Applications</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\xtal32_fcm.c</name>
|
||||
<name>$PROJ_DIR$\applications\main.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\main.c</name>
|
||||
<name>$PROJ_DIR$\applications\xtal32_fcm.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
@@ -2045,7 +2053,22 @@
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\core\device.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
|
||||
@@ -2066,10 +2089,10 @@
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\pin\pin.c</name>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
|
||||
<name>$PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
@@ -2081,7 +2104,7 @@
|
||||
<name>$PROJ_DIR$\board\board_config.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f448.s</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f448.s</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_common.c</name>
|
||||
@@ -2089,27 +2112,33 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_i2c.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_soft_i2c.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_usart.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Finsh</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Kernel</name>
|
||||
@@ -2119,6 +2148,12 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\components.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\cpu_up.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\defunct.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\idle.c</name>
|
||||
</file>
|
||||
@@ -2128,12 +2163,6 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\irq.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\kstdio.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\kstring.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
|
||||
</file>
|
||||
@@ -2159,6 +2188,24 @@
|
||||
<name>$PROJ_DIR$\..\..\..\src\timer.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>klibc</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\kerrno.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\kstdio.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\kstring.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>libcpu</name>
|
||||
<file>
|
||||
@@ -2180,58 +2227,88 @@
|
||||
<group>
|
||||
<name>Libraries</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_fcg.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_clk.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_icg.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_interrupts.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_sram.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_dma.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_gpio.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcm.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_efm.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_pwc.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f448.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_aos.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_utility.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f448.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_fcm.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_tmr0.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_usart.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c</name>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_rmu.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\libraries\hc32f448_ddl\hc32_ll_driver\src\hc32_ll_i2c.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Platform</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\platform\tca9539\tca9539.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>POSIX</name>
|
||||
</group>
|
||||
<group>
|
||||
<name>smp</name>
|
||||
</group>
|
||||
<group>
|
||||
<name>Tests</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\tests\test_soft_i2c.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\tests\test_i2c.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\tests\test_uart_v1.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\tests\test_gpio.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>utestcases</name>
|
||||
</group>
|
||||
</project>
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
@@ -120,7 +120,7 @@
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K.FLM -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp.FLM -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
@@ -140,12 +140,12 @@
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,11 +1,66 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
@@ -19,9 +74,11 @@
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
@@ -32,6 +89,7 @@
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
@@ -39,12 +97,14 @@
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart2"
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_VER_NUM 0x50200
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
@@ -74,6 +134,7 @@
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
@@ -86,10 +147,10 @@
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
@@ -101,6 +162,8 @@
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
@@ -110,18 +173,30 @@
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
@@ -132,57 +207,78 @@
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
@@ -190,66 +286,94 @@
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
#define SOC_FAMILY_HC32
|
||||
#define SOC_SERIES_HC32F4
|
||||
|
||||
@@ -263,19 +387,26 @@
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
|
||||
/* end of On-chip Drivers */
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_TCA9539
|
||||
#define BSP_USING_EXT_IO
|
||||
/* end of Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART2
|
||||
#define BSP_UART2_RX_USING_DMA
|
||||
#define BSP_UART2_TX_USING_DMA
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C_HW
|
||||
#define BSP_USING_I2C1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
@@ -120,7 +120,7 @@
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K.FLM -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp.FLM -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
@@ -140,12 +140,12 @@
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
|
||||
@@ -33,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR</SFDFile>
|
||||
<SFDFile>../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
@@ -245,7 +245,7 @@
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1FFF8000</StartAddress>
|
||||
<StartAddress>0x1fff8000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
@@ -280,7 +280,7 @@
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x03000C00</StartAddress>
|
||||
<StartAddress>0x3000c00</StartAddress>
|
||||
<Size>0x400</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
@@ -300,12 +300,12 @@
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1FFF8000</StartAddress>
|
||||
<StartAddress>0x1fff8000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x200F0000</StartAddress>
|
||||
<StartAddress>0x200f0000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -64,5 +64,15 @@
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/platform</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/tests</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
|
||||
@@ -29,39 +29,37 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下：
|
||||
- 常用接口: USB转串口、SD卡接口、USB FS、3.5mm耳机接口、Line in接口、喇叭接口
|
||||
- 调试接口: 板载DAP调试器、标准JTAG/SWD
|
||||
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F460_LQ100_V2](http://www.xhsc.com.cn)
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F460_LQ100_V2](https://www.xhsc.com.cn)
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| USB 转串口 | 支持 | 使用 UART4 |
|
||||
| LED | 支持 | LED |
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| ADC | 支持 | ADC1~2 |
|
||||
| CAN | 支持 | CAN1 |
|
||||
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
|
||||
| I2C | 支持 | 软件 |
|
||||
| UART | 支持 | UART1~4 |
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
|:-------- |:--------:|:--------:|
|
||||
| USB 转串口 | 支持 | 使用 UART4 |
|
||||
| LED | 支持 | LED |
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
|:-------- |:--------:|:-----------------------------------:|
|
||||
| ADC | 支持 | ADC1~2 |
|
||||
| CAN | 支持 | CAN1 |
|
||||
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
|
||||
| I2C | 支持 | 软件 |
|
||||
| UART | 支持 | UART1~4 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
@@ -104,8 +102,14 @@ msh >
|
||||
|
||||
## 注意事项
|
||||
|
||||
| 板载外设 | 模式 | 注意事项 |
|
||||
| -------- | ------ | ------------------------------------------------------------ |
|
||||
| USB | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） |
|
||||
| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
|
||||
| USB | host | 目前仅实现并测试了对U盘的支持。 |
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
|
||||
@@ -56,7 +56,13 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
|
||||
# include platform
|
||||
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
|
||||
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
|
||||
|
||||
# include tests
|
||||
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
|
||||
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-27 CDT first version
|
||||
* 2024-06-13 CDT modify FCM lower/upper margin to 10%
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
@@ -40,8 +41,8 @@ void xtal32_fcm_thread_entry(void *parameter)
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 90UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 110UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
@@ -162,11 +162,11 @@ menu "On-chip Peripheral Drivers"
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "i2c1 scl pin number"
|
||||
range 1 100
|
||||
default 7
|
||||
default 36
|
||||
config BSP_I2C1_SDA_PIN
|
||||
int "I2C1 sda pin number"
|
||||
range 1 100
|
||||
default 36
|
||||
default 7
|
||||
endif
|
||||
endif
|
||||
|
||||
@@ -318,12 +318,22 @@ menu "On-chip Peripheral Drivers"
|
||||
default n
|
||||
select RT_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC1
|
||||
bool "using adc1"
|
||||
menuconfig BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default n
|
||||
config BSP_USING_ADC2
|
||||
bool "using adc2"
|
||||
if BSP_USING_ADC1
|
||||
config BSP_ADC1_USING_DMA
|
||||
bool "using adc1 dma"
|
||||
default n
|
||||
endif
|
||||
menuconfig BSP_USING_ADC2
|
||||
bool "Enable ADC2"
|
||||
default n
|
||||
if BSP_USING_ADC2
|
||||
config BSP_ADC2_USING_DMA
|
||||
bool "using adc2 dma"
|
||||
default n
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
@@ -338,18 +348,17 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_WDT_TMR
|
||||
bool "Enable Watchdog Timer"
|
||||
bool "Enable Watchdog Timer: 10.7s(max)"
|
||||
default n
|
||||
select RT_USING_WDT
|
||||
if BSP_USING_WDT_TMR
|
||||
config BSP_USING_WDT
|
||||
bool "Using WDT"
|
||||
bool
|
||||
default y
|
||||
|
||||
config BSP_WDT_CONTINUE_COUNT
|
||||
bool "Low Power Mode Keeps Counting"
|
||||
default n
|
||||
if BSP_USING_WDT
|
||||
config BSP_WDT_CONTINUE_COUNT
|
||||
bool "Low Power Mode Keeps Counting"
|
||||
default n
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_RTC
|
||||
@@ -462,26 +471,21 @@ menu "On-chip Peripheral Drivers"
|
||||
bool "Enable timerA output PWM"
|
||||
default n
|
||||
if BSP_USING_PWM_TMRA
|
||||
menuconfig BSP_USING_PWM_TMRA_4
|
||||
bool "Enable timerA-4 output PWM"
|
||||
menuconfig BSP_USING_PWM_TMRA_1
|
||||
bool "Enable timerA-1 output PWM"
|
||||
default n
|
||||
if BSP_USING_PWM_TMRA_4
|
||||
config BSP_USING_PWM_TMRA_4_CH1
|
||||
bool "Enable timerA-4 channel1"
|
||||
if BSP_USING_PWM_TMRA_1
|
||||
config BSP_USING_PWM_TMRA_1_CH1
|
||||
bool "Enable timerA-1 channel1"
|
||||
default n
|
||||
config BSP_USING_PWM_TMRA_4_CH2
|
||||
bool "Enable timerA-4 channel2"
|
||||
config BSP_USING_PWM_TMRA_1_CH2
|
||||
bool "Enable timerA-1 channel2"
|
||||
default n
|
||||
endif
|
||||
menuconfig BSP_USING_PWM_TMRA_5
|
||||
bool "Enable timerA-5 output PWM"
|
||||
default n
|
||||
if BSP_USING_PWM_TMRA_5
|
||||
config BSP_USING_PWM_TMRA_5_CH1
|
||||
bool "Enable timerA-5 channel1"
|
||||
config BSP_USING_PWM_TMRA_1_CH3
|
||||
bool "Enable timerA-1 channel3"
|
||||
default n
|
||||
config BSP_USING_PWM_TMRA_5_CH2
|
||||
bool "Enable timerA-5 channel2"
|
||||
config BSP_USING_PWM_TMRA_1_CH4
|
||||
bool "Enable timerA-1 channel4"
|
||||
default n
|
||||
endif
|
||||
endif
|
||||
@@ -631,7 +635,23 @@ menu "On-chip Peripheral Drivers"
|
||||
bool "Use Timer_a6 As The Hw Timer"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_INPUT_CAPTURE
|
||||
bool "Enable Input Capture"
|
||||
default n
|
||||
select RT_USING_INPUT_CAPTURE
|
||||
if BSP_USING_INPUT_CAPTURE
|
||||
menuconfig BSP_USING_INPUT_CAPTURE_TMR6
|
||||
bool "Use Timer6 As The Input Capture"
|
||||
default n
|
||||
if BSP_USING_INPUT_CAPTURE_TMR6
|
||||
config BSP_USING_INPUT_CAPTURE_TMR6_1
|
||||
bool "unit 1"
|
||||
config BSP_USING_INPUT_CAPTURE_TMR6_2
|
||||
bool "unit 2"
|
||||
config BSP_USING_INPUT_CAPTURE_TMR6_3
|
||||
bool "unit 3"
|
||||
endif
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
@@ -12,9 +12,6 @@ board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/drv_spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
@@ -23,11 +20,11 @@ path += [cwd + '/config/usb_config']
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S']
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S']
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s']
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s']
|
||||
src += [startup_path_prefix + '/hc32f460_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s']
|
||||
|
||||
CPPDEFINES = ['HC32F460', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
* 2024-06-11 CDT remove CLK_Delay for usb, as it is already included in ddl API
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
@@ -16,28 +17,6 @@
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
/**
|
||||
* @brief Switch clock stable time
|
||||
* @note Approx. 30us
|
||||
*/
|
||||
#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL)
|
||||
/**
|
||||
* @brief Clk delay function
|
||||
* @param [in] u32Delay count
|
||||
* @retval when switch clock source, should be delay some time to wait stable.
|
||||
*/
|
||||
static void CLK_Delay(uint32_t u32Delay)
|
||||
{
|
||||
__IO uint32_t u32Timeout = 0UL;
|
||||
|
||||
while (u32Timeout < u32Delay)
|
||||
{
|
||||
u32Timeout++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
@@ -136,8 +115,6 @@ void PeripheralClock_Config(void)
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
|
||||
/* Wait stable here, since the current DDL API does not include this */
|
||||
CLK_Delay(CLK_SYSCLK_SW_STB);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -147,5 +124,3 @@ void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
@@ -104,6 +104,7 @@ void CanPhyEnable(void)
|
||||
GPIO_ResetPins(CAN1_STB_PORT, CAN1_STB_PIN);
|
||||
GPIO_OutputCmd(CAN1_STB_PORT, CAN1_STB_PIN, ENABLE);
|
||||
}
|
||||
|
||||
rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
@@ -207,38 +208,23 @@ rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMRAx)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMRA_4)
|
||||
case (rt_uint32_t)CM_TMRA_4:
|
||||
#ifdef BSP_USING_PWM_TMRA_4_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_4_CH1_PORT, PWM_TMRA_4_CH1_PIN, PWM_TMRA_4_CH1_PIN_FUNC);
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
case (rt_uint32_t)CM_TMRA_1:
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_4_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_4_CH2_PORT, PWM_TMRA_4_CH2_PIN, PWM_TMRA_4_CH2_PIN_FUNC);
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_4_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_4_CH3_PORT, PWM_TMRA_4_CH3_PIN, PWM_TMRA_4_CH3_PIN_FUNC);
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_4_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_4_CH4_PORT, PWM_TMRA_4_CH4_PIN, PWM_TMRA_4_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_5)
|
||||
case (rt_uint32_t)CM_TMRA_5:
|
||||
#ifdef BSP_USING_PWM_TMRA_5_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_5_CH1_PORT, PWM_TMRA_5_CH1_PIN, PWM_TMRA_5_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_5_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_5_CH2_PORT, PWM_TMRA_5_CH2_PIN, PWM_TMRA_5_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_5_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_5_CH3_PORT, PWM_TMRA_5_CH3_PIN, PWM_TMRA_5_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_5_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_5_CH4_PORT, PWM_TMRA_5_CH4_PIN, PWM_TMRA_5_CH4_PIN_FUNC);
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
@@ -276,6 +262,7 @@ rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
@@ -300,6 +287,7 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
@@ -310,6 +298,35 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE)
|
||||
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)tmr_instance)
|
||||
{
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, GPIO_FUNC_3);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
case (rt_uint32_t)CM_TMR6_2:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, GPIO_FUNC_3);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
case (rt_uint32_t)CM_TMR6_3:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, GPIO_FUNC_3);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#ifdef RT_USING_PM
|
||||
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
@@ -317,12 +334,12 @@ void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
case PM_RUN_MODE_HIGH_SPEED:
|
||||
case PM_RUN_MODE_NORMAL_SPEED:
|
||||
SystemClock_Config();
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
break;
|
||||
|
||||
case PM_RUN_MODE_LOW_SPEED:
|
||||
/* Ensure that system clock less than 8M */
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -330,7 +347,7 @@ void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
rt_err_t rt_hw_usb_board_init(void)
|
||||
rt_err_t rt_hw_usbfs_board_init(void)
|
||||
{
|
||||
stc_gpio_init_t stcGpioCfg;
|
||||
(void)GPIO_StructInit(&stcGpioCfg);
|
||||
|
||||
@@ -44,6 +44,16 @@
|
||||
#endif
|
||||
|
||||
/************************ I2C port **********************/
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#define I2C1_SDA_PORT (GPIO_PORT_A)
|
||||
#define I2C1_SDA_PIN (GPIO_PIN_07)
|
||||
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
|
||||
|
||||
#define I2C1_SCL_PORT (GPIO_PORT_C)
|
||||
#define I2C1_SCL_PIN (GPIO_PIN_04)
|
||||
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C3)
|
||||
#define I2C3_SDA_PORT (GPIO_PORT_B)
|
||||
#define I2C3_SDA_PIN (GPIO_PIN_05)
|
||||
@@ -56,12 +66,12 @@
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN11 */
|
||||
#define ADC2_CH_PIN (GPIO_PIN_01)
|
||||
#endif
|
||||
|
||||
@@ -141,49 +151,26 @@
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
/*********** PWM_TMRA configure *********/
|
||||
#if defined(BSP_USING_PWM_TMRA_4)
|
||||
#if defined(BSP_USING_PWM_TMRA_4_CH1)
|
||||
#define PWM_TMRA_4_CH1_PORT (GPIO_PORT_D)
|
||||
#define PWM_TMRA_4_CH1_PIN (GPIO_PIN_12)
|
||||
#define PWM_TMRA_4_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH1)
|
||||
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_4_CH2)
|
||||
#define PWM_TMRA_4_CH2_PORT (GPIO_PORT_D)
|
||||
#define PWM_TMRA_4_CH2_PIN (GPIO_PIN_13)
|
||||
#define PWM_TMRA_4_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH2)
|
||||
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_4_CH3)
|
||||
#define PWM_TMRA_4_CH3_PORT (GPIO_PORT_D)
|
||||
#define PWM_TMRA_4_CH3_PIN (GPIO_PIN_14)
|
||||
#define PWM_TMRA_4_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH3)
|
||||
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_4_CH4)
|
||||
#define PWM_TMRA_4_CH4_PORT (GPIO_PORT_D)
|
||||
#define PWM_TMRA_4_CH4_PIN (GPIO_PIN_15)
|
||||
#define PWM_TMRA_4_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMRA_5)
|
||||
#if defined(BSP_USING_PWM_TMRA_5_CH1)
|
||||
#define PWM_TMRA_5_CH1_PORT (GPIO_PORT_C)
|
||||
#define PWM_TMRA_5_CH1_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMRA_5_CH1_PIN_FUNC (GPIO_FUNC_5)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_5_CH2)
|
||||
#define PWM_TMRA_5_CH2_PORT (GPIO_PORT_C)
|
||||
#define PWM_TMRA_5_CH2_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMRA_5_CH2_PIN_FUNC (GPIO_FUNC_5)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_5_CH3)
|
||||
#define PWM_TMRA_5_CH3_PORT (GPIO_PORT_C)
|
||||
#define PWM_TMRA_5_CH3_PIN (GPIO_PIN_12)
|
||||
#define PWM_TMRA_5_CH3_PIN_FUNC (GPIO_FUNC_5)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_5_CH4)
|
||||
#define PWM_TMRA_5_CH4_PORT (GPIO_PORT_D)
|
||||
#define PWM_TMRA_5_CH4_PIN (GPIO_PIN_00)
|
||||
#define PWM_TMRA_5_CH4_PIN_FUNC (GPIO_FUNC_5)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH4)
|
||||
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -234,6 +221,25 @@
|
||||
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_INPUT_CAPTURE)
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A)
|
||||
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08)
|
||||
#define INPUT_CAPTURE_TMR6_1_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B)
|
||||
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02)
|
||||
#define INPUT_CAPTURE_TMR6_2_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A)
|
||||
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_12)
|
||||
#define INPUT_CAPTURE_TMR6_3_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
@@ -241,10 +247,8 @@
|
||||
/* USBFS Core*/
|
||||
#define USBF_DP_PORT (GPIO_PORT_A)
|
||||
#define USBF_DP_PIN (GPIO_PIN_12)
|
||||
#define USBF_DP_FUNC (GPIO_FUNC_10)
|
||||
#define USBF_DM_PORT (GPIO_PORT_A)
|
||||
#define USBF_DM_PIN (GPIO_PIN_11)
|
||||
#define USBF_DM_FUNC (GPIO_FUNC_10)
|
||||
#define USBF_VBUS_PORT (GPIO_PORT_A)
|
||||
#define USBF_VBUS_PIN (GPIO_PIN_09)
|
||||
#define USBF_VBUS_FUNC (GPIO_FUNC_10)
|
||||
|
||||
@@ -28,10 +28,10 @@ extern "C" {
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
@@ -39,6 +39,26 @@ extern "C" {
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC1_USING_DMA)
|
||||
#ifndef ADC1_EOCA_DMA_CONFIG
|
||||
#define ADC1_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC1_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC1_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC1_EOCA, \
|
||||
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC1_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC1_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC1_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC1_USING_DMA */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
@@ -51,10 +71,10 @@ extern "C" {
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
@@ -62,6 +82,26 @@ extern "C" {
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC2_USING_DMA)
|
||||
#ifndef ADC2_EOCA_DMA_CONFIG
|
||||
#define ADC2_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC2_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC2_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC2_EOCA, \
|
||||
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC2_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC2_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC2_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC2_USING_DMA */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -19,10 +19,6 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
@@ -40,25 +36,49 @@ extern "C" {
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
The following bit time configures are based on CAN Clock 8M
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
.u32Prescaler = 1, \
|
||||
.u32TimeSeg1 = 6, \
|
||||
.u32TimeSeg2 = 2, \
|
||||
.u32SJW = 2 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
.u32Prescaler = 1, \
|
||||
.u32TimeSeg1 = 7, \
|
||||
.u32TimeSeg2 = 3, \
|
||||
.u32SJW = 3 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 1, \
|
||||
.u32TimeSeg1 = 12, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 12, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 12, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
@@ -66,7 +86,7 @@ extern "C" {
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
@@ -74,15 +94,7 @@ extern "C" {
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
@@ -90,25 +102,9 @@ extern "C" {
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 200, \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
|
||||
@@ -133,6 +133,15 @@ extern "C" {
|
||||
#define UART3_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
|
||||
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC1_EOCA_DMA_CHANNEL DMA_CH2
|
||||
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#endif
|
||||
|
||||
/* DMA1 ch3 */
|
||||
@@ -202,6 +211,15 @@ extern "C" {
|
||||
#define UART1_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
|
||||
#define ADC2_EOCA_DMA_INSTANCE CM_DMA2
|
||||
#define ADC2_EOCA_DMA_CHANNEL DMA_CH0
|
||||
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA2_0
|
||||
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define ADC2_EOCA_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#endif
|
||||
|
||||
/* DMA2 ch1 */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user