ch569w-evt : add pwm driver, and spi_xfer bug fix (#6240)

add PWM driver, output checked with logic analyzer
spi_xfer() bug fix for cs_pin and message looping
uart pin_mode init moved to uart driver

bsp/wch/risc-v/Libraries/ch56x_drivers/SConscript

@@ -12,6 +12,9 @@ if GetDepend('SOC_SERIES_CH569'):
     if GetDepend('RT_USING_WDT'):
         src += ['ch56x_wdt.c']
 
+if GetDepend('RT_USING_PWM'):
+    src += ['ch56x_pwm.c']
+
 if GetDepend('RT_USING_HWTIMER'):
     src += ['ch56x_timer.c']
 

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_pwm.h

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-08-04     Emuzit            first version
+ */
+#ifndef __CH56X_PWM_H__
+#define __CH56X_PWM_H__
+
+#include "soc.h"
+#include "ch56x_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PWM_DEVICE_NAME     "pwmx"
+
+#define PWM_CHANNELS        4
+
+#define PWM0_PIN            GET_PIN(B, 15)
+#define PWM1_PIN            GET_PIN(A, 4)
+#define PWM2_PIN            GET_PIN(B, 1)
+#define PWM3_PIN            GET_PIN(B, 2)
+
+union _pwm_ctrl_mod
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t pwm0_out_en : 1;  // RW, PWM output enable
+        uint8_t pwm1_out_en : 1;
+        uint8_t pwm2_out_en : 1;
+        uint8_t pwm3_out_en : 1;
+        uint8_t pwm0_polar  : 1;  // RW, PWM output polarity
+        uint8_t pwm1_polar  : 1;
+        uint8_t pwm2_polar  : 1;
+        uint8_t pwm3_polar  : 1;
+    };
+};
+#define RB_PWM0_OUT_EN      0x01
+#define RB_PWM1_OUT_EN      0x02
+#define RB_PWM2_OUT_EN      0x04
+#define RB_PWM3_OUT_EN      0x08
+#define RB_PWM0_POLAR       0x10
+#define RB_PWM1_POLAR       0x20
+#define RB_PWM2_POLAR       0x40
+#define RB_PWM3_POLAR       0x80
+
+#define PWM_OUT_EN_MASK     0x0f
+
+union _pwm_ctrl_cfg
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t cycle_sel   : 1;  // RW, PWM cycle select, 0/1 for 256/255
+        uint8_t resv_1      : 7;
+    };
+};
+#define RB_PWM_CYCLE_SEL    0x01
+
+#define PWM_CYCLE_SEL_256   0
+#define PWM_CYCLE_SEL_255   1
+
+/*
+ * 0x00  R8_PWM_CTRL_MOD:   PWM control register
+ * 0x01  R8_PWM_CTRL_CFG:   PWM control configuration register
+ * 0x02  R8_PWM_CLOCK_DIV:  PWM clock divisor register
+ * 0x04  R8_PWM0_DATA:      PWM0 data holding register
+ * 0x05  R8_PWM1_DATA:      PWM1 data holding register
+ * 0x06  R8_PWM2_DATA:      PWM2 data holding register
+ * 0x07  R8_PWM3_DATA:      PWM3 data holding register
+ */
+struct pwm_registers
+{
+    union _pwm_ctrl_mod     CTRL_MOD;
+    union _pwm_ctrl_cfg     CTRL_CFG;
+    uint8_t                 CLOCK_DIV;
+    uint8_t                 resv_3;
+    union
+    {
+        uint32_t            R32_PWM_DATA;
+        uint8_t             PWM_DATA[4];
+        struct
+        {
+            uint8_t         PWM0_DATA;
+            uint8_t         PWM1_DATA;
+            uint8_t         PWM2_DATA;
+            uint8_t         PWM3_DATA;
+        };
+    };
+};
+CHECK_STRUCT_SIZE(struct pwm_registers, 8);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_spi.c

@@ -164,11 +164,25 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config
     return RT_EOK;
 }
 
-static rt_uint32_t _spi_xfer_1(struct rt_spi_device *device, struct rt_spi_message *message)
+/**
+ * @brief   Transfer SPI data for single message.
+ *          Message traversing is done by rt_spi_message().
+ *
+ * @param   device is pointer to the rt_spi_device device.
+ *
+ * @param   message is a link list for data/control information,
+ *          only the first entry is processed.
+ *          Note: ch56x can't do SPI send & recv at the same time.
+ *
+ * @return  `message->length1 if successful, 0 otherwise.
+ */
+static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
     struct spi_bus *spi_bus = (struct spi_bus *)device->bus;
     volatile struct spi_registers *sxreg = spi_bus->reg_base;
 
+    union _spi_ctrl_mod ctrl_mod;
+
     uint8_t *data;
     uint32_t size;
 
@@ -179,22 +193,28 @@ static rt_uint32_t _spi_xfer_1(struct rt_spi_device *device, struct rt_spi_messa
     if (size == 0 || size > 4095)
         return 0;
 
+    ctrl_mod.reg = sxreg->CTRL_MOD.reg | RB_SPI_ALL_CLEAR;
+
     /* ch56x can't do SPI send & recv at the same time */
     if (message->send_buf && !message->recv_buf)
     {
         data = (uint8_t *)message->send_buf;
-        sxreg->CTRL_MOD.fifo_dir = SPI_FIFO_DIR_OUTPUT;
+        ctrl_mod.fifo_dir = SPI_FIFO_DIR_OUTPUT;
     }
     else if (!message->send_buf && message->recv_buf)
     {
         data = (uint8_t *)message->recv_buf;
-        sxreg->CTRL_MOD.fifo_dir = SPI_FIFO_DIR_INPUT;
+        ctrl_mod.fifo_dir = SPI_FIFO_DIR_INPUT;
     }
     else
     {
         return 0;
     }
 
+    sxreg->CTRL_MOD.reg = ctrl_mod.reg;
+    ctrl_mod.all_clear = 0;
+    sxreg->CTRL_MOD.reg = ctrl_mod.reg;
+
     /* set MISO pin direction to match xfer if shared SI/SO pin */
     if (device->config.mode & RT_SPI_3WIRE)
     {
@@ -202,7 +222,7 @@ static rt_uint32_t _spi_xfer_1(struct rt_spi_device *device, struct rt_spi_messa
         rt_pin_mode(spi_bus->miso_pin, mode);
     }
 
-    cs_pin = (rt_base_t)device->user_data;
+    cs_pin = (rt_base_t)device->parent.user_data;
     cs_high = device->config.mode & RT_SPI_CS_HIGH;
 
     if (message->cs_take)
@@ -236,6 +256,8 @@ static rt_uint32_t _spi_xfer_1(struct rt_spi_device *device, struct rt_spi_messa
 
     /* wait for transfer done */
     while (sxreg->TOTAL_COUNT > 0);
+    /* disable DMA, anyway */
+    sxreg->CTRL_CFG.dma_enable = 0;
 
     /* non-DMA recv => read data from FIFO */
     if (size > 0)
@@ -259,26 +281,6 @@ static rt_uint32_t _spi_xfer_1(struct rt_spi_device *device, struct rt_spi_messa
     return message->length;
 }
 
-static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
-{
-    uint32_t total_xsize = 0;
-    uint32_t xsize;
-
-    RT_ASSERT(device != NULL);
-    RT_ASSERT(message != NULL);
-
-    while (message != RT_NULL)
-    {
-        xsize = _spi_xfer_1(device, message);
-        if (xsize != message->length)
-            return 0;
-        total_xsize += xsize;
-        message = message->next;
-    }
-
-    return total_xsize;
-}
-
 static const struct rt_spi_ops spi_ops =
 {
     .configure = spi_configure,

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_spi.h

@@ -179,9 +179,6 @@ union _spi_int_flag
  * 0x14  R32_SPIx_DMA_NOW:    SPI DMA current address
  * 0x18  R32_SPIx_DMA_BEG:    SPI DMA start address
  * 0x1c  R32_SPIx_DMA_END:    SPI DMA end address
- *
- * CAVEAT: gcc (as of 8.2.0) tends to read 32-bit word for bit field test.
- * Be careful for those with side effect for read (e.g. RBR, IIR).
  */
 struct spi_registers
 {

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_sys.c

@@ -101,12 +101,15 @@ void sys_slp_clk_off0(uint8_t bits, int off)
     uint8_t u8v;
 
     u8v = sys->SLP_CLK_OFF0.reg;
-    u8v = off ? (u8v | bits) : (u8v & ~bits);
-    level = rt_hw_interrupt_disable();
-    sys_safe_access_enter(sys);
-    sys->SLP_CLK_OFF0.reg = u8v;
-    sys_safe_access_leave(sys);
-    rt_hw_interrupt_enable(level);
+    if ((u8v & bits) != (off ? bits : 0))
+    {
+        u8v = off ? (u8v | bits) : (u8v & ~bits);
+        level = rt_hw_interrupt_disable();
+        sys_safe_access_enter(sys);
+        sys->SLP_CLK_OFF0.reg = u8v;
+        sys_safe_access_leave(sys);
+        rt_hw_interrupt_enable(level);
+    }
 }
 
 /**
@@ -123,12 +126,15 @@ void sys_slp_clk_off1(uint8_t bits, int off)
     uint8_t u8v;
 
     u8v = sys->SLP_CLK_OFF1.reg;
-    u8v = off ? (u8v | bits) : (u8v & ~bits);
-    level = rt_hw_interrupt_disable();
-    sys_safe_access_enter(sys);
-    sys->SLP_CLK_OFF1.reg = u8v;
-    sys_safe_access_leave(sys);
-    rt_hw_interrupt_enable(level);
+    if ((u8v & bits) != (off ? bits : 0))
+    {
+        u8v = off ? (u8v | bits) : (u8v & ~bits);
+        level = rt_hw_interrupt_disable();
+        sys_safe_access_enter(sys);
+        sys->SLP_CLK_OFF1.reg = u8v;
+        sys_safe_access_leave(sys);
+        rt_hw_interrupt_enable(level);
+    }
 }
 
 /**
@@ -171,12 +177,15 @@ int sys_clk_off_by_irqn(uint8_t irqn, int off)
             volatile uint8_t *cxreg = (void *)sys;
             rt_base_t level;
             u8v = cxreg[offset];
-            u8v = off ? (u8v | bitpos) : (u8v & ~bitpos);
-            level = rt_hw_interrupt_disable();
-            sys_safe_access_enter(sys);
-            cxreg[offset] = u8v;
-            sys_safe_access_leave(sys);
-            rt_hw_interrupt_enable(level);
+            if ((u8v & bitpos) != (off ? bitpos : 0))
+            {
+                u8v = off ? (u8v | bitpos) : (u8v & ~bitpos);
+                level = rt_hw_interrupt_disable();
+                sys_safe_access_enter(sys);
+                cxreg[offset] = u8v;
+                sys_safe_access_leave(sys);
+                rt_hw_interrupt_enable(level);
+            }
         }
     }
 

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_uart.c

@@ -16,6 +16,7 @@
 #else
     #include <drivers/serial.h>
 #endif
+#include <drivers/pin.h>
 #include "ch56x_sys.h"
 #include "ch56x_uart.h"
 #include "isr_sp.h"
@@ -25,11 +26,17 @@
     #error "Please define at least one UARTx"
 #endif
 
+/* Type of irqn/rxd_pin/txd_pin are per uart driver perspective
+ * to save some space, still compatible to RT api call, anyway.
+*/
 struct serial_device
 {
     struct rt_serial_device parent;
     volatile struct uart_registers *reg_base;
-    irq_number_t irqn;
+    uint8_t irqn;
+    uint8_t resv;
+    uint8_t rxd_pin;
+    uint8_t txd_pin;
     char *name;
 };
 
@@ -38,6 +45,8 @@ static struct serial_device serial_device_0 =
 {
     .reg_base = (struct uart_registers *)UART0_REG_BASE,
     .irqn = UART0_IRQn,
+    .rxd_pin = UART_RXD0_PIN,
+    .txd_pin = UART_TXD0_PIN,
     .name = "uart0",
 };
 #endif
@@ -47,6 +56,8 @@ static struct serial_device serial_device_1 =
 {
     .reg_base = (struct uart_registers *)UART1_REG_BASE,
     .irqn = UART1_IRQn,
+    .rxd_pin = UART_RXD1_PIN,
+    .txd_pin = UART_TXD1_PIN,
     .name = "uart1",
 };
 #endif
@@ -56,6 +67,8 @@ static struct serial_device serial_device_2 =
 {
     .reg_base = (struct uart_registers *)UART2_REG_BASE,
     .irqn = UART2_IRQn,
+    .rxd_pin = UART_RXD2_PIN,
+    .txd_pin = UART_TXD2_PIN,
     .name = "uart2",
 };
 #endif
@@ -65,6 +78,8 @@ static struct serial_device serial_device_3 =
 {
     .reg_base = (struct uart_registers *)UART3_REG_BASE,
     .irqn = UART3_IRQn,
+    .rxd_pin = UART_RXD3_PIN,
+    .txd_pin = UART_TXD3_PIN,
     .name = "uart3",
 };
 #endif
@@ -233,15 +248,25 @@ int rt_hw_uart_init(void)
     devices[n++] = &serial_device_0;
 #endif
 
-    /* IMPORTANT: pin mode should be set properly @ board init */
-
     while (--n >= 0)
     {
-        uint32_t flag;
+        uint32_t flag, txd_pin, rxd_pin;
         struct serial_device *serial = devices[n];
         serial->parent.ops = &uart_ops;
         serial->parent.config = config;
 
+        txd_pin = serial->txd_pin;
+        rxd_pin = serial->rxd_pin;
+#ifdef BSP_USING_UART0_PIN_ALT
+        if (serial->irqn == UART0_IRQn)
+        {
+            txd_pin = UART_TXD0_ALT;
+            rxd_pin = UART_RXD0_ALT;
+        }
+#endif
+        rt_pin_mode(txd_pin, PIN_MODE_OUTPUT);
+        rt_pin_mode(rxd_pin, PIN_MODE_INPUT_PULLUP);
+
         sys_clk_off_by_irqn(serial->irqn, SYS_SLP_CLK_ON);
 
         flag = RT_DEVICE_FLAG_RDWR   |

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_uart.h

@@ -11,11 +11,24 @@
 #define __CH56X_UART_H__
 
 #include "soc.h"
+#include "ch56x_gpio.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define UART_RXD0_ALT       GET_PIN(A, 5)
+#define UART_TXD0_ALT       GET_PIN(A, 6)
+
+#define UART_RXD0_PIN       GET_PIN(B, 5)
+#define UART_TXD0_PIN       GET_PIN(B, 6)
+#define UART_RXD1_PIN       GET_PIN(A, 7)
+#define UART_TXD1_PIN       GET_PIN(A, 8)
+#define UART_RXD2_PIN       GET_PIN(A, 2)
+#define UART_TXD2_PIN       GET_PIN(A, 3)
+#define UART_RXD3_PIN       GET_PIN(B, 3)
+#define UART_TXD3_PIN       GET_PIN(B, 4)
+
 #ifndef UART_FIFO_SIZE
 #define UART_FIFO_SIZE      8
 #endif

bsp/wch/risc-v/Libraries/ch56x_drivers/soc.h

@@ -13,6 +13,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <assert.h>
+#include <rtdef.h>
 
 #if !defined(SOC_CH567) && \
     !defined(SOC_CH568) && \

bsp/wch/risc-v/ch569w-evt/.config

@@ -110,7 +110,7 @@ CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
-CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
@@ -123,14 +123,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-CONFIG_RT_USING_SPI=y
-# CONFIG_RT_USING_SPI_BITOPS is not set
-# CONFIG_RT_USING_QSPI is not set
-# CONFIG_RT_USING_SPI_MSD is not set
-# CONFIG_RT_USING_SFUD is not set
-# CONFIG_RT_USING_ENC28J60 is not set
-# CONFIG_RT_USING_SPI_WIFI is not set
-CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
@@ -313,6 +307,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_RAPIDJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
 
 #
 # XML: Extensible Markup Language
@@ -491,8 +486,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_RTT_ESP_IDF is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
@@ -656,13 +653,8 @@ CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
-CONFIG_BSP_USING_TIMER=y
-CONFIG_BSP_USING_TMR0=y
-CONFIG_BSP_USING_TMR1=y
-# CONFIG_BSP_USING_TMR2 is not set
-CONFIG_BSP_USING_SPI=y
-CONFIG_BSP_USING_SPI0=y
-# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_TIMER is not set
+# CONFIG_BSP_USING_SPI is not set
 
 #
 # Onboard Peripheral Drivers

bsp/wch/risc-v/ch569w-evt/board/Kconfig

@@ -17,20 +17,25 @@ config BSP_USING_UART
 
     if BSP_USING_UART
         config BSP_USING_UART0
-        bool "using UART0"
-        default n
+            bool "using UART0"
+            default n
+            if BSP_USING_UART0
+                config BSP_USING_UART0_PIN_ALT
+                    bool "UART0 PIN_ALTERNATE (PA5/PA6)"
+                    default n
+            endif
 
         config BSP_USING_UART1
-        bool "using UART1"
-        default y
+            bool "using UART1"
+            default y
 
         config BSP_USING_UART2
-        bool "using UART2"
-        default n
+            bool "using UART2"
+            default n
 
         config BSP_USING_UART3
-        bool "using UART3"
-        default n
+            bool "using UART3"
+            default n
     endif
 
 config BSP_USING_TIMER
@@ -40,16 +45,16 @@ config BSP_USING_TIMER
 
     if BSP_USING_TIMER
         config BSP_USING_TMR0
-        bool "using TMR0"
-        default y
+            bool "using TMR0"
+            default n
 
         config BSP_USING_TMR1
-        bool "using TMR1"
-        default n
+            bool "using TMR1"
+            default n
 
         config BSP_USING_TMR2
-        bool "using TMR2"
-        default n
+            bool "using TMR2"
+            default n
     endif
 
 config BSP_USING_SPI

bsp/wch/risc-v/ch569w-evt/board/board.c

@@ -69,9 +69,6 @@ void rt_hw_board_init()
 #endif
 
 #ifdef RT_USING_CONSOLE
-    /* console is uart1, TXD1/RXD1 : PA8/PA7 */
-    rt_pin_mode(GET_PIN(A, 8), PIN_MODE_OUTPUT);
-    rt_pin_mode(GET_PIN(A, 7), PIN_MODE_INPUT_PULLUP);
     rt_hw_uart_init();
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif

bsp/wch/risc-v/ch569w-evt/board/board.h

@@ -14,6 +14,7 @@
 #include "ch56x_sys.h"
 #include "ch56x_gpio.h"
 #include "ch56x_spi.h"
+#include "ch56x_pwm.h"
 
 #define LED0_PIN            GET_PIN(B, 24)
 #define LED1_PIN            GET_PIN(B, 22)

bsp/wch/risc-v/ch569w-evt/rtconfig.h

@@ -70,10 +70,7 @@
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_HWTIMER
 #define RT_USING_PIN
-#define RT_USING_SPI
-#define RT_USING_WDT
 
 /* Using USB */
 
@@ -181,11 +178,6 @@
 
 #define BSP_USING_UART
 #define BSP_USING_UART1
-#define BSP_USING_TIMER
-#define BSP_USING_TMR0
-#define BSP_USING_TMR1
-#define BSP_USING_SPI
-#define BSP_USING_SPI0
 
 /* Onboard Peripheral Drivers */