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update stm32f4xx and fpu test.

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1903 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
2011-12-31 21:42:12 +00:00
parent 25ab97df39
commit 76e81a9977
8 changed files with 408 additions and 251 deletions
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174
bsp/stm32f40x/applications/application.c
View File

@@ -17,6 +17,8 @@
*/
/*@{*/
#include <stdio.h>
#include "stm32f4xx.h"
#include <board.h>
#include <rtthread.h>
@@ -46,98 +48,136 @@ void rt_init_thread_entry(void* parameter)
lwip_sys_init();
rt_kprintf("TCP/IP initialized!\n");
}
{
extern void eth_to_can_init(void);
extern void can_to_eth_init(void);
extern void upnp_init(void);
extern void setting_init(void);
setting_init();
eth_to_can_init();
can_to_eth_init();
upnp_init();
}
#endif
//FS
//GUI
}
float f_var1;
float f_var2;
float f_var3;
float f_var4;
ALIGN(RT_ALIGN_SIZE)
static char thread_led_stack[1024];
struct rt_thread thread_led;
static void rt_thread_entry_led(void* parameter)
static char thread_led1_stack[1024];
struct rt_thread thread_led1;
static void rt_thread_entry_led1(void* parameter)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* GPIOD Periph clock enable */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
/* GPIOD Periph clock enable */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
/* Configure PD12, PD13, PD14 and PD15 in output pushpull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Configure PD12, PD13, PD14 and PD15 in output pushpull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
while (1)
{
/* PD12 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_12);
f_var1 = 3.141592653;
f_var2 = 123.456;
f_var3 = 0.123456789;
f_var4 = 1.00001;
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
while (1)
{
/* PD12 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_12);
/* PD13 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_13);
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
f_var3 += f_var4;
f_var4 = f_var4 * f_var4;
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
/* PD13 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_13);
/* PD14 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_14);
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
f_var3 += f_var4;
f_var4 = f_var4 * f_var4;
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
/* PD14 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_14);
/* PD15 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_15);
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND/2);
f_var3 += f_var4;
f_var4 = f_var4 * f_var4;
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND*2);
/* PD15 to be toggled */
GPIO_SetBits(GPIOD, GPIO_Pin_15);
GPIO_ResetBits(GPIOD, GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15);
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND*2);
f_var3 += f_var4;
f_var4 = f_var4 * f_var4;
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND);
}
GPIO_ResetBits(GPIOD, GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15);
/* Insert delay */
rt_thread_delay(RT_TICK_PER_SECOND);
f_var3 += f_var4;
f_var4 = f_var4 * f_var4;
}
}
ALIGN(RT_ALIGN_SIZE)
static char thread_led2_stack[1024];
struct rt_thread thread_led2;
static void rt_thread_entry_led2(void* parameter)
{
float f_var_me;
char str_buffer[256];
while(1)
{
f_var_me = f_var1 * f_var2 + f_var3;
sprintf(str_buffer, "%f", f_var_me);
rt_kprintf("thread1 %s\r\n", str_buffer);
rt_thread_delay(RT_TICK_PER_SECOND);
}
}
int rt_application_init()
{
// rt_thread_t init_thread;
//
//#if (RT_THREAD_PRIORITY_MAX == 32)
// init_thread = rt_thread_create("init",
// rt_init_thread_entry, RT_NULL,
// 2048, 8, 20);
//#else
// init_thread = rt_thread_create("init",
// rt_init_thread_entry, RT_NULL,
// 2048, 80, 20);
//#endif
//
// if (init_thread != RT_NULL)
// rt_thread_startup(init_thread);
rt_thread_t init_thread;
#if (RT_THREAD_PRIORITY_MAX == 32)
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, 8, 20);
#else
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, 80, 20);
#endif
if (init_thread != RT_NULL)
rt_thread_startup(init_thread);
//------- init led1 thread
rt_thread_init(&thread_led,
"led",
rt_thread_entry_led,
rt_thread_init(&thread_led1,
"led1",
rt_thread_entry_led1,
RT_NULL,
&thread_led_stack[0],
1024,11,5);
// sizeof(thread_led_stack),11,5);
rt_thread_startup(&thread_led);
&thread_led1_stack[0],
sizeof(thread_led1_stack),11,5);
rt_thread_startup(&thread_led1);
//------- init led2 thread
rt_thread_init(&thread_led2,
"led2",
rt_thread_entry_led2,
RT_NULL,
&thread_led2_stack[0],
sizeof(thread_led2_stack),11,5);
rt_thread_startup(&thread_led2);
return 0;
}

17
bsp/stm32f40x/applications/startup.c
View File

@@ -32,12 +32,14 @@ extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
//extern int Image$$RW_IRAM1$$ZI$$Limit;
extern int Image$$ER_ZI$$ZI$$Limit;
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define STM32_SRAM_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define STM32_SRAM_BEGIN (&__bss_end)
#endif
/*******************************************************************************
@@ -78,16 +80,7 @@ void rtthread_startup(void)
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)STM32_SRAM_END);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
#endif
#endif
rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END);
/* init scheduler system */
rt_system_scheduler_init();

242
bsp/stm32f40x/project.uvopt
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File diff suppressed because it is too large Load Diff

72
bsp/stm32f40x/project.uvproj
View File

@@ -43,14 +43,14 @@
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\obj\</OutputDirectory>
<OutputName>project</OutputName>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread-stm32f4xx</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\obj\</ListingPath>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
@@ -158,7 +158,7 @@
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4100</DriverSelection>
</Flash1>
@@ -208,7 +208,7 @@
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
@@ -334,7 +334,7 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
@@ -344,9 +344,9 @@
<uThumb>0</uThumb>
<VariousControls>
<MiscControls></MiscControls>
<Define>STM32F4XX, USE_STDPERIPH_DRIVER</Define>
<Define>USE_STDPERIPH_DRIVER</Define>
<Undefine></Undefine>
<IncludePath>Libraries\CMSIS\ST\STM32F4xx\Include;..\..\include;drivers;.;applications;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;Libraries\STM32F4xx_StdPeriph_Driver\inc;..\..\components\finsh;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x</IncludePath>
<IncludePath>.;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\STM32F4xx_StdPeriph_Driver\inc;applications;drivers</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -365,7 +365,7 @@
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
@@ -431,11 +431,6 @@
<FileType>1</FileType>
<FilePath>Libraries\CMSIS\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c</FilePath>
</File>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileType>2</FileType>
<FilePath>Libraries\CMSIS\ST\STM32F4xx\Source\Templates\arm\startup_stm32f4xx.s</FilePath>
</File>
<File>
<FileName>misc.c</FileName>
<FileType>1</FileType>
@@ -591,30 +586,35 @@
<FileType>1</FileType>
<FilePath>Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c</FilePath>
</File>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileType>2</FileType>
<FilePath>Libraries\CMSIS\ST\STM32F4xx\Source\Templates\arm\startup_stm32f4xx.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\thread.c</FilePath>
<FilePath>..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
<FilePath>..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
@@ -627,14 +627,9 @@
<FilePath>..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\object.c</FilePath>
<FilePath>..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
@@ -642,19 +637,24 @@
<FilePath>..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\ipc.c</FilePath>
<FilePath>..\..\src\object.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\idle.c</FilePath>
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mem.c</FilePath>
<FilePath>..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>

2
bsp/stm32f40x/rtconfig.h
View File

@@ -6,7 +6,7 @@
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 8
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32

4
bsp/stm32f40x/rtconfig.py
View File

@@ -31,8 +31,8 @@ if PLATFORM == 'gcc':
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=vfp -mfloat-abi=softfp -ffunction-sections -fdata-sections'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'

134
bsp/stm32f40x/stm32_rom.ld Normal file
View File

@@ -0,0 +1,134 @@
/*
* linker script for STM32F10x with GNU ld
* bernard.xiong 2009-10-14
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x100;
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

14
bsp/stm32f40x/template.uvproj
View File

@@ -43,14 +43,14 @@
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\obj\</OutputDirectory>
<OutputName>project</OutputName>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread-stm32f4xx</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\obj\</ListingPath>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
@@ -158,7 +158,7 @@
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4100</DriverSelection>
</Flash1>
@@ -208,7 +208,7 @@
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
@@ -334,7 +334,7 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
@@ -365,7 +365,7 @@
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>