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bsp/nxp：Separate nxp_imx library (#10273)

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This commit is contained in:
hydevcode
2025-05-15 15:44:47 +08:00
committed by GitHub
parent ab1b238d0a
commit 759858127e
3062 changed files with 803 additions and 6383204 deletions
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.github/ALL_BSP_COMPILE.json
+6 -1
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@@ -227,15 +227,19 @@
"nxp/lpc/lpc54114-lite",
"nxp/lpc/lpc176x",
"nxp/imx/imx6sx/cortex-a9",
"nxp/imx/imx6ul",
"nxp/imx/imxrt/imxrt1052-atk-commander",
"nxp/imx/imxrt/imxrt1052-fire-pro",
"nxp/imx/imxrt/imxrt1052-nxp-evk",
"nxp/imx/imxrt/imxrt1052-seeed-ArchMix",
"nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S",
"nxp/imx/imxrt/imxrt1060-nxp-evk",
"nxp/imx/imxrt/imxrt1064-nxp-evk",
"nxp/imx/imxrt/imxrt1021-nxp-evk",
"nxp/imx/imxrt/imxrt1170-nxp-evk",
"nxp/mcx/mcxn/frdm-mcxn947",
"nxp/mcx/mcxn/frdm-mcxn236",
"nxp/mcx/mcxc/frdm-mcxc444",
"nxp/mcx/mcxa/frdm-mcxa153",
"nxp/mcx/mcxa/frdm-mcxa156",
"renesas/ebf_qi_min_6m5",
@@ -453,7 +457,8 @@
"RTT_TOOL_CHAIN": "sourcery-arm",
"RTT_SMART_TOOL_CHAIN": "arm-linux-musleabi",
"SUB_RTT_BSP": [
"qemu-vexpress-a9"
"qemu-vexpress-a9",
"nxp/imx/imx6ull-smart"
]
},
{
bsp/nxp/imx/imx6sx/cortex-a9/Kconfig
+1
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@@ -15,6 +15,7 @@ config SOC_MCIMX6X4
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select PKG_USING_NXP_IMX6SX_DRIVER
default y
config RT_USING_UART1
bsp/nxp/imx/imx6sx/cortex-a9/SConstruct
+17 -2
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@@ -10,6 +10,23 @@ else:
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "nxp-imx6sx-sdk-latest"),
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n==============================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("==============================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
@@ -27,7 +44,5 @@ Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT,has_libcpu=True)
objs += SConscript('../iMX6_Platform_SDK/SConscript', variant_dir='build/iMX6_Platform_SDK/SConscript', duplicate=0)
# make a building
DoBuilding(TARGET, objs)
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/Doxyfile
-1924
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File diff suppressed because it is too large Load Diff
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/LICENSE.txt
-24
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@@ -1,24 +0,0 @@
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
o Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
o Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
o Neither the name of Freescale Semiconductor, Inc. nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/Makefile
-167
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@@ -1,167 +0,0 @@
#-------------------------------------------------------------------------------
# Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
#
# THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
# SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#-------------------------------------------------------------------------------
#
# Top-level Makefile.
#
# This file is responsible for building all libraries and applications.
#
# Targets:
# - all
# - sdk
# - board
# - sdk_unit_test
# - power_modes_test
# - obds
# - gpu_demo
# - smp_primes
# - stream
# - usb_hid_mouse
# - httpd
# - ping
# - clean
# - clean_sdk
# - clean_board
# - clean_sdk_unit_test
# - clean_power_modes_test
# - clean_obds
# - clean_gpu_demo
# - clean_smp_primes
# - clean_stream
# - clean_usb_hid_mouse
# - clean_httpd
# - clean_ping
#
# The clean targets work with any combination of configuration variables. For
# example, clean_sdk with TARGET set will clean libsdk for only that TARGET, while
# clean_sdk without TARGET set will clean libsdk in all targets.
#
include mk/common.mk
# Turn off parallel jobs for this makefile only. Child makefiles will still use the
# specified number of jobs. This isn't strictly necessary, and actually slows the build
# a little bit, but greatly improves the readability of the log output.
.NOTPARALLEL:
# Determine if the target is either the MX6DQ or MX6SDL.
ifeq "$(TARGET)" "mx6dq"
is_dq_or_sdl = 1
else ifeq "$(TARGET)" "mx6sdl"
is_dq_or_sdl = 1
endif
# Library subdirectories that the apps depend upon. Handled automatically by targets.mk.
SUBDIRS = \
sdk \
lwip \
$(BOARD_ROOT)
# List of all applications to build. Applications must reside in the apps directory.
ALL_APPS = \
filesystem \
httpd \
obds \
ping \
power_modes_test \
sdk_unit_test \
stream \
usb_hid_mouse
# Apps that are only built for MX6DQ and MX6SDL.
ifdef is_dq_or_sdl
ALL_APPS += \
caam_blob_gen \
gpu_demo \
smp_primes
endif
# Default target.
.PHONY: all
all: $(sort $(ALL_APPS)) ;
# App targets. All apps depend on the listed subdirectories.
.PHONY: ALL_APPS
$(ALL_APPS): $(SUBDIRS)
@$(call printmessage,build,Building, $@ ,gray,[$(TARGET) $(BOARD) $(BOARD_REVISION)],,\n)
@$(MAKE) $(silent_make) -r -C apps/$@
# Print message before recursive into subdirs.
$(SUBDIRS)::
@$(call printmessage,build,Building, $(@F) ,gray,[$(TARGET) $(BOARD) $(BOARD_REVISION)],,\n)
# Target with a simple name for building the board package.
.PHONY: board
board: $(BOARD_ROOT)
# Target to clean everything.
.PHONY: clean
clean:
@echo "Deleting output directory..."
@rm -rf output
@echo "done."
# Target to clean just the sdk library and objects.
.PHONY: clean_sdk
clean_sdk:
ifdef TARGET
rm -rf $(LIBSDK) $(OUTPUT_ROOT)/lib/obj/sdk
else
rm -rf $(SDK_ROOT)/output/*/lib/libsdk.a $(SDK_ROOT)/output/*/lib/obj/sdk
endif
# Target to clean the board library and objects.
.PHONY: clean_board
clean_board:
ifdef TARGET
ifdef BOARD
rm -rf $(LIBBOARD) $(OUTPUT_ROOT)/lib/obj/board_$(BOARD_WITH_REV)
else
rm -rf $(OUTPUT_ROOT)/lib/libboard* $(OUTPUT_ROOT)/lib/obj/board_*
endif
else
rm -rf $(SDK_ROOT)/output/*/lib/libboard* $(SDK_ROOT)/output/*/lib/obj/board_*
endif
# Set up targets to clean each of the applications. For an app "foo", the target to clean
# just that app is "clean_foo". If no TARGET is passed to make, the app is cleaned
# for all targets.
ALL_APP_CLEAN_TARGETS := $(addprefix clean_,$(ALL_APPS))
.PHONY: $(ALL_APP_CLEAN_TARGETS)
$(ALL_APP_CLEAN_TARGETS):
ifdef TARGET
ifdef BOARD
ifdef BOARD_REVISION
ifdef BOARD_REVISION_IS_DEFAULT
# Clean all revs of the board.
rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD)_rev_*
else
# Specific rev specified so clean just that one rev.
rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD_WITH_REV)
endif
else
# Clean all revs of the board.
rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD)_rev_*
endif
else
# Clean all boards of the app.
rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)
endif
else
# Clean all boards and targets of the app.
rm -rf $(SDK_ROOT)/output/*/$(patsubst clean_%,%,$@)
endif
include mk/targets.mk
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/README.pdf
BIN
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bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/SConscript
-123
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@@ -1,123 +0,0 @@
from building import *
cwd = GetCurrentDir()
# sdk/utility/src/runtime_support.c
# sdk/drivers/keypad/src/keypad_port.c
# sdk/drivers/snvs/src/snvs.c
# sdk/core/src/interrupt.c
src = Split('''
board/common/board_network.c
board/common/board_io_expanders.c
board/common/hardware_modules.c
apps/common/platform_init.c
apps/common/print_version.c
sdk/utility/src/sdk_version.c
sdk/utility/src/text_color.c
sdk/utility/src/menu.c
sdk/utility/src/spinlock.c
sdk/utility/src/system_util.c
sdk/core/src/ccm_pll.c
sdk/core/src/abort_handler.c
sdk/core/src/mmu.c
sdk/core/src/armv7_cache.c
sdk/core/src/gic.c
sdk/common/ioexpander/src/max7310.c
sdk/common/pmic/pfuse/pf0100.c
sdk/common/profile/profile.c
sdk/drivers/hdmi/src/hdmi_tx.c
sdk/drivers/hdmi/src/hdmi_tx_audio.c
sdk/drivers/hdmi/src/hdmi_common.c
sdk/drivers/hdmi/src/hdmi_tx_phy.c
sdk/drivers/vdoa/src/vdoa.c
sdk/drivers/i2c/src/software_i2c_port.cpp
sdk/drivers/i2c/src/imx_i2c_slave.c
sdk/drivers/i2c/src/i2c_device.cpp
sdk/drivers/i2c/src/imx_i2c.c
sdk/drivers/pmu/src/pmu_driver.cpp
sdk/drivers/sdma/src/sdma.c
sdk/drivers/sdma/src/sdma_script_info.c
sdk/drivers/eim/src/eim.c
sdk/drivers/timer/src/epit.c
sdk/drivers/timer/src/gpt.c
sdk/drivers/timer/src/timer.c
sdk/drivers/ipu/src/ipu_ic.c
sdk/drivers/ipu/src/ips_disp_panel.c
sdk/drivers/ipu/src/ipu_csi.c
sdk/drivers/ipu/src/ipu_dmfc.c
sdk/drivers/ipu/src/ipu_di.c
sdk/drivers/ipu/src/ipu_vdi.c
sdk/drivers/ipu/src/ipu_dc.c
sdk/drivers/ipu/src/ipu_idmac.c
sdk/drivers/ipu/src/ipu_dp.c
sdk/drivers/ipu/src/ipu_common.c
sdk/drivers/pcie/src/pcie_phy.c
sdk/drivers/pcie/src/pcie.c
sdk/drivers/pcie/src/pcie_prot.c
sdk/drivers/gpio/src/gpio.c
sdk/drivers/gpio/src/gpio_pin.cpp
sdk/drivers/gpio/src/imx6sdl_gpio_map.c
sdk/drivers/ocotp/src/ocotp.c
sdk/drivers/usb/src/mx6x_usb.c
sdk/drivers/usb/src/usb_common.c
sdk/drivers/usb/src/usbd_drv.c
sdk/drivers/usb/src/usbh_drv.c
sdk/drivers/caam/src/caam.c
sdk/drivers/uart/src/imx_uart.c
sdk/drivers/enet/src/enet_drv.c
sdk/drivers/tempmon/src/tempmon.c
sdk/drivers/epdc/src/mxc_epdc.c
sdk/drivers/cpu_utility/src/cpu_workpoint.c
sdk/drivers/cpu_utility/src/cpu_multicore.c
sdk/drivers/cpu_utility/src/cpu_get_cores.c
sdk/drivers/gpmi/src/gpmi_dma_components.cpp
sdk/drivers/gpmi/src/gpmi_dma_sequences.cpp
sdk/drivers/gpmi/src/bch_ecc.c
sdk/drivers/gpmi/src/gpmi_dma_isr.cpp
sdk/drivers/gpmi/src/gpmi_nand_operations.cpp
sdk/drivers/gpmi/src/gpmi.cpp
sdk/drivers/board_id/src/board_id.c
sdk/drivers/audio/src/imx_esai.c
sdk/drivers/audio/src/snd_card.c
sdk/drivers/audio/src/wm8958_dac.c
sdk/drivers/audio/src/imx-ssi.c
sdk/drivers/audio/src/imx_audmux.c
sdk/drivers/audio/src/sgtl5000.c
sdk/drivers/audio/src/imx_spdif.c
sdk/drivers/audio/src/cs42888.c
sdk/drivers/audio/src/wm8962.c
sdk/drivers/ldb/src/ldb.c
sdk/drivers/spi/src/ecspi.c
sdk/drivers/spi/src/spi_device.cpp
sdk/drivers/accelerometer/src/mma8451.c
sdk/drivers/usdhc/src/usdhc_sd.c
sdk/drivers/usdhc/src/usdhc_host.c
sdk/drivers/usdhc/src/usdhc_mmc.c
sdk/drivers/usdhc/src/usdhc.c
sdk/drivers/pwm/src/pwm.c
sdk/drivers/video/src/adv7180.c
sdk/drivers/rtc/src/rtc.c
sdk/drivers/rtc/src/srtc.c
sdk/drivers/flexcan/src/can.c
''')
CPPPATH = [
cwd + '/board/common',
cwd + '/board/mx6sdl/sabre_ai',
cwd + '/board/mx6sdl/sabre_ai/rev_b_iomux',
cwd + '/sdk',
cwd + '/sdk/common',
cwd + '/sdk/core',
cwd + '/sdk/drivers',
cwd + '/sdk/utility',
cwd + '/sdk/include',
cwd + '/sdk/include/mx6sdl',
cwd + '/sdk/include/mx6sdl/registers'
]
CPPDEFINES = ['CHIP_MX6SDL', 'BOARD_SABRE_AI', 'BOARD_REV_B']
group = DefineGroup('PlatformSDK', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/basic_sdk_app.ld.S
-293
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@@ -1,293 +0,0 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
/*
* OCRAM
*/
#if defined(CHIP_MX6SDL) || defined(CHIP_MX6SL)
// mx6sl and mx6sdl both have 128kB of OCRAM.
#define OCRAM_LEN 128K
#elif defined(CHIP_MX6DQ)
// mx6dq has 256kB of OCRAM
#define OCRAM_LEN 256K
#else
#error Unknown chip!
#endif
/*
* External DDR
*/
#if defined(CHIP_MX6SL)
// mx6sl has only one DDR chip select that starts at a different address
#define DDR_ORG 0x80000000
#elif defined(CHIP_MX6SDL) || defined(CHIP_MX6DQ)
// mx6dq and mx6sdl DDR memory starts at this address
#define DDR_ORG 0x10000000
#else
#error Unknown chip!
#endif
#if defined(BOARD_SABRE_AI)
// mx6dq and mx6sdl sabre-ai board has 2GB of DDR3
#define DDR_LEN 2048M
#else
// all other boards have 1GB of DDR3
#define DDR_LEN 1024M
#endif
// Maximum size of the signed image
#if !defined(MAX_IMAGE_SIZE)
#define MAX_IMAGE_SIZE 4M
#endif
// Maximum size of HAB CSF data
#if !defined(MAX_HAB_CSF_DATA_SIZE)
#define MAX_HAB_CSF_DATA_SIZE 8K
#endif
// Size of stacks section
#if !defined(STACK_SIZE)
#define STACK_SIZE 48K
#endif
// Size of the malloc heap, defaults to 128MB
#if !defined(HEAP_SIZE)
#define HEAP_SIZE 128M
#endif
// Size of the L1 page table.
#define L1_PAGE_TABLE_SIZE 16K
// Size of the RAM vectors table at the top of OCRAM.
//
// The vectors in ROM at address 0 point to these RAM vectors.
#define RAM_VECTORS_SIZE 72
INPUT (crtbegin.o crti.o crtend.o crtn.o)
MEMORY
{
OCRAM (rwx) : ORIGIN = 0x00900000, LENGTH = OCRAM_LEN
DDR (rwx) : ORIGIN = DDR_ORG, LENGTH = DDR_LEN
}
SECTIONS
{
/*
* -- OCRAM --
*
* Nothing in OCRAM can be loaded at boot, because the boot image must be a contiguous
* region of memory.
*/
/* MMU L1 page table */
.l1_page_table (NOLOAD) :
{
__l1_page_table_start = .;
. += L1_PAGE_TABLE_SIZE;
} > OCRAM
/* allocate a heap in ocram */
.heap.ocram (NOLOAD) : ALIGN(4)
{
__heap_ocram_start = .;
. += LENGTH(OCRAM) - L1_PAGE_TABLE_SIZE - RAM_VECTORS_SIZE ;
__heap_ocram_end = .;
} > OCRAM
/* RAM vector table comes at the end of OCRAM */
.ram_vectors (ORIGIN(OCRAM) + LENGTH(OCRAM) - RAM_VECTORS_SIZE) (NOLOAD) :
{
__ram_vectors_start = .;
. += RAM_VECTORS_SIZE;
__ram_vectors_end = .;
} > OCRAM
/*
* -- DDR --
*/
/* -- read-only sections -- */
_start_image_add = ORIGIN(DDR);
.ivt (ORIGIN(DDR)) :
{
. = . + 0x400;
*(.ivt)
} > DDR
.boot_data :
{
__start_boot_data = .;
*(.boot_data)
} > DDR
/* aligned to ease the hexdump read of generated binary */
.dcd_hdr : ALIGN(16)
{
__start_dcd = .;
*(.dcd_hdr)
} > DDR
.dcd_wrt_cmd :
{
*(.dcd_wrt_cmd)
} > DDR
.dcd_data :
{
*(.dcd_data)
} > DDR
.text : ALIGN(8)
{
CREATE_OBJECT_SYMBOLS
*(.startup)
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
} > DDR
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} > DDR
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > DDR
.rodata :
{
*(.rodata .rodata.* .gnu.linkonce.r.*)
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
} > DDR
/* Unwind index. This section is related to C++ exceptions, and is required even
though exceptions are disabled with -fno-exceptions. */
PROVIDE_HIDDEN(__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > DDR
PROVIDE_HIDDEN(__exidx_end = .);
/* -- read-write sections -- */
.data : ALIGN(8)
{
*(.data .data.* .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
} > DDR
/* Reserve some space for HAB CSF data */
.hab.data (_start_image_add + MAX_IMAGE_SIZE) : ALIGN(4)
{
__hab_data = .;
. += MAX_HAB_CSF_DATA_SIZE;
. = ALIGN (32);
__hab_data_end = .;
} > DDR
/* End of HAB reserved space (must place it before BSS section) */
_image_size = . - _start_image_add;
/* The .bss section comes after the hab data because it is not signed */
.bss :
{
__bss_start__ = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
*(.bss)
__bss_end__ = .;
} > DDR
/* Region to contain exception handler stacks */
.stacks (NOLOAD) :
{
__stacks_start = .;
. += STACK_SIZE;
__stacks_end = .;
top_of_stacks = .;
} > DDR
/* define range of the malloc heap */
free_memory_start = ALIGN(32); /* malloc starts allocating from here */
. += HEAP_SIZE;
free_memory_end = .;
_end = .;
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/ivt.c
-82
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@@ -1,82 +0,0 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "hab_defines.h"
extern unsigned * _start_image_add;
extern unsigned * __start_boot_data;
extern unsigned * _image_size;
extern unsigned * __hab_data;
extern uint8_t input_dcd_hdr[];
extern void _start(void);
struct hab_ivt input_ivt __attribute__ ((section (".ivt"))) ={
/** @ref hdr word with tag #HAB_TAG_IVT, length and HAB version fields
* (see @ref data)
*/
IVT_HDR(sizeof(struct hab_ivt), HAB_VER(4, 0)),
/** Absolute address of the first instruction to execute from the
* image
*/
(hab_image_entry_f)_start,
/** Reserved in this version of HAB: should be NULL. */
NULL,
/** Absolute address of the image DCD: may be NULL. */
&input_dcd_hdr,
/** Absolute address of the Boot Data: may be NULL, but not interpreted
* any further by HAB
*/
&__start_boot_data,
/** Absolute address of the IVT.*/
(const void*) (&input_ivt),
/** Absolute address of the image CSF.*/
(const void*) &__hab_data,
/** Reserved in this version of HAB: should be zero. */
0
};
typedef struct {
uint32_t start; /**< Start address of the image */
uint32_t size; /**< Size of the image */
uint32_t plugin; /**< Plugin flag */
} boot_data_t;
boot_data_t bd __attribute__ ((section (".boot_data"))) ={
(uint32_t) &_start_image_add,
(uint32_t) &_image_size,
0,
};
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/platform_init.c
-79
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@@ -1,79 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "board_io_expanders.h"
#include "platform_init.h"
#include "core/cortex_a9.h"
#include "core/mmu.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void platform_init(void)
{
enable_neon_fpu();
disable_strict_align_check();
mmu_init();
// Map some SDRAM for DMA
#if defined(BOARD_EVB)
mmu_map_l1_range(0x30000000, 0x30000000, 0x70000000, kNoncacheable, kShareable, kRWAccess);
#elif defined(BOARD_SMART_DEVICE)
mmu_map_l1_range(0x20000000, 0x20000000, 0x30000000, kNoncacheable, kShareable, kRWAccess);
#endif
// Enable interrupts. Until this point, the startup code has left interrupts disabled.
gic_init();
arm_set_interrupt_state(true);
// Initialize clock sources, dividers, ...
ccm_init();
// Configure the EPIT timer used for system delay function.
system_time_init();
// Initialize the debug/console UART
uart_init(g_debug_uart_port, 115200, PARITY_NONE, STOPBITS_ONE, EIGHTBITS, FLOWCTRL_OFF);
// flush UART RX FIFO
uint8_t c;
do {
c = uart_getchar(g_debug_uart_port);
} while (c != NONE_CHAR);
// Some init for the board
board_ioexpander_init();
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/platform_init.h
-55
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__PLATFORM_INIT_H__)
#define __PLATFORM_INIT_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
//! @brief Do basic hardware initialization to make the system usable.
//!
//! Performs minimal initialization to enable most drivers to work. The GIC,
//! CCM, and UART drivers are inited. The systme timer is inited. And
//! board_ioexpander_init() is called.
void platform_init(void);
#if defined(__cplusplus)
}
#endif
#endif // __PLATFORM_INIT_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/print_clock_info.c
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/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "print_clock_info.h"
#include "core/ccm_pll.h"
#include "registers/regsuart.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void show_freq(void)
{
printf("========== Clock frequencies ===========\n");
printf("CPU: %d kHz\n", get_main_clock(CPU_CLK)/1000);
printf("DDR: %d kHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000);
printf("IPG: %d kHz\n", get_main_clock(IPG_CLK)/1000);
peri_clocks_t clk = UART1_MODULE_CLK + (g_debug_uart_port - HW_UART1);
printf("Debug UART: %d Hz\n", get_peri_clock(clk));
printf("========================================\n\n");
}
//! @todo Rewrite for MMDC controller. This code is currently for MX53.
void show_ddr_config(void)
{
#if 0
uint32_t temp1, dsiz, row, col, cs_info;
uint32_t temp2, num_banks, ddr_type;
uint32_t density, megabyte;
uint32_t num_rows = 1, num_cols = 1, num_dsiz = 1, i = 1;
printf("========== DDR configuration ===========\n");
megabyte = 1024 * 1024;
/* read ESDCTL and gather information */
temp1 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x00);
dsiz = ((temp1 & (0x00030000)) >> 16);
/*Calculate dsize */
while (i <= dsiz) {
num_dsiz *= 2;
i++;
}
dsiz = 16 * num_dsiz;
row = ((temp1 & (0x07000000)) >> 24) + 11;
col = ((temp1 & (0x00700000)) >> 20) + 9;
cs_info = (temp1 & (0xC0000000)) >> 30;
/* read ESDMISC to get # of BANK info */
temp2 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x18);
num_banks = (!((temp2 & (0x00000020)) >> 5)) * 4 + 4;
ddr_type = (temp2 & (0x00000018)) >> 3;
printf("data bits: %d, num_banks: %d \n", dsiz, num_banks);
printf("row: %d, col: %d \n", row, col);
if (ddr_type == 1)
printf("DDR type is DDR2 \n");
else if (ddr_type == 2)
printf("DDR type is LPDDR2\n");
else
printf("DDR type is DDR3 \n");
if (cs_info == 0)
printf("No chip select is enabled \n");
else if (cs_info == 2)
printf("Chip select CSD0 is used \n");
else if (cs_info == 1)
printf("Chip select CSD1 is used \n");
else
printf("Both chip select CSD0 and CSD1 are used \n");
/* Now calculate the DDR density per chip select */
i = 1;
/* First need to calculate the number of rows and cols 2^row and 2^col */
while (i <= row) {
num_rows *= 2;
i++;
}
debug_printf("num_rows= %d\n", num_rows);
i = 1;
while (i <= col) {
num_cols *= 2;
i++;
}
debug_printf("num_cols= %d\n", num_cols);
density = num_rows * num_cols / megabyte;
density = density * dsiz * num_banks / 8;
printf("Density per chip select: %dMB \n", density);
printf("========================================\n\n");
#endif // 0
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/print_clock_info.h
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@@ -1,68 +0,0 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__PRINT_CLOCK_INFO_H__)
#define __PRINT_CLOCK_INFO_H__
#include "sdk.h"
//! @addtogroup app_common
//! @{
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Display module frequency
*/
void show_freq(void);
/*!
* @brief Display the board's DDR configuration
*/
void show_ddr_config(void);
#if defined(__cplusplus)
}
#endif
//! @}
#endif // __PRINT_CLOCK_INFO_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/print_version.c
-73
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@@ -1,73 +0,0 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file print_version.c
* @brief Contains function to print out the app release version.
*/
#include "sdk.h"
#include "sdk_version.h"
#include "board_id/board_id.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* print out the diag release version info
*
*/
void print_version(void)
{
char chip_str[64] = { 0 };
char chip_rev_str[64] = { 0 };
char board_str[64] = { 0 };
char board_rev_str[64] = { 0 };
fsl_board_id_t fsl_board_id = get_board_id();
chip_name(chip_str, fsl_board_id.B.CHIP_TYPE_ID, false);
chip_revision(chip_rev_str, fsl_board_id.B.CHIP_REV_MAJOR, fsl_board_id.B.CHIP_REV_MINOR);
board_name(board_str, BOARD_TYPE);
board_revision(board_rev_str, BOARD_REVISION);
printf("\n\n\n\n");
printf("**************************************************************************\n");
printf(" Platform SDK (%s) for %s %s %s %s\n", k_sdk_version, chip_str, chip_rev_str,
board_str, board_rev_str);
printf(" Build: %s, %s\n", __DATE__, __TIME__);
printf(" %s\n", k_sdk_copyright);
printf("**************************************************************************\n\n");
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/apps/common/print_version.h
-59
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@@ -1,59 +0,0 @@
/*
* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file print_version.h
* @brief release version define - should be changed for each release
*/
#if !defined(__PRINT_VERSION_H__)
#define __PRINT_VERSION_H__
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Prints the version header to the console.
*/
void print_version(void);
#if defined(__cplusplus)
}
#endif
#endif // __PRINT_VERSION_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_audio.c
-118
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@@ -1,118 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsesai.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void SGTL5000PowerUp_and_clockinit(void)
{
}
/*!
*
* Additional code related to clock configuration
*
*/
unsigned int spdif_get_tx_clk_freq(void)
{
return 30000000;
}
/*! From obds
* Audio Codec Power on
*/
void audio_codec_power_on (void)
{
#ifdef BOARD_SMART_DEVICE
//CODEC PWR_EN, key_col12
gpio_set_gpio(GPIO_PORT4, 10);
gpio_set_direction(GPIO_PORT4, 10, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT4, 10, GPIO_HIGH_LEVEL);
#endif
}
/*! From obds
* Audio Clock Config
*/
void audio_clock_config(void)
{
#if defined(BOARD_SMART_DEVICE)
ccm_iomux_config();
HW_CCM_CCOSR_WR(BF_CCM_CCOSR_CLKO2_EN(1)
| BF_CCM_CCOSR_CLKO2_DIV(6)
| BF_CCM_CCOSR_CLKO2_SEL(0x13)
| BF_CCM_CCOSR_CLKO_SEL(1));
#endif
}
/*!
* @brief SPDIF clock configuration
*
* Use the default setting as follow:
* CDCDR[spdif0_clk_sel](PLL3)->CDCDR[spdif0_clk_pred](div2)->CDCDR[spdif0_clk_podf](div8)-> spdif0_clk_root, so
* the freqency of spdif0_clk should be 480/2/8 = 30MHz.
*/
void spdif_clk_cfg(void)
{
HW_CCM_CDCDR.B.SPDIF0_CLK_SEL = 3; // PLL3
HW_CCM_CDCDR.B.SPDIF0_CLK_PODF = 7; // div 8
HW_CCM_CDCDR.B.SPDIF0_CLK_PRED = 1; // div 2
clock_gating_config(SPDIF_BASE_ADDR, CLOCK_ON);
return;
}
/*!
* Power no esai codec.
*/
int esai_codec_power_on(void)
{
// No need to do anything for BOARD_SABRE_AI
return 0;
}
void esai_clk_sel_gate_on()
{
// source from PLL3_508
HW_CCM_CSCMR2.B.ESAI_CLK_SEL = 1;
clock_gating_config(REGS_ESAI_BASE, CLOCK_ON);
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_buttons.c
-105
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@@ -1,105 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
//! @brief IOMUX configuration for the Android_Buttons
//! @todo Confirm this functionality. Values written to the PAD registers do not make sense with comments.
void android_buttons_iomux_config()
{
//HOME_(SD2_CMD_GPI1_11)
gpio_set_gpio(GPIO_PORT1, 11);
HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR( // pull-up enabled at pad
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_V(200MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_V(60_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_V(SLOW));
//BACK_(SD2_DATA3_GPI1_12)
gpio_set_gpio(GPIO_PORT1, 12);
HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR( // pull-up enabled at pad
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_V(200MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_V(60_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_V(SLOW));
//PROG_(SD4_DATA4_GPI2_12)
gpio_set_gpio(GPIO_PORT2, 12);
HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR( // pull-up enabled at pad
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_V(200MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_V(60_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_V(SLOW));
//VOL+_(SD4_DATA7_GPI2_15)
gpio_set_gpio(GPIO_PORT2, 15);
HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR( // pull-up enabled at pad
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_V(200MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_V(60_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_V(SLOW));
//VOL-_(DISP0_DATA20_GPI5_14)
gpio_set_gpio(GPIO_PORT5, 14);
HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR( // pull-up enabled at pad
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED_V(200MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE_V(60_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE_V(SLOW));
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_camera.c
-884
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File diff suppressed because it is too large Load Diff
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_can.c
-87
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@@ -1,87 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "iomux_config.h"
#include "ioexpander/max7310.h"
#include "gpio/gpio.h"
#include "registers/regsflexcan.h"
#include "flexcan/flexcan.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* board dependent IOMUX configuration functions
*/
void hw_can_iomux_config(uint32_t module_instance)
{
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
/* CAN_EN active high output */
max7310_set_gpio_output(1, 6, GPIO_HIGH_LEVEL); //expander b, io6
/* CAN_STBY active high output */
max7310_set_gpio_output(1, 5, GPIO_HIGH_LEVEL); //expander b, io5
#endif
flexcan_iomux_config(module_instance);
#ifdef BOARD_SABRE_AI
switch (module_instance)
{
case HW_FLEXCAN1:
board_ioexpander_iomux_config();
/* Select CAN, ENET_CAN1_STEER(PORT_EXP_B3) */
max7310_set_gpio_output(1, 3, GPIO_HIGH_LEVEL); //expander b, io3
/* Select ALT5 mode of GPIO_4 for GPIO1_4 - CAN1_NERR_B */
/* active low input */
gpio_set_gpio(GPIO_PORT1, 4);
gpio_set_direction(GPIO_PORT1, 4, GPIO_GDIR_INPUT);
break;
case HW_FLEXCAN2:
/* Select ALT5 mode of SD4_DAT3 for GPIO2_11 - CAN2_NERR_B */
/* active low input */
gpio_set_gpio(GPIO_PORT2, 11);
gpio_set_direction(GPIO_PORT2, 11, GPIO_GDIR_INPUT);
break;
default:
printf("ERR: invalid FLEXCAN instance for iomux config\n");
break;
}
#endif
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_display.c
-322
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@@ -1,322 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccmanalog.h"
#include "registers/regsccm.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* Provide the LVDS power through GPIO pins
*/
void lvds_power_on(void)
{
#if defined(BOARD_EVB)
board_ioexpander_iomux_config();
/*3.3V power supply through the load switch FDC6331L */
max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
max7310_set_gpio_output(1, 1, GPIO_HIGH_LEVEL);
/*lvds backlight enable, GPIO_9 */
gpio_set_gpio(GPIO_PORT1, 9);
gpio_set_direction(GPIO_PORT1, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 9, GPIO_HIGH_LEVEL);
#endif
#ifdef BOARD_SMART_DEVICE
// 3v3 on by default
// AUX_5V_EN LVDS0 power
gpio_set_gpio(GPIO_PORT6, 10);
gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
// PMIC_5V LVDS1 power on by default
// backlight both lvds1/0, disp0_contrast/disp0_pwm, gpio1[21]
gpio_set_gpio(GPIO_PORT1, 21);
gpio_set_direction(GPIO_PORT1, 21, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 21, GPIO_HIGH_LEVEL);
#endif
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
/*3.3V power supply through IOexpander */
max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
/*lvds backlight enable, GPIO_9 */
gpio_set_gpio(GPIO_PORT2, 9);
gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 9, GPIO_HIGH_LEVEL);
#endif
}
/*! From obds
* Disable the display panel
*/
void disable_para_panel(void)
{
gpio_set_gpio(GPIO_PORT2, 31);
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 31, GPIO_LOW_LEVEL);
}
/*! Copy from OBDS
* Provide the power for TFT LCD backlight
*/
void tftlcd_backlight_en(char *panel_name)
{
if (!strcmp(panel_name, "CLAA01 WVGA")) {
/*GPIO to provide backlight */
gpio_set_gpio(GPIO_PORT4, 20);
gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT4, 20, GPIO_HIGH_LEVEL);
} else if (!strcmp(panel_name, "BoundaryDev WVGA")) {
#if defined (BOARD_REV_A)
/*lvds/parallel display backlight enable, GPIO2_0 */
gpio_set_gpio(GPIO_PORT2, 9);
gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 9, GPIO_HIGH_LEVEL);
// lcd_contrast conflict with actual BoundaryDev display so seeting to input
// since TSC not used on SABRE AI
gpio_set_gpio(GPIO_PORT4, 20);
gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_INPUT);
#elif defined (BOARD_REV_B) || defined(BOARD_REV_C)
gpio_set_gpio(GPIO_PORT4, 20);
gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT4, 20, GPIO_HIGH_LEVEL);
#endif
} else {
printf("Unsupported panel!\n");
}
#if 0
#ifdef BOARD_SABRE_AI
/*lvds/parallel display backlight enable, GPIO2_0 */
gpio_set_gpio(GPIO_PORT2, 9);
gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 9, GPIO_LOW_LEVEL);
// lcd_contrast conflict with actual BoundaryDev display so seeting to input
// since TSC not used on SABRE AI
gpio_set_gpio(GPIO_PORT4, 20);
gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_INPUT);
#endif
#ifdef BOARD_SMART_DEVICE
/* AUX_3V15 */
gpio_set_gpio(GPIO_PORT6, 9);
HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT6, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 9, GPIO_HIGH_LEVEL);
// backlight both lvds1/0, disp0_contrast/disp0_pwm, gpio1[21]
gpio_set_gpio(GPIO_PORT1, 21);
gpio_set_direction(GPIO_PORT1, 21, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 21, GPIO_HIGH_LEVEL);
// AUX_5V_EN LVDS0 power
gpio_set_gpio(GPIO_PORT6, 10);
gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
#endif
#endif
}
/*! Copy from OBDS
* Reset the TFT LCD
*/
void tftlcd_reset(char *panel_name)
{
if (!strcmp(panel_name, "CLAA01 WVGA")) {
#ifdef BOARD_EVB
gpio_set_gpio(GPIO_PORT2, 31);
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 31, GPIO_LOW_LEVEL);
hal_delay_us(1000);
gpio_set_level(GPIO_PORT2, 31, GPIO_HIGH_LEVEL);
hal_delay_us(1000);
#endif
#ifdef BOARD_SMART_DEVICE
gpio_set_gpio(GPIO_PORT3, 8);
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT3, 8, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 8, GPIO_LOW_LEVEL);
hal_delay_us(1000);
gpio_set_level(GPIO_PORT3, 8, GPIO_HIGH_LEVEL);
hal_delay_us(1000);
#endif
}
}
/*!
* @brief Configure ldb clock as per the display resolution.
*
* ldb clock is derived from PLL5, ldb on ipu1
*/
void ldb_clock_config(int freq, int ipu_index)
{
if (freq == 65000000) //for XGA resolution
{
//config pll3 PFD1 to 455M. pll3 is 480M
BW_CCM_ANALOG_PFD_480_PFD1_FRAC(19);
// set ldb_di0_clk_sel to PLL3 PFD1
HW_CCM_CS2CDR.B.LDB_DI0_CLK_SEL = 3;
HW_CCM_CS2CDR.B.LDB_DI1_CLK_SEL = 3;
// set clk_div to 7
HW_CCM_CSCMR2.B.LDB_DI0_IPU_DIV = 1;
HW_CCM_CSCMR2.B.LDB_DI1_IPU_DIV = 1;
if (ipu_index == 1) {
//set ipu1_di0_clk_sel from ldb_di0_clk
HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 3; // ldb_di0_clk
HW_CCM_CHSCCDR.B.IPU1_DI1_CLK_SEL = 3; // ldb_di0_clk
}
#if CHIP_MX6DQ
else {
//set ipu2_di0_clk_sel from ldb_di0_clk
HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 3;
HW_CCM_CSCDR2.B.IPU2_DI1_CLK_SEL = 3;
}
#endif // CHIP_MX6DQ
} else {
printf("The frequency %d for LDB is not supported yet.", freq);
}
}
void epdc_clock_setting(int freq)
{
#if defined(CHIP_MX6SDL)
HW_CCM_CSCDR2.B.EPDC_PIX_PRE_CLK_SEL = 0x3; // 307M PFD
HW_CCM_CSCDR2.B.EPDC_PIX_CLK_SEL = 0x0;
/*set the output as 271M */
BW_CCM_ANALOG_PFD_528_PFD0_FRAC(0x23);
HW_CCM_CSCDR2.B.EPDC_PIX_PODF = 0x7; // post divider
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO_3.B.MUX_MODE = ALT4; //set as clko
#endif
#if defined(CHIP_MX6SL)
HW_CCM_CSCDR2.B.EPDC_PIX_CLK_SEL = 0x5; //Use 540MPFD
HW_CCM_CSCDR2.B.EPDC_PIX_PRED = 0x5; //pred for EPDC
HW_CCM_CBCMR.B.EPDC_PIX_PODF = 0x4;
/*set the AXI clock, divided from MMDC clock */
HW_CCM_CHSCCDR.B.EPDC_AXI_CLK_SEL = 0x0;
HW_CCM_CHSCCDR.B.EPDC_AXI_PODF = 0x1;
#endif
}
void epdc_power_supply(void)
{
int i = 0;
#if defined(CHIP_MX6SDL)
#if defined(BOARD_EVB)
/*PMIC wakeup */
gpio_set_gpio(GPIO_PORT2, 31);
gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 31, GPIO_HIGH_LEVEL);
/*PMIC vcom */
gpio_set_gpio(GPIO_PORT3, 17);
gpio_set_direction(GPIO_PORT3, 17, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 17, GPIO_HIGH_LEVEL);
#elif defined(BOARD_SMART_DEVICE)
/*PMIC wakeup */
gpio_set_gpio(GPIO_PORT3, 20);
gpio_set_direction(GPIO_PORT3, 20, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 20, GPIO_HIGH_LEVEL);
/*PMIC vcom */
gpio_set_gpio(GPIO_PORT3, 17);
gpio_set_direction(GPIO_PORT3, 17, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 17, GPIO_HIGH_LEVEL);
#endif
#endif
#if defined(CHIP_MX6SL)
//EN : pmic_wakeup gpio2.14
gpio_set_gpio(GPIO_PORT2, 14);
gpio_set_direction(GPIO_PORT2, 14, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 14, GPIO_HIGH_LEVEL);
//CEN : pmic_vcom gpio2.3
gpio_set_gpio(GPIO_PORT2, 3);
gpio_set_direction(GPIO_PORT2, 3, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 3, GPIO_HIGH_LEVEL);
#endif
for (i = 0; i < 1000000; i++)
__asm("nop");
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_hdmi.c
-193
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@@ -1,193 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* config instance hdmi_tx of Module HDMI_TX to Protocol CEC
* port including CEC_LINE
*/
void hdmi_tx_cec_pgm_iomux(void)
{
// config EIM_A25 pad for hdmi_tx instance CEC_LINE port
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE_V(ALT6));
// Pad EIM_A25 is involved in Daisy Chain.
HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(
BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY_V(EIM_ADDR25_ALT6));
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS_V(22K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE_V(SLOW));
}
/*!
* config instance hdmi_tx of Module HDMI_TX to Protocol DDC
* ports including DDC_SCL, DDC_SDA.
*/
void hdmi_tx_ddc_pgm_iomux(void)
{
// config KEY_COL3 pad for hdmi_tx instance DDC_SCL port
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(ALT2));
// Pad KEY_COL3 is involved in Daisy Chain.
HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(
BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY_V(KEY_COL3_ALT2));
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(22K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(SLOW));
// config KEY_ROW3 pad for hdmi_tx instance DDC_SDA port
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_V(ALT2));
// Pad KEY_ROW3 is involved in Daisy Chain.
HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(
BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY_V(KEY_ROW3_ALT2));
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_V(22K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_V(SLOW));
}
/*!
* config instance hdmi_tx of Module HDMI_TX to Protocol PHYDTB
* ports including {OPHYDTB[1]}, {OPHYDTB[0]}
*/
void hdmi_tx_phydtb_pgm_iomux(void)
{
// config SD1_DAT1 pad for hdmi_tx instance OPHYDTB[0] port
HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(6/*ALT6*/));
HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_V(FAST));
// config SD1_DAT0 pad for hdmi_tx instance OPHYDTB[1] port
HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(6/*ALT6*/));
HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_V(100K_OHM_PD) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_V(KEEP) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_V(FAST));
}
/*!
* HDMI pin mux and internal connection mux
* be noted that the HDMI is drivern by the IPU1 di0 here
*/
void hdmi_pgm_iomux(void)
{
ipu1_iomux_config();
hdmi_tx_cec_pgm_iomux();
hdmi_tx_ddc_pgm_iomux();
hdmi_tx_phydtb_pgm_iomux();
}
/*!
* HDMI power up
*/
void ext_hdmi_transmitter_power_on(void)
{
/*3.3V for core, default is on */
/*5V for IO, default is on */
}
void hdmi_clock_set(int ipu_index, uint32_t pclk)
{
switch (pclk) {
case 74250000:
case 148500000:
if (ipu_index == 1) {
//clk output from 540M PFD1 of PLL3
HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 0; // derive clock from divided pre-muxed ipu1 di0 clock
HW_CCM_CHSCCDR.B.IPU1_DI0_PODF = 5; // div by 6
HW_CCM_CHSCCDR.B.IPU1_DI0_PRE_CLK_SEL = 5; // derive clock from 540M PFD
}
#if CHIP_MX6DQ
else {
//clk output from 540M PFD1 of PLL3
HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 0; // derive clock from divided pre-muxed ipu1 di0 clock
HW_CCM_CSCDR2.B.IPU2_DI0_PODF = 5; // div by 6
HW_CCM_CSCDR2.B.IPU2_DI0_PRE_CLK_SEL = 5; // derive clock from 540M PFD
}
#endif // CHIP_MX6DQ
//config PFD1 of PLL3 to be 445MHz
BW_CCM_ANALOG_PFD_480_PFD1_FRAC(0x13);
break;
default:
printf("the hdmi pixel clock is not supported!\n");
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_i2c.c
-87
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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "board_i2c.h"
#include "registers/regsi2c.h"
////////////////////////////////////////////////////////////////////////////////
// Globals
////////////////////////////////////////////////////////////////////////////////
const i2c_device_info_t g_wm8958_i2c_device = { HW_I2C2, (0x34 >> 1), 100000 };
const i2c_device_info_t g_wm8962_i2c_device = { HW_I2C1, (0x34 >> 1), 48000 };
const i2c_device_info_t g_sgtl5000_i2c_device = { HW_I2C2, 0x0a, 100000 };
#if defined (BOARD_EVB)
const i2c_device_info_t g_cs42888_i2c_device = { HW_I2C1, (0x90 >> 1), 100000 };
#else
const i2c_device_info_t g_cs42888_i2c_device = { HW_I2C2, (0x90 >> 1), 100000 };
#endif
const i2c_device_info_t g_pmic_ltc3589_i2c_device = { HW_I2C2, (0x68 >> 1), 170000 };
const i2c_device_info_t g_pmic_da9053_i2c_device = { HW_I2C1, (0x90 >> 1), 170000 };
const i2c_device_info_t g_pmic_max17135_i2c_device = { HW_I2C1, (0x90 >> 1), 170000 };
const i2c_device_info_t g_pmic_pf0100_i2c_device = { HW_I2C2, (0x10 >> 1), 170000 };
#if defined(BOARD_EVB)
const i2c_device_info_t g_adv7180_i2c_device = { HW_I2C1, (0x42 >> 1), 50000 };
#else
const i2c_device_info_t g_adv7180_i2c_device = { HW_I2C3, (0x42 >> 1), 50000 };
#endif
const i2c_device_info_t g_os81050_i2c_device = { HW_I2C3, (0x40 >> 1), 50000 };
#if defined(BOARD_SMART_DEVICE)
const i2c_device_info_t g_p1003_tsc_i2c_device = { HW_I2C3, (0x8 >> 1), 50000 };
#else
const i2c_device_info_t g_p1003_tsc_i2c_device = { HW_I2C2, (0x8 >> 1), 50000 };
#endif
const i2c_device_info_t g_at24cx_i2c_device = { HW_I2C3, (0xa0 >> 1), 170000 };
const i2c_device_info_t g_si476x_i2c_device = { HW_I2C2, (0xC6 >> 1), 50000 };
#if defined(BOARD_SMART_DEVICE)
const i2c_device_info_t g_mma8451_i2c_device = { HW_I2C1, 0x1C, 170000 };
#elif defined(BOARD_SABRE_AI)
const i2c_device_info_t g_mma8451_i2c_device = { HW_I2C3, 0x1C, 170000 };
#endif
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_i2c.h
-77
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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__BOARD_I2C_H__)
#define __BOARD_I2C_H__
#include "sdk_types.h"
#include "i2c/imx_i2c.h"
////////////////////////////////////////////////////////////////////////////////
// Externs
////////////////////////////////////////////////////////////////////////////////
//! @name Audio codecs
//@{
extern const i2c_device_info_t g_wm8958_i2c_device;
extern const i2c_device_info_t g_wm8962_i2c_device;
extern const i2c_device_info_t g_sgtl5000_i2c_device;
extern const i2c_device_info_t g_cs42888_i2c_device;
//@}
//! @name PMICs
//@{
extern const i2c_device_info_t g_pmic_ltc3589_i2c_device;
extern const i2c_device_info_t g_pmic_da9053_i2c_device;
extern const i2c_device_info_t g_pmic_pf0100_i2c_device;
extern const i2c_device_info_t g_pmic_max17135_i2c_device;
//@}
//! @brief ADV7180 video decoder
extern const i2c_device_info_t g_adv7180_i2c_device;
//! @brief OS81050 MLB MOST controller
extern const i2c_device_info_t g_os81050_i2c_device;
//! @brief P1003 touch screen controller
extern const i2c_device_info_t g_p1003_tsc_i2c_device;
//! @brief AT24Cxx EEPROM
extern const i2c_device_info_t g_at24cx_i2c_device;
//! @brief Si476x FM tuner
extern const i2c_device_info_t g_si476x_i2c_device;
//! @brief MMA8451 accelerometer.
extern const i2c_device_info_t g_mma8451_i2c_device;
#endif // __BOARD_I2C_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_io_expanders.c
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/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "board_io_expanders.h"
#include "registers/regsi2c.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Globals
////////////////////////////////////////////////////////////////////////////////
imx_i2c_request_t max7310_i2c_req_array[MAX7310_NBR];
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void board_ioexpander_init(void)
{
#if defined(BOARD_SABRE_AI)
// Bring max7310 out of reset
// (this iomux setting should be done in gpio_iomux_config())
gpio_set_gpio(GPIO_PORT1, 15);
gpio_set_direction(GPIO_PORT1, 15, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 15, GPIO_HIGH_LEVEL);
// for I2C3 steering
// Select ALT5 mode of EIM_A24 for GPIO5_4 - EIMD18_I2C3_STEER(EIM_A24)
// high output to select I2C3 option
// (this iomux setting should be done in gpio_iomux_config())
gpio_set_gpio(GPIO_PORT5, 4);
gpio_set_direction(GPIO_PORT5, 4, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT5, 4, GPIO_HIGH_LEVEL);
#endif
// Build array of I2C request structures.
#if defined(BOARD_EVB) || defined(BOARD_SABRE_AI)
// Configure some board signals through I/O expanders
max7310_i2c_req_array[0].ctl_addr = HW_I2C3; // the I2C controller base address
max7310_i2c_req_array[0].dev_addr = MAX7310_I2C_ID0; // the I2C DEVICE address
max7310_init(0, MAX7310_ID0_DEF_DIR, MAX7310_ID0_DEF_VAL);
max7310_i2c_req_array[1].ctl_addr = HW_I2C3; // the I2C controller base address
max7310_i2c_req_array[1].dev_addr = MAX7310_I2C_ID1; // the I2C DEVICE address
max7310_init(1, MAX7310_ID1_DEF_DIR, MAX7310_ID1_DEF_VAL);
#endif
#if defined(BOARD_SABRE_AI)
max7310_i2c_req_array[2].ctl_addr = HW_I2C3; // the I2C controller base address
max7310_i2c_req_array[2].dev_addr = MAX7310_I2C_ID2; // the I2C DEVICE address
max7310_init(2, MAX7310_ID2_DEF_DIR, MAX7310_ID2_DEF_VAL);
#endif
}
void board_ioexpander_iomux_config(void)
{
#if defined(BOARD_SABRE_AI)
i2c3_iomux_config();
#if !defined(BOARD_REV_A)
/*
* for I2C3 steering:
*
* i2c3_iomux_config() selected ALT5 mode of EIM_A24
* for GPIO5_4 - EIMD18_I2C3_STEER(EIM_A24)
*
* high output to select I2C3 option
*/
gpio_set_direction(GPIO_PORT5, 4, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT5, 4, GPIO_HIGH_LEVEL);
#endif // !defined(BOARD_REV_A)
#endif // defined(BOARD_SABRE_AI)
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_io_expanders.h
-125
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/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__BOARD_IO_EXPANDERS_H__)
#define __BOARD_IO_EXPANDERS_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
/*
* BOARD_SMART_DEVICE for compile error
*/
#if defined(BOARD_SMART_DEVICE)
#define MAX7310_NBR 0
#endif
/* For the ARD board which has 3 MAX7310 */
#ifdef BOARD_SABRE_AI
#define MAX7310_NBR 3
/* I/O expander A */
#define MAX7310_I2C_BASE_ID0 3
#define MAX7310_I2C_ID0 0x30
#define MAX7310_ID0_DEF_DIR 0x00 // init direction for the I/O
#define MAX7310_ID0_DEF_VAL 0xFF // init value for the output
/* I/O expander B */
#define MAX7310_I2C_BASE_ID1 3
#define MAX7310_I2C_ID1 0x32
#define MAX7310_ID1_DEF_DIR 0x00 // init direction for the I/O
#define MAX7310_ID1_DEF_VAL 0xE7 // init value for the output
/* I/O expander C */
#define MAX7310_I2C_BASE_ID2 3
#define MAX7310_I2C_ID2 0x34
#define MAX7310_ID2_DEF_DIR 0x00 // init direction for the I/O
#define MAX7310_ID2_DEF_VAL 0x57 // init value for the output
#endif
#ifdef BOARD_EVB
/* For the EVB board which has 2 MAX7310 */
#define MAX7310_NBR 2
/* Number 1 controls: BACKLIGHT_ON, PORT3_P114, CPU_PER_RST_B, PORT3_P110,
PORT3_P105, PORT3_P112, PORT3_P107, PORT3_P109.
*/
#define MAX7310_I2C_BASE_ID0 3
#define MAX7310_I2C_ID0 (0x36 >> 1)
#define MAX7310_ID0_DEF_DIR 0x00 // init direction for the I/O
#define MAX7310_ID0_DEF_VAL 0xFF // init value for the output
/* Number 2 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116,
PORT2_P81, PORT3_P101
*/
#define MAX7310_I2C_BASE_ID1 3
#define MAX7310_I2C_ID1 (0x3E >> 1)
#define MAX7310_ID1_DEF_DIR 0x00 // init direction for the I/O
#define MAX7310_ID1_DEF_VAL 0x09 // init value for the output
#endif
////////////////////////////////////////////////////////////////////////////////
// Globals
////////////////////////////////////////////////////////////////////////////////
//! @brief Array of I2C requests for all used expanders on the board.
//!
//! This array is primarily used to pass details about I2C addresses and ports
//! to the max7310 driver.
extern imx_i2c_request_t max7310_i2c_req_array[];
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Init the array of I/O expanders.
*/
void board_ioexpander_init(void);
/*!
* @brief Configure the IOMUX so we can access the I/O expander.
*/
void board_ioexpander_iomux_config(void);
#if defined(__cplusplus)
}
#endif
#endif // __BOARD_IO_EXPANDERS_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_mipi.c
-225
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@@ -1,225 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* Provide the mipi camera power and reset
*/
void mipi_cam_power_on(void)
{
#if defined(BOARD_EVB)
board_ioexpander_iomux_config();
/*reset of camera sensor, pin 27 */
max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
hal_delay_us(1000);
max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
/*power supply through pin25 of connector, for cam_pdown, power down and then up */
max7310_set_gpio_output(0, 0, GPIO_LOW_LEVEL);
hal_delay_us(1000);
max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
// max7310_set_gpio_output(1, 1, GPIO_HIGH_LEVEL);
#endif
#if defined(BOARD_SABRE_AI)
board_ioexpander_iomux_config();
/*power supply through pin25 of connector, direct connected to P3V3_DELAY,
controlled by CPU_PER_RST_B */
/*reset of camera sensor, together with the reset button */
max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
hal_delay_us(1000);
max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
#endif
#if defined(BOARD_SMART_DEVICE)
/*power supply through pin25 of connector, for cam_pdown */
gpio_set_gpio(GPIO_PORT6, 9);
HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT6, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 9, GPIO_HIGH_LEVEL);
/*reset of camera sensor, pin 27 */
gpio_set_gpio(GPIO_PORT6, 10);
HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 10, GPIO_LOW_LEVEL);
hal_delay_us(1000);
gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
#endif
}
/*!
* enable mipi backlight
*/
void mipi_backlight_en(void)
{
//configure pin19 of the mipi dsi/csi connector
#ifdef BOARD_EVB
//set GPIO1_9 to 0 so clear vbus on board
gpio_set_direction(GPIO_PORT1, 9, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 9, GPIO_HIGH_LEVEL);
#endif
#ifdef BOARD_SABRE_AI
//default be populated by P3V3_DELAYED
#endif
#ifdef BOARD_SMART_DEVICE
gpio_set_gpio(GPIO_PORT2, 0);
HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT2, 0, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT2, 0, GPIO_HIGH_LEVEL);
#endif
}
/*!
* reset MIPI display
*/
void mipi_display_reset(void)
{
#ifdef BOARD_EVB
/*pin29 of mipi connector for the LCD reset*/
gpio_set_gpio(GPIO_PORT5, 0);
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT5, 0, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT5, 0, GPIO_LOW_LEVEL);
hal_delay_us(1000);
gpio_set_level(GPIO_PORT5, 0, GPIO_HIGH_LEVEL);
hal_delay_us(1000);
#endif
#ifdef BOARD_SABRE_AI
/*binded with the board reset button*/
#endif
#ifdef BOARD_SMART_DEVICE
/*pin29 of mipi connector for the LCD reset*/
gpio_set_gpio(GPIO_PORT6, 11);
HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(SLOW));
gpio_set_direction(GPIO_PORT6, 11, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 11, GPIO_LOW_LEVEL);
hal_delay_us(1000);
gpio_set_level(GPIO_PORT6, 11, GPIO_HIGH_LEVEL);
hal_delay_us(1000);
#endif
}
void mipi_clock_set(void)
{
BW_CCM_ANALOG_PFD_480_PFD1_FRAC(0x10);
}
void mipi_csi2_clock_set(void)
{
//set VIDPLL(PLL5) to 596MHz
HW_CCM_ANALOG_PLL_VIDEO_WR(BF_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(0) |
BF_CCM_ANALOG_PLL_VIDEO_ENABLE(1));
HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(0x00000000);
HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(0x00000001);
while (!HW_CCM_ANALOG_PLL_VIDEO.B.LOCK) ; //waiting for PLL lock
BF_CLR(CCM_ANALOG_PLL_VIDEO, BYPASS);
//select CSI0_HSYNC osc_clk 24MHz, CKO1 output drives cko2 clock
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE_V(ALT3));
HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE_V(SLOW));
HW_CCM_CCOSR_WR(
BF_CCM_CCOSR_CLKO1_SEL(0) |
BF_CCM_CCOSR_CLKO1_DIV(0) |
BF_CCM_CCOSR_CLKO1_EN(1) |
BF_CCM_CCOSR_CLKO_SEL(1) | // select cko2 for cko1 output
BF_CCM_CCOSR_CLKO2_SEL(0xe) | // osc_clk
BF_CCM_CCOSR_CLKO2_DIV(0) | // div 1
BF_CCM_CCOSR_CLKO2_EN(1));
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_nand.c
-64
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@@ -1,64 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gpmi/gpmi.h"
#include "core/ccm_pll.h"
#include "registers/regsgpmi.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
//! @brief Configure and enable the GPMI and BCH clocks.
//!
//! The GPMI clock is selected to be sourced from the main PLL3 clock (480 MHz), then
//! divided by 4 and again by 1. The resulting clock is 120 MHz.
void gpmi_nand_clk_setup(void)
{
HW_CCM_ANALOG_PFD_528_CLR(BM_CCM_ANALOG_PFD_528_PFD2_CLKGATE);
// Gate clocks before adjusting dividers.
clock_gating_config(REGS_GPMI_BASE, CLOCK_OFF);
HW_CCM_CS2CDR.B.ENFC_CLK_SEL = 2; // Select pll3 clock (480 MHz)
HW_CCM_CS2CDR.B.ENFC_CLK_PRED = 3; // Divide by 4
HW_CCM_CS2CDR.B.ENFC_CLK_PODF = 0; // Divide by 1
// Ungate clocks.
clock_gating_config(REGS_GPMI_BASE, CLOCK_ON);
HW_CCM_CCGR0.B.CG2 = CLOCK_ON; // apbhdma_hclk_enable
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_network.c
-109
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@@ -1,109 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/* ENET iomux config */
void imx_ar8031_iomux()
{
enet_iomux_config(); // iomux tool output
}
/*CPU_PER_RST_B low to high*/
void imx_KSZ9021RN_reset(void)
{
//max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
//hal_delay_us(1000000);
//max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
#ifdef BOARD_SABRE_LITE
// Config gpio3_GPIO[23] to pad EIM_D23(D25)
gpio_set_gpio(GPIO_PORT3, 23);
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE_V(SLOW));
gpio_set_direction(GPIO3, 23, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO3, 23, GPIO_LOW_LEVEL);
hal_delay_us(1000000); // hold in reset for a delay
gpio_set_level(GPIO3, 23, GPIO_LOW_HIGH);
#endif
}
/*CPU_PER_RST_B low to high*/
void imx_ar8031_reset(void)
{
#if defined(BOARD_SMART_DEVICE)
/* Select ALT5 mode of ENET_CRS-DV for GPIO1_25 - PGMII_NRST */
/* active low output */
gpio_set_direction(GPIO_PORT1, 25, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT1, 25, GPIO_LOW_LEVEL);
hal_delay_us(500);
gpio_set_level(GPIO_PORT1, 25, GPIO_HIGH_LEVEL);
#elif defined(BOARD_SABRE_AI) && !defined(BOARD_REV_A)
/* CPU_PER_RST_B low to high */
// max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
// hal_delay_us(1000);
// max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
#endif
}
/*! From obds
* ENET iomux config
*/
void imx_enet_iomux(void)
{
enet_iomux_config(); // iomux tool output
#ifdef BOARD_SABRE_AI
/* Select ENET, ENET_CAN1_STEER(PORT_EXP_B3) */
max7310_set_gpio_output(1, 2, GPIO_LOW_LEVEL);
/* Select ALT5 mode of GPIO_19 for GPIO4_5 - PGMIT_INT_B */
/* active low input */
gpio_set_gpio(GPIO_PORT4, 5);
gpio_set_direction(GPIO_PORT4, 5, GPIO_GDIR_INPUT);
#endif
}
void imx_enet_phy_reset(void)
{
imx_ar8031_reset();
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_pcie.c
-141
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@@ -1,141 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
#include "registers/regspmu.h"
#include "registers/regsiomuxc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void pcie_clk_setup(uint32_t enable)
{
if (enable) {
// gate on pci-e clks
HW_CCM_CCGR4.B.CG0 = CLOCK_ON;
// clear the powerdown bit
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_POWERDOWN);
// enable pll
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE);
// wait the pll locked
while (!HW_CCM_ANALOG_PLL_ENET.B.LOCK) ;
// Disable bypass
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_BYPASS);
// enable pci-e ref clk
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE_125M);
}
}
void pcie_card_pwr_setup(uint32_t enable)
{
#if defined(BOARD_EVB)
i2c_init(I2C3_BASE_ADDR, 100000);
board_ioexpander_iomux_config();
if (enable) {
//enable pciemini_3.3v
max7310_set_gpio_output(1, 2, 1);
} else {
max7310_set_gpio_output(1, 2, 0);
}
#endif
#if defined(BOARD_SMART_DEVICE)
gpio_set_gpio(GPIO_PORT3, 19);
gpio_set_direction(GPIO_PORT3, 19, GPIO_GDIR_OUTPUT);
if(enable){
gpio_set_level(GPIO_PORT3, 19, GPIO_HIGH_LEVEL);
}else{
gpio_set_level(GPIO_PORT3, 19, GPIO_LOW_LEVEL);
}
#endif
}
void pcie_enable_extrn_125mhz_clk(uint32_t enable)
{
if (enable) {
//Enable 125MHz output of Enet_PLL
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE_125M);
// Select PCIe clock source and switch to output buffer, ie, CLK1_N/CLK1_P
HW_PMU_MISC1_CLR(BM_PMU_MISC1_LVDSCLK1_IBEN);
HW_PMU_MISC1.B.LVDS1_CLK_SEL = BV_PMU_MISC1_LVDS1_CLK_SEL__PCIE_REF;
HW_PMU_MISC1_SET(BM_PMU_MISC1_LVDSCLK1_OBEN);
}
}
// The external 100 MHz clock
void pcie_enable_extrn_100mhz_clk(uint32_t enable)
{
#if defined(CHIP_MX6SDL)
#define BV_PMU_MISC1_LVDS1_CLK_SEL__SATA_REF 11
#endif
if (enable) {
//Enable 100MHz output of Enet_PLL
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE_100M);
HW_PMU_MISC1_CLR(BM_PMU_MISC1_LVDSCLK1_IBEN);
HW_PMU_MISC1.B.LVDS1_CLK_SEL = BV_PMU_MISC1_LVDS1_CLK_SEL__SATA_REF;
HW_PMU_MISC1_SET(BM_PMU_MISC1_LVDSCLK1_OBEN);
}
}
void pcie_card_rst(void)
{
#if defined(BOARD_EVB)
i2c_init(I2C3_BASE_ADDR, 100000);
board_ioexpander_iomux_config();
max7310_set_gpio_output(0, 2, 0);
hal_delay_us(200 * 1000);
max7310_set_gpio_output(0, 2, 1);
#endif
#if defined(BOARD_SMART_DEVICE)
gpio_set_gpio(GPIO_PORT4, 5);
gpio_set_direction(GPIO_PORT4, 5, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT4, 5, GPIO_LOW_LEVEL);
hal_delay_us(200 * 1000);
gpio_set_level(GPIO_PORT4, 5, GPIO_HIGH_LEVEL);
#endif
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_sata.c
-130
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@@ -1,130 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsccm.h"
#include "registers/regsccmanalog.h"
#include "registers/regspmu.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* SATA power on
*/
void sata_power_on(void)
{
//enable SATA_3V3 and SATA_5V with MX7310 U19 CTRL_0
#if defined(BOARD_SMART_DEVICE)
//AUX_5V_EN
gpio_set_gpio(GPIO_PORT6, 10);
gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
#elif defined(BOARD_EVB)
board_ioexpander_iomux_config();
//enable SATA_3V3 and SATA_5V with MX7310 CTRL_0
max7310_set_gpio_output(1, 0, GPIO_HIGH_LEVEL);
// sata_phy_clk_sel = CCM_PLL_ENET;
#else
#endif
}
/*!
* SATA power off
*/
void sata_power_off(void)
{
board_ioexpander_iomux_config();
//disable SATA_3V3 and SATA_5V with MX7310 U19 CTRL_0
max7310_set_gpio_output(1, 0, GPIO_LOW_LEVEL);
}
// The external 100 MHz clock is used by SATA, which is only present on the mx6dq.
void enable_extrn_100mhz_clk(uint32_t enable)
{
if (enable) {
// Disable SATA clock gating used as external reference
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE_100M);
// Select SATA clock source and switch to output buffer.
HW_PMU_MISC1_CLR(BM_PMU_MISC1_LVDSCLK1_IBEN);
HW_PMU_MISC1.B.LVDS1_CLK_SEL = BV_PMU_MISC1_LVDS1_CLK_SEL__SATA_REF;
HW_PMU_MISC1_SET(BM_PMU_MISC1_LVDSCLK1_OBEN);
}
}
/*!
* @brief SATA related clocks enable function
*/
void sata_clock_enable(void)
{
// Set SATA timings 0x05932046
reg32_write(0x020E0034, 0x05932044);
hal_delay_us(1000);
// Enable SATA PLL
reg32_write(0x020E0034, 0x05932046);
hal_delay_us(1000);
//enable SATA_CLK in CCGR5
clock_gating_config(SATA_BASE_ADDR, CLOCK_ON);
//enable ENET_PLL (PLL8). done in freq_populate()
//enale SATA_CLK in the ENET_PLL register
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE_100M);
//config ENET PLL div_select for SATA - 100MHz
HW_CCM_ANALOG_PLL_ENET.B.DIV_SELECT = 0x2; // 0b10-100MHz
}
/*!
* @brief SATA related clocks dis function
*/
void sata_clock_disable(void)
{
//disable SATA_CLK in CCGR5.
clock_gating_config(SATA_BASE_ADDR, CLOCK_OFF);
//disable ENET_PLL (PLL8)
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_ENABLE_100M);
}
/*!
* @brief SATA related function to get the PHY source clock
*/
void sata_get_phy_src_clk(sata_phy_ref_clk_t * phy_ref_clk)
{
*phy_ref_clk = CCM_PLL_ENET;
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_usb.c
-149
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@@ -1,149 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "usb/usb.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* This function enables Vbus for the given USB port\n
* The procedure to enable Vbus depends on both the Chip and board hardware\n
*
* @param port USB module to initialize
*/
void usbEnableVbus(usb_module_t * port)
{
switch (port->controllerID) {
case OTG:
case OTG1:
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
// Vbus control is on I2C port expander C1 for the ARD board.
max7310_set_gpio_output(2, 1, 1);
#endif
#if defined(BOARD_EVB) || defined(BOARD_SMART_DEVICE)
gpio_set_gpio(GPIO_PORT3, 22);
gpio_set_direction(GPIO_PORT3, 22, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 22, GPIO_HIGH_LEVEL);
#endif
break;
case Host1:
case OTG2:
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
// Vbus control is on I2C port expander B7 for the ARD board.
max7310_set_gpio_output(1, 7, 1);
#endif
#ifdef BOARD_EVB
gpio_set_gpio(GPIO_PORT3, 31);
gpio_set_direction(GPIO_PORT3, 31, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 31, GPIO_HIGH_LEVEL);
#endif
#ifdef BOARD_SMART_DEVICE
gpio_set_gpio(GPIO_PORT3, 30);
gpio_set_direction(GPIO_PORT3, 30, GPIO_GDIR_OUTPUT);
gpio_set_level(GPIO_PORT3, 30, GPIO_HIGH_LEVEL);
#endif
break;
case Host2:
#ifdef BOARD_EVB
#endif
break;
case Host3:
// Nothing to be done here.
break;
default:
// no such controller
break;
}
}
/*!
* This function disables Vbus for the given USB port\n
* The procedure to enable Vbus depends on both the Chip and board hardware\n
* This implementation is for the MX6q Sabre-AI board\n
*
* @param port USB module to initialize
*/
void usbDisableVbus(usb_module_t * port)
{
switch (port->controllerID) {
case OTG:
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
max7310_set_gpio_output(2, 1, 0);
#endif
#if defined(BOARD_EVB) || defined(BOARD_SMART_DEVICE)
gpio_set_level(GPIO_PORT3, 22, GPIO_LOW_LEVEL);
#endif
break;
case Host1:
#ifdef BOARD_SABRE_AI
board_ioexpander_iomux_config();
max7310_set_gpio_output(1, 7, 0);
#endif
#ifdef BOARD_EVB
gpio_set_level(GPIO_PORT3, 31, GPIO_LOW_LEVEL);
#endif
#ifdef BOARD_SMART_DEVICE
gpio_set_level(GPIO_PORT3, 30, GPIO_LOW_LEVEL);
#endif
case Host2:
#ifdef BOARD_EVB
#endif
break;
case Host3:
// Nothing to be done here.
break;
default:
// no such controller
break;
}
}
/*!
* USB HUB reset function
*/
void reset_usb_hub(void)
{
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/board_usdhc.c
-143
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@@ -1,143 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sdk.h"
#include "registers/regsiomuxc.h"
#include "registers/regsusdhc.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*!
* Set up the GPIO for USDHC
*/
void usdhc_gpio_config(uint32_t instance)
{
switch (instance) {
case HW_USDHC1:
#if defined(BOARD_SABRE_AI)
/* Select ALT5 mode of CSI0_DATA_EN for GPIO5_20 - SDb_WP(CSI0_DATA_EN_GPIO5_20) */
gpio_set_gpio(GPIO_PORT5, 20);
gpio_set_direction(GPIO_PORT5, 20, GPIO_GDIR_INPUT);
#endif
break;
case HW_USDHC2:
break;
case HW_USDHC3:
#if defined(BOARD_SABRE_AI)
/* Select ALT5 mode of NANDF_CS2 for GPIO6_15 - SDa_CD_B(GPIO6_15) */
gpio_set_gpio(GPIO_PORT6, 15);
gpio_set_direction(GPIO_PORT6, 15, GPIO_GDIR_INPUT);
/* Select ALT5 mode of SD2_DAT2 for GPIO1_13 - SDa_WP(SD2_DAT2_GPIO1_13) */
gpio_set_gpio(GPIO_PORT1, 13);
gpio_set_direction(GPIO_PORT1, 13, GPIO_GDIR_INPUT);
#endif
break;
case HW_USDHC4:
break;
default:
break;
}
}
bool usdhc_card_detected(uint32_t instance)
{
bool ret_val = false;
#if defined(BOARD_SABRE_AI)
if (instance == HW_USDHC1) {
// SDb_CD_B
// Bit HIGH == pin LOW == Card Detected.
if (BG_USDHC_PRES_STATE_CDPL(HW_USDHC_PRES_STATE_RD(instance))) {
ret_val = true;
}
} else if (instance == HW_USDHC3) {
// SDa_CD_B using GPIO6_15
// Bit LOW == pin LOW == Card Detected.
ret_val = gpio_get_level(GPIO_PORT6, 15) == GPIO_LOW_LEVEL;
}
#elif defined(BOARD_SMART_DEVICE)
if (instance == HW_USDHC2) {
// SD2_CD_B using GPIO2_02
// Bit LOW == pin LOW == Card Detected.
ret_val = gpio_get_level(GPIO_PORT2, 2) == GPIO_LOW_LEVEL;
} else if (instance == HW_USDHC3) {
// SD3_CD_B using GPIO2_00
// Bit LOW == pin LOW == Card Detected.
ret_val = gpio_get_level(GPIO_PORT2, 0) == GPIO_LOW_LEVEL;
}
#else
if (BG_USDHC_PRES_STATE_CDPL(HW_USDHC_PRES_STATE_RD(instance))) {
// Bit HIGH == pin LOW == Card Detected.
ret_val = true;
}
#endif
return ret_val;
}
bool usdhc_write_protected(uint32_t instance)
{
bool ret_val = true;
#if defined(BOARD_SABRE_AI)
if (instance == HW_USDHC1) {
// SDb_WP (CSI0_DATA_EN_GPIO5_20)
// Bit HIGH == pin HIGH == Write Protected.
ret_val = gpio_get_level(GPIO_PORT5, 20) == GPIO_HIGH_LEVEL;
} else if (instance == HW_USDHC3) {
// SDa_WP (SD2_DAT2_GPIO1_13)
// Bit HIGH == pin HIGH == Write Protected.
ret_val = gpio_get_level(GPIO_PORT1, 13) == GPIO_HIGH_LEVEL;
}
#elif defined(BOARD_SMART_DEVICE)
if (instance == HW_USDHC2) {
// SD2_WP using GPIO2_03
// Bit HIGH == pin HIGH == Write Protected.
ret_val = gpio_get_level(GPIO_PORT2, 3) == GPIO_HIGH_LEVEL;
} else if (instance == HW_USDHC3) {
// SD3_WP using GPIO2_01
// Bit HIGH == pin HIGH == Write Protected.
ret_val = gpio_get_level(GPIO_PORT2, 1) == GPIO_HIGH_LEVEL;
}
#else
if (BG_USDHC_PRES_STATE_WPSPL(HW_USDHC_PRES_STATE_RD(instance))) {
// Bit HIGH == pin LOW == NOT Write Protected (Write Enabled).
ret_val = false;
}
#endif
return ret_val;
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/buffers.h
-90
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@@ -1,90 +0,0 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file buffers.h
* @definitions for ALL buffer memory space regions used by sdk drivers
*/
#define IPU_DEFAULT_WORK_CLOCK 264000000
#define IPU_DMA_MEMORY_START 0x40000000
#define IPU_DMA_MEMORY_END 0x43FFFFFF
#define HDMI_AUDIO_BUF_START 0x4fff0000
#define HDMI_AUDIO_BUF_END 0x4fff4000
#define CH23_EBA0 (IPU_DMA_MEMORY_START + 0x00000000)
#define CH23_EBA1 (IPU_DMA_MEMORY_START + 0x00400000)
#define CH27_EBA0 (IPU_DMA_MEMORY_START + 0x00800000)
#define CH27_EBA1 (IPU_DMA_MEMORY_START + 0x00C00000)
#define CH28_EBA0 (IPU_DMA_MEMORY_START + 0x01000000)
#define CH28_EBA1 (IPU_DMA_MEMORY_START + 0x01400000)
#define CH0_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
#define CH0_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
/*for dual video playback*/
#define IPU1_CH23_EBA0 CH23_EBA0
#define IPU1_CH23_EBA1 CH23_EBA1
#define IPU2_CH23_EBA0 CH27_EBA0
#define IPU2_CH23_EBA1 CH27_EBA1
// for video playback after resizing&rotation
#define CH22_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
#define CH22_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
#define CH21_EBA0 (IPU_DMA_MEMORY_START + 0x02000000)
#define CH21_EBA1 (IPU_DMA_MEMORY_START + 0x02400000)
#define CH20_EBA0 (IPU_DMA_MEMORY_START + 0x02800000)
#define CH20_EBA1 (IPU_DMA_MEMORY_START + 0x02C00000)
/* put the TWO video instance on different CS to
improve the performance.
*/
#define VPU_WORK_BUFFERS (0x44100000)
#define VIDEO_BUFFERS_START (0x48000000)
#define VIDEO_BUFFERS_END (0x4FFFFFFF)
/*OCRAM partition table*/
#define VPU_SEC_AXI_START 0x00910000
#define VPU_SEC_AXI_END 0x0091FFFF
/* OCRAM ADMA buffer */
#define USDHC_ADMA_BUFFER1 0x00907000
#define USDHC_ADMA_BUFFER2 0x00908000
#define USDHC_ADMA_BUFFER3 0x00909000
#define USDHC_ADMA_BUFFER4 0x0090A000
// USB buffers
#define QH_BUFFER 0x00908000 // internal RAM
#define TD_BUFFER 0x00908200 // internal RAM
#define SATA_PROTOCOL_BUFFER_BASE 0x0090a000
#define SATA_PROTOCOL_BUFFER_SIZE 0x1000
#define SATA_TRANSFER_BUFFER_BASE 0x0090c000
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/hardware_modules.c
-56
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@@ -1,56 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file hardware.c
* @brief This file contains the module definitions and some init functions.
*
* @ingroup diag_init
*/
#include "registers/regsuart.h"
#include "registers/regsepit.h"
#include "sdk_types.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
#if defined(BOARD_SMART_DEVICE)
uint32_t g_debug_uart_port = HW_UART1;
#else
uint32_t g_debug_uart_port = HW_UART4;
#endif
uint32_t g_system_timer_port = HW_EPIT1;
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/common/readme.txt
-10
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@@ -1,10 +0,0 @@
Notes about board/common directory:
Because the mx6dq and mx6sdl chips share the same boards, board code common to
those chips is placed in this directory.
Board code for the mx6sl goes under in the board directories under board/mx6sl,
as there is very little shared with the mx6dq and mx6sdl since they don't use
the same boards.
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/Makefile
-57
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@@ -1,57 +0,0 @@
#-------------------------------------------------------------------------------
# Copyright (c) 2012 Freescale Semiconductor, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# o Redistributions of source code must retain the above copyright notice, this list
# of conditions and the following disclaimer.
#
# o Redistributions in binary form must reproduce the above copyright notice, this
# list of conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution.
#
# o Neither the name of Freescale Semiconductor, Inc. nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#-------------------------------------------------------------------------------
include $(SDK_ROOT)/mk/common.mk
TARGET_LIB_NAME := board_$(BOARD_WITH_REV)
SOURCES := \
$(SDK_ROOT)/board/common/hardware_modules.c \
$(SDK_ROOT)/board/common/board_io_expanders.c \
$(SDK_ROOT)/board/common/board_i2c.c \
$(SDK_ROOT)/board/common/board_audio.c \
$(SDK_ROOT)/board/common/board_buttons.c \
$(SDK_ROOT)/board/common/board_camera.c \
$(SDK_ROOT)/board/common/board_can.c \
$(SDK_ROOT)/board/common/board_display.c \
$(SDK_ROOT)/board/common/board_hdmi.c \
$(SDK_ROOT)/board/common/board_mipi.c \
$(SDK_ROOT)/board/common/board_nand.c \
$(SDK_ROOT)/board/common/board_network.c \
$(SDK_ROOT)/board/common/board_pcie.c \
$(SDK_ROOT)/board/common/board_sata.c \
$(SDK_ROOT)/board/common/board_usb.c \
$(SDK_ROOT)/board/common/board_usdhc.c \
$(SDK_ROOT)/board/$(TARGET)/$(BOARD)/dcd.c \
$(wildcard iomux/*.c)
include $(SDK_ROOT)/mk/targets.mk
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/dcd.c
-173
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@@ -1,173 +0,0 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "hab_defines.h"
#include "soc_memory_map.h"
#include "sdk.h"
//! @brief dcd data, list of (register, value) pairs to initialize ddr
uint8_t input_dcd[] __attribute__ ((section (".dcd_data")))= {
/*Use default DDR frequency: 528MHz*/
// To allow DDR re-initialization if it was already set up:
// reset the MMDC and disable the chip selects.
DCD_DATA(MMDC_P0_BASE_ADDR + MDMISC_OFFSET, 0x00001602),
DCD_DATA(MMDC_P0_BASE_ADDR + MDCTL_OFFSET, 0x03110000),
/* configure the IOMUX for the DDR3 interface */
//DDR IO TYPE:
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, 0x000c0000),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000),
//CLOCK:
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1, 0x00000030),
//ADDRESS:
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_ADDDS, 0x00000030),
//CONTROL:
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, 0x000c0030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, 0x00003000),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, 0x00003000),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0, 0x00003030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1, 0x00003030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_CTLDS, 0x00000030),
//DATA STROBE:
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, 0x00020000),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6, 0x00000038),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7, 0x00000038),
//DATA:
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, 0x00020000),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B0DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B1DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B2DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B3DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B4DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B5DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B6DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_GRP_B7DS, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, 0x00000030),
DCD_DATA(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, 0x00000030),
/* DDR3 calibrations */
//ZQ:
DCD_DATA(MMDC_P0_BASE_ADDR + MPZQHWCTRL_OFFSET, 0xa1390003),
DCD_DATA(MMDC_P1_BASE_ADDR + MPZQHWCTRL_OFFSET, 0xa1390003),
//write leveling:
DCD_DATA(MMDC_P0_BASE_ADDR + MPWLDECTRL0_OFFSET, 0x001F001F),
DCD_DATA(MMDC_P0_BASE_ADDR + MPWLDECTRL1_OFFSET, 0x001F001F),
DCD_DATA(MMDC_P1_BASE_ADDR + MPWLDECTRL0_OFFSET, 0x00440044),
DCD_DATA(MMDC_P1_BASE_ADDR + MPWLDECTRL1_OFFSET, 0x00440044),
//Read DQS Gating calibration:
DCD_DATA(MMDC_P0_BASE_ADDR + MPDGCTRL0_OFFSET, 0x4333033F),
DCD_DATA(MMDC_P0_BASE_ADDR + MPDGCTRL1_OFFSET, 0x0339033E),
DCD_DATA(MMDC_P1_BASE_ADDR + MPDGCTRL0_OFFSET, 0x433F0343),
DCD_DATA(MMDC_P1_BASE_ADDR + MPDGCTRL1_OFFSET, 0x03490320),
//Read calibration:
DCD_DATA(MMDC_P0_BASE_ADDR + MPRDDLCTL_OFFSET, 0x42363838),
DCD_DATA(MMDC_P1_BASE_ADDR + MPRDDLCTL_OFFSET, 0x3F343242),
//Write calibration:
DCD_DATA(MMDC_P0_BASE_ADDR + MPWRDLCTL_OFFSET, 0x35373933),
DCD_DATA(MMDC_P1_BASE_ADDR + MPWRDLCTL_OFFSET, 0x48254a36),
//read data bit delay: (3 is the reccommended default value)
DCD_DATA(MMDC_P0_BASE_ADDR + MPRDDQBY0DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P0_BASE_ADDR + MPRDDQBY1DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P0_BASE_ADDR + MPRDDQBY2DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P0_BASE_ADDR + MPRDDQBY3DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P1_BASE_ADDR + MPRDDQBY0DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P1_BASE_ADDR + MPRDDQBY1DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P1_BASE_ADDR + MPRDDQBY2DL_OFFSET, 0x33333333),
DCD_DATA(MMDC_P1_BASE_ADDR + MPRDDQBY3DL_OFFSET, 0x33333333),
//complete calibrations by forcing measurement
DCD_DATA(MMDC_P0_BASE_ADDR + MPMUR0_OFFSET, 0x00000800),
DCD_DATA(MMDC_P1_BASE_ADDR + MPMUR0_OFFSET, 0x00000800),
/* configure the MMDC */
//DDR3, 528MHz, 64-bit mode, only MMDC0 is initiated:
DCD_DATA(MMDC_P0_BASE_ADDR + MDPDC_OFFSET, 0x00020036),
DCD_DATA(MMDC_P0_BASE_ADDR + MDOTC_OFFSET, 0x09444040),
DCD_DATA(MMDC_P0_BASE_ADDR + MDCFG0_OFFSET, 0x555A7975),
DCD_DATA(MMDC_P0_BASE_ADDR + MDCFG1_OFFSET, 0xFF538F64),
DCD_DATA(MMDC_P0_BASE_ADDR + MDCFG2_OFFSET, 0x01ff00db),
DCD_DATA(MMDC_P0_BASE_ADDR + MDMISC_OFFSET, 0x00081740),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x00008000),
DCD_DATA(MMDC_P0_BASE_ADDR + MDRWD_OFFSET, 0x000026d2),
DCD_DATA(MMDC_P0_BASE_ADDR + MDOR_OFFSET, 0x005b0e21),
DCD_DATA(MMDC_P0_BASE_ADDR + MDASP_OFFSET, 0x00000027),
DCD_DATA(MMDC_P0_BASE_ADDR + MDCTL_OFFSET, 0xc31a0000),
/* Initialize 2GB DDR3 - Micron MT41J128M */
//MR2:
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x04088032),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x0408803a),
//MR3:
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x00008033),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x0000803b),
//MR1:
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x00048031),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x00048039),
//MR0:
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x09408030),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x09408038),
//DDR device ZQ calibration:
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x04008040),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x04008048),
//final DDR setup, before operation start:
DCD_DATA(MMDC_P0_BASE_ADDR + MDREF_OFFSET, 0x00005800),
DCD_DATA(MMDC_P0_BASE_ADDR + MPODTCTRL_OFFSET, 0x00022227),
DCD_DATA(MMDC_P1_BASE_ADDR + MPODTCTRL_OFFSET, 0x00022227),
DCD_DATA(MMDC_P0_BASE_ADDR + MDPDC_OFFSET, 0x00025576),
DCD_DATA(MMDC_P0_BASE_ADDR + MAPSR_OFFSET, 0x00011006),
DCD_DATA(MMDC_P0_BASE_ADDR + MDSCR_OFFSET, 0x00000000),
};
//! @brief HAB command write data header, with tag,
//! size of dcd data with hdr,
//! parameter field (size of register value and flag)
uint8_t input_dcd_wrt_cmd[] __attribute__ ((section (".dcd_wrt_cmd")))= {
HAB_CMD_WRT_DAT,
EXPAND_UINT16(sizeof(input_dcd) + HDR_BYTES),
WRT_DAT_PAR(0, HAB_DATA_WIDTH_WORD) //!< flag 0, width 4
};
//! @brief HAB dcd header with dcd tag, size of entire dcd and version.
uint8_t input_dcd_hdr[] __attribute__ ((section (".dcd_hdr")))= {
HAB_TAG_DCD,
EXPAND_UINT16(sizeof(input_dcd) + sizeof(input_dcd_wrt_cmd) + HDR_BYTES),
HAB_VER(4,0)
};
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/i.MX6DQ_EVB_X3.IoMuxDesign.xml
-2338
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File diff suppressed because it is too large Load Diff
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/ccm_iomux_config.c
-105
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@@ -1,105 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: ccm_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for ccm module.
void ccm_iomux_config(void)
{
// Config ccm.CCM_CLKO1 to pad GPIO00(T5)
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(0x00000000);
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_GPIO00(0x020E0220)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ccm signal: CCM_CLKO1
// ALT2 (2) - Select instance: kpp signal: KEY_COL5
// ALT3 (3) - Select instance: asrc signal: ASRC_EXT_CLK
// ALT4 (4) - Select instance: epit1 signal: EPIT1_OUT
// ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO00
// ALT6 (6) - Select instance: usb signal: USB_H1_PWR
// ALT7 (7) - Select instance: snvs signal: SNVS_VIO_5
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(ALT0));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_GPIO00(0x020E05F0)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// NOTE: Read Only Field
// The value of this field is fixed and cannot be changed.
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE_V(SLOW));
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/dcic_iomux_config.c
-50
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@@ -1,50 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: dcic_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
#include "registers/regsdcic.h"
#include "io.h"
#include <assert.h>
void dcic_iomux_config(int instance)
{
switch (instance)
{
case HW_DCIC1:
return dcic1_iomux_config();
case HW_DCIC2:
return dcic2_iomux_config();
default:
assert(false);
}
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/ecspi1_iomux_config.c
-439
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@@ -1,439 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: ecspi1_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for ecspi1 module.
void ecspi1_iomux_config(void)
{
// Config ecspi1.ECSPI1_MISO to pad EIM_DATA17(F21)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(0x00000001);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(0x0001B0B0);
// HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17(0x020E0094)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA17
// ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MISO
// ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN06
// ALT3 (3) - Select instance: ipu2 signal: IPU2_CSI1_PIXCLK
// ALT4 (4) - Select instance: dcic1 signal: DCIC1_OUT
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO17
// ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE_V(ALT1));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17(0x020E03A8)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE_V(SLOW));
// Pad EIM_DATA17 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_ECSPI1_MISO_SELECT_INPUT(0x020E07F8)
// DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA17_ALT1
// Selecting Pads Involved in Daisy Chain.
// EIM_DATA17_ALT1 (0) - Select signal ecspi1 ECSPI1_MISO as input from pad EIM_DATA17(ALT1).
// DISP0_DATA22_ALT2 (1) - Select signal ecspi1 ECSPI1_MISO as input from pad DISP0_DATA22(ALT2).
// KEY_COL1_ALT0 (2) - Select signal ecspi1 ECSPI1_MISO as input from pad KEY_COL1(ALT0).
// CSI0_DATA06_ALT2 (3) - Select signal ecspi1 ECSPI1_MISO as input from pad CSI0_DATA06(ALT2).
HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(
BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_V(EIM_DATA17_ALT1));
// Config ecspi1.ECSPI1_MOSI to pad EIM_DATA18(D24)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000001);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B0B0);
// HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E0098)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA18
// ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
// ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
// ALT3 (3) - Select instance: ipu2 signal: IPU2_CSI1_DATA17
// ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
// ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT1));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E03AC)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
// Pad EIM_DATA18 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_ECSPI1_MOSI_SELECT_INPUT(0x020E07FC)
// DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA18_ALT1
// Selecting Pads Involved in Daisy Chain.
// EIM_DATA18_ALT1 (0) - Select signal ecspi1 ECSPI1_MOSI as input from pad EIM_DATA18(ALT1).
// DISP0_DATA21_ALT2 (1) - Select signal ecspi1 ECSPI1_MOSI as input from pad DISP0_DATA21(ALT2).
// KEY_ROW0_ALT0 (2) - Select signal ecspi1 ECSPI1_MOSI as input from pad KEY_ROW0(ALT0).
// CSI0_DATA05_ALT2 (3) - Select signal ecspi1 ECSPI1_MOSI as input from pad CSI0_DATA05(ALT2).
HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(
BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_V(EIM_DATA18_ALT1));
// Config ecspi1.ECSPI1_SCLK to pad EIM_DATA16(C25)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(0x00000001);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(0x0001B0B0);
// HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16(0x020E0090)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA16
// ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SCLK
// ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN05
// ALT3 (3) - Select instance: ipu2 signal: IPU2_CSI1_DATA18
// ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO16
// ALT6 (6) - Select instance: i2c2 signal: I2C2_SDA
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE_V(ALT1));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16(0x020E03A4)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE_V(SLOW));
// Pad EIM_DATA16 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT(0x020E07F4)
// DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA16_ALT1
// Selecting Pads Involved in Daisy Chain.
// EIM_DATA16_ALT1 (0) - Select signal ecspi1 ECSPI1_SCLK as input from pad EIM_DATA16(ALT1).
// DISP0_DATA20_ALT2 (1) - Select signal ecspi1 ECSPI1_SCLK as input from pad DISP0_DATA20(ALT2).
// KEY_COL0_ALT0 (2) - Select signal ecspi1 ECSPI1_SCLK as input from pad KEY_COL0(ALT0).
// CSI0_DATA04_ALT2 (3) - Select signal ecspi1 ECSPI1_SCLK as input from pad CSI0_DATA04(ALT2).
HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(
BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY_V(EIM_DATA16_ALT1));
// Config ecspi1.ECSPI1_SS0 to pad EIM_EB2(E22)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(0x00000001);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(0x0001B0B0);
// HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_EB2(0x020E008C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_EB2
// ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS0
// ALT3 (3) - Select instance: ipu2 signal: IPU2_CSI1_DATA19
// ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
// ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO30
// ALT6 (6) - Select instance: i2c2 signal: I2C2_SCL
// ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG30
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE_V(ALT1));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_EB2(0x020E03A0)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE_V(SLOW));
// Pad EIM_EB2 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_ECSPI1_SS0_SELECT_INPUT(0x020E0800)
// DAISY [1:0] - MUX Mode Select Field Reset: EIM_EB2_ALT1
// Selecting Pads Involved in Daisy Chain.
// EIM_EB2_ALT1 (0) - Select signal ecspi1 ECSPI1_SS0 as input from pad EIM_EB2(ALT1).
// DISP0_DATA23_ALT2 (1) - Select signal ecspi1 ECSPI1_SS0 as input from pad DISP0_DATA23(ALT2).
// KEY_ROW1_ALT0 (2) - Select signal ecspi1 ECSPI1_SS0 as input from pad KEY_ROW1(ALT0).
// CSI0_DATA07_ALT2 (3) - Select signal ecspi1 ECSPI1_SS0 as input from pad CSI0_DATA07(ALT2).
HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(
BF_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY_V(EIM_EB2_ALT1));
// Config ecspi1.ECSPI1_SS1 to pad EIM_DATA19(G21)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(0x00000001);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(0x0001B0B0);
// HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19(0x020E009C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA19
// ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS1
// ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN08
// ALT3 (3) - Select instance: ipu2 signal: IPU2_CSI1_DATA16
// ALT4 (4) - Select instance: uart1 signal: UART1_CTS_B
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO19
// ALT6 (6) - Select instance: epit1 signal: EPIT1_OUT
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE_V(ALT1));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19(0x020E03B0)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE_V(SLOW));
// Pad EIM_DATA19 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_ECSPI1_SS1_SELECT_INPUT(0x020E0804)
// DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA19_ALT1
// Selecting Pads Involved in Daisy Chain.
// EIM_DATA19_ALT1 (0) - Select signal ecspi1 ECSPI1_SS1 as input from pad EIM_DATA19(ALT1).
// DISP0_DATA15_ALT2 (1) - Select signal ecspi1 ECSPI1_SS1 as input from pad DISP0_DATA15(ALT2).
// KEY_COL2_ALT0 (2) - Select signal ecspi1 ECSPI1_SS1 as input from pad KEY_COL2(ALT0).
HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(
BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY_V(EIM_DATA19_ALT1));
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/ecspi_iomux_config.c
-59
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@@ -1,59 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: ecspi_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
#include "registers/regsecspi.h"
#include "io.h"
#include <assert.h>
void ecspi_iomux_config(int instance)
{
switch (instance)
{
case HW_ECSPI1:
return ecspi1_iomux_config();
case HW_ECSPI2:
return ecspi2_iomux_config();
case HW_ECSPI3:
return ecspi3_iomux_config();
case HW_ECSPI4:
return ecspi4_iomux_config();
case HW_ECSPI5:
return ecspi5_iomux_config();
default:
assert(false);
}
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/enet_iomux_config.c
-1338
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bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/epit_iomux_config.c
-50
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@@ -1,50 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: epit_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
#include "registers/regsepit.h"
#include "io.h"
#include <assert.h>
void epit_iomux_config(int instance)
{
switch (instance)
{
case HW_EPIT1:
return epit1_iomux_config();
case HW_EPIT2:
return epit2_iomux_config();
default:
assert(false);
}
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/esai_iomux_config.c
-958
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bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/flexcan1_iomux_config.c
-185
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@@ -1,185 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: flexcan1_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for flexcan1 module.
void flexcan1_iomux_config(void)
{
// Config flexcan1.FLEXCAN1_RX to pad KEY_ROW2(W4)
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(0x00000002);
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(0x0001B0B0);
// HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2(0x020E020C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS2
// ALT1 (1) - Select instance: enet signal: ENET_TX_DATA2
// ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_RX
// ALT3 (3) - Select instance: kpp signal: KEY_ROW2
// ALT4 (4) - Select instance: usdhc2 signal: SD2_VSELECT
// ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO11
// ALT6 (6) - Select instance: hdmi signal: HDMI_TX_CEC_LINE
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_V(ALT2));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2(0x020E05DC)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_V(SLOW));
// Pad KEY_ROW2 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_FLEXCAN1_RX_SELECT_INPUT(0x020E07E4)
// DAISY [1:0] - MUX Mode Select Field Reset: KEY_ROW2_ALT2
// Selecting Pads Involved in Daisy Chain.
// KEY_ROW2_ALT2 (0) - Select signal flexcan1 FLEXCAN1_RX as input from pad KEY_ROW2(ALT2).
// GPIO08_ALT3 (1) - Select signal flexcan1 FLEXCAN1_RX as input from pad GPIO08(ALT3).
// SD3_CLK_ALT2 (2) - Select signal flexcan1 FLEXCAN1_RX as input from pad SD3_CLK(ALT2).
HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(
BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_V(KEY_ROW2_ALT2));
// Config flexcan1.FLEXCAN1_TX to pad GPIO07(R3)
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(0x00000003);
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_GPIO07(0x020E0240)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: esai signal: ESAI_TX4_RX1
// ALT1 (1) - Select instance: ecspi5 signal: ECSPI5_RDY
// ALT2 (2) - Select instance: epit1 signal: EPIT1_OUT
// ALT3 (3) - Select instance: flexcan1 signal: FLEXCAN1_TX
// ALT4 (4) - Select instance: uart2 signal: UART2_TX_DATA
// ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO07
// ALT6 (6) - Select instance: spdif signal: SPDIF_LOCK
// ALT7 (7) - Select instance: usb signal: USB_OTG_HOST_MODE
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE_V(ALT3));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_GPIO07(0x020E0610)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE_V(SLOW));
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/flexcan2_iomux_config.c
-181
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@@ -1,181 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: flexcan2_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for flexcan2 module.
void flexcan2_iomux_config(void)
{
// Config flexcan2.FLEXCAN2_RX to pad KEY_ROW4(V5)
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(0x00000000);
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(0x0001B0B0);
// HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(0x00000000);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4(0x020E021C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_RX
// ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG5
// ALT2 (2) - Select instance: usb signal: USB_OTG_PWR
// ALT3 (3) - Select instance: kpp signal: KEY_ROW4
// ALT4 (4) - Select instance: uart5 signal: UART5_CTS_B
// ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO15
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(ALT0));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4(0x020E05EC)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(SLOW));
// Pad KEY_ROW4 is involved in Daisy Chain.
// Input Select Register:
// IOMUXC_FLEXCAN2_RX_SELECT_INPUT(0x020E07E8)
// DAISY [0] - MUX Mode Select Field Reset: KEY_ROW4_ALT0
// Selecting Pads Involved in Daisy Chain.
// KEY_ROW4_ALT0 (0) - Select signal flexcan2 FLEXCAN2_RX as input from pad KEY_ROW4(ALT0).
// SD3_DATA1_ALT2 (1) - Select signal flexcan2 FLEXCAN2_RX as input from pad SD3_DATA1(ALT2).
HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(
BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(KEY_ROW4_ALT0));
// Config flexcan2.FLEXCAN2_TX to pad KEY_COL4(T6)
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(0x00000000);
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_KEY_COL4(0x020E0218)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_TX
// ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG4
// ALT2 (2) - Select instance: usb signal: USB_OTG_OC
// ALT3 (3) - Select instance: kpp signal: KEY_COL4
// ALT4 (4) - Select instance: uart5 signal: UART5_RTS_B
// ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO14
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(ALT0));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_KEY_COL4(0x020E05E8)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(SLOW));
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/flexcan_iomux_config.c
-50
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@@ -1,50 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: flexcan_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
#include "registers/regsflexcan.h"
#include "io.h"
#include <assert.h>
void flexcan_iomux_config(int instance)
{
switch (instance)
{
case HW_FLEXCAN1:
return flexcan1_iomux_config();
case HW_FLEXCAN2:
return flexcan2_iomux_config();
default:
assert(false);
}
}
bsp/nxp/imx/imx6sx/iMX6_Platform_SDK/board/mx6dq/evb/iomux/gpio3_iomux_config.c
-175
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@@ -1,175 +0,0 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// File: gpio3_iomux_config.c
/* ------------------------------------------------------------------------------
* <auto-generated>
* This code was generated by a tool.
* Runtime Version:3.4.0.0
*
* Changes to this file may cause incorrect behavior and will be lost if
* the code is regenerated.
* </auto-generated>
* ------------------------------------------------------------------------------
*/
#include "iomux_config.h"
#include "registers/regsiomuxc.h"
// Function to configure IOMUXC for gpio3 module.
void gpio3_iomux_config(void)
{
// Config gpio3.GPIO3_IO24 to pad EIM_DATA24(F22)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24(0x020E00B4)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA24
// ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS2
// ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA
// ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS2
// ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS2
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO24
// ALT6 (6) - Select instance: audmux signal: AUD5_RXFS
// ALT7 (7) - Select instance: uart1 signal: UART1_DTR_B
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24(0x020E03C8)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE_V(SLOW));
// Config gpio3.GPIO3_IO25 to pad EIM_DATA25(G22)
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(0x00000005);
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25(0x020E00B8)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: eim signal: EIM_DATA25
// ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS3
// ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA
// ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS3
// ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS3
// ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO25
// ALT6 (6) - Select instance: audmux signal: AUD5_RXC
// ALT7 (7) - Select instance: uart1 signal: UART1_DSR_B
HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE_V(ALT5));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25(0x020E03CC)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// TBD (0) - TBD
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS_V(100K_OHM_PU) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE_V(PULL) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE_V(ENABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE_V(DISABLED) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED_V(100MHZ) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE_V(40_OHM) |
BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE_V(SLOW));
}

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