Merge branch 'master' of https://github.com/RT-Thread/rt-thread

2026-11-09 20:45:41 +08:00 · 2015-09-20 14:51:22 +08:00
commit 72f79d8eef
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,33 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-dm365.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# libc testsuite 
+objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)
+
@@ -0,0 +1,11 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,116 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <mmu.h>
+#include "board.h"
+
+/**
+ * @addtogroup dm365
+ */
+/*@{*/
+
+extern void rt_hw_clock_init(void);
+extern void rt_hw_uart_init(void);
+
+static struct mem_desc dm365_mem_desc[] = {
+	{ 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED },       /* 128M cached SDRAM memory */
+	{ 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED },     /* 128M No cached SDRAM memory */
+	{ 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
+	{ 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* CFG BUS peripherals */
+	{ 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* AEMIF */
+};
+
+
+/**
+ * This function will handle rtos timer
+ */
+void rt_timer_handler(int vector, void *param)
+{
+	rt_tick_increase();
+}
+
+/**
+ * This function will init timer0 for system ticks
+ */
+ void rt_hw_timer_init()
+ {
+	/* timer0, input clocks 24MHz */
+	volatile timer_regs_t *regs =
+		(volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
+
+	/*disable timer*/
+	regs->tcr &= ~(0x3UL << 6);
+
+	//TIMMODE 32BIT UNCHAINED MODE
+	regs->tgcr |=(0x1UL << 2);
+
+	/*not in reset timer */
+	regs->tgcr |= (0x1UL << 0);
+
+	//regs->tgcr &= ~(0x1UL << 1);
+
+	/* set Period Registers */
+	regs->prd12 = 24000000/RT_TICK_PER_SECOND;
+	regs->tim12 = 0;
+
+	/* Set enable mode */
+	regs->tcr |= (0x2UL << 6); //period mode
+	
+
+	/* install interrupt handler */
+	rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
+							RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
+	rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
+
+ }
+
+/**
+ * This function will init dm365 board
+ */
+void rt_hw_board_init()
+{
+	psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
+	psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
+	/* initialize the system clock */
+	//rt_hw_clock_init();
+	davinci_clk_init();
+
+	/* initialize uart */
+	rt_hw_uart_init();
+#ifdef RT_USING_CONSOLE
+	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+	/* initialize mmu */
+	rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
+
+	/* initialize timer0 */
+	rt_hw_timer_init();
+
+}
+
+/*@}*/
@@ -0,0 +1,33 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <dm36x.h>
+
+void rt_hw_board_init(void);
+
+#endif
@@ -0,0 +1,148 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <dm36x.h>
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#endif
+
+extern void rt_hw_interrupt_init(void);
+extern void rt_hw_board_init(void);
+extern void rt_serial_init(void);
+extern void rt_system_timer_init(void);
+extern void rt_system_scheduler_init(void);
+extern void rt_thread_idle_init(void);
+extern void rt_hw_cpu_icache_enable(void);
+extern void rt_show_version(void);
+extern void rt_system_heap_init(void*, void*);
+extern void rt_hw_finsh_init(void);
+extern void rt_application_init(void);
+
+/**
+ * @addtogroup dm365
+ */
+
+/*@{*/
+#if defined(__CC_ARM)
+	extern int Image$$ER_ZI$$ZI$$Base;
+	extern int Image$$ER_ZI$$ZI$$Length;
+	extern int Image$$ER_ZI$$ZI$$Limit;
+#elif (defined (__GNUC__))
+	rt_uint8_t _irq_stack_start[1024];
+	rt_uint8_t _fiq_stack_start[1024];
+	rt_uint8_t _undefined_stack_start[512];
+	rt_uint8_t _abort_stack_start[512];
+	rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
+	extern unsigned char __bss_start;
+	extern unsigned char __bss_end;
+#endif
+
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+#endif
+
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* enable cpu cache */
+	//rt_hw_cpu_icache_enable();
+	//rt_hw_cpu_dcache_enable();
+
+	/* initialize hardware interrupt */
+	rt_hw_interrupt_init();
+
+	/* initialize board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+	
+	/* initialize tick */
+	rt_system_tick_init();
+
+	/* initialize kernel object */
+	rt_system_object_init();
+
+	/* initialize timer system */
+	rt_system_timer_init();
+
+	/* initialize heap memory system */
+#ifdef __CC_ARM
+	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
+#else
+	rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
+#endif
+
+#ifdef RT_USING_MODULE
+	/* initialize module system*/
+	rt_system_module_init();
+#endif
+
+	/* initialize scheduler system */
+	rt_system_scheduler_init();
+
+	/* initialize application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* initialize finsh */
+	finsh_system_init();
+#ifdef RT_USING_DEVICE
+	finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#endif
+
+	/* initialize system timer thread */
+	rt_system_timer_thread_init();
+
+	/* initialize idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	rt_uint32_t RT_UNUSED level;
+
+	/* disable interrupt first */
+	level = rt_hw_interrupt_disable();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/
@@ -0,0 +1,85 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x80000000;
+
+	. = ALIGN(4);
+	.text :	
+	{
+		*(.init)
+		*(.text)
+		*(.gnu.linkonce.t*)
+		
+		/* section information for finsh shell */
+		. = ALIGN(4);
+		__fsymtab_start = .;
+		KEEP(*(FSymTab))
+		__fsymtab_end = .;
+		. = ALIGN(4);
+		__vsymtab_start = .;
+		KEEP(*(VSymTab))
+		__vsymtab_end = .;
+		. = ALIGN(4);	
+
+		/* section information for modules */
+		. = ALIGN(4);
+		__rtmsymtab_start = .;
+		KEEP(*(RTMSymTab))
+		__rtmsymtab_end = .;
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
+
+	. = ALIGN(4);
+	.ctors :
+	{
+		PROVIDE(__ctors_start__ = .);
+		KEEP(*(SORT(.ctors.*)))
+		KEEP(*(.ctors))
+		PROVIDE(__ctors_end__ = .);
+	}
+
+	.dtors :
+	{
+		PROVIDE(__dtors_start__ = .);
+		KEEP(*(SORT(.dtors.*)))
+		KEEP(*(.dtors))
+		PROVIDE(__dtors_end__ = .);
+	}
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+		*(.data.*)
+		*(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(4);
+	.nobss : { *(.nobss) }
+
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	__bss_end = .;
+
+	/* stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+
+	_end = .;
+}
@@ -0,0 +1,31 @@
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+#src_drv = ['']
+
+# The set of source files associated with this SConscript file.
+path = [cwd]
+
+src = Split("""
+davinci_serial.c
+""")
+
+if GetDepend('RT_USING_GPIO'):
+	src += ['gpio.c']
+
+if GetDepend('RT_USING_I2C'):
+	src += ['i2c-davinci.c']
+
+if GetDepend('RT_USING_SDIO'):
+	src += ['mmcsd.c']
+
+if GetDepend('RT_USING_SPI'):
+	src += ['spi-davinci.c']
+
+if GetDepend('RT_USING_LWIP'):
+	src += ['davinci_emac.c']
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,176 @@
+/*
+ * File      : gpio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+#include <rtthread.h>
+#include "gpio.h"
+
+#define GPIO0_BASE			(DAVINCI_GPIO_BASE + 0x10)
+#define GPIO1_BASE			(DAVINCI_GPIO_BASE + 0x38)
+#define GPIO2_BASE			(DAVINCI_GPIO_BASE + 0x60)
+#define GPIO3_BASE			(DAVINCI_GPIO_BASE + 0x88)
+
+
+static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE;
+
+#define GPIO_OE			(dm365_gpio_base + 0x00)
+#define GPIO_DATAIN		(dm365_gpio_base + 0x10)
+#define GPIO_DATAOUT		(dm365_gpio_base + 0x04)
+#define GPIO_CLROUT		(dm365_gpio_base + 0x0C)
+#define GPIO_SETOUT		(dm365_gpio_base + 0x08)
+
+#define gpio_dirin(n)		*(volatile unsigned int *)((GPIO_OE)) |= 1<<(n)
+#define gpio_dirout(n)	*(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n))
+#define gpio_set(n)		*(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n)
+#define gpio_clr(n)		*(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n)
+#define gpio_get(n)		( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 )
+
+ #define GPIO_GRP_MASK (5)
+ 
+static int gpio_to_base(unsigned int gpio)
+{
+	unsigned int grp_idx;
+	int ret;
+
+	grp_idx = gpio >> GPIO_GRP_MASK;  
+
+	switch (grp_idx) {
+		case 0:
+			dm365_gpio_base = (unsigned int)GPIO0_BASE;
+			ret = 0;
+			break;
+		case 1:
+			dm365_gpio_base = (unsigned int)GPIO1_BASE;
+			ret = 0;
+			break;
+		case 2:
+			dm365_gpio_base = (unsigned int)GPIO2_BASE;
+			ret = 0;
+			break;    
+		case 3:
+			dm365_gpio_base = (unsigned int)GPIO3_BASE;
+			ret = 0;
+			break;   
+		default:
+			ret =-RT_EIO;
+			break;      
+	}
+	return ret;
+}
+
+
+int gpio_direction_input(unsigned int gpio)
+{
+	unsigned int offset;
+	int ret=0;
+
+	rt_ubase_t temp = rt_hw_interrupt_disable();
+	ret = gpio_to_base(gpio); 
+	if (ret < 0) {
+		goto gpio_free;
+	}
+	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+
+	gpio_dirin(offset);
+
+gpio_free:
+	rt_hw_interrupt_enable(temp);
+
+	return ret;
+}
+
+int gpio_direction_output(unsigned int gpio, int value)
+{
+	unsigned int offset;
+	int ret=0;
+
+	rt_ubase_t temp = rt_hw_interrupt_disable();
+	ret = gpio_to_base(gpio); 
+	if (ret < 0) {
+		goto gpio_free;
+	}
+
+	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+
+	if (value) {
+		gpio_set(offset);
+	}
+	else {
+		gpio_clr(offset);
+	}
+
+	gpio_dirout(offset);
+
+gpio_free:
+	rt_hw_interrupt_enable(temp);
+
+	return ret;
+}
+
+int  gpio_set_value(unsigned int gpio, int value)
+{
+	unsigned int offset;
+	int ret=0;
+
+	rt_ubase_t temp = rt_hw_interrupt_disable();
+	ret = gpio_to_base(gpio); 
+	if (ret < 0) {
+		goto gpio_free;
+	}
+
+	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+
+	if (value) {
+		gpio_set(offset);
+	}
+	else {
+		gpio_clr(offset);
+	}
+
+gpio_free:
+	rt_hw_interrupt_enable(temp);
+
+	return ret;
+}
+
+int gpio_get_value(unsigned int gpio)
+{
+	unsigned int offset;
+	int ret=0;
+
+	rt_ubase_t temp = rt_hw_interrupt_disable();
+	ret = gpio_to_base(gpio); 
+	if (ret < 0) {
+		goto gpio_free;
+	}
+
+	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+	ret = gpio_get(offset);
+
+gpio_free:
+	rt_hw_interrupt_enable(temp);
+
+	return ret;
+}
+
+
@@ -0,0 +1,73 @@
+/*
+ * File      : gpio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+#ifndef	__DM365_GPIO_H
+#define	__DM365_GPIO_H
+#include <dm36x.h>
+
+#define	GPIO(X)		(X)		
+
+
+#define get_io(r)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r)))
+#define set_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v)
+#define and_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v)
+#define or_io(r,v)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v)
+
+#define v_get_io(r)			*((volatile u_int *)(r))
+#define v_set_io(r,v)		*((volatile u_int *)(r)) = (v)
+#define v_and_io(r,v)		*((volatile u_int *)(r)) &= (v)
+#define v_or_io(r,v)			*((volatile u_int *)(r)) |= (v)
+
+enum gpio_intr_mode
+{
+    LEVELDETECT_LOW = 0,
+    LEVELDETECT_HIGH,
+    RISINGDETECT,  
+    FALLINGDETECT,
+    EDGEDETECT	//both rising-edge and falling-edge detect
+};
+
+enum gpio_intr_req
+{
+    INTR_REQ_A = 0,
+    INTR_REQ_B
+};
+
+enum gpio_intr_num
+{
+	GPIOINT0A = 96,
+	GPIOINT0B,
+	GPIOINT1A,
+	GPIOINT1B, 
+};
+
+enum pin_func_mod
+{
+    GPIO_MOD = 0x80,
+    SPI_MOD =0x01,
+    VP_MOD=0x04,
+    IIC_MOD=0x20
+};
+
+#endif				/* __TI814X_GPIO_H */
@@ -0,0 +1,199 @@
+/*
+ * File      : mii.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-03-18     weety		first version
+ */
+
+
+#ifndef __MII_H__
+#define __MII_H__
+
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
+#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
+#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x003f  /* Unused...                   */
+#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x00c0  /* Unused...                   */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
+#define ADVERTISE_RESV          0x1000  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
+#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
+#define LPA_RESV                0x1000  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status */
+#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status */
+#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u.  We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half.  If your phy does not support
+ * 100T4 this is fine.  If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+rt_inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+        unsigned int ret;
+
+        if (negotiated & LPA_100FULL)
+                ret = LPA_100FULL;
+        else if (negotiated & LPA_100BASE4)
+                ret = LPA_100BASE4;
+        else if (negotiated & LPA_100HALF)
+                ret = LPA_100HALF;
+        else if (negotiated & LPA_10FULL)
+                ret = LPA_10FULL;
+        else
+                ret = LPA_10HALF;
+
+        return ret;
+}
+
+/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
+#define SPEED_10		10
+#define SPEED_100		100
+#define SPEED_1000		1000
+#define SPEED_2500		2500
+#define SPEED_10000		10000
+
+
+#endif /* __MII_H__ */
+
@@ -0,0 +1,145 @@
+/*
+ * File      : mmcsd.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+#ifndef __DAVINCI_MMC_H__
+#define __DAVINCI_MMC_H__
+
+/* DAVINCI_MMCCTL definitions */
+#define MMCCTL_DATRST         (1 << 0)
+#define MMCCTL_CMDRST         (1 << 1)
+#define MMCCTL_WIDTH_8_BIT    (1 << 8)
+#define MMCCTL_WIDTH_4_BIT    (1 << 2)
+#define MMCCTL_DATEG_DISABLED (0 << 6)
+#define MMCCTL_DATEG_RISING   (1 << 6)
+#define MMCCTL_DATEG_FALLING  (2 << 6)
+#define MMCCTL_DATEG_BOTH     (3 << 6)
+#define MMCCTL_PERMDR_LE      (0 << 9)
+#define MMCCTL_PERMDR_BE      (1 << 9)
+#define MMCCTL_PERMDX_LE      (0 << 10)
+#define MMCCTL_PERMDX_BE      (1 << 10)
+
+/* DAVINCI_MMCCLK definitions */
+#define MMCCLK_CLKEN          (1 << 8)
+#define MMCCLK_CLKRT_MASK     (0xFF << 0)
+
+/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
+#define MMCST0_DATDNE         (1 << 0)	/* data done */
+#define MMCST0_BSYDNE         (1 << 1)	/* busy done */
+#define MMCST0_RSPDNE         (1 << 2)	/* command done */
+#define MMCST0_TOUTRD         (1 << 3)	/* data read timeout */
+#define MMCST0_TOUTRS         (1 << 4)	/* command response timeout */
+#define MMCST0_CRCWR          (1 << 5)	/* data write CRC error */
+#define MMCST0_CRCRD          (1 << 6)	/* data read CRC error */
+#define MMCST0_CRCRS          (1 << 7)	/* command response CRC error */
+#define MMCST0_DXRDY          (1 << 9)	/* data transmit ready (fifo empty) */
+#define MMCST0_DRRDY          (1 << 10)	/* data receive ready (data in fifo)*/
+#define MMCST0_DATED          (1 << 11)	/* DAT3 edge detect */
+#define MMCST0_TRNDNE         (1 << 12)	/* transfer done */
+
+/* DAVINCI_MMCST1 definitions */
+#define MMCST1_BUSY           (1 << 0)
+
+/* DAVINCI_MMCCMD definitions */
+#define MMCCMD_CMD_MASK       (0x3F << 0)
+#define MMCCMD_PPLEN          (1 << 7)
+#define MMCCMD_BSYEXP         (1 << 8)
+#define MMCCMD_RSPFMT_MASK    (3 << 9)
+#define MMCCMD_RSPFMT_NONE    (0 << 9)
+#define MMCCMD_RSPFMT_R1456   (1 << 9)
+#define MMCCMD_RSPFMT_R2      (2 << 9)
+#define MMCCMD_RSPFMT_R3      (3 << 9)
+#define MMCCMD_DTRW           (1 << 11)
+#define MMCCMD_STRMTP         (1 << 12)
+#define MMCCMD_WDATX          (1 << 13)
+#define MMCCMD_INITCK         (1 << 14)
+#define MMCCMD_DCLR           (1 << 15)
+#define MMCCMD_DMATRIG        (1 << 16)
+
+/* DAVINCI_MMCFIFOCTL definitions */
+#define MMCFIFOCTL_FIFORST    (1 << 0)
+#define MMCFIFOCTL_FIFODIR_WR (1 << 1)
+#define MMCFIFOCTL_FIFODIR_RD (0 << 1)
+#define MMCFIFOCTL_FIFOLEV    (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
+#define MMCFIFOCTL_ACCWD_4    (0 << 3) /* access width of 4 bytes    */
+#define MMCFIFOCTL_ACCWD_3    (1 << 3) /* access width of 3 bytes    */
+#define MMCFIFOCTL_ACCWD_2    (2 << 3) /* access width of 2 bytes    */
+#define MMCFIFOCTL_ACCWD_1    (3 << 3) /* access width of 1 byte     */
+
+/* DAVINCI_SDIOST0 definitions */
+#define SDIOST0_DAT1_HI       (1 << 0)
+#define SDIOST0_INTPRD        (1 << 1)
+#define SDIOST0_RDWTST        (1 << 2)
+
+/* DAVINCI_SDIOIEN definitions */
+#define SDIOIEN_IOINTEN       (1 << 0)
+#define SDIOIEN_RWSEN         (1 << 1)
+
+/* DAVINCI_SDIOIST definitions */
+#define SDIOIST_IOINT         (1 << 0)
+#define SDIOIST_RWS           (1 << 1)
+
+/* MMCSD Init clock in Hz in opendrain mode */
+#define MMCSD_INIT_CLOCK		200000
+
+#define MAX_CCNT	((1 << 16) - 1)
+
+#define MAX_NR_SG	16
+
+#define MMC_DATA_WRITE	(1 << 8)
+#define MMC_DATA_READ	(1 << 9)
+#define MMC_DATA_STREAM	(1 << 10)
+
+typedef struct {
+	volatile rt_uint32_t MMCCTL;
+	volatile rt_uint32_t MMCCLK;
+	volatile rt_uint32_t MMCST0;
+	volatile rt_uint32_t MMCST1;
+	volatile rt_uint32_t MMCIM;
+	volatile rt_uint32_t MMCTOR;
+	volatile rt_uint32_t MMCTOD;
+	volatile rt_uint32_t MMCBLEN;
+	volatile rt_uint32_t MMCNBLK;
+	volatile rt_uint32_t MMCNBLC;
+	volatile rt_uint32_t MMCDRR;
+	volatile rt_uint32_t MMCDXR;
+	volatile rt_uint32_t MMCCMD;
+	volatile rt_uint32_t MMCARGHL;
+	volatile rt_uint32_t MMCRSP01;
+	volatile rt_uint32_t MMCRSP23;
+	volatile rt_uint32_t MMCRSP45;
+	volatile rt_uint32_t MMCRSP67;
+	volatile rt_uint32_t MMCDRSP;
+	volatile rt_uint32_t reserved0;
+	volatile rt_uint32_t MMCCIDX;
+	volatile rt_uint32_t reserved1[4];
+	volatile rt_uint32_t SDIOCTL;
+	volatile rt_uint32_t SDIOST0;
+	volatile rt_uint32_t SDIOIEN;
+	volatile rt_uint32_t SDIOIST;
+	volatile rt_uint32_t MMCFIFOCTL;
+}mmcsd_regs_t;
+
+extern rt_int32_t rt_hw_mmcsd_init(void);
+
+#endif
@@ -0,0 +1,75 @@
+/*
+ * File      : spi-davinci.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+#ifndef __DAVINCI_SPI_H
+#define __DAVINCI_SPI_H
+
+typedef unsigned long  u32;
+typedef unsigned short u16;
+typedef unsigned char  u8;
+typedef unsigned int   bool;
+
+#define SPI_INTERN_CS	0xFF
+
+enum {
+	SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+	SPI_VERSION_2, /* For DA8xx */
+};
+
+/**
+ * davinci_spi_config - Per-chip-select configuration for SPI slave devices
+ *
+ * @wdelay:	amount of delay between transmissions. Measured in number of
+ *		SPI module clocks.
+ * @odd_parity:	polarity of parity flag at the end of transmit data stream.
+ *		0 - odd parity, 1 - even parity.
+ * @parity_enable: enable transmission of parity at end of each transmit
+ *		data stream.
+ * @io_type:	type of IO transfer. Choose between polled, interrupt and DMA.
+ * @timer_disable: disable chip-select timers (setup and hold)
+ * @c2tdelay:	chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:	chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:	transmit data finished to SPI ENAn pin inactive time. Measured
+ *		in number of SPI clocks.
+ * @c2edelay:	chip-select active to SPI ENAn signal active time. Measured in
+ *		number of SPI clocks.
+ */
+struct davinci_spi_config {
+	u8	wdelay;
+	u8	odd_parity;
+	u8	parity_enable;
+#define SPI_IO_TYPE_INTR	0
+#define SPI_IO_TYPE_POLL	1
+#define SPI_IO_TYPE_DMA		2
+	u8	io_type;
+	u8	timer_disable;
+	u8	c2tdelay;
+	u8	t2cdelay;
+	u8	t2edelay;
+	u8	c2edelay;
+};
+
+extern int rt_hw_spi_init(void);
+
+#endif	/* __DAVINCI_SPI_H */
@@ -0,0 +1,22 @@
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split("""
+start_gcc.S
+dm365.c
+dma.c
+findbit.S
+interrupt.c
+psc.c
+reset.c
+system_clock.c
+trap.c
+""")
+
+# The set of source files associated with this SConscript file.
+path = [cwd]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,75 @@
+/*
+ * File      : dm365_timer.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+#ifndef __ASM_ARCH_TIME_H
+#define __ASM_ARCH_TIME_H
+
+/* Timer register offsets */
+#define PID12				0x0
+#define TIM12				0x10
+#define TIM34				0x14
+#define PRD12				0x18
+#define PRD34				0x1c
+#define TCR				0x20
+#define TGCR				0x24
+#define WDTCR				0x28
+#define CMP12(n)			(0x60 + ((n) << 2))
+
+/* Timer register bitfields */
+#define ENAMODE12_SHIFT 		6
+#define ENAMODE34_SHIFT 		22
+#define TCR_ENAMODE_DISABLE		0x0
+#define TCR_ENAMODE_ONESHOT		0x1
+#define TCR_ENAMODE_PERIODIC		0x2
+#define TCR_ENAMODE_MASK		0x3
+
+#define TGCR_TIMMODE_SHIFT		2
+#define TGCR_TIMMODE_64BIT_GP		0x0
+#define TGCR_TIMMODE_32BIT_UNCHAINED	0x1
+#define TGCR_TIMMODE_64BIT_WDOG 	0x2
+#define TGCR_TIMMODE_32BIT_CHAINED	0x3
+
+#define TGCR_TIM12RS_SHIFT		0
+#define TGCR_TIM34RS_SHIFT		1
+#define TGCR_RESET			0x0
+#define TGCR_UNRESET			0x1
+#define TGCR_RESET_MASK 		0x3
+
+#define WDTCR_WDEN_SHIFT		14
+#define WDTCR_WDEN_DISABLE		0x0
+#define WDTCR_WDEN_ENABLE		0x1
+#define WDTCR_WDKEY_SHIFT		16
+#define WDTCR_WDKEY_SEQ0		0xA5C6
+#define WDTCR_WDKEY_SEQ1		0xDA7E
+
+enum {
+	T0_BOT,
+	T0_TOP,
+	T1_BOT,
+	T1_TOP,
+	NUM_TIMERS
+};
+
+#endif /* __ASM_ARCH_TIME_H__ */
+
@@ -0,0 +1,71 @@
+/*
+ * File      : psc.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+#include "dm36x.h"
+
+
+/* ------------------------------------------------------------------------ *
+ *  psc_change_state( id, state )                                           *
+ *      id    = Domain #ID                                                  *
+ *      state = ( ENABLE, DISABLE, SYNCRESET, RESET )                       *
+ *              (   =3  ,   =2   ,    =1    ,   =0  )                       *
+ * ------------------------------------------------------------------------ */
+void psc_change_state(int id, int state)
+{
+	rt_uint32_t mdstat, mdctl;
+
+	if (id > DAVINCI_DM365_LPSC_KALEIDO)
+		return;
+
+	mdstat = PSC_MDSTAT_BASE + (id * 4);
+	mdctl = PSC_MDCTL_BASE + (id * 4);
+
+    /*
+     *  Step 0 - Ignore request if the state is already set as is
+     */
+    if ((readl(mdstat) & 0x1f) == state)
+        return;
+
+    /*
+     *  Step 1 - Wait for PTSTAT.GOSTAT to clear
+     */
+    while (readl(PSC_PTSTAT) & 1) ;
+
+    /*
+     *  Step 2 - Set MDCTLx.NEXT to new state
+     */
+    writel(readl(mdctl) & (~0x1f), mdctl);
+    writel(readl(mdctl) | state, mdctl);
+
+    /*
+     *  Step 3 - Start power transition ( set PTCMD.GO to 1 )
+     */
+    writel(readl(PSC_PTCMD) | 1, PSC_PTCMD);
+
+    /*
+     *  Step 4 - Wait for PTSTAT.GOSTAT to clear
+     */
+    while (readl(PSC_PTSTAT) & 1) ;
+}
+
@@ -0,0 +1,109 @@
+/*
+ * File      : psc.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+#ifndef __DM36X_PSC_H
+#define __DM36X_PSC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* PSC register offsets */
+#define EPCPR		0x070
+#define PTCMD		0x120
+#define PTSTAT		0x128
+#define PDSTAT		0x200
+#define PDCTL1		0x304
+#define MDSTAT(n)	(0x800 + (n) * 4)
+#define MDCTL(n)	(0xA00 + (n) * 4)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN		0
+#define DAVINCI_GPSC_DSPDOMAIN		1
+
+
+#define DAVINCI_DM365_LPSC_TPCC		0
+#define DAVINCI_DM365_LPSC_TPTC0	1
+#define DAVINCI_DM365_LPSC_TPTC1	2
+#define DAVINCI_DM365_LPSC_TPTC2	3
+#define DAVINCI_DM365_LPSC_TPTC3	4
+#define DAVINCI_DM365_LPSC_TIMER3	5
+#define DAVINCI_DM365_LPSC_SPI1		6
+#define DAVINCI_DM365_LPSC_MMC_SD1	7
+#define DAVINCI_DM365_LPSC_McBSP	8
+#define DAVINCI_DM365_LPSC_USB		9
+#define DAVINCI_DM365_LPSC_PWM3		10
+#define DAVINCI_DM365_LPSC_SPI2		11
+#define DAVINCI_DM365_LPSC_RTO		12
+#define DAVINCI_DM365_LPSC_DDR_EMIF	13
+#define DAVINCI_DM365_LPSC_AEMIF	14
+#define DAVINCI_DM365_LPSC_MMC_SD	15
+#define DAVINCI_DM365_LPSC_MMC_SD0	15
+#define DAVINCI_DM365_LPSC_MEMSTICK	16
+#define DAVINCI_DM365_LPSC_TIMER4	17
+#define DAVINCI_DM365_LPSC_I2C		18
+#define DAVINCI_DM365_LPSC_UART0	19
+#define DAVINCI_DM365_LPSC_UART1	20
+#define DAVINCI_DM365_LPSC_UHPI		21
+#define DAVINCI_DM365_LPSC_SPI0		22
+#define DAVINCI_DM365_LPSC_PWM0		23
+#define DAVINCI_DM365_LPSC_PWM1		24
+#define DAVINCI_DM365_LPSC_PWM2		25
+#define DAVINCI_DM365_LPSC_GPIO		26
+#define DAVINCI_DM365_LPSC_TIMER0	27
+#define DAVINCI_DM365_LPSC_TIMER1	28
+#define DAVINCI_DM365_LPSC_TIMER2	29
+#define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30
+#define DAVINCI_DM365_LPSC_ARM		31
+#define DAVINCI_DM365_LPSC_SCR0		33
+#define DAVINCI_DM365_LPSC_SCR1		34
+#define DAVINCI_DM365_LPSC_EMU		35
+#define DAVINCI_DM365_LPSC_CHIPDFT	36
+#define DAVINCI_DM365_LPSC_PBIST	37
+#define DAVINCI_DM365_LPSC_SPI3		38
+#define DAVINCI_DM365_LPSC_SPI4		39
+#define DAVINCI_DM365_LPSC_CPGMAC	40
+#define DAVINCI_DM365_LPSC_RTC		41
+#define DAVINCI_DM365_LPSC_KEYSCAN	42
+#define DAVINCI_DM365_LPSC_ADCIF	43
+#define DAVINCI_DM365_LPSC_VOICE_CODEC	44
+#define DAVINCI_DM365_LPSC_DAC_CLKRES	45
+#define DAVINCI_DM365_LPSC_DAC_CLK	46
+#define DAVINCI_DM365_LPSC_VPSSMSTR	47
+#define DAVINCI_DM365_LPSC_IMCOP	50
+#define DAVINCI_DM365_LPSC_KALEIDO	51
+
+#define PSC_ENABLE     3
+#define PSC_DISABLE    2
+#define PSC_SYNCRESET  1
+#define PSC_RESET      0
+
+void psc_change_state(int id, int state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,77 @@
+/*
+ * File      : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "dm36x.h"
+
+/**
+ * @addtogroup DM36X
+ */
+/*@{*/
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void machine_reset()
+{
+	reset_system();
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void machine_shutdown()
+{
+
+}
+
+#ifdef RT_USING_FINSH
+
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
+
+#ifdef FINSH_USING_MSH
+int cmd_reset(int argc, char** argv)
+{
+	rt_hw_cpu_reset();
+	return 0;
+}
+
+int cmd_shutdown(int argc, char** argv)
+{
+	rt_hw_cpu_shutdown();
+	return 0;
+}
+
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
+
+#endif
+#endif
+
+/*@}*/
@@ -0,0 +1,37 @@
+/*
+ * File      : system_clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+
+#include <rtthread.h>
+#include "dm36x.h"
+
+
+/**
+ * @brief System Clock Configuration
+ */
+void rt_hw_clock_init(void)
+{
+
+}
+
@@ -0,0 +1,200 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2010-11-13     weety		first version
+ */
+
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "dm36x.h"
+
+/**
+ * @addtogroup DM36X
+ */
+/*@{*/
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+
+void rt_hw_show_register (struct rt_hw_register *regs)
+{
+	rt_kprintf("Execption:\n");
+	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When ARM7TDMI comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_udef(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("undefined instruction\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+
+#ifdef RT_USING_FINSH
+	list_thread();
+#endif
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("software interrupt\n");
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("prefetch abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+
+#ifdef RT_USING_FINSH
+	list_thread();
+#endif
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_register *regs)
+{
+	rt_uint32_t fault_addr;
+	rt_uint32_t fault_status;
+	asm  volatile ("mrc p15, 0, %0, c6, c0, 0"
+			:
+			:"r"(fault_addr)
+			:"cc");
+	rt_kprintf("unhandler access to 0x%08x\n", fault_addr);
+
+	/* read DFSR */
+	asm volatile ("MRC p15, 0, %0, c5, c0, 0"
+			:
+			:"r"(fault_status)
+			:"cc");
+	rt_kprintf("fault status 0x%08x\n", fault_status);
+
+	rt_hw_show_register(regs);
+
+	rt_kprintf("data abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+
+#ifdef RT_USING_FINSH
+	list_thread();
+#endif
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_register *regs)
+{
+	rt_kprintf("not used\n");
+	rt_hw_show_register(regs);
+	rt_hw_cpu_shutdown();
+}
+
+extern struct rt_irq_desc irq_desc[];
+
+
+void rt_hw_trap_irq()
+{
+	rt_isr_handler_t isr_func;
+	rt_uint32_t val, irq, mask;
+	void *param;
+
+	/* get irq number */
+	val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24);
+	irq = (val >> 2) - 1;
+	/* clear pending register */
+	mask = 1 << (irq & 0x1f);
+	if (irq > 31)
+		writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1
+	else
+		writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0
+	
+	/* get interrupt service routine */
+	isr_func = irq_desc[irq].handler;
+	param = irq_desc[irq].param;
+
+	/* turn to interrupt service routine */
+	isr_func(irq, param);
+	irq_desc[irq].counter++;
+}
+
+void rt_hw_trap_fiq()
+{
+	rt_kprintf("fast interrupt request\n");
+}
+
+/*@}*/
@@ -0,0 +1,84 @@
+import os
+# toolchains options
+ARCH     = 'arm'
+CPU      = 'dm36x'
+TextBase = '0x80000000'
+
+CROSS_TOOL 	= 'gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	#EXEC_PATH 	= '/opt/arm-2010q1/bin'
+	EXEC_PATH = r'D:\arm-2013.11\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'E:/Keil'
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=arm926ej-s'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -DTEXT_BASE=' + TextBase
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_dm365.map,-cref,-u,_start -T dm365_ram.ld' + ' -Ttext ' + TextBase
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSS9'
+    CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --strict --info sizes --info totals --info unused --info veneers --list rtthread-mini2440.map --ro-base 0x30000000 --entry Entry_Point --first Entry_Point'
+
+    CFLAGS += ' -I"' + EXEC_PATH + '/ARM/RV31/INC"'
+    LFLAGS += ' --libpath "' + EXEC_PATH + '/ARM/RV31/LIB"'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+
+    CFLAGS = ''
+    AFLAGS = ''
+    LFLAGS = ''
@@ -0,0 +1,153 @@
+/*
+ * File      : drv_hwtimer.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2015-09-02     heyuanjie87      the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "lpc_timer.h"
+#include "lpc_clkpwr.h"
+#include "drv_hwtimer.h"
+
+#ifdef RT_USING_HWTIMER
+
+static void NVIC_Configuration(void)
+{
+    NVIC_EnableIRQ(TIMER0_IRQn);
+}
+
+static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    LPC_TIM_TypeDef *tim;
+    TIM_TIMERCFG_Type cfg;
+
+    tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
+
+    TIM_DeInit(tim);
+
+    if (state == 1)
+    {
+        NVIC_Configuration();
+
+        cfg.PrescaleOption = TIM_PRESCALE_TICKVAL;
+        cfg.PrescaleValue = 0xFFFF;
+        TIM_Init(tim, TIM_TIMER_MODE, &cfg);
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+    LPC_TIM_TypeDef *tim;
+    TIM_MATCHCFG_Type match;
+
+    tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
+
+    match.MatchChannel = 0;
+    match.IntOnMatch = ENABLE;
+    match.ResetOnMatch = ENABLE;
+    match.StopOnMatch = (opmode == HWTIMER_MODE_ONESHOT)? ENABLE : DISABLE;
+    match.ExtMatchOutputType = 0;
+    match.MatchValue = t;
+
+    TIM_ConfigMatch(tim, &match);
+    TIM_Cmd(tim, ENABLE);
+
+    return RT_EOK;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+    LPC_TIM_TypeDef *tim;
+
+    tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
+
+    TIM_Cmd(tim, DISABLE);
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    LPC_TIM_TypeDef *tim;
+    rt_err_t err = RT_EOK;
+
+    tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        uint32_t clk;
+        uint32_t pre;
+
+        clk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
+        pre = clk / *((uint32_t*)arg) - 1;
+        tim->PR = pre;
+    }
+    break;
+    default:
+    {
+        err = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return err;
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    LPC_TIM_TypeDef *tim;
+
+    tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
+
+    return tim->TC;
+}
+
+static const struct rt_hwtimer_info _info =
+{
+    1000000,           /* the maximum count frequency can be set */
+    2000,              /* the minimum count frequency can be set */
+    0xFFFFFF,          /* the maximum counter value */
+    HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
+};
+
+static const struct rt_hwtimer_ops _ops =
+{
+    timer_init,
+    timer_start,
+    timer_stop,
+    timer_counter_get,
+    timer_ctrl,
+};
+
+static rt_hwtimer_t _timer0;
+
+int lpc_hwtimer_init(void)
+{
+    _timer0.info = &_info;
+    _timer0.ops  = &_ops;
+
+    rt_device_hwtimer_register(&_timer0, "timer0", LPC_TIM0);
+
+    return 0;
+}
+
+void TIMER0_IRQHandler(void)
+{
+    if (TIM_GetIntStatus(LPC_TIM0, TIM_MR0_INT) != RESET)
+    {
+        TIM_ClearIntPending(LPC_TIM0, TIM_MR0_INT);
+        rt_device_hwtimer_isr(&_timer0);
+    }
+}
+
+INIT_BOARD_EXPORT(lpc_hwtimer_init);
+#endif
@@ -0,0 +1,8 @@
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+
+int stm32_hwtimer_init(void);
+
+
+#endif
@@ -0,0 +1,157 @@
+/*
+ * File      : drv_hwtimer.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2015-09-02     heyuanjie87      the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include "drv_hwtimer.h"
+
+#ifdef RT_USING_HWTIMER
+
+static void NVIC_Configuration(void)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    /* Enable the TIM5 global Interrupt */
+    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x00;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    TIM_TypeDef *tim;
+
+    tim = (TIM_TypeDef *)timer->parent.user_data;
+
+    TIM_DeInit(tim);
+
+    if (state == 1)
+    {
+        NVIC_Configuration();
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
+        TIM_CounterModeConfig(tim, TIM_CounterMode_Up);
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+    TIM_TypeDef *tim;
+    uint16_t m;
+
+    tim = (TIM_TypeDef *)timer->parent.user_data;
+    TIM_SetAutoreload(tim, t);
+    m = (opmode == HWTIMER_MODE_ONESHOT)? TIM_OPMode_Single : TIM_OPMode_Repetitive;
+    TIM_SelectOnePulseMode(tim, m);
+    TIM_Cmd(tim, ENABLE);
+
+    return RT_EOK;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+    TIM_TypeDef *tim;
+
+    tim = (TIM_TypeDef *)timer->parent.user_data;
+    TIM_Cmd(tim, DISABLE);
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    TIM_TypeDef *tim;
+    rt_err_t err = RT_EOK;
+
+    tim = (TIM_TypeDef *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        RCC_ClocksTypeDef clk;
+        uint16_t val;
+        rt_uint32_t freq;
+
+        RCC_GetClocksFreq(&clk);
+
+        freq = *((rt_uint32_t*)arg);
+        clk.PCLK1_Frequency *= 2;
+        val = clk.PCLK1_Frequency/freq;
+
+        TIM_ITConfig(tim, TIM_IT_Update, DISABLE);
+        TIM_PrescalerConfig(tim, val - 1, TIM_PSCReloadMode_Immediate);
+        TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
+        TIM_ITConfig(tim, TIM_IT_Update, ENABLE);
+    }
+    break;
+    default:
+    {
+        err = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return err;
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    TIM_TypeDef *tim;
+
+    tim = (TIM_TypeDef *)timer->parent.user_data;
+
+    return TIM_GetCounter(tim);
+}
+
+static const struct rt_hwtimer_info _info =
+{
+    1000000,           /* the maximum count frequency can be set */
+    2000,              /* the minimum count frequency can be set */
+    0xFFFF,            /* the maximum counter value */
+    HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
+};
+
+static const struct rt_hwtimer_ops _ops =
+{
+    timer_init,
+    timer_start,
+    timer_stop,
+    timer_counter_get,
+    timer_ctrl,
+};
+
+static rt_hwtimer_t _timer0;
+
+int stm32_hwtimer_init(void)
+{
+    _timer0.info = &_info;
+    _timer0.ops  = &_ops;
+
+    rt_device_hwtimer_register(&_timer0, "timer0", TIM2);
+
+    return 0;
+}
+
+void TIM2_IRQHandler(void)
+{
+    if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET)
+    {
+        TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
+        rt_device_hwtimer_isr(&_timer0);
+    }
+}
+
+INIT_BOARD_EXPORT(stm32_hwtimer_init);
+#endif
@@ -0,0 +1,8 @@
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+
+int stm32_hwtimer_init(void);
+
+
+#endif
@@ -69,6 +69,9 @@
 /* Using GPIO pin framework */
 #define RT_USING_PIN

+/* Using Hardware Timer framework */
+//#define RT_USING_HWTIMER
+
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
@@ -23,7 +23,7 @@
 */
 /*@{*/

-static void rt_timer_handler(int vector)
+static void rt_timer_handler(int vector, void* param)
 {
 	rt_tick_increase();
 }
@@ -47,7 +47,7 @@ void rt_hw_board_init(void)
 	outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256);

 	/* install interrupt handler */
-	rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL);
+	rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick");
 	rt_hw_interrupt_umask(INTTIMER0);

 #ifdef RT_USING_HOOK
@@ -214,19 +214,14 @@ static rt_size_t rt_console_read(rt_device_t dev, rt_off_t pos, void* buffer, rt
    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }

-static void rt_console_isr(int vector)
+static void rt_console_isr(int vector, void* param)
 {
-//    rt_kprintf("rt_console_isr\r\n");
-//    RT_ASSERT(INTKEYBOARD == vector);
-//	finsh_notify();
-
    char c;
    rt_base_t level;

    while(1)
    {
        c = rt_keyboard_getc();
-//        rt_kprintf(" %x", c);

        if(c == 0)
        {
@@ -285,11 +280,9 @@ static void rt_console_isr(int vector)
 void rt_hw_console_init(void)
 {
    rt_cga_init();
-//    rt_serial_init();
-

    /* install  keyboard isr */
-    rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL);
+    rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL, "kbd");
    rt_hw_interrupt_umask(INTKEYBOARD);

    console_device.type 		= RT_Device_Class_Char;
@@ -320,8 +313,6 @@ void rt_hw_console_init(void)
 *	the name is change to rt_hw_console_output in the v0.3.0
 *
 */
-
-//void rt_console_puts(const char* str)
 void rt_hw_console_output(const char* str)
 {
    while (*str)
@@ -330,49 +321,4 @@ void rt_hw_console_output(const char* str)
    }
 }

-//#define BY2CONS 512
-//
-//static struct
-//{
-//    rt_uint8_t buf[BY2CONS];
-//    rt_uint32_t rpos;
-//    rt_uint32_t wpos;
-//} cons;
-//
-//static void rt_console_intr(char (*proc)(void))
-//{
-//    int c;
-//
-//    while ((c = (*proc)()) != -1)
-//    {
-//        if (c == 0)
-//            continue;
-//        cons.buf[cons.wpos++] = c;
-//        if (cons.wpos == BY2CONS)
-//            cons.wpos = 0;
-//    }
-//}
-
-///**
-// * return the next input character from the console,either from serial,
-// * or keyboard
-// *
-// */
-//int rt_console_getc(void)
-//{
-//    int c;
-//
-//    rt_console_intr(rt_serial_getc);
-//    rt_console_intr(rt_keyboard_getc);
-//
-//    if (cons.rpos != cons.wpos)
-//    {
-//        c = cons.buf[cons.rpos++];
-//        if (cons.rpos == BY2CONS)
-//            cons.rpos = 0;
-//        return c;
-//    }
-//    return 0;
-//}
-
 /*@}*/
@@ -2,10 +2,6 @@
 #ifndef __RTTHREAD_CFG_H__
 #define __RTTHREAD_CFG_H__

-#define RT_USING_NEWLIB
-//#define RT_USING_PTHREADS
-#define RT_USING_DFS_DEVFS
-
 /* RT_NAME_MAX*/
 #define RT_NAME_MAX	    8

@@ -77,6 +73,9 @@
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION

+// #define RT_USING_LIBC
+// #define RT_USING_PTHREADS
+
 /* SECTION: device filesystem */
 #define RT_USING_DFS

@@ -96,6 +95,8 @@
 /* the max number of opened files 		*/
 #define DFS_FD_MAX					4

+#define RT_USING_DFS_DEVFS
+
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 //#define RT_USING_LWIP
 /* LwIP uses RT-Thread Memory Management */
@@ -45,7 +45,7 @@ if PLATFORM == 'gcc':
    DEVICE = ' -mtune=generic'
    CFLAGS = DEVICE + ' -Wall'
    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-ia32.map,-cref,-u,_start -T x86_ram.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-ia32.map,-cref,-u,_start -T x86_ram.lds -nostdlib'

    CPATH = ''
    LPATH = ''
@@ -230,6 +230,7 @@ off_t lseek(int fd, off_t offset, int whence)
        break;

    default:
+        fd_put(d);
        rt_set_errno(-DFS_STATUS_EINVAL);

        return -1;
@@ -237,6 +238,7 @@ off_t lseek(int fd, off_t offset, int whence)

    if (offset < 0)
    {
+        fd_put(d);
        rt_set_errno(-DFS_STATUS_EINVAL);

        return -1;
@@ -457,6 +459,7 @@ int mkdir(const char *path, mode_t mode)

    if (result < 0)
    {
+        fd_put(d);
        fd_put(d);
        rt_set_errno(result);

@@ -465,6 +468,7 @@ int mkdir(const char *path, mode_t mode)

    dfs_file_close(d);
    fd_put(d);
+    fd_put(d);

    return 0;
 }
@@ -0,0 +1,98 @@
+定时器设备
+===
+  
+##功能
+---
+* 时间测量
+* 周期或单次执行回调函数
+  
+##编译
+---
+1. 在rtconfig.h添加 `#define RT_USING_HWTIMER`
+  
+##使用流程
+---
+1. 以读写方式打开设备
+2. 设置超时回调函数（如果需要）
+3. 根据需要设置定时模式（单次/周期）
+4. 设置计数频率（可选）
+5. 写入超时值，定时器随即启动
+6. 停止定时器（可选）
+7. 关闭设备（如果需要）
+  
+应用参考 [hwtimer_test] (/examples/test/hwtimer\_test.c)
+
+##驱动编写指南
+---
+###操作接口
+
+``` 
+struct rt_hwtimer_ops
+{
+    void (*init)(struct rt_hwtimer_device *timer, rt_uint32_t state);
+    rt_err_t (*start)(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode);
+    void (*stop)(struct rt_hwtimer_device *timer);
+    rt_uint32_t (*count_get)(struct rt_hwtimer_device *timer);
+    rt_err_t (*control)(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args);
+};
+```
+
+* init - state <1 打开设备 0 关闭设备> 
+* start - cnt <超时值> - mode <单次/周期>
+* stop - <停止计数>
+* count_get - <读取计数器值>
+* control - <设置计数频率 >
+
+###定时器特征信息
+  
+```
+struct rt_hwtimer_info
+{
+    rt_int32_t maxfreq;   
+    rt_int32_t minfreq;    
+    rt_uint32_t maxcnt;     
+    rt_uint8_t  cntmode;  
+ };
+```
+
+* maxfreq <设备支持的最大计数频率>
+* minfreq <设备支持的最小计数频率>
+* maxcnt  <计数器最大计数值>
+* cntmode <递增计数/递减计数>
+  
+###注册设备
+```
+static rt_hwtimer_t _timer0;
+int stm32_hwtimer_init(void)
+{
+    _timer0.info = &_info;
+    _timer0.ops  = &_ops;
+
+    rt_device_hwtimer_register(&_timer0, "timer0", TIM2);
+
+    return 0;
+}
+```
+  
+###定时器中断
+```
+void timer_irq_handler(void)
+{
+    //其它操作
+    
+    rt_device_hwtimer_isr(&_timer0);
+}
+```
+
+##注意事项
+---
+  
+<font color="#FF0000">可能出现定时误差</font>
+  
+
+误差原因：
+
+假设计数器最大值0xFFFF，计数频率1Mhz，定时时间1秒又1微秒。
+  
+由于定时器一次最多只能计时到65535us，对于1000001us的定时要求。
+可以50000us定时20次完成，此时将会出现计算误差1us。
@@ -0,0 +1,8 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd + '/../include']
+group   = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_HWTIMER'], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,78 @@
+#ifndef __HWTIMER_H__
+#define __HWTIMER_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Timer Control Command */
+typedef enum
+{
+    HWTIMER_CTRL_FREQ_SET = 0x01,    /* set the count frequency */
+    HWTIMER_CTRL_STOP,               /* stop timer */
+    HWTIMER_CTRL_INFO_GET,           /* get a timer feature information */
+    HWTIMER_CTRL_MODE_SET            /* Setting the timing mode(oneshot/period) */
+} rt_hwtimer_ctrl_t;
+
+/* Timing Mode */
+typedef enum
+{
+    HWTIMER_MODE_ONESHOT = 0x01,
+    HWTIMER_MODE_PERIOD
+} rt_hwtimer_mode_t;
+
+/* Time Value */
+typedef struct rt_hwtimerval
+{
+    rt_int32_t sec;      /* second */
+    rt_int32_t usec;     /* microsecond */
+} rt_hwtimerval_t;
+
+#define HWTIMER_CNTMODE_UP      0x01 /* increment count mode */
+#define HWTIMER_CNTMODE_DW      0x02 /* decreasing count mode */
+
+struct rt_hwtimer_device;
+
+struct rt_hwtimer_ops
+{
+    void (*init)(struct rt_hwtimer_device *timer, rt_uint32_t state);
+    rt_err_t (*start)(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode);
+    void (*stop)(struct rt_hwtimer_device *timer);
+    rt_uint32_t (*count_get)(struct rt_hwtimer_device *timer);
+    rt_err_t (*control)(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args);
+};
+
+/* Timer Feature Information */
+struct rt_hwtimer_info
+{
+    rt_int32_t maxfreq;    /* the maximum count frequency timer support */
+    rt_int32_t minfreq;    /* the minimum count frequency timer support */
+    rt_uint32_t maxcnt;    /* counter maximum value */
+    rt_uint8_t  cntmode;   /* count mode (inc/dec) */
+};
+
+typedef struct rt_hwtimer_device
+{
+    struct rt_device parent;
+    const struct rt_hwtimer_ops *ops;
+    const struct rt_hwtimer_info *info;
+
+    rt_int32_t freq;                /* counting frequency set by the user */
+    rt_int32_t overflow;            /* timer overflows */
+    float period_sec;               
+    rt_int32_t cycles;              /* how many times will generate a timeout event after overflow */
+    rt_int32_t reload;              /* reload cycles(using in period mode) */
+    rt_hwtimer_mode_t mode;         /* timing mode(oneshot/period) */
+} rt_hwtimer_t;
+
+rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data);
+void rt_device_hwtimer_isr(rt_hwtimer_t *timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -59,6 +59,11 @@ extern "C"{

 #define RT_SPI_MODE_MASK    (RT_SPI_CPHA | RT_SPI_CPOL | RT_SPI_MSB)

+#define RT_SPI_CS_HIGH  (1<<4)                             /* Chipselect active high */
+#define RT_SPI_NO_CS    (1<<5)                             /* No chipselect */
+#define RT_SPI_3WIRE    (1<<6)                             /* SI/SO pin shared */
+#define RT_SPI_READY    (1<<7)                             /* Slave pulls low to pause */
+
 /**
 * SPI message structure
 */
@@ -370,6 +370,10 @@ rt_inline void rt_work_init(struct rt_work* work, void (*work_func)(struct rt_wo
 #include "drivers/can.h"
 #endif

+#ifdef RT_USING_HWTIMER
+#include "drivers/hwtimer.h"
+#endif
+
 #ifdef __cplusplus
 }
 #endif
@@ -467,6 +467,7 @@ static long _list_device(struct rt_list_node *list)
 		"PM Pseudo Device",
        "Pipe",
        "Portal Device",
+		"Timer Device",
 		"Miscellaneous Device",
        "Unknown"
    };
@@ -229,8 +229,8 @@ struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
            
        #else
            #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc)      \
-                const char __fsym_##cmd##_name[] SECTION(".name") = #cmd;   \
-                const char __fsym_##cmd##_desc[] SECTION(".name") = #desc;  \
+                const char __fsym_##cmd##_name[] SECTION(".rodata.name") = #cmd;   \
+                const char __fsym_##cmd##_desc[] SECTION(".rodata.name") = #desc;  \
                const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \
                {                           \
                    __fsym_##cmd##_name,    \
@@ -239,8 +239,8 @@ struct finsh_sysvar* finsh_sysvar_lookup(const char* name);
                };

            #define FINSH_VAR_EXPORT(name, type, desc)              \
-                const char __vsym_##name##_name[] SECTION(".name") = #name; \
-                const char __vsym_##name##_desc[] SECTION(".name") = #desc; \
+                const char __vsym_##name##_name[] SECTION(".rodata.name") = #name; \
+                const char __vsym_##name##_desc[] SECTION(".rodata.name") = #desc; \
                const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \
                {                           \
                    __vsym_##name##_name,   \
@@ -0,0 +1,80 @@
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <finsh.h>
+
+#ifdef RT_USING_HWTIMER
+
+#define TIMER   "timer0"
+
+static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("HT %d\n", rt_tick_get());
+
+    return 0;
+}
+
+int hwtimer(void)
+{
+    rt_err_t err;
+    rt_hwtimerval_t val;
+    rt_device_t dev = RT_NULL;
+    rt_tick_t tick;
+    rt_hwtimer_mode_t mode;
+    int freq = 10000;
+    int t = 5;
+
+    if ((dev = rt_device_find(TIMER)) == RT_NULL)
+    {
+        rt_kprintf("No Device: %s\n", TIMER);
+        return -1;
+    }
+
+    if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
+    {
+        rt_kprintf("Open %s Fail\n", TIMER);
+        return -1;
+    }
+
+    rt_device_set_rx_indicate(dev, timer_timeout_cb);
+    /* 计数时钟设置(默认1Mhz或支持的最小计数频率) */
+    err = rt_device_control(dev, HWTIMER_CTRL_FREQ_SET, &freq);
+    if (err != RT_EOK)
+    {
+        rt_kprintf("Set Freq=%dhz Fail\n", freq);
+        goto EXIT;
+    }
+
+    /* 周期模式 */
+    mode = HWTIMER_MODE_PERIOD;
+    err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode);
+
+    tick = rt_tick_get();
+    rt_kprintf("Start Timer> Tick: %d\n", tick);
+    /* 设置定时器超时值并启动定时器 */
+    val.sec = t;
+    val.usec = 0;
+    rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec);
+    if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val))
+    {
+        rt_kprintf("SetTime Fail\n");
+        goto EXIT;
+    }
+    rt_kprintf("Sleep %d sec\n", t);
+    rt_thread_delay(t*RT_TICK_PER_SECOND);
+
+    /* 停止定时器 */
+    err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL);
+    rt_kprintf("Timer Stoped\n");
+    /* 读取计数 */
+    rt_device_read(dev, 0, &val, sizeof(val));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", val.sec, val.usec);
+
+EXIT:
+    err = rt_device_close(dev);
+    rt_kprintf("Close %s\n", TIMER);
+
+    return err;
+}
+
+FINSH_FUNCTION_EXPORT(hwtimer, "Test hardware timer");
+#endif
@@ -758,8 +758,9 @@ enum rt_device_class_type
    RT_Device_Class_PM,                                 /**< PM pseudo device */
    RT_Device_Class_Pipe,                               /**< Pipe device */
    RT_Device_Class_Portal,                             /**< Portal device */
-    RT_Device_Class_Miscellaneous,                      /**< Miscellaneous device */
-    RT_Device_Class_Unknown                             /**< unknown device */
+    RT_Device_Class_Timer,                              /**< Timer device */
+	RT_Device_Class_Miscellaneous,                      /**< Miscellaneous device */
+	RT_Device_Class_Unknown                             /**< unknown device */
 };

 /**
@@ -42,7 +42,7 @@ __declspec(allocate("RTMSymTab$f"))const char __rtmsym_##symbol##_name[] = "__vs

 #else
 #define RTM_EXPORT(symbol)                                            \
-const char __rtmsym_##symbol##_name[] SECTION(".name") = #symbol;     \
+const char __rtmsym_##symbol##_name[] SECTION(".rodata.name") = #symbol;     \
 const struct rt_module_symtab __rtmsym_##symbol SECTION("RTMSymTab")= \
 {                                                                     \
    (void *)&symbol,                                                  \
@@ -0,0 +1,109 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety
+ */
+
+/*!
+ * \addtogroup DM36X
+ */
+/*@{*/
+
+#define NOINT          0xc0
+
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    orr r1, r0, #NOINT
+    msr cpsr_c, r1
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+_do_switch:
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    bic r4, r4, #0x20       @ must be ARM mode
+    msr cpsr_cxsf, r4
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r3, [r2]
+    ldr r2, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    str r0, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
@@ -0,0 +1,117 @@
+;/*
+; * File      : context_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; *  This program is free software; you can redistribute it and/or modify
+; *  it under the terms of the GNU General Public License as published by
+; *  the Free Software Foundation; either version 2 of the License, or
+; *  (at your option) any later version.
+; *
+; *  This program is distributed in the hope that it will be useful,
+; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; *  GNU General Public License for more details.
+; *
+; *  You should have received a copy of the GNU General Public License along
+; *  with this program; if not, write to the Free Software Foundation, Inc.,
+; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2011-08-14     weety    copy from mini2440
+; */
+
+NOINT	EQU		0xc0	; disable interrupt in psr
+
+	AREA |.text|, CODE, READONLY, ALIGN=2
+	ARM
+	REQUIRE8
+	PRESERVE8
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable	PROC
+	EXPORT rt_hw_interrupt_disable
+	MRS r0, cpsr
+	ORR r1, r0, #NOINT
+	MSR cpsr_c, r1
+	BX	lr
+	ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable	PROC
+	EXPORT rt_hw_interrupt_enable
+	MSR cpsr_c, r0
+	BX	lr
+	ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch	PROC
+	EXPORT rt_hw_context_switch
+	STMFD	sp!, {lr}			; push pc (lr should be pushed in place of PC)
+	STMFD	sp!, {r0-r12, lr}	; push lr & register file
+
+	MRS		r4, cpsr
+	STMFD	sp!, {r4}			; push cpsr
+	MRS		r4, spsr
+	STMFD	sp!, {r4}			; push spsr
+
+	STR	sp, [r0]				; store sp in preempted tasks TCB
+	LDR	sp, [r1]				; get new task stack pointer
+
+	LDMFD	sp!, {r4}			; pop new task spsr
+	MSR	spsr_cxsf, r4
+	LDMFD	sp!, {r4}			; pop new task cpsr
+	MSR	spsr_cxsf, r4
+
+	LDMFD	sp!, {r0-r12, lr, pc}^	; pop new task r0-r12, lr & pc
+	ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+rt_hw_context_switch_to	PROC
+	EXPORT rt_hw_context_switch_to
+	LDR	sp, [r0]				; get new task stack pointer
+
+	LDMFD	sp!, {r4}			; pop new task spsr
+	MSR	spsr_cxsf, r4
+	LDMFD	sp!, {r4}			; pop new task cpsr
+	MSR	cpsr_cxsf, r4
+
+	LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
+	ENDP
+
+;/*
+; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+; */
+	IMPORT rt_thread_switch_interrupt_flag
+	IMPORT rt_interrupt_from_thread
+	IMPORT rt_interrupt_to_thread
+
+rt_hw_context_switch_interrupt	PROC
+	EXPORT rt_hw_context_switch_interrupt
+	LDR r2, =rt_thread_switch_interrupt_flag
+	LDR r3, [r2]
+	CMP r3, #1
+	BEQ _reswitch
+	MOV r3, #1							; set rt_thread_switch_interrupt_flag to 1
+	STR r3, [r2]
+	LDR r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
+	STR r0, [r2]
+_reswitch
+	LDR r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
+	STR r1, [r2]
+	BX	lr
+	ENDP
+
+	END
@@ -0,0 +1,164 @@
+/*
+ * File      : mmu.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __MMU_H__
+#define __MMU_H__
+
+#include <rtthread.h>
+
+#define CACHE_LINE_SIZE	32
+
+/*
+ * Hardware page table definitions.
+ *
+ * + Level 1 descriptor (PGD)
+ *   - common
+ */
+#define PGD_TYPE_MASK       (3 << 0)
+#define PGD_TYPE_FAULT      (0 << 0)
+#define PGD_TYPE_TABLE      (1 << 0)
+#define PGD_TYPE_SECT       (2 << 0)
+#define PGD_BIT4            (1 << 4)
+#define PGD_DOMAIN(x)       ((x) << 5)
+#define PGD_PROTECTION      (1 << 9)    /* ARMv5 */
+/*
+ *   - section
+ */
+#define PGD_SECT_BUFFERABLE	(1 << 2)
+#define PGD_SECT_CACHEABLE  (1 << 3)
+#define PGD_SECT_XN         (1 << 4)    /* ARMv6 */
+#define PGD_SECT_AP0        (1 << 10)
+#define PGD_SECT_AP1        (1 << 11)
+#define PGD_SECT_TEX(x)     ((x) << 12) /* ARMv5 */
+#define PGD_SECT_APX        (1 << 15)   /* ARMv6 */
+#define PGD_SECT_S          (1 << 16)   /* ARMv6 */
+#define PGD_SECT_nG         (1 << 17)   /* ARMv6 */
+#define PGD_SECT_SUPER      (1 << 18)   /* ARMv6 */
+
+#define PGD_SECT_UNCACHED   (0)
+#define PGD_SECT_BUFFERED   (PGD_SECT_BUFFERABLE)
+#define PGD_SECT_WT         (PGD_SECT_CACHEABLE)
+#define PGD_SECT_WB         (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
+#define PGD_SECT_MINICACHE  (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE)
+#define PGD_SECT_WBWA       (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
+#define PGD_SECT_NONSHARED_DEV  (PGD_SECT_TEX(2))
+
+
+/*
+ * + Level 2 descriptor (PTE)
+ *   - common
+ */
+#define PTE_TYPE_MASK       (3 << 0)
+#define PTE_TYPE_FAULT      (0 << 0)
+#define PTE_TYPE_LARGE      (1 << 0)
+#define PTE_TYPE_SMALL      (2 << 0)
+#define PTE_TYPE_EXT        (3 << 0)    /* ARMv5 */
+#define PTE_BUFFERABLE      (1 << 2)
+#define PTE_CACHEABLE       (1 << 3)
+
+/*
+ *   - extended small page/tiny page
+ */
+#define PTE_EXT_XN          (1 << 0)    /* ARMv6 */
+#define PTE_EXT_AP_MASK     (3 << 4)
+#define PTE_EXT_AP0         (1 << 4)
+#define PTE_EXT_AP1         (2 << 4)
+#define PTE_EXT_AP_UNO_SRO  (0 << 4)
+#define PTE_EXT_AP_UNO_SRW  (PTE_EXT_AP0)
+#define PTE_EXT_AP_URO_SRW  (PTE_EXT_AP1)
+#define PTE_EXT_AP_URW_SRW  (PTE_EXT_AP1|PTE_EXT_AP0)
+#define PTE_EXT_TEX(x)      ((x) << 6)  /* ARMv5 */
+#define PTE_EXT_APX         (1 << 9)    /* ARMv6 */
+#define PTE_EXT_SHARED      (1 << 10)   /* ARMv6 */
+#define PTE_EXT_NG          (1 << 11)   /* ARMv6 */
+
+/*
+ *   - small page
+ */
+#define PTE_SMALL_AP_MASK       (0xff << 4)
+#define PTE_SMALL_AP_UNO_SRO    (0x00 << 4)
+#define PTE_SMALL_AP_UNO_SRW    (0x55 << 4)
+#define PTE_SMALL_AP_URO_SRW    (0xaa << 4)
+#define PTE_SMALL_AP_URW_SRW    (0xff << 4)
+
+/*
+ *  sector table properities
+ */
+#define SECT_CB          (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back
+#define SECT_CNB         (PGD_SECT_CACHEABLE)                     //cache_on, write_through
+#define SECT_NCB         (PGD_SECT_BUFFERABLE)                    //cache_off,WR_BUF on
+#define SECT_NCNB        (0 << 2)                                 //cache_off,WR_BUF off
+
+#define SECT_AP_RW       (PGD_SECT_AP0|PGD_SECT_AP1)              //supervisor=RW, user=RW
+#define SECT_AP_RO       ((0 << 10)|(0 << 11))                    //supervisor=RO, user=NO Access(SR=10)
+
+#define SECT_RW_CB      (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */
+#define SECT_RW_CNB     (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */
+#define SECT_RW_NCNB    (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
+#define SECT_RW_FAULT   (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
+
+#define SECT_RO_CB      (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */
+#define SECT_RO_CNB     (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */
+#define SECT_RO_NCNB    (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
+#define SECT_RO_FAULT   (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
+
+#define SECT_TO_PAGE     (PGD_DOMAIN(0)|PGD_TYPE_TABLE|PGD_BIT4) /* Level 2 descriptor (PTE) entry properity */
+
+/*
+ * page table properities
+ */
+#define PAGE_CB          (PTE_BUFFERABLE|PTE_CACHEABLE)  //cache_on, write_back
+#define PAGE_CNB         (PTE_CACHEABLE)                 //cache_on, write_through
+#define PAGE_NCB         (PTE_BUFFERABLE)                //cache_off,WR_BUF on
+#define PAGE_NCNB        (0 << 2)                        //cache_off,WR_BUF off
+
+#define PAGE_AP_RW       PTE_SMALL_AP_URW_SRW             //supervisor=RW, user=RW
+#define PAGE_AP_RO       PTE_SMALL_AP_UNO_SRO             //supervisor=RO, user=NO Access(SR=10)
+
+#define PAGE_RW_CB      (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */
+#define PAGE_RW_CNB     (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */
+#define PAGE_RW_NCNB    (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
+#define PAGE_RW_FAULT   (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
+
+
+#define PAGE_RO_CB      (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only, cache, write back */
+#define PAGE_RO_CNB     (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only, cache, write through */
+#define PAGE_RO_NCNB    (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
+#define PAGE_RO_FAULT   (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
+
+struct mem_desc {
+	rt_uint32_t vaddr_start;
+	rt_uint32_t vaddr_end;
+	rt_uint32_t paddr_start;
+	rt_uint32_t sect_attr;   /* when page mapped */
+	rt_uint32_t page_attr;   /* only sector mapped valid */
+	rt_uint32_t mapped_mode;
+	#define     SECT_MAPPED  0
+	#define     PAGE_MAPPED  1
+};
+
+
+void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
+
+#endif
+
@@ -0,0 +1,79 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety
+ */
+#include <rtthread.h>
+
+/*****************************/
+/* CPU Mode                  */
+/*****************************/
+#define USERMODE		0x10
+#define FIQMODE			0x11
+#define IRQMODE			0x12
+#define SVCMODE			0x13
+#define ABORTMODE		0x17
+#define UNDEFMODE		0x1b
+#define MODEMASK		0x1f
+#define NOINT			0xc0
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+
+	/* cpsr */
+	if ((rt_uint32_t)tentry & 0x01)
+		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
+	else
+		*(--stk) = SVCMODE;					/* arm mode   */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
@@ -60,7 +60,7 @@ HDINTERRUPTFNC(irq15, 15)
 .type _hdinterrupts,@function
 .globl rt_interrupt_enter
 .globl rt_interrupt_leave
-.globl isr_table
+.globl rt_hw_isr
 .globl rt_thread_switch_interrupt_flag
 .globl rt_interrupt_from_thread
 .globl rt_interrupt_to_thread
@@ -81,10 +81,7 @@ _hdinterrupts:
 	movl (%eax), %eax     /* vector(eax) = *eax */

 	pushl %eax            /* push argument : int vector */
-	shll $0x2, %eax       /* each item takes up 4bytes in isr_table. */
-	movl $isr_table, %ebx /* ebx = &isr_table[0] */
-	addl %eax, %ebx       /* eax = &isr_table[vector] */
-	call *(%ebx)
+	call rt_hw_isr
 	add $4, %esp          /* restore argument */

 	call rt_interrupt_leave
@@ -1,16 +1,27 @@
 /*
 * File      : interrupt.c
 * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
 *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * Change Logs:
 * Date           Author       Notes
+ * 2015/9/15      Bernard      Update to new interrupt framework.
 */
-
+ 
 #include <rtthread.h>
 #include <rthw.h>

@@ -23,9 +34,12 @@ rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;

 /* exception and interrupt handler table */
-rt_isr_handler_t isr_table[MAX_HANDLERS];
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
 rt_uint16_t irq_mask_8259A = 0xFFFF;

+void rt_hw_interrupt_handle(int vector, void* param);
+
 /**
 * @addtogroup I386
 */
@@ -64,19 +78,40 @@ void rt_hw_pic_init()
 	rt_thread_switch_interrupt_flag = 0;
 }

-void rt_hw_interrupt_handle(int vector)
+void rt_hw_interrupt_handle(int vector, void* param)
 {
 	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }

+void rt_hw_isr(int vector)
+{
+	if (vector < MAX_HANDLERS)
+	{
+		irq_desc[vector].handler(vector, irq_desc[vector].param);
+	}
+}
+
 /**
 * This function initializes interrupt descript table and 8259 interrupt controller
 *
 */
 void rt_hw_interrupt_init(void)
 {
+	int idx;
+	
 	rt_hw_idt_init();
 	rt_hw_pic_init();
+
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+#endif
+    }
 }

 void rt_hw_interrupt_umask(int vector)
@@ -93,13 +128,28 @@ void rt_hw_interrupt_mask(int vector)
 	outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8));
 }

-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
+rt_isr_handler_t rt_hw_interrupt_install(int              vector,
+                                         rt_isr_handler_t handler,
+                                         void            *param,
+                                         char            *name)
 {
-	if(vector < MAX_HANDLERS)
-	{
-		if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
-		if (new_handler != RT_NULL) isr_table[vector] = new_handler;
-	}
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
+#endif
+        }
+    }
+
+    return old_handler;
 }

 rt_base_t rt_hw_interrupt_disable(void)
@@ -44,11 +44,6 @@ void rt_hw_idt_init(void)
 	extern void Xdefault;
 	int i, j, func;

-	for(i=0; i<MAX_HANDLERS; i++)
-	{
-		isr_table[i] = rt_hw_interrupt_handle;
-	}
-
 	// install a default handler
 	for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++)
 		SETGATE(idt[i], 0, GD_KT, &Xdefault, 0);
@@ -1073,8 +1073,8 @@ rt_device_t rt_console_set_device(const char *name)
        }

        /* set new console device */
+        rt_device_open(new, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM);
        _console_device = new;
-        rt_device_open(_console_device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM);
    }

    return old;