add new bsp tms320c6678

原始提交PR：https://gitee.com/rtthread/rt-thread/pulls/372 提交者：https://gitee.com/wei-handong ---------------------- 在TI公司C6000 DSP处理器上成功移植rt-thread操作系统；主要在libcpu/ti-dsp/c6x添加keystone架构底层代码，在bsp/ti-c6678添加bsp工程，该工程已在本人的开发板上成功运行 * 添加TMS320C6678处理器，keystone架构底层代码 * 添加支持中断栈部分代码，修改格式 * 修改汇编rt_hw_context_switch_to处关于时间槽的使用；修改格式 * 修改使用C语言构建任务栈帧，清除fls和ffs对<c6x.h>文件的依赖 * 修改bsp tms320c6678工程，并测试 * 删除依赖TI的KeyStone_common.c文件 * 添加编译说明 * update bsp/ti-tms320c6678/README.md. * format code Co-authored-by: Huang bo <hb265419@126.com> Co-authored-by: hdwei <1147479335@qq.com> Co-authored-by: bernard <bernard.xiong@gmail.com> Co-authored-by: rtthread-bot <48120998+rtthread-bot@users.noreply.github.com> Co-authored-by: Meco Man <920369182@qq.com>
2026-10-02 14:23:19 +08:00 · 2022-01-29 16:11:42 +08:00
parent 909b464e78
commit 71ba65e7c0
37 changed files with 3065 additions and 1 deletions
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
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+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+		</project-mappings>
+	</storageModule>
+</cproject>
@@ -0,0 +1,154 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ti-tms320c6678</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>clock.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/clock.c</locationURI>
+		</link>
+		<link>
+			<name>components.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/components.c</locationURI>
+		</link>
+		<link>
+			<name>context.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/context.asm</locationURI>
+		</link>
+		<link>
+			<name>contextinc.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/contextinc.asm</locationURI>
+		</link>
+		<link>
+			<name>cpu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/cpu.c</locationURI>
+		</link>
+		<link>
+			<name>cpuport.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/cpuport.c</locationURI>
+		</link>
+		<link>
+			<name>device.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/device.c</locationURI>
+		</link>
+		<link>
+			<name>idle.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/idle.c</locationURI>
+		</link>
+		<link>
+			<name>interrupt.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/interrupt.c</locationURI>
+		</link>
+		<link>
+			<name>intexc.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/intexc.asm</locationURI>
+		</link>
+		<link>
+			<name>ipc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/ipc.c</locationURI>
+		</link>
+		<link>
+			<name>irq.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/irq.c</locationURI>
+		</link>
+		<link>
+			<name>kservice.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/kservice.c</locationURI>
+		</link>
+		<link>
+			<name>mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/mem.c</locationURI>
+		</link>
+		<link>
+			<name>memheap.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/memheap.c</locationURI>
+		</link>
+		<link>
+			<name>mempool.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/mempool.c</locationURI>
+		</link>
+		<link>
+			<name>object.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/object.c</locationURI>
+		</link>
+		<link>
+			<name>scheduler.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/scheduler.c</locationURI>
+		</link>
+		<link>
+			<name>signal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/signal.c</locationURI>
+		</link>
+		<link>
+			<name>slab.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/slab.c</locationURI>
+		</link>
+		<link>
+			<name>stack.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/stack.c</locationURI>
+		</link>
+		<link>
+			<name>thread.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/thread.c</locationURI>
+		</link>
+		<link>
+			<name>timer.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/timer.c</locationURI>
+		</link>
+		<link>
+			<name>trap.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/trap.c</locationURI>
+		</link>
+		<link>
+			<name>vector.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/vector.asm</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
@@ -0,0 +1,12 @@
+eclipse.preferences.version=1
+encoding//Debug/applications/subdir_rules.mk=UTF-8
+encoding//Debug/applications/subdir_vars.mk=UTF-8
+encoding//Debug/common/subdir_rules.mk=UTF-8
+encoding//Debug/common/subdir_vars.mk=UTF-8
+encoding//Debug/driver/subdir_rules.mk=UTF-8
+encoding//Debug/driver/subdir_vars.mk=UTF-8
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
@@ -0,0 +1,47 @@
+/****************************************************************************/
+/*                                                                          */
+/*                               M6678.cmd                                  */
+/*                         Copyright (c): NUDT                              */
+/*                                                                          */
+/*                                                                          */
+/*    Description: This file is a sample linker command file that can be    */
+/*                 used for linking programs built with the C compiler and  */
+/*                 running the resulting .out file on an M6678              */
+/*                 device.  Use it as a guideline.  You will want to        */
+/*                 change the memory layout to match your specific C6xxx    */
+/*                 target system.  You may want to change the allocation    */
+/*                 scheme according to the size of your program.            */
+/*                                                                          */
+/*                                                                          */
+/****************************************************************************/
+
+-heap  0x800
+-stack 0x1000
+
+MEMORY
+{
+	VECTORS:		o = 0x00800000  l = 0x00000200
+	LL2_CODE:		o = 0x00800200  l = 0x0001FE00
+	LL2_RW_DATA: 	o = 0x00820000  l = 0x00020000   /*set memory protection attribitue as read/write*/
+}
+
+SECTIONS
+{
+	.vecs       	>    VECTORS
+
+	.text           >    LL2_CODE
+	.cinit          >    LL2_CODE
+	.const          >    LL2_CODE
+	.switch         >    LL2_CODE
+	.stack          >    LL2_RW_DATA
+	GROUP
+	{
+		.neardata
+		.rodata
+		.bss
+	} 		>    LL2_RW_DATA
+	.far            >    LL2_RW_DATA
+	.fardata        >    LL2_RW_DATA
+	.cio            >    LL2_RW_DATA
+	.sysmem         >    LL2_RW_DATA
+}
@@ -0,0 +1,49 @@
+### 1. 简介
+
+TMS320C6678是TI基于KeyStone的多核固定浮点数字信号处理器，DSP集成C66x CorePac，每个核心在1GHz至1.25 GHz的运行。该设备支持高性能的信号处理应用，如任务关键，医疗成像，测试和自动化。
+
+### 2. 编译说明
+
+TMS320C6678 工程的编译和下载要使用的是 TI 官方提供的 Code Composer Studio。在本工程使用的是 CCS5.5 版本编译调试，CCS5.5 Compiler version:TIv8.3.5进行编译，需要安装TI提供的CSL库pdk_C6678_1_1_2_6。
+
+### 2.1 导入工程
+
+首先打开 Code Composer Studio，点击 Project -> Import CCS Projects...
+
+![输入图片说明](figures/import(1).png)
+
+在打开的对话框中，点击 Select search -> directory 右边的 Browse... 选择 TMS320C6678 BSP 所在文件夹，如图所示。选择完成后点击 Finish 完成导入。
+
+![输入图片说明](figures/import(2).png)
+
+### 2.2 检查工程路径和编译器
+
+- 检查工程路径是否正确，是否成功安装pdk_C6678_1_1_2_6，本工程安装路径为C盘。
+
+![输入图片说明](figures/filepath.png)
+
+- 检查编译器版本，本工程使用的是TIv8.3.5
+
+![输入图片说明](figures/general.jpg)
+
+### 3. 编译工程
+
+导入工程后，选中导入的 ti-tms320c6678 工程，右键点击，在弹出的菜单中选择 Build Project 即可开始编译。
+
+### 4. 加载和调试
+
+编译完成后，可以开始加载和调试。将板子和 XDS560 仿真器连接，仿真器可以将编译生成的可执行文件加载到L2或MSMC执行。
+
+- 如下图ti-tms320c6678.out是编译之后生成的可执行文件。
+
+![输入图片说明](figures/debug(1).png)
+
+- 本工程目前只支持单核运行，按如下图加载可执行文件。
+
+![输入图片说明](figures/load.png)
+
+- 加载可执行文件完成后，CCS将进入调试模式，可以选择继续运行、单步调试、复位等操作。
+
+![输入图片说明](figures/debug(2).png)
+
+到此，可以开启tms320c6678 + rt-thread的愉快旅程了 :smile: 。
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "board.h"
+#include "interrupt.h"
+#include "drv_timer.h"
+#include "common.h"
+
+#include <rtthread.h>
+
+/**
+ * This function will initial board.
+ */
+void rt_hw_board_init(void)
+{
+    // initial CPU core
+    keystone_cpu_init();
+
+    // initial interrupt controller
+    rt_hw_interrupt_init();
+
+    // initial system timer
+    rt_hw_system_timer_init();
+
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    rt_hw_system_timer_start();
+}
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define RT_HW_HEAP_BEGIN    (void*)0x0C000000
+#define RT_HW_HEAP_END      (void*)0x0C100000
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+void rt_init_thread_entry(void *parameter)
+{
+    rt_kprintf("hello rt-thread\n");
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 4096, 3, 200);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    } else {
+        return -1;
+    }
+
+    return 0;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+void main(void)
+{
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    for(;;){}
+}
+
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+#include <c6x.h>
+#include <cslr_cgem.h>
+#include <cslr_device.h>
+#include <cslr_bootcfg.h>
+#include <cslr_tmr.h>
+#include <csl_tmr.h>
+
+/* DSP core clock speed in Hz */
+#define DSP_CORE_SPEED_HZ   1000000000
+
+extern CSL_CgemRegs * gp_cgem_regs;
+extern CSL_BootcfgRegs * gp_bootcfg_regs;
+
+/*----------------------Timer plus registers definition----------------*/
+typedef struct {
+    volatile unsigned int PID12;
+    volatile unsigned int EMUMGT_CLKSPD;
+    volatile unsigned int GPINT_EN;
+    volatile unsigned int GPDIR_DAT;
+    volatile unsigned int CNTLO;
+    volatile unsigned int CNTHI;
+    volatile unsigned int PRDLO;
+    volatile unsigned int PRDHI;
+    volatile unsigned int TCR;
+    volatile unsigned int TGCR;
+    volatile unsigned int WDTCR;
+    volatile unsigned int TLGC;
+    volatile unsigned int TLMR;
+    volatile unsigned int RELLO;
+    volatile unsigned int RELHI;
+    volatile unsigned int CAPLO;
+    volatile unsigned int CAPHI;
+    volatile unsigned int INTCTL_STAT;
+    volatile unsigned char  RSVD0[24];
+    volatile unsigned int TIMERLO_COMPARE_REG[8];
+    volatile unsigned char  RSVD1[32];
+} CSL_TmrPlusRegs;
+
+#define TMR_TCR_READRSTMODE_HI_SHIFT   (26)
+#define TMR_TCR_CAPEVTMODE_LO_SHIFT    (12)
+#define TMR_TCR_CAPMODE_LO_SHIFT       (11)
+#define TMR_TCR_READRSTMODE_LO_SHIFT   (10)
+
+#define TMR_TCR_READRSTMODE_HI_MASK    (1<<26)
+#define TMR_TCR_CAPEVTMODE_LO_MASK     (3<<12)
+#define TMR_TCR_CAPMODE_LO_MASK        (1<<11)
+#define TMR_TCR_READRSTMODE_LO_MASK    (1<<10)
+
+#define TMR_TGCR_PLUSEN_SHIFT          4
+#define TMR_TGCR_PLUSEN_MASK           (1<<4)
+
+#define TMR_INTCTLSTAT_EN_ALL_CLR_ALL  0x000F000F
+
+#define CSL_TMR_WDTCR_WDKEY_CMD1       (0x0000A5C6u)
+#define CSL_TMR_WDTCR_WDKEY_CMD2       (0x0000DA7Eu)
+
+#define CSL_TMR_ENAMODE_CONT_RELOAD    3
+
+extern CSL_TmrPlusRegs * gp_timer0_regs;
+extern CSL_TmrPlusRegs * gp_timer1_regs;
+extern CSL_TmrPlusRegs * gp_timer2_regs;
+extern CSL_TmrPlusRegs * gp_timer3_regs;
+extern CSL_TmrPlusRegs * gp_timer4_regs;
+extern CSL_TmrPlusRegs * gp_timer5_regs;
+extern CSL_TmrPlusRegs * gp_timer6_regs;
+extern CSL_TmrPlusRegs * gp_timer7_regs;
+extern CSL_TmrPlusRegs * gp_timer8_regs;
+extern CSL_TmrPlusRegs * gp_timer_regs[];
+
+typedef enum
+{
+    TIMER_ONE_SHOT_PULSE = 0,     /*generate one shot pulse with timer*/
+    TIMER_PERIODIC_PULSE,         /*generate periodic pulse with timer*/
+    TIMER_PERIODIC_CLOCK,         /*generate periodic clock with timer*/
+    /*generate periodic square wave with period reload feature, the difference
+    between wave and clock is the duty cycle of clock is always 50%*/
+    TIMER_PERIODIC_WAVE,
+    TIMER_WATCH_DOG               /*configure timer as watch dog*/
+}TTimerMode;
+
+typedef struct  {
+    int timer_num;                /*select one timer*/
+    TTimerMode timerMode;         /*select function of the timer*/
+    unsigned long long period;    /*in the unit of DSP core clock/6*/
+    unsigned long long reload_period;     /*the reload value of period*/
+    int pulseWidth;               /*pulse width between 0~3*/
+}Timer64_Config;
+
+/* Reset a 64-bit timer */
+extern void reset_timer(int timer_num);
+
+/* Initailize a 64-bit timer */
+extern void timer64_init(Timer64_Config * tmrCfg);
+
+extern void keystone_cpu_init(void);
+
+#endif /* __COMMON_H__ */
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "drv_timer.h"
+#include "interrupt.h"
+#include "common.h"
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_systick_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * The function initial system timer interrupt.
+ */
+void rt_hw_system_timer_init(void)
+{
+    // initial system timer interrupt, map local timer interrupt to INT14
+    gp_cgem_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
+    // enable CPU INT14
+    rt_hw_interrupt_umask(1 << 14);
+
+    return ;
+}
+
+/**
+ * The function initial system timer.
+ * Use local timer (== DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
+ *
+ */
+void rt_hw_system_timer_start(void)
+{
+    Timer64_Config tmrCfg;
+
+    // select output on TIMO0 from local timer.
+    gp_bootcfg_regs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
+
+    // configure the timer to generate clocks and interrupts
+    tmrCfg.timer_num = DNUM;
+    tmrCfg.timerMode = TIMER_PERIODIC_CLOCK;
+    tmrCfg.period = (unsigned long long) RT_TICK_PER_SECOND * DSP_CORE_SPEED_HZ / 6000;
+    tmrCfg.reload_period = 0;
+
+    // initial timer
+    timer64_init(&tmrCfg);
+}
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __SYS_TIMER_H__
+#define __SYS_TIMER_H__
+
+#include <c6x.h>
+#include <tistdtypes.h>
+
+void rt_hw_system_timer_init(void);
+
+void rt_hw_system_timer_start(void);
+
+#endif  /* __SYS_TIMER_H__ */
+
@@ -0,0 +1,122 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+#define SOC_C6678
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_USING_ARCH_DATA_TYPE
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_8
+#define RT_THREAD_PRIORITY_MAX 8
+#define RT_TICK_PER_SECOND 100
+//#define RT_USING_HOOK
+//#define RT_USING_IDLE_HOOK
+//#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+//#define RT_DEBUG
+//#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+/* RT-Thread Components */
+
+/* C++ features */
+
+
+/* Command shell */
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+/* Using WiFi */
+
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#include "rtconfig_project.h"
+
+#endif
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-27     xuzhuoyi     the first version
+ */
+
+#ifndef __RTCONFIG_PROJECT_H__
+#define __RTCONFIG_PROJECT_H__
+
+typedef signed   char                   rt_int8_t;      /**<  8bit integer type */
+typedef signed   short                  rt_int16_t;     /**< 16bit integer type */
+typedef signed   long                   rt_int32_t;     /**< 32bit integer type */
+typedef signed   long long              rt_int64_t;     /**< 64bit integer type */
+typedef unsigned char                   rt_uint8_t;     /**<  8bit unsigned integer type */
+typedef unsigned short                  rt_uint16_t;    /**< 16bit unsigned integer type */
+typedef unsigned long                   rt_uint32_t;    /**< 32bit unsigned integer type */
+typedef unsigned long long              rt_uint64_t;    /**< 64bit unsigned integer type */
+
+#endif
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.asm')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __C66XX_H__
+#define __C66XX_H__
+
+extern __cregister volatile unsigned int IERR;    /* Internal Exception Report Register */
+extern __cregister volatile unsigned int ECR;     /* Exception Clear Register */
+extern __cregister volatile unsigned int EFR;     /* Exception Flag Register */
+extern __cregister volatile unsigned int TSR;     /* Task State Register */
+extern __cregister volatile unsigned int ITSR;    /* Interrupt Task State Register */
+extern __cregister volatile unsigned int NTSR;    /* NMI/exception Task State Register */
+extern __cregister volatile unsigned int TSCL;    /* Time Stamp Counter Register - Low Half  */
+extern __cregister volatile unsigned int TSCH;    /* Time Stamp Counter Register - High Half */
+extern __cregister volatile unsigned int DNUM;    /* Core number */
+
+extern __cregister volatile unsigned int AMR;
+extern __cregister volatile unsigned int CSR;
+extern __cregister volatile unsigned int IFR;
+extern __cregister volatile unsigned int ISR;
+extern __cregister volatile unsigned int ICR;
+extern __cregister volatile unsigned int IER;
+extern __cregister volatile unsigned int ISTP;
+extern __cregister volatile unsigned int IRP;
+extern __cregister volatile unsigned int NRP;
+
+#ifdef _BIG_ENDIAN
+#define RT_REG_PAIR(odd, even) unsigned long odd; unsigned long even
+#else
+#define RT_REG_PAIR(odd, even) unsigned long even; unsigned long odd
+#endif
+
+struct rt_hw_register
+{
+    RT_REG_PAIR(b17, b16);
+    RT_REG_PAIR(b19, b18);
+    RT_REG_PAIR(b21, b20);
+    RT_REG_PAIR(b23, b22);
+    RT_REG_PAIR(b25, b24);
+    RT_REG_PAIR(b27, b26);
+    RT_REG_PAIR(b29, b28);
+    RT_REG_PAIR(b31, b30);
+
+    RT_REG_PAIR(b1, b0);
+    RT_REG_PAIR(b3, b2);
+    RT_REG_PAIR(b5, b4);
+    RT_REG_PAIR(b7, b6);
+    RT_REG_PAIR(b9, b8);
+    RT_REG_PAIR(b11, b10);
+    RT_REG_PAIR(b13, b12);
+
+    RT_REG_PAIR(a17, a16);
+    RT_REG_PAIR(a19, a18);
+    RT_REG_PAIR(a21, a20);
+    RT_REG_PAIR(a23, a22);
+    RT_REG_PAIR(a25, a24);
+    RT_REG_PAIR(a27, a26);
+    RT_REG_PAIR(a29, a28);
+    RT_REG_PAIR(a31, a30);
+
+    RT_REG_PAIR(a1, a0);
+    RT_REG_PAIR(a3, a2);
+    RT_REG_PAIR(a5, a4);
+    RT_REG_PAIR(a7, a6);
+    RT_REG_PAIR(a9, a8);
+    RT_REG_PAIR(a11, a10);
+    RT_REG_PAIR(a13, a12);
+
+    RT_REG_PAIR(a15, a14);
+    RT_REG_PAIR(sp, dp);
+};
+
+typedef struct rt_hw_exp_stack_register
+{
+    RT_REG_PAIR(tsr, orig_a4);
+    RT_REG_PAIR(rilc, ilc);
+    RT_REG_PAIR(pc, csr);
+    struct rt_hw_register hw_register;
+} rt_hw_thread_stack_register;
+
+#define __dint()                asm(" DINT")
+#define __rint()                asm(" RINT")
+#define __system_call()         asm(" SWE")
+#define __enter_idle()          asm(" IDLE")
+#define __nop()                 asm(" NOP")
+#define __mfence()              asm(" MFENCE")
+
+#define __SYSREG(ADDR, TYPE)    (*(volatile TYPE*)(ADDR))
+#define __SYSREGA(ADDR, TYPE)   ((volatile TYPE*)(ADDR))
+
+#endif /* __C66XX_H__ */
@@ -0,0 +1,192 @@
+;
+; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Change Logs:
+; Date           Author       Notes
+; 2021-11-16     Dystopia     the first version
+;
+
+;-----------------------------------------------------------
+;                       extern variable
+;-----------------------------------------------------------
+    .ref rt_system_stack_top
+
+;-----------------------------------------------------------
+;                     macro definition
+;-----------------------------------------------------------
+SAVE_ALL    .macro  __rp, __tsr
+    STW .D2T2   B0,*SP--[2]             ; save original B0
+    MVKL    .S2 rt_system_stack_top,B0
+    MVKH    .S2 rt_system_stack_top,B0
+    LDW .D2T2   *B0,B1                  ; system stack
+
+    NOP 3
+    STW .D2T2   B1,*+SP[1]              ; save original B1
+    XOR .D2 SP,B1,B0                    ; check current stack types
+    LDW .D2T2   *+SP[1],B1              ; restore B0/B1
+    LDW .D2T2   *++SP[2],B0
+    SHR .S2 B0,12,B0                    ; 0 if already using system stack
+ [B0]   STDW    .D2T2   SP:DP,*--B1[1]  ; thread: save thread sp/dp system stack
+ [B0]   MV  .S2 B1,SP                   ; and switch to system stack
+||[!B0] STDW    .D2T2   SP:DP,*--SP[1]  ; kernel: nest interrupt save(not support)
+
+    SUBAW   .D2 SP,2,SP
+
+    ADD .D1X    SP,-8,A15
+ || STDW    .D2T1   A15:A14,*SP--[16]   ; save A15:A14
+
+    STDW    .D2T2   B13:B12,*SP--[1]
+ || STDW    .D1T1   A13:A12,*A15--[1]
+ || MVC .S2 __rp,B13
+    STDW    .D2T2   B11:B10,*SP--[1]
+ || STDW    .D1T1   A11:A10,*A15--[1]
+ || MVC .S2 CSR,B12
+
+    STDW    .D2T2   B9:B8,*SP--[1]
+ || STDW    .D1T1   A9:A8,*A15--[1]
+ || MVC .S2 RILC,B11
+    STDW    .D2T2   B7:B6,*SP--[1]
+ || STDW    .D1T1   A7:A6,*A15--[1]
+ || MVC .S2 ILC,B10
+    STDW    .D2T2   B5:B4,*SP--[1]
+ || STDW    .D1T1   A5:A4,*A15--[1]
+    STDW    .D2T2   B3:B2,*SP--[1]
+ || STDW    .D1T1   A3:A2,*A15--[1]
+ || MVC .S2 __tsr,B5
+    STDW    .D2T2   B1:B0,*SP--[1]
+ || STDW    .D1T1   A1:A0,*A15--[1]
+ || MV  .S1X    B5,A5
+
+    STDW    .D2T2   B31:B30,*SP--[1]
+ || STDW    .D1T1   A31:A30,*A15--[1]
+ || MVKL    1,A4
+
+    STDW    .D2T2   B29:B28,*SP--[1]
+ || STDW    .D1T1   A29:A28,*A15--[1]
+    STDW    .D2T2   B27:B26,*SP--[1]
+ || STDW    .D1T1   A27:A26,*A15--[1]
+    STDW    .D2T2   B25:B24,*SP--[1]
+ || STDW    .D1T1   A25:A24,*A15--[1]
+    STDW    .D2T2   B23:B22,*SP--[1]
+ || STDW    .D1T1   A23:A22,*A15--[1]
+    STDW    .D2T2   B21:B20,*SP--[1]
+ || STDW    .D1T1   A21:A20,*A15--[1]
+    STDW    .D2T2   B19:B18,*SP--[1]
+ || STDW    .D1T1   A19:A18,*A15--[1]
+    STDW    .D2T2   B17:B16,*SP--[1]
+ || STDW    .D1T1   A17:A16,*A15--[1]
+
+    STDW    .D2T2   B13:B12,*SP--[1]    ; save PC and CSR
+    STDW    .D2T2   B11:B10,*SP--[1]    ; save RILC and ILC
+    STDW    .D2T1   A5:A4,*SP--[1]      ; save TSR and  orig A4(stack type)
+            .endm
+
+RESTORE_ALL .macro  __rp, __tsr
+    LDDW    .D2T2   *++SP[1],B9:B8      ; get TSR (B9)
+    LDDW    .D2T2   *++SP[1],B11:B10    ; get RILC (B11) and ILC (B10)
+    LDDW    .D2T2   *++SP[1],B13:B12    ; get PC (B13) and CSR (B12)
+
+    ADDAW   .D1X    SP,30,A15
+
+    LDDW    .D1T1   *++A15[1],A17:A16
+ || LDDW    .D2T2   *++SP[1],B17:B16
+    LDDW    .D1T1   *++A15[1],A19:A18
+ || LDDW    .D2T2   *++SP[1],B19:B18
+    LDDW    .D1T1   *++A15[1],A21:A20
+ || LDDW    .D2T2   *++SP[1],B21:B20
+    LDDW    .D1T1   *++A15[1],A23:A22
+ || LDDW    .D2T2   *++SP[1],B23:B22
+    LDDW    .D1T1   *++A15[1],A25:A24
+ || LDDW    .D2T2   *++SP[1],B25:B24
+    LDDW    .D1T1   *++A15[1],A27:A26
+ || LDDW    .D2T2   *++SP[1],B27:B26
+    LDDW    .D1T1   *++A15[1],A29:A28
+ || LDDW    .D2T2   *++SP[1],B29:B28
+    LDDW    .D1T1   *++A15[1],A31:A30
+ || LDDW    .D2T2   *++SP[1],B31:B30
+
+    LDDW    .D1T1   *++A15[1],A1:A0
+ || LDDW    .D2T2   *++SP[1],B1:B0
+    LDDW    .D1T1   *++A15[1],A3:A2
+ || LDDW    .D2T2   *++SP[1],B3:B2
+ || MVC .S2 B9,__tsr
+    LDDW    .D1T1   *++A15[1],A5:A4
+ || LDDW    .D2T2   *++SP[1],B5:B4
+ || MVC .S2 B11,RILC
+    LDDW    .D1T1   *++A15[1],A7:A6
+ || LDDW    .D2T2   *++SP[1],B7:B6
+ || MVC .S2 B10,ILC
+    LDDW    .D1T1   *++A15[1],A9:A8
+ || LDDW    .D2T2   *++SP[1],B9:B8
+ || MVC .S2 B13,__rp
+
+    LDDW    .D1T1   *++A15[1],A11:A10
+ || LDDW    .D2T2   *++SP[1],B11:B10
+ || MVC .S2 B12,CSR
+    LDDW    .D1T1   *++A15[1],A13:A12
+ || LDDW    .D2T2   *++SP[1],B13:B12
+
+    MV  .D2X    A15,SP
+ || MVKL    .S1 rt_system_stack_top,A15
+    MVKH    .S1 rt_system_stack_top,A15
+ || ADDAW   .D1X    SP,6,A14
+    STW .D1T1   A14,*A15                ; save system stack pointer
+
+    LDDW    .D2T1   *++SP[1],A15:A14
+    LDDW    .D2T2   *+SP[1],SP:DP
+    NOP     4
+            .endm
+
+THREAD_SAVE_ALL .macro  __rp, __tsr
+    STDW    .D2T2   SP:DP,*--SP[1]
+    SUBAW   .D2 SP,2,SP
+
+    ADD .D1X    SP,-8,A15
+ || STDW    .D2T1   A15:A14,*SP--[16]   ; save A15:A14
+
+    STDW    .D2T2   B13:B12,*SP--[1]
+ || STDW    .D1T1   A13:A12,*A15--[1]
+ || MVC .S2 __rp,B13
+    STDW    .D2T2   B11:B10,*SP--[1]
+ || STDW    .D1T1   A11:A10,*A15--[1]
+ || MVC .S2 CSR,B12
+
+    STDW    .D2T2   B9:B8,*SP--[1]
+ || STDW    .D1T1   A9:A8,*A15--[1]
+ || MVC .S2 RILC,B11
+    STDW    .D2T2   B7:B6,*SP--[1]
+ || STDW    .D1T1   A7:A6,*A15--[1]
+ || MVC .S2 ILC,B10
+    STDW    .D2T2   B5:B4,*SP--[1]
+ || STDW    .D1T1   A5:A4,*A15--[1]
+    STDW    .D2T2   B3:B2,*SP--[1]
+ || STDW    .D1T1   A3:A2,*A15--[1]
+ || MVC .S2 __tsr,B5
+    STDW    .D2T2   B1:B0,*SP--[1]
+ || STDW    .D1T1   A1:A0,*A15--[1]
+ || MV  .S1X    B5,A5
+
+    STDW    .D2T2   B31:B30,*SP--[1]
+ || STDW    .D1T1   A31:A30,*A15--[1]
+ || MVKL    1,A4
+    STDW    .D2T2   B29:B28,*SP--[1]
+ || STDW    .D1T1   A29:A28,*A15--[1]
+    STDW    .D2T2   B27:B26,*SP--[1]
+ || STDW    .D1T1   A27:A26,*A15--[1]
+    STDW    .D2T2   B25:B24,*SP--[1]
+ || STDW    .D1T1   A25:A24,*A15--[1]
+    STDW    .D2T2   B23:B22,*SP--[1]
+ || STDW    .D1T1   A23:A22,*A15--[1]
+    STDW    .D2T2   B21:B20,*SP--[1]
+ || STDW    .D1T1   A21:A20,*A15--[1]
+    STDW    .D2T2   B19:B18,*SP--[1]
+ || STDW    .D1T1   A19:A18,*A15--[1]
+    STDW    .D2T2   B17:B16,*SP--[1]
+ || STDW    .D1T1   A17:A16,*A15--[1]
+
+    STDW    .D2T2   B13:B12,*SP--[1]    ; save PC and CSR
+    STDW    .D2T2   B11:B10,*SP--[1]    ; save RILC and ILC
+    STDW    .D2T1   A5:A4,*SP--[1]      ; save TSR and orig A4(stack type)
+                .endm
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "trap.h"
+
+/*------------ rt_hw_cpu_shutdown() function ----------------------------------
+ * DESCRIPTION: Shutdown CPU
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+RT_WEAK void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    rt_hw_interrupt_disable();
+
+    RT_ASSERT(0);
+}
+
+/*------------ nested_exception_handler() function ---------------------------
+ * DESCRIPTION: Function handles Nested Exception
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+
+void nested_exception_handler(void)
+{
+    for(;;){}
+}
+
+/*------------ hw_nmi_handler() function --------------------------------------
+ * DESCRIPTION: Function handles NMI interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_nmi_handler(struct rt_hw_exp_stack_register *regs)
+{
+    for(;;){}
+}
+
+/*------------ hw_bad_handler() function --------------------------------------
+ * DESCRIPTION: Function handles Bad interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_bad_handler(void)
+{
+    for(;;){}
+}
+
+/*------------ hw_int4_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT4 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int4_handler(void)
+{
+
+}
+
+/*------------ hw_int5_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT5 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int5_handler(void)
+{
+
+}
+
+/*------------ hw_int6_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT6 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int6_handler(void)
+{
+
+}
+
+/*------------ hw_int7_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT7 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int7_handler(void)
+{
+
+}
+
+/*------------ hw_int8_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT8 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int8_handler(void)
+{
+
+}
+
+/*------------ hw_int9_handler() function -------------------------------------
+ * DESCRIPTION: Function handles INT9 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int9_handler(void)
+{
+
+}
+
+/*------------ hw_int10_handler() function ------------------------------------
+ * DESCRIPTION: Function handles INT10 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int10_handler(void)
+{
+
+}
+
+/*------------ hw_int11_handler() function ------------------------------------
+ * DESCRIPTION: Function handles INT11 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int11_handler(void)
+{
+
+}
+
+/*------------ hw_int12_handler() function ------------------------------------
+ * DESCRIPTION: Function handles INT12 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int12_handler(void)
+{
+
+}
+
+/*------------ hw_int13_handler() function ------------------------------------
+ * DESCRIPTION: Function handles INT13 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int13_handler(void)
+{
+
+}
+
+/*------------------ hw_int14_handler() function ------------------------------
+ * DESCRIPTION: Function handles INT14 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE:
+-----------------------------------------------------------------------------*/
+void hw_int14_handler(void)
+{
+extern void rt_hw_systick_isr();
+    rt_hw_systick_isr();
+}
+
+/*------------ hw_int15_handler() function ------------------------------------
+ * DESCRIPTION: Function handles INT15 interrupt
+ * ARGUMENTS:
+ * None
+ * RETURNED VALUE: None
+-----------------------------------------------------------------------------*/
+void hw_int15_handler(void)
+{
+
+}
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "interrupt.h"
+#include "c66xx.h"
+#include "trap.h"
+
+#define MAX_HANDLERS 128
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    // initial system trap
+    //rt_trap_init();
+
+    /* init exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    if (vector < 0 || vector >= MAX_HANDLERS)
+    {
+        return;
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 0 || vector >= MAX_HANDLERS)
+    {
+        return;
+    }
+    ICR = vector;
+    IER |= vector;
+
+    //enable GIE
+    TSR = TSR | 1;
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS || vector >= 0)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    if (vector < 0 || vector >= MAX_HANDLERS)
+    {
+        return;
+    }
+}
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+void rt_hw_interrupt_clear(int vector);
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif /* __INTERRUPT_H__ */
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include <rtthread.h>
+#include <c66xx.h>
+
+extern rt_uint32_t rt_hw_get_current_dp(void);
+
+/**
+ * @addtogroup C66xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_hw_thread_stack_register *thread_context = RT_NULL;
+    rt_uint32_t stk = 0;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk         = (rt_uint32_t)stack_addr;
+    thread_context = (rt_hw_thread_stack_register *)(stk - sizeof(rt_hw_thread_stack_register));
+
+    thread_context->pc = (rt_uint32_t)tentry;
+    thread_context->csr = 0x0103;
+    thread_context->tsr = 0x3;
+    thread_context->orig_a4 = 1;
+    thread_context->ilc = 0;
+    thread_context->rilc = 0;
+
+    thread_context->hw_register.b17 = 0xB17;
+    thread_context->hw_register.b16  = 0xB16;
+    thread_context->hw_register.b19  = 0xB19;
+    thread_context->hw_register.b18  = 0xB18;
+    thread_context->hw_register.b21  = 0xB21;
+    thread_context->hw_register.b20  = 0xB20;
+    thread_context->hw_register.b23  = 0xB23;
+    thread_context->hw_register.b22  = 0xB22;
+    thread_context->hw_register.b25  = 0xB25;
+    thread_context->hw_register.b24  = 0xB24;
+    thread_context->hw_register.b27  = 0xB27;
+    thread_context->hw_register.b26  = 0xB26;
+    thread_context->hw_register.b29  = 0xB29;
+    thread_context->hw_register.b28  = 0xB28;
+    thread_context->hw_register.b31  = 0xB31;
+    thread_context->hw_register.b30  = 0xB30;
+
+    thread_context->hw_register.b1  = 0xB01;
+    thread_context->hw_register.b0  = 0xB00;
+    thread_context->hw_register.b3  = (rt_uint32_t)texit;
+    thread_context->hw_register.b2  = 0xB02;
+    thread_context->hw_register.b5  = 0xB05;
+    thread_context->hw_register.b4  = 0xB04;
+    thread_context->hw_register.b7  = 0xB07;
+    thread_context->hw_register.b6  = 0xB06;
+    thread_context->hw_register.b9  = 0xB09;
+    thread_context->hw_register.b8  = 0xB08;
+    thread_context->hw_register.b11  = 0xB11;
+    thread_context->hw_register.b10  = 0xB10;
+    thread_context->hw_register.b13  = 0xB13;
+    thread_context->hw_register.b12  = 0xB12;
+
+    thread_context->hw_register.a17  = 0xA17;
+    thread_context->hw_register.a16  = 0xA16;
+    thread_context->hw_register.a19  = 0xA19;
+    thread_context->hw_register.a18  = 0xA18;
+    thread_context->hw_register.a21  = 0xA21;
+    thread_context->hw_register.a20  = 0xA20;
+    thread_context->hw_register.a23  = 0xA23;
+    thread_context->hw_register.a22  = 0xA22;
+    thread_context->hw_register.a25  = 0xA25;
+    thread_context->hw_register.a24  = 0xA24;
+    thread_context->hw_register.a27  = 0xA27;
+    thread_context->hw_register.a26  = 0xA26;
+    thread_context->hw_register.a29  = 0xA29;
+    thread_context->hw_register.a28  = 0xA28;
+    thread_context->hw_register.a31  = 0xA31;
+    thread_context->hw_register.a30  = 0xA30;
+
+    thread_context->hw_register.a1  = 0xA01;
+    thread_context->hw_register.a0  = 0xA00;
+    thread_context->hw_register.a3  = 0xA03;
+    thread_context->hw_register.a2  = 0xA02;
+    thread_context->hw_register.a5  = 0xA05;
+    thread_context->hw_register.a4  = (rt_uint32_t)parameter;
+    thread_context->hw_register.a7  = 0xA07;
+    thread_context->hw_register.a6  = 0xA06;
+    thread_context->hw_register.a9  = 0xA09;
+    thread_context->hw_register.a8  = 0xA08;
+    thread_context->hw_register.a11  = 0xA11;
+    thread_context->hw_register.a10  = 0xA10;
+    thread_context->hw_register.a13  = 0xA13;
+    thread_context->hw_register.a12  = 0xA12;
+
+    thread_context->hw_register.a15  = 0xA15;
+    thread_context->hw_register.a14  = 0xA14;
+    thread_context->hw_register.dp  = rt_hw_get_current_dp();
+    thread_context->hw_register.sp  = (rt_uint32_t)stk;
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)thread_context - 8;
+}
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __TRAP_H__
+#define __TRAP_H__
+
+#include "c66xx.h"
+
+/*
+ * exception operation macro
+ */
+#define disable_exception()
+#define get_except_type()       EFR
+#define ack_exception(type)     ECR = 1ul << (type)
+#define get_iexcept()           IERR
+#define set_iexcept(mask)       IERR = (mask)
+
+/*
+ * exception types
+ */
+#define EXCEPT_TYPE_NXF   31       /* NMI */
+#define EXCEPT_TYPE_EXC   30       /* external exception */
+#define EXCEPT_TYPE_IXF   1        /* internal exception */
+#define EXCEPT_TYPE_SXF   0        /* software exception */
+
+#define EXCEPT_CAUSE_LBX  (1 << 7) /* loop buffer exception */
+#define EXCEPT_CAUSE_PRX  (1 << 6) /* privilege exception */
+#define EXCEPT_CAUSE_RAX  (1 << 5) /* resource access exception */
+#define EXCEPT_CAUSE_RCX  (1 << 4) /* resource conflict exception */
+#define EXCEPT_CAUSE_OPX  (1 << 3) /* opcode exception */
+#define EXCEPT_CAUSE_EPX  (1 << 2) /* execute packet exception */
+#define EXCEPT_CAUSE_FPX  (1 << 1) /* fetch packet exception */
+#define EXCEPT_CAUSE_IFX  (1 << 0) /* instruction fetch exception */
+
+enum SYSTEM_TRAP_CODE
+{
+    ABORT_BUS_ADDRERR = 0,  // bus address error
+    ABORT_BUS_ACCERR,       // bus access permission error
+    ABORT_OPCODE_ILL,       // illegal opcode
+    ABORT_PRVREG_ILL,       // privilege register
+    ABORT_PRVOPC_ILL,       // privileged opcode
+    ABORT_ILLTRP_ILL,       // illegal trap
+    ABORT_BRKPT_ILL,        // handling breakpoints
+};
+
+/*
+ * abort types
+ */
+#define ABORT_TYPE_BUS        0           // bus access abnormal
+#define ABORT_TYPE_MAP        1           // page table mapping error
+#define ABORT_TYPE_UNDDEF     0xff        // undefined exception
+#define ABORT_TYPE_FATAL      0xffffffff  // fatal error
+
+struct rt_exception_info {
+    char *kernel_str;
+    int type;
+    int code;
+};
+
+#define BKPT_OPCODE        0x56454314    /* illegal opcode */
+#define INTC_MEXPMASK    __SYSREGA(0x018000e0, unsigned int)
+
+extern void rt_trap_init(void);
+extern void rt_hw_enable_exception(void);
+extern int __fls(int val);
+extern int __ffs(int val);
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+#define ffz(x) __ffs(~(x))
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int fls(int x)
+{
+    if (!x)
+    {
+        return 0;
+    }
+    return 32 - __fls(x);
+}
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ * Note ffs(0) = 0, ffs(1) = 1, ffs(0x80000000) = 32.
+ */
+static inline int ffs(int x)
+{
+    if (!x)
+    {
+        return 0;
+    }
+    return __ffs(x) + 1;
+}
+
+#endif /* __TRAP_H__ */
@@ -0,0 +1,95 @@
+;
+; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Change Logs:
+; Date           Author       Notes
+; 2021-11-16     Dystopia     the first version
+;
+
+;-----------------------------------------------------------
+;           interrupt vector table for C6000 DSP
+;-----------------------------------------------------------
+
+;-----------------------------------------------------------
+;                       extern function
+;-----------------------------------------------------------
+    .ref _c_int00       ; entry point
+    .ref _nmi_handler
+    .ref _bad_handler
+    .ref _int4_handler
+    .ref _int5_handler
+    .ref _int6_handler
+    .ref _int7_handler
+    .ref _int8_handler
+    .ref _int9_handler
+    .ref _int10_handler
+    .ref _int11_handler
+    .ref _int12_handler
+    .ref _int13_handler
+    .ref _int14_handler
+    .ref _int15_handler
+
+;-----------------------------------------------------------
+;                       macro definition
+;-----------------------------------------------------------
+
+;
+; create interrupt vector for reset (interrupt 0)
+;
+VEC_RESET .macro addr
+    MVKL  addr,B0
+    MVKH  addr,B0
+    B     B0
+    MVC   PCE1,B0
+    NOP   4
+    .align 32
+    .endm
+
+;
+; create interrupt vector for other used interrupts
+;
+IRQVEC  .macro  __name, __isr
+    .align 32
+    .hidden __name
+    .global __name
+__name:
+    B   .S2 __isr
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+        .endm
+;
+;-----------------------------------------------------------
+;
+
+;
+; vector table
+;
+    .sect ".vecs"
+    .align 32
+    .global vector
+vector:
+    VEC_RESET       _c_int00
+    IRQVEC NMI,     _nmi_handler
+    IRQVEC AINT,    _bad_handler
+    IRQVEC MSGINT,  _bad_handler
+    IRQVEC INT4,    _int4_handler
+    IRQVEC INT5,    _int5_handler
+    IRQVEC INT6,    _int6_handler
+    IRQVEC INT7,    _int7_handler
+    IRQVEC INT8,    _int8_handler
+    IRQVEC INT9,    _int9_handler
+    IRQVEC INT10,   _int10_handler
+    IRQVEC INT11,   _int11_handler
+    IRQVEC INT12,   _int12_handler
+    IRQVEC INT13,   _int13_handler
+    IRQVEC INT14,   _int14_handler
+    IRQVEC INT15,   _int15_handler
+
+    .end