[BSP][NXP] Add new features of I2C DMA, CAN, SPI, DWT and SDIO for RT1180 (#11715)

* updated template files, conifg files and script files to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.

* updated different link files of GCC, IAR and KEIL, for supporting multicore kick-off and different loading methods

* Updated .ini files to support debugging in keil. And updeated .mac files to support deugging in iar.

* Updated template files, conifg files and script files of CM7 to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.

* Updated different link files of GCC, IAR and KEIL of CM7 project, for supporting multicore kick-off and different loading methods.

* Modify LittleFS to use the last 1 MB of flash and update CM7 support for LittleFS on QSPI flash.

* Updated different link files of loading to hyperram.

* Updated .ini files of CM7 to support debugging in keil. And updeated .mac files of CM7 to support deugging in iar.

* Remove Keil projects and keep templates only.

* Remove RAMFUNC due to IAR compilation issues, and use linker configuration to place all flash operation code in RAM.

* Add related code to support kick-offing CM7 and rpmsg-lite.

* Add codes to support cherryUSB for CM33 and CM7.

* Add mnt.c to support littleFS for CM7.

* Add codes to support etherCAT for CM7.

* Add codes to support USART12 for RT1180.

* Modify the drv_uart_v2.c to fix some bug to make it can work in CM33, but still cannot work in CM7. Will continue to update in next version.

* Updated README with both Chinese and English versions.

* Move the EtherCAT code into the packages\nxp-imxrt-sdk-latest.

* Remove EtherCAT-related sources, keep only SConscript.

* updated ci.attachconfig.yml for cm33 and cm7 projects.

* Fixed BSP_ROOT path error in rtconfig.py.

* Added drv_netc.c and updated SConscript for netc.

* Updated cherryusb_port.c to avoid worning.

* Updated sconscript to locate multicore directory in packages for header inclusion.

* Updated cm33/board/board.c to avoid worning when enable cm33_kickoff_cm7.

* Deleted peripheral.ethercat, because the related protocol stack has not been uploaded. And added CONFIG_BSP_USING_GPIO=y for Peripheral.netc.:

* Removed the SConscript of multicore and ethercat to packages.

* Added CONFIG_BSP_USING_GPIO=y to Peripheral.hyperflash_dma.

* Added CONFIG_BSP_USING_GPIO=y for Peripheral.hyperflash.

* Reformat code according to coding standards.

* Reformat code according to coding standards.

* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM33.

* Updated flexspi_port.h to support using flexspi api only.

* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM33.

* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM7.

* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM7.

* Added driver of DWT.

* Added driver of flexCAN for RT1180.

* Added driver of i2c dma for RT1180.

* Added driver of lpspi and dma for RT1180.

* Added driver of sdio for RT1180.

* Added driver of RTC for RT1180.

* Updated driver of drv_uart.c and fixed some bugs in drv_uart_v2.c.

* Updated README of imxrt1180-nxp-evk.

* Reformat codes according to tools/ci/clang_format_check.py

* fix: use unsigned shift to avoid UB in drv_can.c

* Removed unnecessary build artifacts and test files.

* bsp/nxp/imxrt: fix CI build errors for non-RT1180 BSPs

* bsp/nxp/imxrt: clang-format drv_lpadc.c to fix CI format check

* Fixed standalone driver compilation errors and code formatting issues.

* Fixed CI attach failures by updating the default linker script for CM7-only ITCM builds with large .text sections.

* [bsp][imxrt] fix BBNSM GPR epoch truncation by storing epoch in two 32-bit GPRs

* [bsp][imxrt] define DBG_TAG/DBG_LVL before rtdbg.h in cm7 mnt.c

* [bsp][imxrt1180] fix(sdcard): add timeout to sd0 wait loop in mnt.c

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md

@@ -34,14 +34,14 @@ This BSP currently provides peripheral support:
 | Rpmsg-lite             | Supported         |           |
 | GPIO                   | supported         |           |
 | UART                   | Supported         |           |
-| SPI                    | Not yet supported |           |
+| SPI                    | supported         |           |
 | I2C                    | supported         |           |
 | ADC                    | supported         |           |
 | Timer                  | supported         |           |
-| SDIO                   | Not yet supported |           |
-| RTC                    | Not yet supported |           |
+| SDIO                   | supported         |           |
+| RTC                    | supported         |           |
 | PWM                    | Not yet supported |           |
-| CAN                    | Not yet supported |           |
+| CAN                    | supported         |           |
 
 ## Usage Instructions
 

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md

@@ -36,14 +36,14 @@ CM33对CM7的kick off将在后续版本中支持。
 | Rpmsg-lite             |     支持     |          |
 | GPIO                   |     支持     |          |
 | UART                   |     支持     |          |
-| SPI                    |   暂不支持   |          |
+| SPI                    |     支持     |          |
 | I2C                    |     支持     |          |
 | ADC                    |     支持     |          |
 | Timer                  |     支持     |          |
-| SDIO                   |   暂不支持   |          |
-| RTC                    |   暂不支持   |          |
+| SDIO                   |     支持     |          |
+| RTC                    |     支持     |          |
 | PWM                    |   暂不支持   |          |
-| CAN                    |   暂不支持   |          |
+| CAN                    |     支持     |          |
 
 
 ## 使用说明

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml

@@ -23,6 +23,37 @@ Peripheral.lpadc1:
     - CONFIG_RT_USING_ADC=y
     - CONFIG_BSP_USING_LPADC=y
     - CONFIG_BSP_USING_LPADC1=y
+Peripheral.lpuart_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_LPUART=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.i2c_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_I2C=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.spi_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_SPI=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.can_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_CAN=y
+Peripheral.rtc_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_RTC=y
+Peripheral.dwt_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_DWT=y
+Peripheral.sdio_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_SDCARD_FATFS=y
 Peripheral.usb_device:
   <<: *scons
   kconfig:

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config

@@ -244,7 +244,7 @@ CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V2=y
 # CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
 CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
-# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_ADC is not set
@@ -1445,15 +1445,18 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y
 #
 # On-chip Peripheral Drivers
 #
-# CONFIG_BSP_USING_DMA is not set
+# CONFIG_BSP_USING_DWT is not set
+CONFIG_BSP_USING_DMA=y
 CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_USB is not set
 # CONFIG_BSP_USING_SDIO is not set
 CONFIG_BSP_USING_LPUART=y
 CONFIG_BSP_USING_LPUART1=y
-# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
-# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
+CONFIG_BSP_LPUART1_RX_USING_DMA=y
+CONFIG_BSP_LPUART1_RX_DMA_CHANNEL=0
+CONFIG_BSP_LPUART1_TX_USING_DMA=y
+CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1
 # CONFIG_BSP_USING_LPUART2 is not set
 # CONFIG_BSP_USING_LPUART3 is not set
 # CONFIG_BSP_USING_LPUART4 is not set
@@ -1465,6 +1468,8 @@ CONFIG_BSP_USING_LPUART1=y
 # CONFIG_BSP_USING_LPUART10 is not set
 # CONFIG_BSP_USING_LPUART11 is not set
 # CONFIG_BSP_USING_LPUART12 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C is not set
 # CONFIG_BSP_USING_CAN is not set
 # CONFIG_BSP_USING_FLEXSPI is not set
 # end of On-chip Peripheral Drivers
@@ -1476,6 +1481,7 @@ CONFIG_BSP_USING_LPUART1=y
 # CONFIG_BSP_USE_MULTICORE is not set
 # CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_FS is not set
+# CONFIG_BSP_USING_QSPI_FLASH is not set
 # end of Onboard Peripheral Drivers
 
 #

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c

@@ -31,9 +31,9 @@
 #include <dfs_fs.h>
 #include <fal.h>
 
-#define FS_PARTITION_NAME  "filesystem"
-#define FS_TYPE_NAME       "lfs"
-#define FS_MOUNT_POINT     "/"
+#define FS_PARTITION_NAME "filesystem"
+#define FS_TYPE_NAME      "lfs"
+#define FS_MOUNT_POINT    "/"
 
 static int _qspi_flash_fs_mount(void)
 {
@@ -97,4 +97,48 @@ INIT_APP_EXPORT(_qspi_flash_fs_mount);
  */
 INIT_COMPONENT_EXPORT(fal_init);
 
-#endif /* BSP_USING_QSPI_FLASH_FS */
+#endif /* BSP_USING_QSPI_FLASH_FS */
+
+/* ====================================================================
+ * SD card FAT filesystem (controlled by BSP_USING_SDCARD_FATFS)
+ *
+ * Dependencies:
+ *   - drv_sdio.c / sdio_port.c (USDHC1 driver + board init)
+ *   - RT-Thread MMCSD / elmfat component
+ *
+ * The driver registers the block device as "sd0" asynchronously, so
+ * this function polls until the device appears before mounting.
+ * ==================================================================== */
+#ifdef BSP_USING_SDCARD_FATFS
+#include <dfs_fs.h>
+#include <dfs_file.h>
+#define DBG_TAG "app.sdcard"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+static int _sdcard_fs_mount(void)
+{
+    rt_tick_t start = rt_tick_get();
+    while (rt_device_find("sd0") == RT_NULL)
+    {
+        if ((rt_tick_get() - start) > (5 * RT_TICK_PER_SECOND))
+        {
+            LOG_E("wait for 'sd0' timeout");
+            return -RT_ETIMEOUT;
+        }
+        rt_thread_mdelay(10);
+    }
+
+    int ret = dfs_mount("sd0", "/", "elm", 0, 0);
+    if (ret != 0)
+    {
+        LOG_E("sd0 mount to '/' failed! (ret=%d)", ret);
+        return ret;
+    }
+
+    LOG_I("sd0 mounted at '/'");
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(_sdcard_fs_mount);
+
+#endif /* BSP_USING_SDCARD_FATFS */

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h

@@ -41,6 +41,34 @@ void BOARD_InitPins(void);                    /* Function assigned for the Corte
 
 void BOARD_InitLeds(void);
 
+#ifdef BSP_USING_LPUART1
+void BOARD_InitLPUART1Pins(void);
+#endif
+
+#ifdef BSP_USING_LPUART10
+void BOARD_InitLPUART10Pins(void);
+#endif
+
+#ifdef BSP_USING_LPUART12
+void BOARD_InitLPUART12Pins(void);
+#endif
+
+#ifdef BSP_USING_I2C2
+void BOARD_InitLPI2C2Pins(void);
+#endif
+
+#ifdef BSP_USING_I2C3
+void BOARD_InitLPI2C3Pins(void);
+#endif
+
+#ifdef BSP_USING_SPI3
+void BOARD_InitLPSPI3Pins(void);
+#endif
+
+#ifdef BSP_USING_SDIO
+void BOARD_InitSDIO1Pins(void);
+#endif
+
 #if defined(__cplusplus)
 }
 #endif

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript

@@ -23,6 +23,9 @@ else:
     MCUX_Config/peripherals.c
     """)
 
+if GetDepend(['BSP_USING_QSPI_FLASH']):
+    src += ['ports/drv_flexspi_nor_flash.c']
+
 if GetDepend(['BSP_USING_QSPI_FLASH_FS']):
     src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c']
 

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c

@@ -1500,24 +1500,21 @@ void rt_hw_board_init()
     extern void BOARD_InitPeripherals(void);
     BOARD_CommonSetting();
     BOARD_ConfigMPU();
-    BOARD_InitPins();
+    BOARD_InitBootPins();
     BOARD_BootClockRUN();
 //    BOARD_InitPeripherals();
 
     NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
 
-    /*init uart device*/
-    rt_hw_uart_init();
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
 
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
 
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
-#endif
-
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h

@@ -30,7 +30,7 @@
 #define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102
 #endif
 #ifndef BOARD_DEBUG_UART_BASEADDR
-#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t)LPUART1
 #endif
 #ifndef BOARD_DEBUG_UART_INSTANCE
 #define BOARD_DEBUG_UART_INSTANCE 1U
@@ -88,7 +88,7 @@
 #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO1_0_IRQHandler
 #define BOARD_USER_BUTTON_NAME        "SW8"
 
-#define BOARD_WAKEUP_BUTTON_NAME      "SW4"
+#define BOARD_WAKEUP_BUTTON_NAME "SW4"
 
 /*! @brief The board flash size */
 #define BOARD_FLASH_SIZE (0x1000000U)
@@ -167,17 +167,17 @@ void PHY_Reset(void);
 #if defined(__ARMCC_VERSION)
 extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
 extern int Image$$ARM_LIB_HEAP$$ZI$$Limit;
-#define HEAP_BEGIN  ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
-#define HEAP_END    ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit)
+#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
+#define HEAP_END   ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Limit)
 #elif defined(__ICCARM__)
-#pragma section="HEAP"
-#define HEAP_BEGIN    (__section_begin("HEAP"))
-#define HEAP_END      (__section_end("HEAP"))
+#pragma section = "HEAP"
+#define HEAP_BEGIN (__section_begin("HEAP"))
+#define HEAP_END   (__section_end("HEAP"))
 #elif defined(__GNUC__)
 extern int __HeapBase;
 extern int __HeapLimit;
-#define HEAP_BEGIN  ((void *)&__HeapBase)
-#define HEAP_END  ((void *)&__HeapLimit)
+#define HEAP_BEGIN ((void *)&__HeapBase)
+#define HEAP_END   ((void *)&__HeapLimit)
 #endif
 
 void rt_hw_board_init(void);

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c

@@ -20,8 +20,8 @@
 /*
  * Logging configuration
  */
-#define LOG_TAG     "drv.flash"
-#define LOG_LVL     LOG_LVL_INFO
+#define LOG_TAG "drv.flash"
+#define LOG_LVL LOG_LVL_INFO
 #include <rtdbg.h>
 
 /*
@@ -29,10 +29,10 @@
  * FLASH_BUSY_STATUS_OFFSET = 0  : WIP bit is SR[0]
  * FLASH_QUAD_ENABLE        = 0x40 : write to SR to enable Quad mode
  */
-#define FLASH_QUAD_ENABLE_VAL       0x40U
+#define FLASH_QUAD_ENABLE_VAL 0x40U
 
 /* WIP polling upper limit to prevent infinite loop on Flash failure */
-#define WIP_TIMEOUT_COUNT           2000000UL
+#define WIP_TIMEOUT_COUNT 2000000UL
 
 /*
  * Internal write buffer (must reside in SRAM)
@@ -45,9 +45,9 @@
 static uint8_t SDK_ALIGN(s_write_buf[QSPI_PAGE_SIZE], 4);
 
 /* Internal state */
-static imxrt_flexspi_handle_t  *s_handle  = RT_NULL;
-static struct rt_mutex          s_mutex;
-static int                      s_inited  = 0;
+static imxrt_flexspi_handle_t *s_handle = RT_NULL;
+static struct rt_mutex s_mutex;
+static int s_inited = 0;
 
 /*
  * _range_valid - check whether [offset, offset+size) is within Flash
@@ -109,10 +109,10 @@ static status_t _nor_write_enable(rt_uint32_t base_addr)
     flexspi_transfer_t xfer;
 
     xfer.deviceAddress = base_addr;
-    xfer.port          = FLASH_PORT;
-    xfer.cmdType       = kFLEXSPI_Command;
-    xfer.SeqNumber     = 1;
-    xfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+    xfer.port = FLASH_PORT;
+    xfer.cmdType = kFLEXSPI_Command;
+    xfer.SeqNumber = 1;
+    xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
 
     return FLEXSPI_TransferBlocking(s_handle->base, &xfer);
 }
@@ -125,19 +125,19 @@ static status_t _nor_write_enable(rt_uint32_t base_addr)
  */
 static status_t _nor_wait_busy(void)
 {
-    rt_uint32_t        read_val = 0;
-    rt_uint32_t        timeout  = 0;
-    status_t           status;
-    rt_bool_t          is_busy;
+    rt_uint32_t read_val = 0;
+    rt_uint32_t timeout = 0;
+    status_t status;
+    rt_bool_t is_busy;
     flexspi_transfer_t xfer;
 
     xfer.deviceAddress = 0;
-    xfer.port          = FLASH_PORT;
-    xfer.cmdType       = kFLEXSPI_Read;
-    xfer.SeqNumber     = 1;
-    xfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
-    xfer.data          = &read_val;
-    xfer.dataSize      = 1;
+    xfer.port = FLASH_PORT;
+    xfer.cmdType = kFLEXSPI_Read;
+    xfer.SeqNumber = 1;
+    xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    xfer.data = &read_val;
+    xfer.dataSize = 1;
 
     do
     {
@@ -161,8 +161,7 @@ static status_t _nor_wait_busy(void)
         {
             return kStatus_Timeout;
         }
-    }
-    while (is_busy);
+    } while (is_busy);
 
     return kStatus_Success;
 }
@@ -174,17 +173,17 @@ static status_t _nor_wait_busy(void)
  */
 static status_t _nor_erase_sector(rt_uint32_t addr)
 {
-    rt_base_t          level;
-    status_t           status;
+    rt_base_t level;
+    status_t status;
     flexspi_transfer_t xfer;
 
     level = rt_hw_interrupt_disable();
 
     xfer.deviceAddress = addr;
-    xfer.port          = FLASH_PORT;
-    xfer.cmdType       = kFLEXSPI_Command;
-    xfer.SeqNumber     = 1;
-    xfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+    xfer.port = FLASH_PORT;
+    xfer.cmdType = kFLEXSPI_Command;
+    xfer.SeqNumber = 1;
+    xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
 
     status = FLEXSPI_TransferBlocking(s_handle->base, &xfer);
     if (status != kStatus_Success)
@@ -220,8 +219,8 @@ static status_t _nor_erase_sector(rt_uint32_t addr)
  */
 static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src)
 {
-    rt_base_t          level;
-    status_t           status;
+    rt_base_t level;
+    status_t status;
     flexspi_transfer_t xfer;
 
     level = rt_hw_interrupt_disable();
@@ -241,12 +240,12 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src)
     }
 
     xfer.deviceAddress = addr;
-    xfer.port          = FLASH_PORT;
-    xfer.cmdType       = kFLEXSPI_Write;
-    xfer.SeqNumber     = 1;
-    xfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
-    xfer.data          = (rt_uint32_t *)src;
-    xfer.dataSize      = QSPI_PAGE_SIZE;
+    xfer.port = FLASH_PORT;
+    xfer.cmdType = kFLEXSPI_Write;
+    xfer.SeqNumber = 1;
+    xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+    xfer.data = (rt_uint32_t *)src;
+    xfer.dataSize = QSPI_PAGE_SIZE;
 
     status = FLEXSPI_TransferBlocking(s_handle->base, &xfer);
     if (status != kStatus_Success)
@@ -279,9 +278,9 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src)
  */
 int rt_qspi_flash_init(void)
 {
-    rt_uint8_t         vendor_id = 0;
-    rt_uint32_t        temp      = 0;
-    status_t           status;
+    rt_uint8_t vendor_id = 0;
+    rt_uint32_t temp = 0;
+    status_t status;
     flexspi_transfer_t xfer;
 
     if (s_inited)
@@ -299,12 +298,12 @@ int rt_qspi_flash_init(void)
 
     /* Read Vendor ID to verify Flash connectivity (SDK: flexspi_nor_get_vendor_id) */
     xfer.deviceAddress = 0;
-    xfer.port          = FLASH_PORT;
-    xfer.cmdType       = kFLEXSPI_Read;
-    xfer.SeqNumber     = 1;
-    xfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READID;
-    xfer.data          = &temp;
-    xfer.dataSize      = 1;
+    xfer.port = FLASH_PORT;
+    xfer.cmdType = kFLEXSPI_Read;
+    xfer.SeqNumber = 1;
+    xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
+    xfer.data = &temp;
+    xfer.dataSize = 1;
 
     status = FLEXSPI_TransferBlocking(s_handle->base, &xfer);
     if (status != kStatus_Success)
@@ -410,7 +409,7 @@ void *rt_qspi_flash_mmap(rt_uint32_t offset, rt_size_t size)
 int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size)
 {
     rt_size_t written = 0;
-    status_t  status;
+    status_t status;
 
     if (!s_inited)
     {
@@ -477,7 +476,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size)
 {
     rt_uint32_t addr;
     rt_uint32_t addr_end;
-    status_t    status;
+    status_t status;
 
     if (!s_inited)
     {
@@ -496,7 +495,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size)
         return -RT_EINVAL;
     }
 
-    addr     = offset;
+    addr = offset;
     addr_end = offset + (rt_uint32_t)size;
 
     rt_mutex_take(&s_mutex, RT_WAITING_FOREVER);

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c

@@ -17,8 +17,8 @@
 /*
  * Logging configuration
  */
-#define LOG_TAG     "fal.flash"
-#define LOG_LVL     LOG_LVL_INFO
+#define LOG_TAG "fal.flash"
+#define LOG_LVL LOG_LVL_INFO
 #include <rtdbg.h>
 
 /* FAL ops bridge */
@@ -44,13 +44,12 @@ static int _fal_erase(long offset, size_t size)
     return rt_qspi_flash_erase((rt_uint32_t)offset, size);
 }
 
-const struct fal_flash_dev imxrt1180_nor_flash =
-{
-    .name       = "norflash0",
-    .addr       = QSPI_FLASH_BASE,
-    .len        = QSPI_FLASH_SIZE,
-    .blk_size   = QSPI_SECTOR_SIZE,
-    .ops        = { _fal_init, _fal_read, _fal_write, _fal_erase },
+const struct fal_flash_dev imxrt1180_nor_flash = {
+    .name = "norflash0",
+    .addr = QSPI_FLASH_BASE,
+    .len = QSPI_FLASH_SIZE,
+    .blk_size = QSPI_SECTOR_SIZE,
+    .ops = { _fal_init, _fal_read, _fal_write, _fal_erase },
     .write_gran = QSPI_PAGE_SIZE,
 };
 

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/flexspi_port.h

@@ -13,32 +13,39 @@
 #define FLEXSPI_PORT_H__
 
 /* parameters for flexpsi peripheral */
-#define FLEXSPI1_CONTROL_BASE FLEXSPI1
-#define FLEXSPI2_CONTROL_BASE FLEXSPI2
-#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/
-#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */
-#define ARD_SEQ_NUMBER 1       /* Sequence number for AHB read command */
-#define ARD_SEQ_INDEX 0        /* Sequence ID for AHB read command */
-#define AWR_SEQ_NUMBER 0       /* Sequence number for AHB write command */
-#define AWR_SEQ_INDEX 0        /* Sequence ID for AHB write command */
-#define ARD_SEQ_CMD 0xBB       /* cmd for read */
-#define AWR_SEQ_CMD 0xAA       /* cmd for write */
-#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
-#define FLASH_PORT kFLEXSPI_PortA1
-#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M
-#define CLOCK_DIV 2U
-#define CUSTOM_LUT_LENGTH 60U
+#define FLEXSPI1_CONTROL_BASE     FLEXSPI1
+#define FLEXSPI2_CONTROL_BASE     FLEXSPI2
+#define FLEXSPI_ROOT_CLK          (12000000U) /* serial root clk: 12MHz*/
+#define FLASH_SIZE                (16 * 1024) /* device size 16*1024(KB) = 16MB */
+#define ARD_SEQ_NUMBER            1       /* Sequence number for AHB read command */
+#define ARD_SEQ_INDEX             0        /* Sequence ID for AHB read command */
+#define AWR_SEQ_NUMBER            0       /* Sequence number for AHB write command */
+#define AWR_SEQ_INDEX             0        /* Sequence ID for AHB write command */
+#define ARD_SEQ_CMD               0xBB       /* cmd for read */
+#define AWR_SEQ_CMD               0xAA       /* cmd for write */
+#define FLEXSPI_RX_SAMPLE_CLOCK   kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
+#define FLASH_PORT                kFLEXSPI_PortA1
+#define CLOCK_SRC                 kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M
+#define CLOCK_DIV                 2U
+#define CUSTOM_LUT_LENGTH         60U
 #define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U)
 #define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U)
 
-#define COMBINATION_MODE   0U
-#define FREE_RUNNING_MODE  0U
+#define COMBINATION_MODE  0U
+#define FREE_RUNNING_MODE 0U
 
-#define EXAMPLE_FLEXSPI_AMBA_BASE       FlexSPI1_AMBA_BASE
-#define FLASH_PAGE_SIZE                 256
-#define SECTOR_SIZE                     0x1000 /* 4K */
-#define EXAMPLE_FLEXSPI_CLOCK           kCLOCK_Flexspi1
-#define FLASH_PORT                      kFLEXSPI_PortA1
+#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE
+#define FLASH_PAGE_SIZE           256
+#define SECTOR_SIZE               0x1000 /* 4K */
+#define EXAMPLE_FLEXSPI_CLOCK     kCLOCK_Flexspi1
+#define FLASH_PORT                kFLEXSPI_PortA1
+
+/* DMA related. */
+#define FLEXSPI_DMA                   (DMA4)
+#define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx
+#define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx
+#define FLEXSPI_TX_DMA_CHANNEL        0U
+#define FLEXSPI_RX_DMA_CHANNEL        2U
 
 #define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL        7
 #define NOR_CMD_LUT_SEQ_IDX_READ_FAST          13

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h

@@ -151,6 +151,7 @@
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V2
 #define RT_SERIAL_BUF_STRATEGY_OVERWRITE
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN
 /* end of Device Drivers */
 
@@ -420,9 +421,14 @@
 
 /* On-chip Peripheral Drivers */
 
+#define BSP_USING_DMA
 #define BSP_USING_GPIO
 #define BSP_USING_LPUART
 #define BSP_USING_LPUART1
+#define BSP_LPUART1_RX_USING_DMA
+#define BSP_LPUART1_RX_DMA_CHANNEL 0
+#define BSP_LPUART1_TX_USING_DMA
+#define BSP_LPUART1_TX_DMA_CHANNEL 1
 /* end of On-chip Peripheral Drivers */
 
 /* Onboard Peripheral Drivers */

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h

@@ -62,22 +62,22 @@ typedef enum _FlashReadSampleClkSource
 {
     kFlexSPIReadSampleClk_LoopbackInternally = 0,
     kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
-    kFlexSPIReadSampleClk_Reversed           = 2,
-    kFlexSPIReadSampleClk_FlashProvidedDqs   = 3,
+    kFlexSPIReadSampleClk_Reversed = 2,
+    kFlexSPIReadSampleClk_FlashProvidedDqs = 3,
 } flexspi_read_sample_clk_t;
 
 //!@brief Flash Type Definition
 enum
 {
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3     //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_SerialNOR = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM = 3     //!< Flash devices are Serial RAM/HyperFLASH
 };
 
 //!@brief Flash Pad Definitions
 enum
 {
-    kSerialFlash_1Pad  = 1,
+    kSerialFlash_1Pad = 1,
     kSerialFlash_2Pads = 2,
     kSerialFlash_4Pads = 4,
     kSerialFlash_8Pads = 8,
@@ -86,10 +86,10 @@ enum
 //!@brief Definitions for FlexSPI Serial Clock Frequency
 typedef enum _FlexSpiSerialClockFreq
 {
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_80MHz  = 4,
+    kFlexSpiSerialClk_30MHz = 1,
+    kFlexSpiSerialClk_50MHz = 2,
+    kFlexSpiSerialClk_60MHz = 3,
+    kFlexSpiSerialClk_80MHz = 4,
     kFlexSpiSerialClk_100MHz = 5,
     kFlexSpiSerialClk_120MHz = 6,
     kFlexSpiSerialClk_133MHz = 7,

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c

@@ -61,4 +61,4 @@ const container container_data =
 };
 /* clang-format on */
 
-#endif
+#endif

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml

@@ -24,6 +24,37 @@ Peripheral.qspi_flash_FS:
   <<: *scons
   kconfig:
     - CONFIG_BSP_USING_QSPI_FLASH_FS=y
+Peripheral.lpuart_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_LPUART=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.i2c_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_I2C=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.spi_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_SPI=y
+    - CONFIG_BSP_USING_DMA=y
+Peripheral.can_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_CAN=y
+Peripheral.rtc_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_RTC=y
+Peripheral.dwt_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_DWT=y
+Peripheral.sdio_device:
+  <<: *scons
+  kconfig:
+    - CONFIG_BSP_USING_SDCARD_FATFS=y
 Peripheral.usb_device:
   <<: *scons
   kconfig:

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config

@@ -243,10 +243,11 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
 CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_USING_SERIAL_V1=y
-# CONFIG_RT_USING_SERIAL_V2 is not set
-# CONFIG_RT_SERIAL_USING_DMA is not set
-CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
+CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_ADC is not set
@@ -1449,8 +1450,9 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y
 #
 # On-chip Peripheral Drivers
 #
-# CONFIG_BSP_USING_DMA is not set
-# CONFIG_BSP_USING_GPIO is not set
+# CONFIG_BSP_USING_DWT is not set
+CONFIG_BSP_USING_DMA=y
+CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_USB is not set
 # CONFIG_BSP_USING_SDIO is not set
@@ -1467,8 +1469,12 @@ CONFIG_BSP_USING_LPUART=y
 # CONFIG_BSP_USING_LPUART10 is not set
 # CONFIG_BSP_USING_LPUART11 is not set
 CONFIG_BSP_USING_LPUART12=y
-# CONFIG_BSP_LPUART12_RX_USING_DMA is not set
-# CONFIG_BSP_LPUART12_TX_USING_DMA is not set
+CONFIG_BSP_LPUART12_RX_USING_DMA=y
+CONFIG_BSP_LPUART12_RX_DMA_CHANNEL=22
+CONFIG_BSP_LPUART12_TX_USING_DMA=y
+CONFIG_BSP_LPUART12_TX_DMA_CHANNEL=23
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_CAN is not set
 # CONFIG_BSP_USING_FLEXSPI is not set
 # end of On-chip Peripheral Drivers
@@ -1481,13 +1487,15 @@ CONFIG_BSP_USING_LPUART12=y
 # CONFIG_BSP_USING_ETHERCAT is not set
 # CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_FS is not set
+# CONFIG_BSP_USING_QSPI_FLASH is not set
+# CONFIG_BSP_USING_OSPI_FLASH is not set
 # end of Onboard Peripheral Drivers
 
 #
 # Board extended module Drivers
 #
-CONFIG_BSP_LINKER_SCRIPT_RAM=y
+# CONFIG_BSP_LINKER_SCRIPT_RAM is not set
 # CONFIG_BSP_LINKER_SCRIPT_HYPERRAM is not set
-# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR is not set
+CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y
 # CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set
 # end of Hardware Drivers Config

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c

@@ -9,6 +9,9 @@
  */
 
 #include <rtthread.h>
+#define DBG_TAG "mnt"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
 
 /* ====================================================================
  * QSPI NOR Flash LittleFS (controlled by BSP_USING_QSPI_FLASH_FS)
@@ -98,3 +101,30 @@ INIT_APP_EXPORT(_qspi_flash_fs_mount);
 INIT_COMPONENT_EXPORT(fal_init);
 
 #endif /* BSP_USING_QSPI_FLASH_FS */
+
+#ifdef BSP_USING_SDCARD_FATFS
+#include <dfs_fs.h>
+
+static int _sdcard_fs_mount(void)
+{
+    rt_tick_t start = rt_tick_get();
+    while (rt_device_find("sd0") == RT_NULL)
+    {
+        if ((rt_tick_get() - start) > (5 * RT_TICK_PER_SECOND))
+        {
+            LOG_E("wait for 'sd0' timeout");
+            return -RT_ETIMEOUT;
+        }
+        rt_thread_mdelay(10);
+    }
+    int ret = dfs_mount("sd0", "/", "elm", 0, 0);
+    if (ret != 0)
+    {
+        LOG_E("sd0 mount to '/' failed! (ret=%d)", ret);
+        return ret;
+    }
+    LOG_I("sd0 mounted at '/'");
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(_sdcard_fs_mount);
+#endif /* BSP_USING_SDCARD_FATFS */

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h

@@ -37,7 +37,133 @@ void BOARD_InitBootPins(void);
  * @brief Configures pin routing and optionally pin electrical features.
  *
  */
-void BOARD_InitPins(void);                    /* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void);                    /* Function assigned for the Cortex-M7 */
+
+#ifdef BSP_USING_LPUART12
+void BOARD_InitLPUART12Pins(void);
+#endif
+
+#ifdef BSP_USING_I2C2
+void BOARD_InitLPI2C2Pins(void);
+#endif
+
+#ifdef BSP_USING_I2C3
+void BOARD_InitLPI2C3Pins(void);
+#endif
+
+#ifdef BSP_USING_SPI3
+void BOARD_InitLPSPI3Pins(void);
+#endif
+
+#ifdef BSP_USING_SDIO
+void BOARD_InitSDIO1Pins(void);
+#endif
+
+#ifdef BSP_USING_ETH
+/* GPIO_AD_25 (coord M15), ENET0_RST_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_PERIPHERAL RGPIO4   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_CHANNEL    25U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO          RGPIO4   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN      25U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN_MASK (1U << 25U)   /*!< GPIO pin mask */
+
+/* GPIO_B1_13 (coord B11), ENET1_RST_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_PERIPHERAL RGPIO6   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_CHANNEL    13U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO          RGPIO6   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN      13U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN_MASK (1U << 13U)   /*!< GPIO pin mask */
+
+/* GPIO_AD_28 (coord L16), ENET2_RST_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_PERIPHERAL RGPIO4   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_CHANNEL    28U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO          RGPIO4   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN      28U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN_MASK (1U << 28U)   /*!< GPIO pin mask */
+
+/* GPIO_B2_01 (coord E10), ENET3_RST_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_PERIPHERAL RGPIO6   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_CHANNEL    15U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO          RGPIO6   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN      15U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN_MASK (1U << 15U)   /*!< GPIO pin mask */
+
+/* GPIO_AD_13 (coord N15), ENET4_RST_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_PERIPHERAL RGPIO4   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_CHANNEL    13U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO          RGPIO4   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN      13U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN_MASK (1U << 13U)   /*!< GPIO pin mask */
+
+/* GPIO_AD_12 (coord P17), ENET4_INT_B */
+/* Routed pin properties */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_PERIPHERAL RGPIO4   /*!< Peripheral name */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_SIGNAL     gpio_io   /*!< Signal name */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_CHANNEL    12U   /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO          RGPIO4   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN      12U   /*!< GPIO pin number */
+#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN_MASK (1U << 12U)   /*!< GPIO pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPhyAccessPins(void);           /* Function assigned for the Cortex-M33 */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitEpPins(void);                  /* Function assigned for the Cortex-M33 */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSwtPort0Pins(void);            /* Function assigned for the Cortex-M33 */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSwtPort1Pins(void);            /* Function assigned for the Cortex-M33 */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSwtPort2Pins(void);            /* Function assigned for the Cortex-M33 */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSwtPort3Pins(void);            /* Function assigned for the Cortex-M33 */
+
+#endif
+
 
 #ifdef BSP_USING_ETH
 /* GPIO_AD_25 (coord M15), ENET0_RST_B */

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript

@@ -21,6 +21,9 @@ else:
     MCUX_Config/pin_mux.c
     """)
 
+if GetDepend(['BSP_USING_QSPI_FLASH']):
+    src += ['ports/drv_flexspi_nor_flash.c']
+
 if GetDepend(['BSP_USING_QSPI_FLASH_FS']):
     src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c']
 

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c

@@ -1264,8 +1264,9 @@ void rt_hw_board_init()
     NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
 
-    /*init uart device*/
-    rt_hw_uart_init();
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
 
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
@@ -1280,8 +1281,6 @@ void rt_hw_board_init()
     rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n",
                HEAP_BEGIN, HEAP_END,
                (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN);
-
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 }
 

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c

@@ -127,9 +127,9 @@ status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool en
 
     /* Write enable */
     flashXfer.deviceAddress = baseAddr;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
     if (enableOctal)
     {
         flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI;
@@ -148,14 +148,14 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal)
 {
     /* Wait status ready. */
     bool isBusy;
-    uint32_t readValue=0;
+    uint32_t readValue = 0;
     status_t status;
     flexspi_transfer_t flashXfer;
 
     flashXfer.deviceAddress = 0;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Read;
-    flashXfer.SeqNumber     = 1;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
     if (enableOctal)
     {
         flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI;
@@ -165,7 +165,7 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal)
         flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS;
     }
 
-    flashXfer.data     = &readValue;
+    flashXfer.data = &readValue;
     flashXfer.dataSize = 1;
 
     do
@@ -239,12 +239,12 @@ status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base)
 
     /* Enable quad mode. */
     flashXfer.deviceAddress = 0;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Write;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_ENTEROPI;
-    flashXfer.data          = &writeValue;
-    flashXfer.dataSize      = 1;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI;
+    flashXfer.data = &writeValue;
+    flashXfer.dataSize = 1;
 
     status = FLEXSPI_TransferBlocking(base, &flashXfer);
     if (status != kStatus_Success)
@@ -252,7 +252,7 @@ status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base)
         return status;
     }
 
-    status             = flexspi_nor_wait_bus_busy(base, true);
+    status = flexspi_nor_wait_bus_busy(base, true);
 
     /* Do software reset. */
     FLEXSPI_SoftwareReset(base);
@@ -284,11 +284,11 @@ status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
     }
 
     flashXfer.deviceAddress = address;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
-    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
     if (status != kStatus_Success)
     {
@@ -331,17 +331,17 @@ status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, co
 
     /* Prepare page program command */
     flashXfer.deviceAddress = dstAddr;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Write;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
-    flashXfer.data          = (uint32_t *)src;
-    flashXfer.dataSize      = FLASH_PAGE_SIZE;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
 #ifdef BSP_USING_DMA
     g_completionFlag = false;
-    status                  = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
+    status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
 #else
-    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
 #endif
     if (status != kStatus_Success)
     {
@@ -373,14 +373,14 @@ status_t flexspi_nor_read_data(FLEXSPI_Type *base, uint32_t startAddress, uint32
 
     /* Read page. */
     flashXfer.deviceAddress = readAddress;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Read;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READ;
-    flashXfer.data          = buffer;
-    flashXfer.dataSize      = length;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = length;
 #ifdef BSP_USING_DMA
-    g_completionFlag        = false;
+    g_completionFlag = false;
 
     status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
 
@@ -406,14 +406,14 @@ status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
 {
     /* Read manufacturer ID based on JEP106V spec, max continuation code table is 9, max manufacturer ID starts from
      * 9 + 1. */
-    uint8_t id[10] = {0x00U};
+    uint8_t id[10] = { 0x00U };
     flexspi_transfer_t flashXfer;
     flashXfer.deviceAddress = 0;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Read;
-    flashXfer.SeqNumber     = 1;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
     flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID_OPI;
-    flashXfer.data     = (uint32_t *)id;
+    flashXfer.data = (uint32_t *)id;
     flashXfer.dataSize = 10U;
 
     status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
@@ -444,10 +444,10 @@ status_t flexspi_nor_erase_chip(FLEXSPI_Type *base)
     }
 
     flashXfer.deviceAddress = 0;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_CHIPERASE;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE;
 
     status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
@@ -486,18 +486,18 @@ status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const u
 
     /* Prepare page program command */
     flashXfer.deviceAddress = dstAddr;
-    flashXfer.port          = FLASH_PORT;
-    flashXfer.cmdType       = kFLEXSPI_Write;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
-    flashXfer.data          = (uint32_t *)src;
-    flashXfer.dataSize      = length;
+    flashXfer.port = FLASH_PORT;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = length;
 #ifdef BSP_USING_DMA
-    g_completionFlag        = false;
+    g_completionFlag = false;
 
-    status                  = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
+    status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
 #else
-    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
 #endif
     if (status != kStatus_Success)
     {

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h

@@ -18,7 +18,7 @@
 #error "Please enable only one of BSP_USING_QSPI_FLASH_FS or BSP_USING_OSPI_FLASH"
 #endif
 
-#if defined(BSP_USING_QSPI_FLASH_FS)
+#if defined(BSP_USING_QSPI_FLASH_FS) || defined(BSP_USING_QSPI_FLASH)
 /* parameters for flexpsi peripheral */
 #define FLEXSPI1_CONTROL_BASE     FLEXSPI1
 #define FLEXSPI2_CONTROL_BASE     FLEXSPI2

bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h

@@ -152,8 +152,9 @@
 #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN
 /* end of Device Drivers */
 
@@ -423,8 +424,14 @@
 
 /* On-chip Peripheral Drivers */
 
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
 #define BSP_USING_LPUART
 #define BSP_USING_LPUART12
+#define BSP_LPUART12_RX_USING_DMA
+#define BSP_LPUART12_RX_DMA_CHANNEL 22
+#define BSP_LPUART12_TX_USING_DMA
+#define BSP_LPUART12_TX_DMA_CHANNEL 23
 /* end of On-chip Peripheral Drivers */
 
 /* Onboard Peripheral Drivers */
@@ -433,7 +440,7 @@
 
 /* Board extended module Drivers */
 
-#define BSP_LINKER_SCRIPT_RAM
+#define BSP_LINKER_SCRIPT_FLEXSPI_NOR
 /* end of Hardware Drivers Config */
 
 #endif

bsp/nxp/imx/imxrt/libraries/drivers/SConscript

@@ -22,7 +22,10 @@ if  GetDepend('BSP_USING_CLOCK_TIMER'):
     src += ['drv_timer.c']
 
 if GetDepend('BSP_USING_RTC'):
-    src += ['drv_rtc.c']
+    if GetDepend('SOC_IMXRT1180_SERIES'):
+        src += ['drv_rtc_bbnsm.c']
+    else:
+        src += ['drv_rtc.c']
 
 if  GetDepend('BSP_USING_SPI'):
     src += ['drv_spi.c']
@@ -33,6 +36,9 @@ if  GetDepend('BSP_USING_I2C'):
 if GetDepend('BSP_USING_WDT'):
     src += ['drv_wdt.c']
 
+if GetDepend('BSP_USING_DWT'):
+    src += ['drv_dwt.c']
+
 if GetDepend('BSP_USING_PWM'):
     src += ['drv_pwm.c']
 

bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c

@@ -20,7 +20,7 @@
 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
 
-#define LOG_TAG             "drv.adc"
+#define LOG_TAG "drv.adc"
 #include <drv_log.h>
 #include "drv_adc.h"
 #include "fsl_adc.h"
@@ -52,8 +52,7 @@ static rt_err_t imxrt_hp_adc_convert(struct rt_adc_device *device, rt_uint32_t c
     return RT_EOK;
 }
 
-static struct rt_adc_ops imxrt_adc_ops =
-{
+static struct rt_adc_ops imxrt_adc_ops = {
     .enabled = imxrt_hp_adc_enabled,
     .convert = imxrt_hp_adc_convert,
 };

bsp/nxp/imx/imxrt/libraries/drivers/drv_can.c

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2019-06-27     misonyo     the first version.
  * 2022-09-01     xjy198903   add support for imxrt1170
+ * 2026-08-13     nxp-ran     add support for imxrt1180 (SOC_IMXRT1180_SERIES)
  */
 
 #include <rtthread.h>
@@ -18,18 +19,18 @@
 #include "fsl_iomuxc.h"
 #include "fsl_flexcan.h"
 
-#define LOG_TAG    "drv.can"
+#define LOG_TAG "drv.can"
 #include <drv_log.h>
 
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
-    #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
 
-#define RX_MB_COUNT     32
+#define RX_MB_COUNT 32
 static flexcan_frame_t frame[RX_MB_COUNT];    /* one frame buffer per RX MB */
 static rt_uint32_t filter_mask = 0;
 
-#ifdef SOC_IMXRT1170_SERIES
+#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
 #define USE_IMPROVED_TIMING_CONFIG (1U)
 #endif
 
@@ -55,8 +56,7 @@ struct imxrt_can
     struct rt_can_device can_dev;
 };
 
-struct imxrt_can flexcans[] =
-{
+struct imxrt_can flexcans[] = {
 #ifdef BSP_USING_CAN1
     {
         .name = "can1",
@@ -83,30 +83,30 @@ struct imxrt_can flexcans[] =
 uint32_t GetCanSrcFreq(CAN_Type *can_base)
 {
     uint32_t freq;
-#ifdef SOC_IMXRT1170_SERIES
-    uint32_t base = (uint32_t) can_base;
+#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
+    uint32_t base = (uint32_t)can_base;
     switch (base)
-        {
-        case CAN1_BASE:
-            freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can1) / 100000U) * 100000U;
-            break;
-        case CAN2_BASE:
-            freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can2) / 100000U) * 100000U;
-            break;
-        case CAN3_BASE:
-            freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U;
-            break;
-        default:
-            freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U;
-            break;
-        }
+    {
+    case CAN1_BASE:
+        freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can1) / 100000U) * 100000U;
+        break;
+    case CAN2_BASE:
+        freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can2) / 100000U) * 100000U;
+        break;
+    case CAN3_BASE:
+        freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U;
+        break;
+    default:
+        freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U;
+        break;
+    }
 #else
     freq = (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 6) / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1U);
 #endif
     return freq;
 }
 
-#ifdef SOC_IMXRT1170_SERIES
+#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
 static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)
 #else
 static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData)
@@ -179,13 +179,13 @@ static rt_err_t can_cfg(struct rt_can_device *can_dev, struct can_configure *cfg
         break;
     }
 
-#ifdef SOC_IMXRT1170_SERIES
+#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
     flexcan_timing_config_t timing_config;
     rt_memset(&timing_config, 0, sizeof(flexcan_timing_config_t));
 
-    if(FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, GetCanSrcFreq(can->base), &timing_config))
+    if (FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, GetCanSrcFreq(can->base), &timing_config))
     {
-        /* Update the improved timing configuration*/
+        /* Update the improved timing configuration */
         rt_memcpy(&(config.timingConfig), &timing_config, sizeof(flexcan_timing_config_t));
     }
     else
@@ -222,7 +222,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg)
     rt_uint32_t argval, mask;
     rt_uint32_t res = RT_EOK;
     flexcan_rx_mb_config_t mbConfig;
-    struct rt_can_filter_config  *cfg;
+    struct rt_can_filter_config *cfg;
     struct rt_can_filter_item *item;
     rt_uint8_t i, count, index;
 
@@ -234,7 +234,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg)
     switch (cmd)
     {
     case RT_DEVICE_CTRL_SET_INT:
-        argval = (rt_uint32_t) arg;
+        argval = (rt_uint32_t)arg;
         if (argval == RT_DEVICE_FLAG_INT_RX)
         {
             mask = kFLEXCAN_RxWarningInterruptEnable;
@@ -302,10 +302,9 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg)
             /* user does not specify hdr index,set hdr_bank from RX MB 1 */
             if (item->hdr_bank == -1)
             {
-
                 for (i = 0; i < 32; i++)
                 {
-                    if (!(filter_mask & (1 << i)))
+                    if (!(filter_mask & (1U << i)))
                     {
                         index = i;
                         break;
@@ -314,7 +313,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg)
             }
             else    /* use user specified hdr_bank */
             {
-                if (filter_mask & (1 << item->hdr_bank))
+                if (filter_mask & (1U << item->hdr_bank))
                 {
                     res = -RT_ERROR;
                     LOG_E("%s hdr%d filter already set!\n", can->name, item->hdr_bank);
@@ -329,7 +328,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg)
             /* RX MB index from 1 to 32,hdr index 0~31 map RX MB index 1~32. */
             FLEXCAN_SetRxIndividualMask(can->base, index + 1, mask);
             FLEXCAN_SetRxMbConfig(can->base, index + 1, &mbConfig, true);
-            filter_mask |= 1 << index;
+            filter_mask |= 1U << index;
 
             item++;
             count--;
@@ -372,7 +371,7 @@ static rt_ssize_t can_send(struct rt_can_device *can_dev, const void *buf, rt_ui
     RT_ASSERT(buf != RT_NULL);
 
     can = (struct imxrt_can *)can_dev->parent.user_data;
-    msg = (struct rt_can_msg *) buf;
+    msg = (struct rt_can_msg *)buf;
     RT_ASSERT(can != RT_NULL);
     RT_ASSERT(msg != RT_NULL);
 
@@ -439,7 +438,7 @@ static rt_ssize_t can_recv(struct rt_can_device *can_dev, void *buf, rt_uint32_t
     RT_ASSERT(can_dev != RT_NULL);
 
     can = (struct imxrt_can *)can_dev->parent.user_data;
-    pmsg = (struct rt_can_msg *) buf;
+    pmsg = (struct rt_can_msg *)buf;
     RT_ASSERT(can != RT_NULL);
 
     index = boxno - 1;
@@ -477,12 +476,11 @@ static rt_ssize_t can_recv(struct rt_can_device *can_dev, void *buf, rt_uint32_t
     return 0;
 }
 
-static struct rt_can_ops imxrt_can_ops =
-{
-    .configure    = can_cfg,
-    .control      = can_control,
-    .sendmsg      = can_send,
-    .recvmsg      = can_recv,
+static struct rt_can_ops imxrt_can_ops = {
+    .configure = can_cfg,
+    .control = can_control,
+    .sendmsg = can_send,
+    .recvmsg = can_recv,
 };
 
 int rt_hw_can_init(void)

bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-01-01     RTT          the first version, generic i.MX RT DWT driver
+ */
+
+#include "drv_dwt.h"
+
+#ifdef BSP_USING_DWT
+
+#include <rtthread.h>
+
+/* CMSIS standard variable updated by SystemCoreClockUpdate() in the SDK's
+ * system_<device>.c. Declared extern here to stay device-family-agnostic. */
+extern uint32_t SystemCoreClock;
+
+/* CoreDebug and DWT register base addresses (Cortex-M, ARMv7-M / ARMv8-M) */
+#define DWT_CTRL        (*(volatile rt_uint32_t *)0xE0001000UL)  /* DWT Control */
+#define DWT_CYCCNT      (*(volatile rt_uint32_t *)0xE0001004UL)  /* Cycle Count */
+#define CoreDebug_DEMCR (*(volatile rt_uint32_t *)0xE000EDFCUL) /* DEMCR */
+
+/* DEMCR: enable DWT and ITM trace */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
+/* DWT_CTRL: enable cycle counter */
+#define DWT_CTRL_CYCCNTENA_Msk (1UL << 0)
+/* DWT_CTRL: NOCYCCNT - set if the cycle counter is not implemented */
+#define DWT_CTRL_NOCYCCNT_Msk (1UL << 25)
+
+/**
+ * Initialize the DWT cycle counter.
+ */
+rt_err_t dwt_init(void)
+{
+    /* Enable DWT trace by setting TRCENA in DEMCR */
+    CoreDebug_DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+
+    /* Check that the cycle counter is implemented on this device */
+    if (DWT_CTRL & DWT_CTRL_NOCYCCNT_Msk)
+    {
+        return -RT_ERROR;
+    }
+
+    /* Reset then enable the cycle counter */
+    DWT_CYCCNT = 0U;
+    DWT_CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+    return RT_EOK;
+}
+
+/**
+ * Read the current DWT cycle counter value.
+ */
+rt_uint32_t dwt_get_cycles(void)
+{
+    return DWT_CYCCNT;
+}
+
+/**
+ * Convert a cycle count to microseconds using SystemCoreClock.
+ */
+rt_uint32_t dwt_cycles_to_us(rt_uint32_t cycles)
+{
+    return (rt_uint32_t)((rt_uint64_t)cycles * 1000000UL / SystemCoreClock);
+}
+
+/**
+ * Busy-wait for the requested number of microseconds.
+ */
+void dwt_delay_us(rt_uint32_t us)
+{
+    rt_uint32_t start = DWT_CYCCNT;
+    rt_uint32_t ticks = (rt_uint32_t)((rt_uint64_t)us * SystemCoreClock / 1000000UL);
+
+    /* Unsigned subtraction handles counter wrap-around correctly */
+    while ((DWT_CYCCNT - start) < ticks)
+    {
+        /* busy wait */
+    }
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+
+/**
+ * MSH command: dwt_test
+ * Tests the DWT cycle counter by measuring rt_thread_mdelay(100) and
+ * a 200 us busy-wait delay, then prints the results over the console.
+ */
+static void dwt_test(int argc, char **argv)
+{
+    rt_uint32_t t0, t1, elapsed_us;
+
+    if (dwt_init() != RT_EOK)
+    {
+        rt_kprintf("[DWT] init FAILED: cycle counter not implemented on this device\r\n");
+        return;
+    }
+    rt_kprintf("[DWT] init OK, cycle counter started\r\n");
+
+    /* test 1: measure a 100 ms OS delay */
+    t0 = dwt_get_cycles();
+    rt_thread_mdelay(100);
+    t1 = dwt_get_cycles();
+    elapsed_us = dwt_cycles_to_us(t1 - t0);
+    rt_kprintf("[DWT] rt_thread_mdelay(100) took %u us\r\n", elapsed_us);
+
+    /* test 2: busy-wait 200 us and measure it back */
+    t0 = dwt_get_cycles();
+    dwt_delay_us(200);
+    t1 = dwt_get_cycles();
+    elapsed_us = dwt_cycles_to_us(t1 - t0);
+    rt_kprintf("[DWT] dwt_delay_us(200) measured %u us\r\n", elapsed_us);
+}
+MSH_CMD_EXPORT(dwt_test, test DWT cycle counter and us delay);
+
+#endif /* RT_USING_FINSH */
+
+#endif /* BSP_USING_DWT */

bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-01-01     RTT          the first version, generic i.MX RT DWT driver
+ */
+
+#ifndef DRV_DWT_H__
+#define DRV_DWT_H__
+
+#include <rtthread.h>
+#include <stdint.h>
+
+#ifdef BSP_USING_DWT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize the DWT cycle counter.
+ * Enables the CoreDebug trace and sets CYCCNTENA in DWT_CTRL.
+ * Must be called before using any other dwt_* functions.
+ *
+ * @return RT_EOK on success, -RT_ERROR if DWT is not available.
+ */
+rt_err_t dwt_init(void);
+
+/**
+ * Read the current DWT cycle counter value.
+ *
+ * @return 32-bit free-running cycle count. Wraps around after 2^32 cycles.
+ */
+rt_uint32_t dwt_get_cycles(void);
+
+/**
+ * Convert a DWT cycle count difference to microseconds.
+ * Uses the CMSIS SystemCoreClock variable for the conversion.
+ *
+ * @param cycles  number of cycles to convert
+ * @return elapsed time in microseconds
+ */
+rt_uint32_t dwt_cycles_to_us(rt_uint32_t cycles);
+
+/**
+ * Busy-wait delay using the DWT cycle counter.
+ * dwt_init() must have been called before using this function.
+ *
+ * @param us  delay duration in microseconds
+ */
+void dwt_delay_us(rt_uint32_t us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_USING_DWT */
+
+#endif /* DRV_DWT_H__ */

bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.h

@@ -20,20 +20,20 @@ extern "C" {
 
 /* Put critical transfer code into ITCM (Code TCM) */
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
-#define FLEXSPI_RAM_CODE  __attribute__((section("CodeQuickAccess"), noinline))
+#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline))
 #elif defined(__GNUC__)
-#define FLEXSPI_RAM_CODE  __attribute__((section("CodeQuickAccess"), noinline))
+#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline))
 #elif defined(__ICCARM__)
-#define FLEXSPI_RAM_CODE  __ramfunc
+#define FLEXSPI_RAM_CODE __ramfunc
 #else
 #define FLEXSPI_RAM_CODE
 #endif
 
 typedef struct
 {
-    FLEXSPI_Type   *base;
-    flexspi_port_t  port;
-    uint32_t        ahb_base;
+    FLEXSPI_Type *base;
+    flexspi_port_t port;
+    uint32_t ahb_base;
 } imxrt_flexspi_handle_t;
 
 /* Get initialized FlexSPI handle (FlexSPI1 or FlexSPI2 decided by BSP config) */

bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.h

@@ -14,7 +14,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#define GET_PIN(PORTx, PIN)      (32 * (PORTx - 1) + (PIN & 31))    /* PORTx:1,2,3,4,5 */
+#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31))    /* PORTx:1,2,3,4,5 */
 
 int rt_hw_pin_init(void);
 

bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c

@@ -20,7 +20,7 @@
 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
 
-#define LOG_TAG             "drv.lpadc"
+#define LOG_TAG "drv.lpadc"
 #include <drv_log.h>
 #include "drv_lpadc.h"
 #include "fsl_lpadc.h"
@@ -40,7 +40,7 @@ static struct rt_adc_device lpadc2_device;
 #include "fsl_edma.h"
 
 volatile bool g_Transfer_Done = false;
-AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = {0x0,0x0,0x0,0x0,0x0,0x0,0x0};
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
 
 /* User callback function for EDMA transfer. */
 void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
@@ -57,13 +57,17 @@ static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t cha
     ADC_Type *base;
     /* channel check*/
 
-    if(channel < 4) return -RT_EINVAL;
+    if (channel < 4)
+    {
+        return -RT_EINVAL;
+    }
 
     base = (ADC_Type *)(device->parent.user_data);
-    if( RT_TRUE == enabled )
+    if (RT_TRUE == enabled)
     {
         LPADC_Enable(base, true);
-    } else
+    }
+    else
     {
         LPADC_Enable(base, false);
     }
@@ -74,12 +78,12 @@ static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t cha
 static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
 {
     ADC_Type *base;
-    uint32_t data_mask=0xffffffff;
+    uint32_t data_mask = 0xffffffff;
 #if defined(BSP_LPADC1_USING_DMA)
 
 #else
-    uint8_t i=0;
-    uint32_t adc_result[7] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0};  /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */
+    uint8_t i = 0;
+    uint32_t adc_result[7] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };  /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */
     lpadc_conv_result_t mLpadcResultConfigStruct;
 #endif
 
@@ -87,7 +91,7 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha
 
     LPADC_DoSoftwareTrigger(base, 1U);
 #if defined(BSP_LPADC1_USING_DMA)
-	extern edma_handle_t DMA4_CH0_Handle;
+    extern edma_handle_t DMA4_CH0_Handle;
     data_mask = 0xffff;
     g_Transfer_Done = false;
     EDMA_StartTransfer(&DMA4_CH0_Handle);
@@ -96,7 +100,7 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha
     {
     }
 #else
-    for(i=0;i<7;i++)
+    for (i = 0; i < 7; i++)
     {
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
         while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U))
@@ -108,17 +112,23 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha
         adc_result[i] = (mLpadcResultConfigStruct.convValue);
     }
 #endif
-    switch(channel)
+    switch (channel)
     {
-        case 4: *value = adc_result[0] & data_mask;
+    case 4:
+        *value = adc_result[0] & data_mask;
         break;
-        case 5: *value = adc_result[4] & data_mask;
+    case 5:
+        *value = adc_result[4] & data_mask;
         break;
-        case 6: *value = adc_result[2] & data_mask;
+    case 6:
+        *value = adc_result[2] & data_mask;
         break;
-        case 7: *value = adc_result[3] & data_mask;
+    case 7:
+        *value = adc_result[3] & data_mask;
         break;
-        default: *value = 0; return -RT_EINVAL;
+    default:
+        *value = 0;
+        return -RT_EINVAL;
     }
 
     return RT_EOK;
@@ -135,8 +145,7 @@ static rt_int16_t imxrt_lp_adc_get_vref(struct rt_adc_device *device)
 }
 
 
-static struct rt_adc_ops imxrt_lpadc_ops =
-{
+static struct rt_adc_ops imxrt_lpadc_ops = {
     .enabled = imxrt_lp_adc_enabled,
     .convert = imxrt_lp_adc_convert,
     .get_resolution = imxrt_lp_adc_get_resolution,

bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-08-14     nxp-ran      First version for MIMXRT1180 CM33 BBNSM RTC.
+ *
+ * This driver is for the MIMXRT1180 (RT1180) CM33 core only.
+ * The RT1180 does not have SNVS; the battery-backed domain is BBNSM.
+ * CM33 in TrustZone secure world can access BBNSM registers directly.
+ *
+ * Do NOT use drv_rtc.c (SNVS/SNVS_LP) for RT1180 -- use this driver.
+ */
+
+#ifndef DRV_RTC_BBNSM_H__
+#define DRV_RTC_BBNSM_H__
+
+#include <rtdevice.h>
+
+int rt_hw_rtc_init(void);
+
+#endif /* DRV_RTC_BBNSM_H__ */

bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c

@@ -13,7 +13,7 @@
 
 #ifdef BSP_USING_CLOCK_TIMER
 
-#define LOG_TAG             "drv.clock_timer"
+#define LOG_TAG "drv.clock_timer"
 #include <drv_log.h>
 
 #include <rtdevice.h>
@@ -40,13 +40,13 @@
 /* The effective GPT input clock after root/prescaler configuration.
  * 1170: 24 MHz root / 3 = 8 MHz; 1180: 240 MHz root / 3 = 80 MHz. */
 #if defined(SOC_IMXRT1180_SERIES)
-#define IMXRT_GPT_MAXFREQ   (80000000U)
+#define IMXRT_GPT_MAXFREQ (80000000U)
 #elif defined(SOC_IMXRT1170_SERIES)
-#define IMXRT_GPT_MAXFREQ   (8000000U)
+#define IMXRT_GPT_MAXFREQ (8000000U)
 #else
-#define IMXRT_GPT_MAXFREQ   (25000000U)
+#define IMXRT_GPT_MAXFREQ (25000000U)
 #endif
-#define IMXRT_GPT_MINFREQ   (1U)
+#define IMXRT_GPT_MINFREQ (1U)
 
 static void NVIC_Configuration(void)
 {
@@ -135,22 +135,22 @@ static void imxrt_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state)
 
     if (state == 1)
     {
-    #if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
-    #ifdef BSP_USING_CLOCK_TIMER1
+#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES)
+#ifdef BSP_USING_CLOCK_TIMER1
         /*Clock setting for GPT*/
         CLOCK_SetRootClockMux(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
         CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
-    #endif
-    #ifdef BSP_USING_CLOCK_TIMER2
+#endif
+#ifdef BSP_USING_CLOCK_TIMER2
         /*Clock setting for GPT*/
         CLOCK_SetRootClockMux(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
         CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
-    #endif
-    #else
+#endif
+#else
         /*Clock setting for GPT*/
         CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
         CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
-    #endif
+#endif
 
         /* Initialize GPT module by default config */
         GPT_GetDefaultConfig(&gptConfig);
@@ -198,8 +198,7 @@ static void imxrt_clock_timer_stop(rt_clock_timer_t *timer)
     GPT_StopTimer(clock_timer_dev);
 }
 
-static const struct rt_clock_timer_ops imxrt_clock_timer_ops =
-{
+static const struct rt_clock_timer_ops imxrt_clock_timer_ops = {
     .init = imxrt_clock_timer_init,
     .start = imxrt_clock_timer_start,
     .stop = imxrt_clock_timer_stop,
@@ -207,8 +206,7 @@ static const struct rt_clock_timer_ops imxrt_clock_timer_ops =
     .control = imxrt_clock_timer_control,
 };
 
-static const struct rt_clock_timer_info imxrt_clock_timer_info =
-{
+static const struct rt_clock_timer_info imxrt_clock_timer_info = {
     IMXRT_GPT_MAXFREQ,  /* the maximum count frequency can be set */
     IMXRT_GPT_MINFREQ,  /* the minimum count frequency can be set */
     0xFFFFFFFF,
@@ -229,7 +227,7 @@ int rt_hw_clock_timer_init(void)
 
 #ifdef BSP_USING_CLOCK_TIMER1
     GPT_timer1.info = &imxrt_clock_timer_info;
-    GPT_timer1.ops  = &imxrt_clock_timer_ops;
+    GPT_timer1.ops = &imxrt_clock_timer_ops;
     ret = rt_clock_timer_register(&GPT_timer1, "gpt1", GPT1);
 
     if (ret != RT_EOK)

bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c

@@ -359,18 +359,20 @@ static void uart_isr(struct imxrt_uart *uart)
 {
     RT_ASSERT(uart != RT_NULL);
 
-    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
+    /* Check and clear overrun first: when overrun is set, the RX data register
+     * content is unreliable on LPUART. Clear before reading to avoid consuming
+     * a corrupted byte. */
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag)
+    {
+        LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag);
+    }
+    else if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
     {
         uint8_t ch = LPUART_ReadByte(uart->uart_base);
         rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_PUTC, &ch);
         rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND);
     }
 
-    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag)
-    {
-        LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag);
-    }
-
     if ((LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag) &&
         (LPUART_GetEnabledInterrupts(uart->uart_base) & kLPUART_TxDataRegEmptyInterruptEnable))
     {
@@ -667,6 +669,11 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable both the LPUART interrupt sources and the NVIC line so that
+         * no RX/TX interrupts fire after the device is closed. */
+        LPUART_DisableInterrupts(uart->uart_base,
+                                 kLPUART_RxDataRegFullInterruptEnable |
+                                     kLPUART_TxDataRegEmptyInterruptEnable);
         DisableIRQ(uart->irqn);
         break;