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Merge branch 'master' of https://github.com/chengxiaohu/rt-thread

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chengxiaohu
2019-11-20 23:38:35 +08:00
parent 2a512f3df0 1bf5f67e8a
commit 6b8a3469f8
208 changed files with 35789 additions and 43700 deletions
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1
.travis.yml
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@@ -88,6 +88,7 @@ env:
- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f427-robomaster-a' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'

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bsp/es32f0334/drivers/drv_pm.c
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-08 wangyq the first version
* 2019-05-06 Zero-Free adapt to the new power management interface
*/
#include <rthw.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_pm.h"
#include <ald_pmu.h>
#ifdef RT_USING_PM
static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode)
{
switch (mode)
{
case PM_SLEEP_MODE_NONE:
break;
case PM_SLEEP_MODE_IDLE:
__WFI();
break;
case PM_SLEEP_MODE_LIGHT:
break;
case PM_SLEEP_MODE_DEEP:
pmu_stop2_enter();
break;
case PM_SLEEP_MODE_STANDBY:
pmu_standby_enter(PMU_STANDBY_PORT_NONE);
break;
case PM_SLEEP_MODE_SHUTDOWN:
break;
default:
RT_ASSERT(0);
break;
}
}
static int drv_hw_pm_init(void)
{
static const struct rt_pm_ops _ops =
{
_drv_pm_enter,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL
};
rt_uint8_t timer_mask = 0;
/* initialize timer mask(no need tickless) */
// timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
/* initialize system pm module */
rt_system_pm_init(&_ops, timer_mask, RT_NULL);
return 0;
}
INIT_BOARD_EXPORT(drv_hw_pm_init);
#endif

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bsp/es32f0334/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
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bsp/es32f0334/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf
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bsp/es32f0334/libraries/CMSIS/Include/SConscript
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@@ -1,11 +0,0 @@
Import('ES32_SDK_ROOT')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
include_path = [cwd]
group = DefineGroup('CMSIS2', src, depend = [''], CPPPATH = include_path)
Return('group')

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bsp/es32f0334/libraries/CMSIS/Include/core_cm3.h
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bsp/es32f0334/libraries/CMSIS/Include/core_cm4.h
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bsp/es32f0334/libraries/CMSIS/Include/core_cm7.h
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bsp/es32f0334/libraries/CMSIS/RTOS/Template/cmsis_os.h
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bsp/es32f0334/libraries/CMSIS/index.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to the CMSIS main page after 0 seconds</title>
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
</body>
</html>

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm
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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h
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/**
*********************************************************************************
*
* @file ald_acmp.h
* @brief Header file of ACMP module driver.
*
* @version V1.0
* @date 13 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_ACMP_H__
#define __ALD_ACMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup ACMP
* @{
*/
/** @defgroup ACMP_Public_Types ACMP Public Types
* @{
*/
/**
* @brief Acmp interrupt
*/
typedef enum {
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
} acmp_it_t;
/**
* @brief Acmp interrupt
*/
typedef enum {
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_flag_t;
/**
* @brief Acmp interrupt flag
*/
typedef enum {
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_status_t;
/**
* @brief Acmp positive input
*/
typedef enum {
ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */
} acmp_pos_input_t;
/**
* @brief Acmp negative input
*/
typedef enum {
ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10, /**< VDD as negative input */
ACMP_NEG_CAP = 11, /**< Capacitive as negative input */
ACMP_NEG_DAC0_CH0 = 12, /**< DAC0 channel 0 as negative input */
ACMP_NEG_DAC0_CH1 = 13, /**< DAC0 channel 1 as negative input */
} acmp_neg_input_t;
/**
* @brief Acmp mode
*/
typedef enum {
ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */
ACMP_LOW_POWER = 1, /**< Low power mode */
ACMP_MIDDLE_POWER = 2, /**< Middle power mode */
ACMP_HIGH_POWER = 3, /**< High power mode */
} acmp_mode_t;
/**
* @brief Acmp warm-up time
*/
typedef enum {
ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */
} acmp_warm_time_t;
/**
* @brief Acmp hysteresis level
*/
typedef enum {
ACMP_HYST_0 = 0, /**< No hysteresis */
ACMP_HYST_15 = 1, /**< 15mV hysteresis */
ACMP_HYST_22 = 2, /**< 22mV hysteresis */
ACMP_HYST_29 = 3, /**< 29mV hysteresis */
ACMP_HYST_36 = 4, /**< 36mV hysteresis */
ACMP_HYST_43 = 5, /**< 43mV hysteresis */
ACMP_HYST_50 = 6, /**< 50mV hysteresis */
ACMP_HYST_57 = 7, /**< 57mV hysteresis */
} acmp_hystsel_t;
/**
* @brief Acmp inactive state
*/
typedef enum {
ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */
} acmp_inactval_t;
/**
* @brief which edges set up interrupt
*/
typedef enum {
ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */
} acmp_edge_t;
/**
* @brief Acmp output function
*/
typedef enum {
ACMP_OUT_DISABLE = 0, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1, /**< Enable acmp output */
} acmp_out_func_t;
/**
* @brief Acmp warm-up interrupt function
*/
typedef enum {
ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */
} acmp_warm_it_func;
/**
* @brief Acmp gpio output invert
*/
typedef enum {
ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */
} acmp_invert_t;
/**
* @brief The location of the acmp i/o pin
*/
typedef enum {
ACMP_LOCATION_O = 0, /**< Location 0 */
ACMP_LOCATION_1 = 1, /**< Location 1 */
ACMP_LOCATION_2 = 2, /**< Location 2 */
} acmp_location_t;
/**
* @brief Acmp output config structure definition
*/
typedef struct {
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
acmp_location_t location; /**< The location of acmp I/0 pin */
} acmp_output_config_t;
/**
* @brief Acmp init structure definition
*/
typedef struct {
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */
acmp_pos_input_t pos_port; /**< Acmp positive port select */
acmp_neg_input_t neg_port; /**< Acmp negative port select */
acmp_inactval_t inactval; /**< Acmp inavtive output value */
acmp_edge_t edge; /** Select edges to set interrupt flag */
uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */
} acmp_init_t;
/**
* @brief ACMP Handle Structure definition
*/
typedef struct acmp_handle_s {
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */
void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */
} acmp_handle_t;
/**
* @}
*/
/** @defgroup ACMP_Public_Macros ACMP Public Macros
* @{
*/
#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
/**
* @}
*/
/** @defgroup ACMP_Private_Macros ACMP Private Macros
* @{
*/
#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \
((x) == ACMP1))
#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \
((x) == ACMP_IT_WARMUP))
#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \
((x) == ACMP_FLAG_WARMUP))
#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \
((x) == ACMP_STATUS_WARMUP))
#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD) || \
((x) == ACMP_NEG_CAP) || \
((x) == ACMP_NEG_DAC0_CH0) || \
((x) == ACMP_NEG_DAC0_CH1))
#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \
((x) == ACMP_INACTVAL_HIGH))
#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \
((x) == ACMP_OUT_ENABLE))
#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \
((x) == ACMP_GPIO_INV))
#define IS_ACMP_LOCATION_TYPE(x) (((x) == ACMP_LOCATION_O) || \
((x) == ACMP_LOCATION_1) || \
((x) == ACMP_LOCATION_2))
#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \
((x) == ACMP_WARM_ENABLE))
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions
* @{
*/
/** @addtogroup ACMP_Public_Functions_Group1
* @{
*/
ald_status_t acmp_init(acmp_handle_t *hperh);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group2
* @{
*/
ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it);
it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group3
* @{
*/
void acmp_irq_handle(acmp_handle_t *hperh);
ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config);
uint8_t acmp_out_result(acmp_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
extern "C" }
#endif
#endif

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h
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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
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/**
*********************************************************************************
*
* @file ald_bkpc.h
* @brief Header file of BKPC module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_BKPC_H__
#define __ALD_BKPC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup BKPC
* @{
*/
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup BKPC_Public_Types BKPC Public Types
* @{
*/
/**
* @brief BKPC ldo output select
*/
typedef enum {
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
*/
typedef enum {
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
/**
* @}
*/
/**
* @defgroup BKPC_Private_Macros BKPC Private Macros
* @{
*/
#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions
* @{
*/
/** @addtogroup BKPC_Public_Functions_Group1
* @{
*/
/* control functions */
extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions_Group2
* @{
*/
/* IO operation functions */
extern void bkpc_write_ram(uint8_t idx, uint32_t value);
extern uint32_t bkpc_read_ram(uint8_t idx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_BKPC_H__ */

615
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h
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191
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h
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/**
*********************************************************************************
*
* @file ald_crc.h
* @brief Header file of CRC module driver.
*
* @version V1.0
* @date 6 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRC_H__
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Public_Types CRC Public Types
* @{
*/
/**
* @brief CRC mode
*/
typedef enum {
CRC_MODE_CCITT = 0, /**< Ccitt */
CRC_MODE_8 = 1, /**< Crc8 */
CRC_MODE_16 = 2, /**< Crc16 */
CRC_MODE_32 = 3, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum {
CRC_LEN_AUTO = 0, /**< Auto */
CRC_DATASIZE_8 = 1, /**< Byte */
CRC_DATASIZE_16 = 2, /**< Half word */
CRC_DATASIZE_32 = 3, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum {
CRC_WERR_NO = 0, /**< No error */
CRC_WERR_ERR = 1, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum {
CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct {
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
} crc_init_t;
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s {
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
#ifdef ALD_DMA
dma_handle_t hdma; /**< CRC DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
} crc_handle_t;
/**
* @}
*/
/** @defgroup CRC_Public_Macros CRC Public Macros
* @{
*/
#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
/**
* @}
*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_CRC(x) ((x) == CRC)
#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
/**
* @}
*/
/** @addtogroup CRC_Public_Functions
* @{
*/
/** @addtogroup CRC_Public_Functions_Group1
* @{
*/
ald_status_t crc_init(crc_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRC_Public_Functions_Group2
* @{
*/
uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
/**
* @}
*/
#ifdef ALD_DMA
/** @addtogroup CRC_Public_Functions_Group3
* @{
*/
ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t crc_dma_pause(crc_handle_t *hperh);
ald_status_t crc_dma_resume(crc_handle_t *hperh);
ald_status_t crc_dma_stop(crc_handle_t *hperh);
/**
* @}
*/
#endif
/** @addtogroup CRC_Public_Functions_Group4
* @{
*/
crc_state_t crc_get_state(crc_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CRC_H__ */

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/**
*********************************************************************************
*
* @file ald_crypt.h
* @brief Header file of CRYPT module driver.
*
* @version V1.0
* @date 7 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRYPT_H__
#define __ALD_CRYPT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRYPT
* @{
*/
/** @defgroup CRYPT_Public_Types CRYPT Public Types
* @{
*/
/**
* @brief CRYPT encrypt or decrypt select
*/
typedef enum {
CRYPT_DECRYPT = 0, /**< Decrypt */
CRYPT_ENCRYPT = 1, /**< Encrypt */
} crypt_encs_t;
/**
* @brief CRYPT mode select
*/
typedef enum {
CRYPT_MODE_ECB = 0, /**< ECB */
CRYPT_MODE_CBC = 1, /**< CBC */
CRYPT_MODE_CTR = 2, /**< CTR */
} crypt_mode_t;
/**
* @brief CRYPT data type
*/
typedef enum {
CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */
} crypt_datatype_t;
/**
* @brief CRYPT interrupt
*/
typedef enum {
CRYPT_IT_IT = 0x80, /**< Interrupt */
} crypt_it_t;
/**
* @brief CRYPT interrupt flag
*/
typedef enum {
CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100, /**< Complete flag */
} crypt_flag_t;
/**
* @brief CRYPT state structures definition
*/
typedef enum {
CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4, /**< Error */
} crypt_state_t;
/**
* @brief CRYPT data type
*/
typedef enum {
DATA_32_BIT = 0, /**< 32 bit data,don't swap */
DATA_16_BIT = 1, /**< 16 bit data,swap */
DATA_8_BIT = 2, /**< 8 bit data,swap */
DATA_1_BIT = 3, /**< 1 bit data, swap */
} crypt_data_t;
/**
* @brief CRYPT init structure definition
*/
typedef struct {
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
} crypt_init_t;
/**
* @brief CRYPT Handle Structure definition
*/
typedef struct crypt_handle_s {
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
#ifdef ALD_DMA
dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */
dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */
#endif
uint8_t *plain_text; /**< Pointer to plain text */
uint8_t *cipher_text; /**< Pointer to cipher text */
uint32_t size; /**< The size of crypt data buf */
uint32_t count; /**< The count of crypt data buf */
uint32_t step; /**< The step of once crypt 4(aes) */
uint32_t dir; /**< ENCRYPT or DECRYPT */
uint32_t iv[4]; /**< The iv of crypt */
uint32_t key[4]; /**< The key of crypt */
lock_state_t lock; /**< Locking object */
crypt_state_t state; /**< CRYPT operation state */
void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */
void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */
} crypt_handle_t;
/**
* @}
*/
/** @defgroup CRYPT_Public_Macros CRYPT Public Macros
* @{
*/
#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
/**
* @}
*/
/** @defgroup CRYPT_Private_Macros CRYPT Private Macros
* @{
*/
#define IS_CRYPT(x) ((x) == CRYPT)
#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \
((x) == CRYPT_FLAG_DONE))
#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \
((x) == IV_4_LEN))
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions
* @{
*/
/** @addtogroup CRYPT_Public_Functions_Group1
* @{
*/
ald_status_t crypt_init(crypt_handle_t *hperh);
ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv);
ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group2
* @{
*/
ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
#ifdef ALD_DMA
ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
#endif
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group3
* @{
*/
#ifdef ALD_DMA
ald_status_t crypt_dma_pause(crypt_handle_t *hperh);
ald_status_t crypt_dma_resume(crypt_handle_t *hperh);
ald_status_t crypt_dma_stop(crypt_handle_t *hperh);
#endif
void crypt_irq_handle(crypt_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group4
* @{
*/
void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group5
* @{
*/
crypt_state_t crypt_get_state(crypt_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h
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/**
*********************************************************************************
*
* @file ald_dbgc.h
* @brief DEBUGCON module driver.
*
* @version V1.0
* @date 04 Jun 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_DBGC_H__
#define __ALD_DBGC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup DBGC DBGC
* @brief DBGC module driver
* @{
*/
/** @defgroup DBGC_Public_Types DBGC Public Types
* @{
*/
/**
* @brief Debug mode select
*/
typedef enum {
DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */
} dbgc_mode_t;
/**
* @brief Debug peripheral select
*/
typedef enum {
DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1u << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */
DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */
DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */
} dbgc_perh_t;
/**
* @}
*/
/** @defgroup DBGC_Public_Functions DBGC Public Functions
* @{
*/
/**
* @brief Gets version.
* @retval Version
*/
__INLINE uint32_t dbgc_get_rev_id(void)
{
return (DBGC->IDCODE >> 16);
}
/**
* @brief Gets core id.
* @retval Core id
*/
__INLINE uint32_t dbgc_get_core_id(void)
{
return (DBGC->IDCODE >> 12) & 0xF;
}
/**
* @brief Gets device id
* @retval device id
*/
__INLINE uint32_t dbgc_get_device_id(void)
{
return DBGC->IDCODE & 0xFFF;
}
/**
* @brief Configures low power debug mode
* @param mode: The mode of low power.
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
{
if (state)
SET_BIT(DBGC->CR, mode);
else
CLEAR_BIT(DBGC->CR, mode);
}
/**
* @brief Configures peripheral debug mode
* @param perh: The peripheral.
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
{
if ((perh >> 16) & 0x1) {
if (state)
SET_BIT(DBGC->APB2FZ, perh);
else
CLEAR_BIT(DBGC->APB2FZ, perh);
}
else {
if (state)
SET_BIT(DBGC->APB1FZ, perh);
else
CLEAR_BIT(DBGC->APB1FZ, perh);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h
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/**
*********************************************************************************
*
* @file ald_dma.h
* @brief DMA module Library.
*
* @version V1.0
* @date 09 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_DMA_H__
#define __ALD_DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup DMA
* @{
*/
/**
* @defgroup DMA_Public_Macros DMA Public Macros
* @{
*/
#define DMA_CH_COUNT 6
#define DMA_ERR 31
/**
* @}
*/
/**
* @defgroup DMA_Public_Types DMA Public Types
* @{
*/
/**
* @brief Input source to DMA channel
*/
typedef enum {
DMA_MSEL_NONE = 0x0, /**< NONE */
DMA_MSEL_GPIO = 0x1, /**< GPIO */
DMA_MSEL_CRYPT = 0x2, /**< CRYPT */
DMA_MSEL_ACMP = 0x3, /**< ACMP */
DMA_MSEL_DAC0 = 0x4, /**< DAC0 */
DMA_MSEL_ADC0 = 0x6, /**< ADC0 */
DMA_MSEL_CRC = 0x7, /**< CRC */
DMA_MSEL_UART0 = 0x8, /**< UART0 */
DMA_MSEL_UART1 = 0x9, /**< UART1 */
DMA_MSEL_UART2 = 0xA, /**< UART2 */
DMA_MSEL_UART3 = 0xB, /**< UART3 */
DMA_MSEL_USART0 = 0xC, /**< USART0 */
DMA_MSEL_USART1 = 0xD, /**< USART1 */
DMA_MSEL_SPI0 = 0xE, /**< SPI0 */
DMA_MSEL_SPI1 = 0xF, /**< SPI1 */
DMA_MSEL_I2C0 = 0x10, /**< I2C0 */
DMA_MSEL_I2C1 = 0x11, /**< I2C1 */
DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */
DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */
DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */
DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */
DMA_MSEL_RTC = 0x16, /**< RTC */
DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */
DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */
DMA_MSEL_DMA = 0x19, /**< DMA */
DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */
DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */
DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */
DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */
DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */
DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */
DMA_MSEL_PIS = 0x20, /**< PIS */
DMA_MSEL_TRNG = 0x21, /**< TRNG */
} dma_msel_t;
/**
* @brief Input signal to DMA channel
*/
typedef enum {
DMA_MSIGSEL_NONE = 0x0, /**< NONE */
DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */
DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */
DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */
DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */
DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */
DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */
DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */
DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */
DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */
DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */
DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */
DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */
DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */
DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */
DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */
DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */
DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */
DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */
DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */
DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */
DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */
DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */
DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */
DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */
DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */
DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */
DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */
DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */
DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */
DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */
DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */
DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */
DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */
DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */
DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */
DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */
DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */
DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */
DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */
DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */
DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */
DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */
DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */
DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */
DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */
DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */
DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */
DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */
DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */
DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */
DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */
DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */
DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */
DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */
DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */
DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */
} dma_msigsel_t;
/**
* @brief DMA Descriptor control type
*/
typedef union {
struct {
uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */
uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */
uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */
uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */
uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */
uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */
uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */
uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */
uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */
};
uint32_t word;
} dma_ctrl_t;
/**
* @brief Channel control data structure
*/
typedef struct {
void *src; /**< Source data end pointer */
void *dst; /**< Destination data end pointer */
dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */
uint32_t use; /**< Reserve for user */
} dma_descriptor_t;
/**
* @brief data increment
*/
typedef enum {
DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */
DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */
DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */
DMA_DATA_INC_NONE = 0x3, /**< No increment */
} dma_data_inc_t;
/**
* @brief Data size
*/
typedef enum {
DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */
DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */
DMA_DATA_SIZE_WORD = 0x2, /**< Word */
} dma_data_size_t;
/**
* @brief The operating mode of the DMA cycle
*/
typedef enum {
DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */
DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */
DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */
DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */
DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */
DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */
} dma_cycle_ctrl_t;
/**
* @brief Control how many DMA transfers can occur
* before the controller re-arbitrates
*/
typedef enum {
DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */
DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */
DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */
DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */
DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */
DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */
DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */
DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */
DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */
DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */
DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */
} dma_arbiter_config_t;
/**
* @brief Callback function pointer and param
*/
typedef struct {
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void* arg); /**< DMA occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_call_back_t;
/**
* @brief DMA channal configure structure
*/
typedef struct {
void *src; /**< Source data begin pointer */
void *dst; /**< Destination data begin pointer */
uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */
dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */
dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */
dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */
dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
type_func_t primary; /**< Use primary descriptor or alternate descriptor */
type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */
type_func_t high_prio; /**< High priority or default priority */
type_func_t iterrupt; /**< Enable/disable interrupt */
dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */
dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */
uint8_t channel; /**< Channel index */
} dma_config_t;
/**
* @brief DMA handle structure definition
*/
typedef struct {
DMA_TypeDef *perh; /**< DMA registers base address */
dma_config_t config; /**< Channel configure structure. @ref dma_config_t */
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_handle_t;
/**
* @}
*/
/**
* @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG)
#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \
((x) == DMA_DATA_INC_HALFWORD) || \
((x) == DMA_DATA_INC_WORD) || \
((x) == DMA_DATA_INC_NONE))
#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \
((x) == DMA_DATA_SIZE_HALFWORD) || \
((x) == DMA_DATA_SIZE_WORD))
#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \
((x) == DMA_CYCLE_CTRL_BASIC) || \
((x) == DMA_CYCLE_CTRL_AUTO) || \
((x) == DMA_CYCLE_CTRL_PINGPONG) || \
((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \
((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER))
#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \
((x) == DMA_R_POWER_2) || \
((x) == DMA_R_POWER_4) || \
((x) == DMA_R_POWER_8) || \
((x) == DMA_R_POWER_16) || \
((x) == DMA_R_POWER_32) || \
((x) == DMA_R_POWER_64) || \
((x) == DMA_R_POWER_128) || \
((x) == DMA_R_POWER_256) || \
((x) == DMA_R_POWER_512) || \
((x) == DMA_R_POWER_1024))
#define IS_DMA(x) ((x) == DMA0)
#define IS_DMA_CHANNEL(x) ((x) <= 5)
#define IS_DMA_DATA_SIZE(x) ((x) <= 1024)
#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31))
/**
* @}
*/
/**
* @addtogroup DMA_Public_Functions
* @{
*/
/** @addtogroup DMA_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void dma_reset(DMA_TypeDef *DMAx);
extern void dma_init(DMA_TypeDef *DMAx);
extern void dma_config_struct(dma_config_t *p);
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group2
* @{
*/
/* Configure DMA channel functions */
extern void dma_config_auto(dma_handle_t *hperh);
extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
uint16_t size, uint8_t channel, void (*cbk)(void *arg));
extern void dma_config_basic(dma_handle_t *hperh);
extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group3
* @{
*/
/* DMA control functions */
extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
void dma0_irq_cbk(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__ALD_DMA_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h
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/**
*********************************************************************************
*
* @file ald_gpio.h
* @brief Header file of GPIO module driver
*
* @version V1.0
* @date 07 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_GPIO_H__
#define __ALD_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup GPIO
* @{
*/
/**
* @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
#define GPIO_PIN_0 (1U << 0)
#define GPIO_PIN_1 (1U << 1)
#define GPIO_PIN_2 (1U << 2)
#define GPIO_PIN_3 (1U << 3)
#define GPIO_PIN_4 (1U << 4)
#define GPIO_PIN_5 (1U << 5)
#define GPIO_PIN_6 (1U << 6)
#define GPIO_PIN_7 (1U << 7)
#define GPIO_PIN_8 (1U << 8)
#define GPIO_PIN_9 (1U << 9)
#define GPIO_PIN_10 (1U << 10)
#define GPIO_PIN_11 (1U << 11)
#define GPIO_PIN_12 (1U << 12)
#define GPIO_PIN_13 (1U << 13)
#define GPIO_PIN_14 (1U << 14)
#define GPIO_PIN_15 (1U << 15)
#define GPIO_PIN_ALL (0xFFFF)
/**
* @}
*/
/**
* @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @brief GPIO mode
*/
typedef enum {
GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1, /**< Input */
GPIO_MODE_OUTPUT = 0x2, /**< Output */
} gpio_mode_t;
/**
* @brief GPIO open-drain or push-pull
*/
typedef enum {
GPIO_PUSH_PULL = 0x0, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */
GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */
} gpio_odos_t;
/**
* @brief GPIO push-up or push-down
*/
typedef enum {
GPIO_FLOATING = 0x0,/**< Floating */
GPIO_PUSH_UP = 0x1,/**< Push-Up */
GPIO_PUSH_DOWN = 0x2,/**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
} gpio_push_t;
/**
* @brief GPIO output drive
*/
typedef enum {
GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */
} gpio_out_drive_t;
/**
* @brief GPIO filter
*/
typedef enum {
GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */
} gpio_filter_t;
/**
* @brief GPIO type
*/
typedef enum {
GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1, /**< TTL Type */
} gpio_type_t;
/**
* @brief GPIO functions
*/
typedef enum {
GPIO_FUNC_0 = 0, /**< function #0 */
GPIO_FUNC_1 = 1, /**< function #1 */
GPIO_FUNC_2 = 2, /**< function #2 */
GPIO_FUNC_3 = 3, /**< function #3 */
GPIO_FUNC_4 = 4, /**< function #4 */
GPIO_FUNC_5 = 5, /**< function #5 */
GPIO_FUNC_6 = 6, /**< function #6 */
GPIO_FUNC_7 = 7, /**< function #7 */
} gpio_func_t;
/**
* @brief GPIO Init Structure definition
*/
typedef struct {
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
This parameter can be any value of @ref gpio_mode_t */
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
This parameter can be a value of @ref gpio_odos_t */
gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins.
This parameter can be a value of @ref gpio_push_t */
gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins.
This parameter can be a value of @ref gpio_out_drive_t */
gpio_filter_t flt; /**< Specifies the input filter for the selected pins.
This parameter can be a value of @ref gpio_filter_t */
gpio_type_t type; /**< Specifies the type for the selected pins.
This parameter can be a value of @ref gpio_type_t */
gpio_func_t func; /**< Specifies the function for the selected pins.
This parameter can be a value of @ref gpio_func_t */
} gpio_init_t;
/**
* @brief EXTI trigger style
*/
typedef enum {
EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */
} exti_trigger_style_t;
/**
* @brief EXTI filter clock select
*/
typedef enum {
EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */
} exti_filter_clock_t;
/**
* @brief EXTI Init Structure definition
*/
typedef struct {
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
} exti_init_t;
/**
* @}
*/
/**
* @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define PIN_MASK 0xFFFF
#define UNLOCK_KEY 0x55AA
#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))
#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \
((x) == GPIO_OUT_DRIVE_STRONG))
#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \
((x) == GPIO_FILTER_ENABLE))
#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \
((x) == GPIO_TYPE_CMOS))
#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \
((x) == EXTI_FILTER_CLOCK_32K))
#define IS_GPIO_FUNC(x) ((x) <= 7)
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions
* @{
*/
/** @addtogroup GPIO_Public_Functions_Group1
* @{
*/
void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_func_default(GPIO_TypeDef *GPIOx);
void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group2
* @{
*/
uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
uint16_t gpio_read_port(GPIO_TypeDef *GPIOx);
void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group3
* @{
*/
void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
flag_status_t gpio_exti_get_flag_status(uint16_t pin);
void gpio_exti_clear_flag_status(uint16_t pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_GPIO_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h
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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h
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/**
*********************************************************************************
*
* @file ald_lcd.h
* @brief Header file of LCD module driver.
*
* @version V1.0
* @date 29 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_LCD_H__
#define __ALD_LCD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LCD
* @{
*/
/** @defgroup LCD_Public_Types LCD Public Types
* @{
*/
/**
* @brief Lcd vlcd voltage type
*/
typedef enum {
LCD_VCHPS_3V2 = 0, /**< 3.2V */
LCD_VCHPS_3V8 = 1, /**< 3.8V */
LCD_VCHPS_4V8 = 2, /**< 4.8V */
LCD_VCHPS_5V4 = 3, /**< 5.4V */
} lcd_vchps_t;
/**
* @brief Lcd function type
*/
typedef enum {
LCD_FUNC_DISABLE = 0, /**< Lcd's function disable */
LCD_FUNC_ENABLE = 1, /**< Lcd's function enable */
} lcd_func_t;
/**
* @brief Lcd voltage type
*/
typedef enum {
LCD_VSEL_VDD = 0, /**< VDD */
LCD_VSEL_CP = 1, /**< Charge pump output */
LCD_VSEL_VLCD = 2, /**< VLCD input */
} lcd_vsel_t;
/**
* @brief Lcd resistance select bit
*/
typedef enum {
LCD_RES_1MOHM = 0, /**< 1M ohm */
LCD_RES_2MOHM = 1, /**< 2M ohm */
LCD_RES_3MOHM = 2, /**< 3M ohm */
} lcd_res_t;
/**
* @brief Lcd bias selector
*/
typedef enum {
LCD_BIAS_1_4 = 0, /**< 1/4 bias */
LCD_BIAS_1_2 = 2, /**< 1/2 bias */
LCD_BIAS_1_3 = 3, /**< 1/3 bias */
} lcd_bias_t;
/**
* @brief Lcd duty
*/
typedef enum {
LCD_DUTY_STATIC = 0, /**< Static duty (COM0) */
LCD_DUTY_1_2 = 1, /**< 1/2 duty (COM0~COM1) */
LCD_DUTY_1_3 = 2, /**< 1/3 duty (COM0~COM2) */
LCD_DUTY_1_4 = 3, /**< 1/4 duty (COM0~COM3) */
LCD_DUTY_1_6 = 4, /**< 1/6 duty (COM0~COM5) */
LCD_DUTY_1_8 = 5, /**< 1/8 duty (COM0~COM7) */
} lcd_duty_t;
/**
* @brief Lcd prescaler
*/
typedef enum {
LCD_PRS_1 = 0, /**< CLKPRS = LCDCLK / 1 */
LCD_PRS_2 = 1, /**< CLKPRS = LCDCLK / 2 */
LCD_PRS_4 = 2, /**< CLKPRS = LCDCLK / 4 */
LCD_PRS_8 = 3, /**< CLKPRS = LCDCLK / 8 */
LCD_PRS_16 = 4, /**< CLKPRS = LCDCLK / 16 */
LCD_PRS_32 = 5, /**< CLKPRS = LCDCLK / 32 */
LCD_PRS_64 = 6, /**< CLKPRS = LCDCLK / 64 */
LCD_PRS_128 = 7, /**< CLKPRS = LCDCLK / 128 */
LCD_PRS_256 = 8, /**< CLKPRS = LCDCLK / 256 */
LCD_PRS_512 = 9, /**< CLKPRS = LCDCLK / 512 */
LCD_PRS_1024 = 10, /**< CLKPRS = LCDCLK / 1024 */
LCD_PRS_2048 = 11, /**< CLKPRS = LCDCLK / 2048 */
LCD_PRS_4096 = 12, /**< CLKPRS = LCDCLK / 4096 */
LCD_PRS_8192 = 13, /**< CLKPRS = LCDCLK / 8192 */
LCD_PRS_16384 = 14, /**< CLKPRS = LCDCLK / 16384 */
LCD_PRS_32768 = 15, /**< CLKPRS = LCDCLK / 32768 */
} lcd_prs_t;
/**
* @brief Lcd divider
*/
typedef enum {
LCD_DIV_16 = 0, /**< DIVCLK = CLKPRS / 16 */
LCD_DIV_17 = 1, /**< DIVCLK = CLKPRS / 17 */
LCD_DIV_18 = 2, /**< DIVCLK = CLKPRS / 18 */
LCD_DIV_19 = 3, /**< DIVCLK = CLKPRS / 19 */
LCD_DIV_20 = 4, /**< DIVCLK = CLKPRS / 20 */
LCD_DIV_21 = 5, /**< DIVCLK = CLKPRS / 21 */
LCD_DIV_22 = 6, /**< DIVCLK = CLKPRS / 22 */
LCD_DIV_23 = 7, /**< DIVCLK = CLKPRS / 23 */
LCD_DIV_24 = 8, /**< DIVCLK = CLKPRS / 24 */
LCD_DIV_25 = 9, /**< DIVCLK = CLKPRS / 25 */
LCD_DIV_26 = 10, /**< DIVCLK = CLKPRS / 26 */
LCD_DIV_27 = 11, /**< DIVCLK = CLKPRS / 27 */
LCD_DIV_28 = 12, /**< DIVCLK = CLKPRS / 28 */
LCD_DIV_29 = 13, /**< DIVCLK = CLKPRS / 29 */
LCD_DIV_30 = 14, /**< DIVCLK = CLKPRS / 30 */
LCD_DIV_31 = 15, /**< DIVCLK = CLKPRS / 31 */
} lcd_div_t;
/**
* @brief Lcd blink mode
*/
typedef enum {
LCD_BLINK_OFF = 0, /**< Blink disabled */
LCD_BLINK_SEG0_COM0 = 1, /**< Blink enabled on SEG0, COM0 */
LCD_BLINK_SEG0_COMX2 = 2, /**< Blink enabled on SEG0, COMx2 */
LCD_BLINK_ALLSEG_ALLCOM = 3, /**< Blink enabled on all SEG and all COM */
} lcd_blink_t;
/**
* @brief Lcd blink frequency
*/
typedef enum {
LCD_BLFRQ_8 = 0, /**< DIVCLK / 8 */
LCD_BLFRQ_16 = 1, /**< DIVCLK / 16 */
LCD_BLFRQ_32 = 2, /**< DIVCLK / 32 */
LCD_BLFRQ_64 = 3, /**< DIVCLK / 64 */
LCD_BLFRQ_128 = 4, /**< DIVCLK / 128 */
LCD_BLFRQ_256 = 5, /**< DIVCLK / 256 */
LCD_BLFRQ_512 = 6, /**< DIVCLK / 512 */
LCD_BLFRQ_1024 = 7, /**< DIVCLK / 1024 */
} lcd_blfrq_t;
/**
* @brief Lcd dead time
*/
typedef enum {
LCD_DEAD_TIME_NONE = 0, /**< No dead time */
LCD_DEAD_TIME_1_DIVCLK = 1, /**< Dead time is 1 divclk */
LCD_DEAD_TIME_2_DIVCLK = 2, /**< Dead time is 2 divclk */
LCD_DEAD_TIME_3_DIVCLK = 3, /**< Dead time is 3 divclk */
LCD_DEAD_TIME_4_DIVCLK = 4, /**< Dead time is 4 divclk */
LCD_DEAD_TIME_5_DIVCLK = 5, /**< Dead time is 5 divclk */
LCD_DEAD_TIME_6_DIVCLK = 6, /**< Dead time is 6 divclk */
LCD_DEAD_TIME_7_DIVCLK = 7, /**< Dead time is 7 divclk */
} lcd_dead_t;
/**
* @brief Lcd pulse keep time
*/
typedef enum {
LCD_PON_NONE = 0, /**< No pulse keep time */
LCD_PON_1_PRSCLK = 1, /**< Pulse keep 1 prsclk */
LCD_PON_2_PRSCLK = 2, /**< Pulse keep 2 prsclk */
LCD_PON_3_PRSCLK = 3, /**< Pulse keep 3 prsclk */
LCD_PON_4_PRSCLK = 4, /**< Pulse keep 4 prsclk */
LCD_PON_5_PRSCLK = 5, /**< Pulse keep 5 prsclk */
LCD_PON_6_PRSCLK = 6, /**< Pulse keep 6 prsclk */
LCD_PON_7_PRSCLK = 7, /**< Pulse keep 7 prsclk */
} lcd_pluse_on_t;
/**
* @brief Lcd vgs select
*/
typedef enum {
LCD_VGS_0 = 0, /**< Grey level display voltage is 30/45 vlcd */
LCD_VGS_1 = 1, /**< Grey level display voltage is 31/45 vlcd */
LCD_VGS_2 = 2, /**< Grey level display voltage is 32/45 vlcd */
LCD_VGS_3 = 3, /**< Grey level display voltage is 33/45 vlcd */
LCD_VGS_4 = 4, /**< Grey level display voltage is 34/45 vlcd */
LCD_VGS_5 = 5, /**< Grey level display voltage is 35/45 vlcd */
LCD_VGS_6 = 6, /**< Grey level display voltage is 36/45 vlcd */
LCD_VGS_7 = 7, /**< Grey level display voltage is 37/45 vlcd */
LCD_VGS_8 = 8, /**< Grey level display voltage is 38/45 vlcd */
LCD_VGS_9 = 9, /**< Grey level display voltage is 39/45 vlcd */
LCD_VGS_10 = 10, /**< Grey level display voltage is 40/45 vlcd */
LCD_VGS_11 = 11, /**< Grey level display voltage is 41/45 vlcd */
LCD_VGS_12 = 12, /**< Grey level display voltage is 42/45 vlcd */
LCD_VGS_13 = 13, /**< Grey level display voltage is 43/45 vlcd */
LCD_VGS_14 = 14, /**< Grey level display voltage is 44/45 vlcd */
LCD_VGS_15 = 15, /**< Grey level display voltage is equal to vlcd */
} lcd_vgs_t;
/**
* @brief Lcd wave choose
*/
typedef enum {
LCD_WAVE_A = 0, /**< Wave type is A */
LCD_WAVE_B = 1, /**< Wave type is B */
} lcd_wfs_t;
/**
* @brief Lcd status select bit
*/
typedef enum {
LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */
LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/
LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */
LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */
LCD_STATUS_ALL = 0xFFFFFFF, /**< All flag */
} lcd_status_t;
/**
* @brief Lcd interrupt type
*/
typedef enum {
LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */
LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/
} lcd_it_t;
/**
* @brief Lcd interrupt flag
*/
typedef enum {
LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
} lcd_flag_t;
/**
* @brief Lcd interrupt type
*/
typedef enum {
SEG_0_TO_31 = 0, /**< Segment 0 to 31 to be set */
SEG_32_TO_59 = 1, /**< Segment 32 to 59 to be set */
} lcd_seg_t;
/**
* @brief Lcd configure
*/
typedef struct
{
lcd_vsel_t lcd_vsel; /**< Lcd power choose */
lcd_vchps_t lcd_vchps; /**< Charge pump voltage choose */
lcd_func_t lcd_vbufld; /**< Low drive mode function */
lcd_func_t lcd_vbufhd; /**< High drive mode function */
uint32_t lcd_dsld; /**< Low drive mode level */
uint32_t lcd_dshd; /**< High drive mode level */
lcd_res_t lcd_resld; /**< Low dirve mode resistance choose */
lcd_res_t lcd_reshd; /**< High dirve mode resistance choose */
lcd_bias_t lcd_bias; /**< LCD bias */
lcd_duty_t lcd_duty; /**< LCD duty */
lcd_wfs_t lcd_wfs; /**< Wave choose */
lcd_prs_t lcd_prs; /**< Lcd clock prs */
lcd_div_t lcd_div; /**< Lcd div */
lcd_dead_t lcd_dead; /**< Lcd dead time */
lcd_pluse_on_t lcd_pon; /**< Lcd pluse on time */
lcd_vgs_t lcd_vgs; /**< Lcd gray level display voltage */
cmu_lcd_clock_sel_t clock; /**< Lcd clock choose */
} lcd_init_t;
/**
* @brief Lcd handle Structure definition
*/
typedef struct lcd_handle_s {
LCD_TypeDef *perh; /**< LCD registers base address */
lcd_init_t init; /**< LCD initialize parameters */
lock_state_t lock; /**< Locking object */
void (*display_cplt_cbk)(struct lcd_handle_s *arg); /**< Display completed callback */
void (*frame_start_cbk)(struct lcd_handle_s *arg); /**< Frame start callback */
} lcd_handle_t;
/**
* @}
*/
/** @defgroup LCD_Public_Macro LCD Public Macros
* @{
*/
#define LCD_HD_ENABLE(x) (SET_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
#define LCD_HD_DISABLE(x) (CLEAR_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
/**
* @}
*/
/**
* @defgroup LCD_Private_Macros LCD Private Macros
* @{
*/
#define IS_LCD_PERH_TYPE(x) ((x) == LCD)
#define IS_LCD_VCHPS_TYPE(x) (((x) == LCD_VCHPS_3V2) || \
((x) == LCD_VCHPS_3V8) || \
((x) == LCD_VCHPS_4V8) || \
((x) == LCD_VCHPS_5V4))
#define IS_LCD_VSEL_TYPE(x) (((x) == LCD_VSEL_VDD) || \
((x) == LCD_VSEL_CP) || \
((x) == LCD_VSEL_VLCD))
#define IS_LCD_FUNC_TYPE(x) (((x) == LCD_FUNC_DISABLE) || \
((x) == LCD_FUNC_ENABLE))
#define IS_LCD_LEVEL_TYPE(x) (((x) > 0) | ((x) <= 0xF))
#define IS_LCD_RES_TYPE(x) (((x) == LCD_RES_1MOHM) || \
((x) == LCD_RES_2MOHM) || \
((x) == LCD_RES_3MOHM))
#define IS_LCD_BIAS_TYPE(x) (((x) == LCD_BIAS_1_4) || \
((x) == LCD_BIAS_1_2) || \
((x) == LCD_BIAS_1_3))
#define IS_LCD_DUTY_TYPE(x) (((x) == LCD_DUTY_STATIC) || \
((x) == LCD_DUTY_1_2) || \
((x) == LCD_DUTY_1_3) || \
((x) == LCD_DUTY_1_4) || \
((x) == LCD_DUTY_1_6) || \
((x) == LCD_DUTY_1_8))
#define IS_LCD_WFS_TYPE(x) (((x) == LCD_WAVE_A) || \
((x) == LCD_WAVE_B))
#define IS_LCD_PRS_TYPE(x) (((x) == LCD_PRS_1) || \
((x) == LCD_PRS_2) || \
((x) == LCD_PRS_4) || \
((x) == LCD_PRS_8) || \
((x) == LCD_PRS_16) || \
((x) == LCD_PRS_32) || \
((x) == LCD_PRS_64) || \
((x) == LCD_PRS_128) || \
((x) == LCD_PRS_256) || \
((x) == LCD_PRS_512) || \
((x) == LCD_PRS_1024) || \
((x) == LCD_PRS_2048) || \
((x) == LCD_PRS_4096) || \
((x) == LCD_PRS_8192) || \
((x) == LCD_PRS_16384) || \
((x) == LCD_PRS_32768))
#define IS_LCD_DIV_TYPE(x) (((x) == LCD_DIV_16) || \
((x) == LCD_DIV_17) || \
((x) == LCD_DIV_18) || \
((x) == LCD_DIV_19) || \
((x) == LCD_DIV_20) || \
((x) == LCD_DIV_21) || \
((x) == LCD_DIV_22) || \
((x) == LCD_DIV_23) || \
((x) == LCD_DIV_24) || \
((x) == LCD_DIV_25) || \
((x) == LCD_DIV_26) || \
((x) == LCD_DIV_27) || \
((x) == LCD_DIV_28) || \
((x) == LCD_DIV_29) || \
((x) == LCD_DIV_30) || \
((x) == LCD_DIV_31))
#define IS_LCD_BLINK_MODE(x) (((x) == LCD_BLINK_OFF) || \
((x) == LCD_BLINK_SEG0_COM0) || \
((x) == LCD_BLINK_SEG0_COMX2) || \
((x) == LCD_BLINK_ALLSEG_ALLCOM))
#define IS_LCD_BLFRQ_TYPE(x) (((x) == LCD_BLFRQ_8) || \
((x) == LCD_BLFRQ_16) || \
((x) == LCD_BLFRQ_32) || \
((x) == LCD_BLFRQ_64) || \
((x) == LCD_BLFRQ_128) || \
((x) == LCD_BLFRQ_256) || \
((x) == LCD_BLFRQ_512) || \
((x) == LCD_BLFRQ_1024))
#define IS_LCD_STATUS_TYPE(x) (((x) == LCD_STATUS_RDY) || \
((x) == LCD_STATUS_ENS) || \
((x) == LCD_STATUS_UDR) || \
((x) == LCD_STATUS_FCRSF) || \
((x) == LCD_STATUS_ALL))
#define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \
((x) == LCD_FLAG_UDD) || \
((x) == LCD_STATUS_ALL))
#define IS_LCD_IT_TYPE(x) (((x) == LCD_IT_SOF) || \
((x) == LCD_IT_UDD))
#define IS_LCD_FLAG_TYPE(x) (((x) == LCD_FLAG_SOF) || \
((x) == LCD_FLAG_UDD))
#define IS_LCD_SEG_TYPE(x) (((x) == SEG_0_TO_31) || \
((x) == SEG_32_TO_59))
#define IS_LCD_DEAD_TYPE(x) (((x) == LCD_DEAD_TIME_NONE) || \
((x) == LCD_DEAD_TIME_1_DIVCLK) || \
((x) == LCD_DEAD_TIME_2_DIVCLK) || \
((x) == LCD_DEAD_TIME_3_DIVCLK) || \
((x) == LCD_DEAD_TIME_4_DIVCLK) || \
((x) == LCD_DEAD_TIME_5_DIVCLK) || \
((x) == LCD_DEAD_TIME_6_DIVCLK) || \
((x) == LCD_DEAD_TIME_7_DIVCLK))
#define IS_LCD_PON_TYPE(x) (((x) == LCD_PON_NONE) || \
((x) == LCD_PON_1_PRSCLK) || \
((x) == LCD_PON_2_PRSCLK) || \
((x) == LCD_PON_3_PRSCLK) || \
((x) == LCD_PON_4_PRSCLK) || \
((x) == LCD_PON_5_PRSCLK) || \
((x) == LCD_PON_6_PRSCLK) || \
((x) == LCD_PON_7_PRSCLK))
#define IS_LCD_VGS_TYPE(x) (((x) == LCD_VGS_0) || \
((x) == LCD_VGS_1) || \
((x) == LCD_VGS_2) || \
((x) == LCD_VGS_3) || \
((x) == LCD_VGS_4) || \
((x) == LCD_VGS_5) || \
((x) == LCD_VGS_6) || \
((x) == LCD_VGS_7) || \
((x) == LCD_VGS_8) || \
((x) == LCD_VGS_9) || \
((x) == LCD_VGS_10) || \
((x) == LCD_VGS_11) || \
((x) == LCD_VGS_12) || \
((x) == LCD_VGS_13) || \
((x) == LCD_VGS_14) || \
((x) == LCD_VGS_15))
#define IS_LCD_BUFFER_TYPE(x) ((x) <= 15)
/**
* @}
*/
/** @addtogroup LCD_Public_Functions
* @{
*/
/**
* @addtogroup LCD_Public_Functions_Group1
* @{
*/
/* Initialization and enable functions */
ald_status_t lcd_init(lcd_handle_t *hperh);
ald_status_t lcd_cmd(lcd_handle_t *hperh, type_func_t state);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group2
* @{
*/
/* Config output and blink function */
ald_status_t lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq);
ald_status_t lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data);
ald_status_t lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group3
* @{
*/
/* Query lcd status function */
uint32_t lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_flag);
/**
* @}
*/
/**
* @addtogroup LCD_Public_Functions_Group4
* @{
*/
/* Interrupt function */
ald_status_t lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state);
flag_status_t lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it);
it_status_t lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
ald_status_t lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
void lcd_irq_handler(lcd_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LCD_H__ */

358
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h
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@@ -1,358 +0,0 @@
/**
*********************************************************************************
*
* @file ald_lptim.c
* @brief LPTIM module driver.
* This is the common part of the LPTIM initialization
*
* @version V1.0
* @date 09 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_LPTIM_H__
#define __ALD_LPTIM_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LPTIM
* @{
*/
/** @defgroup LPTIM_Public_Types LPTIM Public Types
* @{
*/
/**
* @brief LPTIM clock select
*/
typedef enum {
LPTIM_CKSEL_INTERNAL = 0, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1, /**< Select external clock */
} lptim_cksel_t;
/**
* @brief LPTIM clock pol
*/
typedef enum {
LPTIM_CKPOL_RISING = 0, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1, /**< using falling edge */
} lptim_ckpol_t;
/**
* @brief LPTIM clock fliter
*/
typedef enum {
LPTIM_CKFLT_0 = 0, /**< not clock filter */
LPTIM_CKFLT_2 = 1, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3, /**< 8 cycle filter */
} lptim_ckflt_t;
/**
* @brief LPTIM trigger fliter
*/
typedef enum {
LPTIM_TRGFLT_0 = 0, /**< not clock filter */
LPTIM_TRGFLT_2 = 1, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3, /**< 8 cycle filter */
} lptim_trgflt_t;
/**
* @brief LPTIM prescaler
*/
typedef enum {
LPTIM_PRESC_1 = 0, /**< No prescaler is used */
LPTIM_PRESC_2 = 1, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7, /**< Clock is divided by 128 */
} lptim_presc_t;
/**
* @brief LPTIM trig select
*/
typedef enum {
LPTIM_TRIGSEL_EXT0 = 0, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7, /**< Trigger select external channel 7 */
} lptim_trigsel_t;
/**
* @brief LPTIM start mode select
*/
typedef enum {
LPTIM_MODE_SINGLE = 0, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1, /**< Start continuous mode */
} lptim_mode_t;
/**
* @brief LPTIM trig en
*/
typedef enum {
LPTIM_TRIGEN_SW = 0, /**< software trigger */
LPTIM_TRIGEN_RISING = 1, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3, /**< rising and falling edge trigger */
} lptim_trigen_t;
/**
* @brief LPTIM wave
*/
typedef enum {
LPTIM_WAVE_NONE = 0, /**< Output close */
LPTIM_WAVE_TOGGLE = 1, /**< Output toggle */
LPTIM_WAVE_PULSE = 2, /**< Output pulse */
LPTIM_WAVE_PWM = 3, /**< Output PWM */
} lptim_wave_t;
/**
* @brief LPTIM interrupt
*/
typedef enum {
LPTIM_IT_CMPMAT = 1, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4, /**< external trigger interrupt bit */
} lptim_it_t;
/**
* @brief LPTIM Interrupt flag
*/
typedef enum {
LPTIM_FLAG_CMPMAT = 1, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4, /**< Update interrupt flag */
} lptim_flag_t;
/**
* @brief LPTIM state structures definition
*/
typedef enum {
LPTIM_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04, /**< Reception process is ongoing */
} lptim_state_t;
/**
* @brief LPTIM Init Structure definition
*/
typedef struct {
lptim_presc_t psc; /**< Specifies the prescaler value */
uint16_t arr; /**< Specifies the update value */
uint16_t cmp; /**< Specifies the compare value */
cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */
lptim_mode_t mode; /**< Specifies the start mode */
} lptim_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct {
lptim_trigen_t mode; /**< Specifies the trigger mode */
lptim_trigsel_t sel; /**< Specifies the trigger source select */
} lptim_trigger_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct {
lptim_cksel_t sel; /**< Specifies the clock select */
lptim_ckpol_t polarity; /**< Specifies the clock polarity */
} lptim_clock_source_init_t;
/**
* @brief LPTIM Handle Structure definition
*/
typedef struct lptim_handle_s {
LPTIM_TypeDef *perh; /**< Register base address */
lptim_init_t init; /**< LPTIM Time required parameters */
lock_state_t lock; /**< Locking object */
lptim_state_t state; /**< LPTIM operation state */
void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */
void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */
void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */
} lptim_handle_t;
/**
* @}
*/
/** @defgroup LPTIM_Public_Macros LPTIM Public Macros
* @{
*/
#define LPTIM_ENABLE(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
#define LPTIM_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
#define LPTIM_CNTSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_CNTSTRT_MSK))
#define LPTIM_SNGSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_SNGSTRT_MSK))
#define LPTIM_UPDATE_ENABLE(x) (SET_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
#define LPTIM_UPDATE_DISABLE(x) (CLEAR_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
#define LPTIM_PRELOAD_IMM(x) (SET_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
#define LPTIM_PRELOAD_WAIT(x) (CLEAR_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
#define LPTIM_WAVEPOL_NORMAL(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 0 << LP16T_CON0_WAVE_POSS))
#define LPTIM_WAVEPOL_INVERSE(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 1 << LP16T_CON0_WAVE_POSS))
/**
* @}
*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
* @{
*/
#define IS_LPTIM(x) ((x) == LPTIM0)
#define IS_LPTIM_CKSEL(x) (((x) == LPTIM_CKSEL_INTERNAL) || \
((x) == LPTIM_CKSEL_EXTERNAL))
#define IS_LPTIM_CKPOL(x) (((x) == LPTIM_CKPOL_RISING) || \
((x) == LPTIM_CKPOL_FALLING))
#define IS_LPTIM_MODE(x) (((x) == LPTIM_MODE_SINGLE) || \
((x) == LPTIM_MODE_CONTINUOUS))
#define IS_LPTIM_CKFLT(x) (((x) == LPTIM_CKFLT_0) || \
((x) == LPTIM_CKFLT_2) || \
((x) == LPTIM_CKFLT_4) || \
((x) == LPTIM_CKFLT_8))
#define IS_LPTIM_TRGFLT(x) (((x) == LPTIM_TRGFLT_0) || \
((x) == LPTIM_TRGFLT_2) || \
((x) == LPTIM_TRGFLT_4) || \
((x) == LPTIM_TRGFLT_8))
#define IS_LPTIM_PRESC(x) (((x) == LPTIM_PRESC_1) || \
((x) == LPTIM_PRESC_2) || \
((x) == LPTIM_PRESC_4) || \
((x) == LPTIM_PRESC_8) || \
((x) == LPTIM_PRESC_16) || \
((x) == LPTIM_PRESC_32) || \
((x) == LPTIM_PRESC_64) || \
((x) == LPTIM_PRESC_128))
#define IS_LPTIM_TRIGSEL(x) (((x) == LPTIM_TRIGSEL_EXT0) || \
((x) == LPTIM_TRIGSEL_EXT1) || \
((x) == LPTIM_TRIGSEL_EXT2) || \
((x) == LPTIM_TRIGSEL_EXT3) || \
((x) == LPTIM_TRIGSEL_EXT4) || \
((x) == LPTIM_TRIGSEL_EXT5) || \
((x) == LPTIM_TRIGSEL_EXT6) || \
((x) == LPTIM_TRIGSEL_EXT7))
#define IS_LPTIM_TRIGEN(x) (((x) == LPTIM_TRIGEN_SW) || \
((x) == LPTIM_TRIGEN_RISING) || \
((x) == LPTIM_TRIGEN_FALLING) || \
((x) == LPTIM_TRIGEN_BOTH))
#define IS_LPTIM_IT(x) (((x) == LPTIM_IT_CMPMAT) || \
((x) == LPTIM_IT_ARRMAT) || \
((x) == LPTIM_IT_EXTTRIG))
#define IS_LPTIM_FLAG(x) (((x) == LPTIM_FLAG_CMPMAT) || \
((x) == LPTIM_FLAG_ARRMAT) || \
((x) == LPTIM_FLAG_EXTTRIG))
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions
* @{
*/
/** @addtogroup LPTIM_Public_Functions_Group1
* @{
*/
void lptim_reset(lptim_handle_t *hperh);
void lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config);
void lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config);
void lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt);
void lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group2
* @{
*/
ald_status_t lptim_toggle_init(lptim_handle_t *hperh);
void lptim_toggle_start(lptim_handle_t *hperh);
void lptim_toggle_stop(lptim_handle_t *hperh);
void lptim_toggle_start_by_it(lptim_handle_t *hperh);
void lptim_toggle_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
* @{
*/
ald_status_t lptim_pulse_init(lptim_handle_t *hperh);
void lptim_pulse_start(lptim_handle_t *hperh);
void lptim_pulse_stop(lptim_handle_t *hperh);
void lptim_pulse_start_by_it(lptim_handle_t *hperh);
void lptim_pulse_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group4
* @{
*/
ald_status_t lptim_pwm_init(lptim_handle_t *hperh);
void lptim_pwm_start(lptim_handle_t *hperh);
void lptim_pwm_stop(lptim_handle_t *hperh);
void lptim_pwm_start_by_it(lptim_handle_t *hperh);
void lptim_pwm_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group5
* @{
*/
void lptim_irq_handle(lptim_handle_t *hperh);
void lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state);
it_status_t lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it);
flag_status_t lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
void lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group6
* @{
*/
lptim_state_t lptim_get_state(lptim_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LPTIM_H__ */

468
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h
View File

@@ -1,468 +0,0 @@
/**
*********************************************************************************
*
* @file ald_lpuart.h
* @brief Header file of Low Power UART module library.
*
* @version V1.0
* @date 30 May 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_LPUART_H__
#define __ALD_LPUART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
#include "ald_cmu.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup LPUART
* @{
*/
/**
* @defgroup LPUART_Public_Macros LPUART Public Macros
* @{
*/
/**
* @defgroup LPUART_Public_Macros1 LPUART FIFO Reset
* @{
*/
#define LPUART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_TXRESET_MSK))
#define LPUART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_RXRESET_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros2 LPUART RS485 RX Enable
* @{
*/
#define LPUART_RS485_RX_DISABLE(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
#define LPUART_RS485_RX_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros4 LPUART LoopMode Enable
* @{
*/
#define LPUART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
#define LPUART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros5 LPUART IrDA TX Enable
* @{
*/
#define LPUART_IRTX_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
#define LPUART_IRTX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros6 LPUART IRWIDTH Enable
* @{
*/
#define LPUART_IRWIDTH_DISABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
#define LPUART_IRWIDTH_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros7 LPUART CTS/RTS Enable
* @{
*/
#define LPUART_CTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
#define LPUART_CTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
#define LPUART_RTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
#define LPUART_RTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros8 LPUART CTS/RTS Polarity
* @{
*/
#define LPUART_CTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
#define LPUART_CTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
#define LPUART_RTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
#define LPUART_RTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
/**
* @}
*/
/**
* @defgroup LPUART_Public_Macros10 LPUART Update Enable
* @{
*/
#define LPUART_UPDATE_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
#define LPUART_UPDATE_DISABLE(hperh) (SET_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup LPUART_Public_Types LPUART Public Types
* @{
*/
/**
* @brief LPUART Word Length
*/
typedef enum {
LPUART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4, /**< 9-bits */
} lpuart_word_length_t;
/**
* @brief LPUART Stop Bits
*/
typedef enum {
LPUART_STOP_BITS_1 = 0x0, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1, /**< 2-bits */
} lpuart_stop_bits_t;
/**
* @brief LPUART Parity
*/
typedef enum {
LPUART_PARITY_NONE = 0x0, /**< Not parity */
LPUART_PARITY_ODD = 0x1, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3, /**< Even parity */
} lpuart_parity_t;
/**
* @brief LPUART Mode
*/
typedef enum {
LPUART_MODE_UART = 0x0, /**< UART */
LPUART_MODE_IrDA = 0x2, /**< IrDA */
LPUART_MODE_RS485 = 0x3, /**< RS485 */
} lpuart_mode_t;
/**
* @brief LPUART Hardware Flow Control
*/
typedef enum {
LPUART_HW_FLOW_CTL_NONE = 0x0, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS */
} lpuart_hw_flow_ctl_t;
/**
* @brief ALD LPUART State
*/
typedef enum {
LPUART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPUART_STATE_ERROR = 0x04, /**< Error */
} lpuart_state_t;
/**
* @brief LPUART Error Codes
*/
typedef enum {
LPUART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
} lpuart_error_t;
/**
* @brief LPUART Init structure definition
*/
typedef struct {
uint32_t baud; /**< Specifies the lpuart communication baud rate */
lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
lpuart_parity_t parity; /**< Specifies the parity mode */
lpuart_mode_t mode; /**< Specifies uart mode */
lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */
} lpuart_init_t;
/**
* @brief LPUART handle structure definition
*/
typedef struct lpuart_handle_s {
LPUART_TypeDef *perh; /**< LPUART registers base address */
lpuart_init_t init; /**< LPUART communication parameters */
uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */
uint16_t tx_size; /**< LPUART Tx Transfer size */
uint16_t tx_count; /**< LPUART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */
uint16_t rx_size; /**< LPUART Rx Transfer size */
uint16_t rx_count; /**< LPUART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
lpuart_state_t state; /**< LPUART communication state */
lpuart_error_t err_code; /**< LPUART Error code */
void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */
} lpuart_handle_t;
/**
* @brief LPUART RS485 Configure Structure definition
*/
typedef struct {
type_func_t RS485_NMM; /**< Normal Point Mode */
type_func_t RS485_AAD; /**< Auto-Address Detect */
type_func_t RS485_AUD; /**< Auto-Direction Mode */
type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */
uint8_t RS485_ADDCMP; /**< Address for compare */
} lpuart_rs485_config_t;
/**
* @brief LPUART DMA Requests
*/
typedef enum {
LPUART_DMA_REQ_TX = 0x0, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1, /**< RX dma */
} lpuart_dma_req_t;
/**
* @brief LPUART RXFIFO size
*/
typedef enum {
LPUART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
} lpuart_rxfifo_t;
/**
* @brief LPUART Interrupts Types
*/
typedef enum {
LPUART_IT_RBR = (1U << 0), /**< RBR */
LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IT_RXTO = (1U << 3), /**< RXTO */
LPUART_IT_RXOV = (1U << 4), /**< RXOV */
LPUART_IT_TXOV = (1U << 5), /**< TXOV */
LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IT_DATWK = (1U << 8), /**< DATWK */
LPUART_IT_PERR = (1U << 9), /**< PERR */
LPUART_IT_FERR = (1U << 10), /**< FERR */
LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IT_ADET = (1U << 12), /**< ADET */
LPUART_IT_TC = (1U << 15), /**< TC */
} lpuart_it_t;
/**
* @brief LPUART Flags Types
*/
typedef enum {
LPUART_IF_RBR = (1U << 0), /**< RBR */
LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IF_RXTO = (1U << 3), /**< RXTO */
LPUART_IF_RXOV = (1U << 4), /**< RXOV */
LPUART_IF_TXOV = (1U << 5), /**< TXOV */
LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IF_DATWK = (1U << 8), /**< DATWK */
LPUART_IF_PERR = (1U << 9), /**< PERR */
LPUART_IF_FERR = (1U << 10), /**< FERR */
LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IF_ADET = (1U << 12), /**< ADET */
LPUART_IF_TC = (1U << 15), /**< TC */
} lpuart_flag_t;
/**
* @brief LPUART Status Types
*/
typedef enum {
LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */
LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */
LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */
LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */
LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */
LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */
LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */
} lpuart_status_t;
/**
* @}
*/
/** @defgroup LPUART_Private_Macros LPUART Private Macros
* @{
*/
#define IS_LPUART(x) ((x) == LPUART0)
#define IS_LPUART_DATA(x) ((x) <= 0x1FF)
#define IS_LPUART_BAUDRATE(x) (((x) > 0) && ((x) <= 115200))
#define IS_LPUART_WORD_LENGTH(x) (((x) == LPUART_WORD_LENGTH_5B) || \
((x) == LPUART_WORD_LENGTH_6B) || \
((x) == LPUART_WORD_LENGTH_7B) || \
((x) == LPUART_WORD_LENGTH_8B) || \
((x) == LPUART_WORD_LENGTH_9B))
#define IS_LPUART_STOPBITS(x) (((x) == LPUART_STOP_BITS_1) || \
((x) == LPUART_STOP_BITS_2))
#define IS_LPUART_PARITY(x) (((x) == LPUART_PARITY_NONE) || \
((x) == LPUART_PARITY_ODD) || \
((x) == LPUART_PARITY_EVEN))
#define IS_LPUART_MODE(x) (((x) == LPUART_MODE_UART) || \
((x) == LPUART_MODE_IrDA) || \
((x) == LPUART_MODE_RS485))
#define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\
(((x) == LPUART_HW_FLOW_CTL_NONE) || \
((x) == LPUART_HW_FLOW_CTL_RTS) || \
((x) == LPUART_HW_FLOW_CTL_CTS) || \
((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
#define IS_LPUART_DMAREQ(x) (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX))
#define IS_LPUART_RXFIFO(x) (((x) == LPUART_RXFIFO_1BYTE) || \
((x) == LPUART_RXFIFO_4BYTE) || \
((x) == LPUART_RXFIFO_8BYTE) || \
((x) == LPUART_RXFIFO_14BYTE))
#define IS_LPUART_IT(x) (((x) == LPUART_IT_RBR) || \
((x) == LPUART_IT_TBEMP) || \
((x) == LPUART_IT_CTSDET) || \
((x) == LPUART_IT_RXTO) || \
((x) == LPUART_IT_RXOV) || \
((x) == LPUART_IT_TXOV) || \
((x) == LPUART_IT_CTSWK) || \
((x) == LPUART_IT_DATWK) || \
((x) == LPUART_IT_PERR) || \
((x) == LPUART_IT_FERR) || \
((x) == LPUART_IT_BRKERR) || \
((x) == LPUART_IT_ADET) || \
((x) == LPUART_IT_TC))
#define IS_LPUART_IF(x) (((x) == LPUART_IF_RBR) || \
((x) == LPUART_IF_TBEMP) || \
((x) == LPUART_IF_CTSDET) || \
((x) == LPUART_IF_RXTO) || \
((x) == LPUART_IF_RXOV) || \
((x) == LPUART_IF_TXOV) || \
((x) == LPUART_IF_CTSWK) || \
((x) == LPUART_IF_DATWK) || \
((x) == LPUART_IF_PERR) || \
((x) == LPUART_IF_FERR) || \
((x) == LPUART_IF_BRKERR) || \
((x) == LPUART_IF_ADET) || \
((x) == LPUART_IF_TC))
#define IS_LPUART_STAT(x) (((x) == LPUART_STAT_RXEMP) || \
((x) == LPUART_STAT_RXFULL) || \
((x) == LPUART_STAT_TXEMP) || \
((x) == LPUART_STAT_TXFULL) || \
((x) == LPUART_STAT_TXIDLE) || \
((x) == LPUART_STAT_CTSSTAT) || \
((x) == LPUART_STAT_RTSSTAT))
#define LPUART_STATE_TX_MASK (1 << 4)
#define LPUART_STATE_RX_MASK (1 << 5)
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions
* @{
*/
/** @addtogroup LPUART_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void lpuart_init(lpuart_handle_t *hperh);
void lpuart_reset(lpuart_handle_t *hperh);
void lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t lpuart_dma_pause(lpuart_handle_t *hperh);
ald_status_t lpuart_dma_resume(lpuart_handle_t *hperh);
ald_status_t lpuart_dma_stop(lpuart_handle_t *hperh);
#endif
void lpuart_irq_handle(lpuart_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group3
* @{
*/
/* Peripheral Control functions */
void lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status);
void lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val);
void lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status);
void lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
void lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
ald_status_t lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout);
flag_status_t lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag);
flag_status_t lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
void lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
it_status_t lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it);
/**
* @}
*/
/** @addtogroup LPUART_Public_Functions_Group4
* @{
*/
/* Peripheral State and Errors functions */
lpuart_state_t lpuart_get_state(lpuart_handle_t *hperh);
uint32_t lpuart_get_error(lpuart_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_LPUART_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h
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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h
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/**
*********************************************************************************
*
* @file ald_pmu.h
* @brief Header file of PMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_PMU_H__
#define __ALD_PMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_syscfg.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup PMU
* @{
*/
/** @defgroup PMU_Public_Macros PMU Public Macros
* @{
*/
#define PMU_SRAM0_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM0_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
/**
* @}
*/
/** @defgroup PMU_Public_Types PMU Public Types
* @{
*/
/**
* @brief Standby wakeup port select
*/
typedef enum {
PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */
PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */
PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */
PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */
PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */
PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */
PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */
PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */
PMU_STANDBY_PORT_NONE = 0xF, /**< NONE */
} pmu_standby_wakeup_sel_t;
/**
* @brief Low power mode
*/
typedef enum {
PMU_LP_STOP1 = 0x0, /**< Stop1 */
PMU_LP_STOP2 = 0x1, /**< Stop2 */
PMU_LP_STANDBY = 0x2, /**< Standby */
} pmu_lp_mode_t;
typedef enum {
PMU_SR_WUF = (1U << 0),
PMU_SR_STANDBYF = (1U << 1),
} pmu_status_t;
/**
* @brief LVD voltage select
*/
typedef enum {
PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */
} pmu_lvd_voltage_sel_t;
/**
* @brief LVD trigger mode
*/
typedef enum {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */
} pmu_lvd_trigger_mode_t;
/**
* @brief LDO output voltage selest in low power mode
*/
typedef enum {
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4, /**< 1.2V */
} pmu_ldo_lpmode_output_t;
/**
* @}
*/
/**
* @defgroup PMU_Private_Macros PMU Private Macros
* @{
*/
#define IS_PMU_STANDBY_PORT_SEL(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_PA4) || \
((x) == PMU_STANDBY_PORT_SEL_PA5) || \
((x) == PMU_STANDBY_PORT_SEL_PA6) || \
((x) == PMU_STANDBY_PORT_SEL_PA7) || \
((x) == PMU_STANDBY_PORT_NONE))
#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \
((x) == PMU_SR_STANDBYF))
#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_2_3) || \
((x) == PMU_LVD_VOL_SEL_EXT))
#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
/**
* @}
*/
/** @addtogroup PMU_Public_Functions
* @{
*/
/** @addtogroup PMU_Public_Functions_Group1
* @{
*/
/* Low power mode select */
__STATIC_INLINE__ void __sleep()
{
__WFI();
}
__STATIC_INLINE__ void __sleep_deep()
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
void pmu_stop1_enter(void);
void pmu_stop2_enter(void);
void pmu_standby_enter(pmu_standby_wakeup_sel_t port);
void pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
flag_status_t pmu_get_status(pmu_status_t sr);
void pmu_clear_status(pmu_status_t sr);
/**
* @}
*/
/** @addtogroup PMU_Public_Functions_Group2
* @{
*/
/* LVD configure */
void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
void lvd_irq_cbk(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_PMU_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h
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/**
*********************************************************************************
*
* @file ald_rmu.h
* @brief Header file of RMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_RMU_H__
#define __ALD_RMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup RMU
* @{
*/
/** @defgroup RMU_Public_Types RMU Public Types
* @{
*/
/**
* @brief RMU BOR fliter
*/
typedef enum {
RMU_BORFLT_1 = 0x1, /**< 1 cycle */
RMU_BORFLT_2 = 0x2, /**< 2 cycles */
RMU_BORFLT_3 = 0x3, /**< 3 cycles */
RMU_BORFLT_4 = 0x4, /**< 4 cycles */
RMU_BORFLT_5 = 0x5, /**< 5 cycles */
RMU_BORFLT_6 = 0x6, /**< 6 cycles */
RMU_BORFLT_7 = 0x7, /**< 7 cycles */
} rmu_bor_filter_t;
/**
* @brief RMU BOR voltage
*/
typedef enum {
RMU_VOL_1_7 = 0x0, /**< 1.7V */
RMU_VOL_2_0 = 0x1, /**< 2.0V */
RMU_VOL_2_1 = 0x2, /**< 2.1V */
RMU_VOL_2_2 = 0x3, /**< 2.2V */
RMU_VOL_2_3 = 0x4, /**< 2.3V */
RMU_VOL_2_4 = 0x5, /**< 2.4V */
RMU_VOL_2_5 = 0x6, /**< 2.5V */
RMU_VOL_2_6 = 0x7, /**< 2.6V */
RMU_VOL_2_8 = 0x8, /**< 2.8V */
RMU_VOL_3_0 = 0x9, /**< 3.0V */
RMU_VOL_3_1 = 0xA, /**< 3.1V */
RMU_VOL_3_3 = 0xB, /**< 3.3V */
RMU_VOL_3_6 = 0xC, /**< 3.6V */
RMU_VOL_3_7 = 0xD, /**< 3.7V */
RMU_VOL_4_0 = 0xE, /**< 4.0V */
RMU_VOL_4_3 = 0xF, /**< 4.3V */
} rmu_bor_vol_t;
/**
* @brief RMU reset status
*/
typedef enum {
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
RMU_RST_NMRST = (1U << 3), /**< NMRST */
RMU_RST_IWDT = (1U << 4), /**< IWDT */
RMU_RST_WWDT = (1U << 5), /**< WWDT */
RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */
RMU_RST_CHIP = (1U << 7), /**< CHIP */
RMU_RST_MCU = (1U << 8), /**< MCU */
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
} rmu_state_t;
/**
* @brief RMU periperal select bit
*/
typedef enum {
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */
RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */
RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */
RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */
RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */
RMU_PERH_TIM0 = (1U << 0) | (1U << 28), /**< APB1: TIM0 */
RMU_PERH_TIM1 = (1U << 1) | (1U << 28), /**< APB1: TIM1 */
RMU_PERH_TIM2 = (1U << 2) | (1U << 28), /**< APB1: TIM2 */
RMU_PERH_TIM3 = (1U << 3) | (1U << 28), /**< APB1: TIM3 */
RMU_PERH_TIM4 = (1U << 4) | (1U << 28), /**< APB1: TIM4 */
RMU_PERH_TIM5 = (1U << 5) | (1U << 28), /**< APB1: TIM5 */
RMU_PERH_TIM6 = (1U << 6) | (1U << 28), /**< APB1: TIM6 */
RMU_PERH_TIM7 = (1U << 7) | (1U << 28), /**< APB1: TIM7 */
RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */
RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */
RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */
RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */
RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */
RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */
RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */
RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */
RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */
RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */
RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */
RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */
RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */
RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */
RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */
RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */
RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */
RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */
RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */
RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */
RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */
RMU_PERH_TEMP = (1U << 16) | (1U << 29), /**< APB2: TEMP */
RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */
RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */
} rmu_peripheral_t;
/**
* @}
*/
/**
* @defgroup RMU_Private_Macros RMU Private Macros
* @{
*/
#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_1) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_3) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_5) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_1) || \
((x) == RMU_VOL_3_3) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_7) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_3))
#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR))
#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG))
#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
((x) == RMU_PERH_CRYPT) || \
((x) == RMU_PERH_TRNG) || \
((x) == RMU_PERH_PIS) || \
((x) == RMU_PERH_CHIP) || \
((x) == RMU_PERH_CPU) || \
((x) == RMU_PERH_TIM0) || \
((x) == RMU_PERH_TIM1) || \
((x) == RMU_PERH_TIM2) || \
((x) == RMU_PERH_TIM3) || \
((x) == RMU_PERH_TIM4) || \
((x) == RMU_PERH_TIM5) || \
((x) == RMU_PERH_TIM6) || \
((x) == RMU_PERH_TIM7) || \
((x) == RMU_PERH_UART0) || \
((x) == RMU_PERH_UART1) || \
((x) == RMU_PERH_UART2) || \
((x) == RMU_PERH_UART3) || \
((x) == RMU_PERH_USART0) || \
((x) == RMU_PERH_USART1) || \
((x) == RMU_PERH_SPI0) || \
((x) == RMU_PERH_SPI1) || \
((x) == RMU_PERH_SPI2) || \
((x) == RMU_PERH_I2C0) || \
((x) == RMU_PERH_I2C1) || \
((x) == RMU_PERH_CAN0) || \
((x) == RMU_PERH_LPTIM0) || \
((x) == RMU_PERH_LPUART0) || \
((x) == RMU_PERH_ADC0) || \
((x) == RMU_PERH_ADC1) || \
((x) == RMU_PERH_ACMP0) || \
((x) == RMU_PERH_ACMP1) || \
((x) == RMU_PERH_OPAMP) || \
((x) == RMU_PERH_DAC0) || \
((x) == RMU_PERH_WWDT) || \
((x) == RMU_PERH_LCD) || \
((x) == RMU_PERH_IWDT) || \
((x) == RMU_PERH_RTC) || \
((x) == RMU_PERH_TEMP) || \
((x) == RMU_PERH_BKPC) || \
((x) == RMU_PERH_BKPRAM))
/**
* @}
*/
/** @addtogroup RMU_Public_Functions
* @{
*/
void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
flag_status_t rmu_get_reset_status(rmu_state_t state);
void rmu_clear_reset_status(rmu_state_t state);
void rmu_reset_periperal(rmu_peripheral_t perh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_RMU_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h
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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h
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/**
*********************************************************************************
*
* @file ald_usart.h
* @brief Header file of SMARTCARD driver module.
*
* @version V1.0
* @date 25 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SMARTCARD_H__
#define __ALD_SMARTCARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
#include "ald_usart.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SMARTCARD
* @{
*/
/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants
* @{
*/
/**
* @brief SMARTCARD error codes
*/
typedef enum {
SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
} smartcard_error_t;
/**
* @brief SMARTCARD Prescaler
*/
typedef enum {
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */
} smartcard_prescaler_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct {
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
usart_parity_t parity; /**< Specifies the parity mode.
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/
usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref usart_last_bit_t */
smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock. The value given in the register (5 significant bits)
is multiplied by 2 to give the division factor of the source clock frequency. */
uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */
} smartcard_init_t;
/**
* @brief ALD state structures definition
*/
typedef enum {
SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04 /**< Error */
} smartcard_state_t;
/**
* @brief SMARTCARD handle structure definition
*/
typedef struct smartcard_handle_s {
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */
uint16_t tx_size; /**< SmartCard Tx Transfer size */
uint16_t tx_count; /**< SmartCard Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */
uint16_t rx_size; /**< SmartCard Rx Transfer size */
uint16_t rx_count; /**< SmartCard Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
smartcard_state_t state; /**< SmartCard communication state */
uint32_t err_code; /**< SmartCard Error code */
void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */
} smartcard_handle_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros
* @{
*/
/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset
* @{
*/
#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data
* @{
*/
#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable
* @{
*/
#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable
* @{
*/
#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions
* @{
*/
/** @addtogroup SMARTCARD_Public_Functions_Group1
* @{
*/
/* Initialization functions */
ald_status_t smartcard_init(smartcard_handle_t *hperh);
ald_status_t smartcard_reset(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
#endif
void smartcard_irq_handle(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group3
* @{
*/
/* Peripheral State and Errors functions functions */
smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh);
uint32_t smartcard_get_error(smartcard_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_SMARTCARD_H__ */

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bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h
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/**
*********************************************************************************
*
* @file ald_spi.c
* @brief Header file of SPI module driver.
*
* @version V1.0
* @date 13 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SPI_H__
#define __ALD_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Public_Types SPI Public Types
* @{
*/
/**
* @brief clock phase
*/
typedef enum {
SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */
} spi_cpha_t;
/**
* @brief clock polarity
*/
typedef enum {
SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */
} spi_cpol_t;
/**
* @brief master selection
*/
typedef enum {
SPI_MODE_SLAVER = 0, /**< Slave mode */
SPI_MODE_MASTER = 1, /**< Master mode */
} spi_mode_t;
/**
* @brief baud rate control
*/
typedef enum {
SPI_BAUD_2 = 0, /**< fpclk/2 */
SPI_BAUD_4 = 1, /**< fpclk/4 */
SPI_BAUD_8 = 2, /**< fpclk/8 */
SPI_BAUD_16 = 3, /**< fpclk/16 */
SPI_BAUD_32 = 4, /**< fpclk/32 */
SPI_BAUD_64 = 5, /**< fpclk/64 */
SPI_BAUD_128 = 6, /**< fpclk/128 */
SPI_BAUD_256 = 7, /**< fpclk/256 */
} spi_baud_t;
/**
* @brief frame format
*/
typedef enum {
SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */
} spi_firstbit_t;
/**
* @brief data frame format
*/
typedef enum {
SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */
} spi_datasize_t;
/**
* @brief interrupt control
*/
typedef enum {
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
} spi_it_t;
/**
* @brief interrupt flag
*/
typedef enum {
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
SPI_IF_MODF = (1U << 5), /**< mode fault */
SPI_IF_OVE = (1U << 6), /**< overrun flag */
SPI_IF_BUSY = (1U << 7), /**< busy flag */
} spi_flag_t;
/**
* @brief SPI error status
*/
typedef enum {
SPI_ERROR_NONE = 0, /**< none */
SPI_ERROR_MODF = 1, /**< mode fault */
SPI_ERROR_CRC = 2, /**< crc error */
SPI_ERROR_OVE = 4, /**< overrun error */
SPI_ERROR_DMA = 8, /**< dma error */
SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */
} spi_error_t;
/**
* @brief SPI state structures definition
*/
typedef enum {
SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */
SPI_STATE_ERROR = 0x04, /**< Error */
} spi_state_t;
/**
* @brief SPI direction definition
*/
typedef enum {
SPI_DIRECTION_2LINES = 0, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */
} spi_direction_t;
/**
* @brief SPI dma request definition
*/
typedef enum {
SPI_DMA_REQ_TX = 0, /**< TX dma request */
SPI_DMA_REQ_RX = 1, /**< RX dma request */
} spi_dma_req_t;
/**
* @brief SPI TXE/RXNE status definition
*/
typedef enum {
SPI_SR_TXBE = 0, /**< SR.TXE set */
SPI_SR_RXBNE = 1, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */
} spi_sr_status_t;
/**
* @brief SPI init structure definition
*/
typedef struct {
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
spi_baud_t baud; /**< SPI baudrate prescaler */
spi_cpha_t phase; /**< SPI clock phase */
spi_cpol_t polarity; /**< SPI clock polarity */
spi_firstbit_t first_bit; /**< SPI first bit */
type_func_t ss_en; /**< SPI ssm enable or disable */
type_func_t crc_calc; /**< SPI crc calculation */
uint16_t crc_poly; /**< SPI crc polynomial */
} spi_init_t;
/**
* @brief SPI handle structure definition
*/
typedef struct spi_handle_s {
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
uint16_t tx_size; /**< SPI Tx transfer size */
uint16_t tx_count; /**< SPI Tx transfer counter */
uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
uint16_t rx_size; /**< SPI Rx Transfer size */
uint16_t rx_count; /**< SPI Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
spi_state_t state; /**< SPI communication state */
uint32_t err_code; /**< SPI error code */
void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */
void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */
void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */
} spi_handle_t;
/**
* @}
*/
/** @defgroup SPI_Public_Macros SPI Public Macros
* @{
*/
#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define SPI_CRC_RESET(x) \
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
/**
* @}
*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#define IS_SPI(x) (((x) == SPI0) || \
((x) == SPI1) || \
((x) == SPI2))
#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
((x) == SPI_CPOL_HIGH))
#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \
((x) == SPI_MODE_MASTER))
#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \
((x) == SPI_BAUD_4) || \
((x) == SPI_BAUD_8) || \
((x) == SPI_BAUD_16) || \
((x) == SPI_BAUD_32) || \
((x) == SPI_BAUD_64) || \
((x) == SPI_BAUD_128) || \
((x) == SPI_BAUD_256))
#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))
#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \
((x) == SPI_BIDMODE_SOLE))
#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \
((x) == SPI_DMA_REQ_RX))
#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \
((x) == SPI_SR_RXBNE) || \
((x) == SPI_SR_TXBE_RXBNE))
#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \
((x) == SPI_IT_RXBNE) || \
((x) == SPI_IT_TXBE))
#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \
((x) == SPI_IF_TXBE) || \
((x) == SPI_IF_CRCERR) || \
((x) == SPI_IF_MODF) || \
((x) == SPI_IF_OVE) || \
((x) == SPI_IF_BUSY))
/**
* @}
*/
/** @addtogroup SPI_Public_Functions
* @{
*/
/** @addtogroup SPI_Public_Functions_Group1
* @{
*/
ald_status_t spi_init(spi_handle_t *hperh);
void spi_reset(spi_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group2
* @{
*/
int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
uint8_t spi_recv_byte_fast(spi_handle_t *hperh);
ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
ald_status_t spi_dma_pause(spi_handle_t *hperh);
ald_status_t spi_dma_resume(spi_handle_t *hperh);
ald_status_t spi_dma_stop(spi_handle_t *hperh);
#endif
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group3
* @{
*/
void spi_irq_handle(spi_handle_t *hperh);
void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group4
* @{
*/
spi_state_t spi_get_state(spi_handle_t *hperh);
uint32_t spi_get_error(spi_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

199
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_temp.h
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@@ -1,199 +0,0 @@
/**
*********************************************************************************
*
* @file ald_temp.h
* @brief Header file of TEMP module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TEMP_H__
#define __ALD_TEMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TEMP
* @{
*/
/** @defgroup TEMP_Public_Macros TEMP Public Macros
* @{
*/
#define TEMP_LOCK() (WRITE_REG(TEMP->WPR, 0x0))
#define TEMP_UNLOCK() (WRITE_REG(TEMP->WPR, 0xA55A9669))
#define TEMP_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_REQ_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_REQ_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_CTN_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_CTN_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_RESET() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_RST_MSK); \
TEMP_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup TEMP_Public_Types TEMP Public Types
* @{
*/
/**
* @brief Temperature update time
*/
typedef enum {
TEMP_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */
TEMP_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */
TEMP_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */
TEMP_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */
TEMP_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */
} temp_update_cycle_t;
/**
* @brief Temperature output mode
*/
typedef enum {
TEMP_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */
TEMP_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */
TEMP_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */
TEMP_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */
TEMP_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */
} temp_output_mode_t;
/**
* @brief Source select
*/
typedef enum {
TEMP_SOURCE_LOSC = 0x0, /**< LOSC */
TEMP_SOURCE_LRC = 0x1, /**< LRC */
TEMP_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */
TEMP_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */
} temp_source_sel_t;
/**
* @brief TEMP init structure definition
*/
typedef struct {
temp_update_cycle_t cycle; /**< Temperature update time */
temp_output_mode_t mode; /**< Temperature output mode */
uint8_t ctn; /**< Continue mode */
uint8_t psc; /**< Perscaler */
} temp_init_t;
/**
* @brief Define callback function type
*/
typedef void (*temp_cbk)(uint16_t value, ald_status_t status);
/**
* @}
*/
/**
* @defgroup TEMP_Private_Macros TEMP Private Macros
* @{
*/
#define IS_TEMP_UPDATE_CYCLE(x) (((x) == TEMP_UPDATE_CYCLE_3) || \
((x) == TEMP_UPDATE_CYCLE_4) || \
((x) == TEMP_UPDATE_CYCLE_5) || \
((x) == TEMP_UPDATE_CYCLE_6) || \
((x) == TEMP_UPDATE_CYCLE_7))
#define IS_TEMP_OUTPUT_MODE(x) (((x) == TEMP_OUTPUT_MODE_200) || \
((x) == TEMP_OUTPUT_MODE_400) || \
((x) == TEMP_OUTPUT_MODE_800) || \
((x) == TEMP_OUTPUT_MODE_1600) || \
((x) == TEMP_OUTPUT_MODE_3200))
#define IS_TEMP_SOURCE_SEL(x) (((x) == TEMP_SOURCE_LOSC) || \
((x) == TEMP_SOURCE_LRC) || \
((x) == TEMP_SOURCE_HRC_DIV_1M ) || \
((x) == TEMP_SOURCE_HOSC_DIV_1M))
/**
* @}
*/
/** @addtogroup TEMP_Public_Functions
* @{
*/
/** @addtogroup TEMP_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void temp_init(temp_init_t *init);
extern void temp_source_selcet(temp_source_sel_t sel);
/**
* @}
*/
/** @addtogroup TEMP_Public_Functions_Group2
* @{
*/
/* Control functions */
extern ald_status_t temp_get_value(uint16_t *temp);
extern void temp_get_value_by_it(temp_cbk cbk);
void temp_irq_handle(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TEMP_H__ */

1086
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h
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176
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h
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@@ -1,176 +0,0 @@
/**
*********************************************************************************
*
* @file ald_trng.h
* @brief Header file of TRNG module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TRNG_H__
#define __ALD_TRNG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TRNG
* @{
*/
/** @defgroup TRNG_Public_Macros TRNG Public Macros
* @{
*/
#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
/**
* @}
*/
/** @defgroup TRNG_Public_Types TRNG Public Types
* @{
*/
/**
* @brief Data width
*/
typedef enum {
TRNG_DSEL_1B = 0x0, /**< 1-bit */
TRNG_DSEL_8B = 0x1, /**< 8-bit */
TRNG_DSEL_16B = 0x2, /**< 16-bit */
TRNG_DSEL_32B = 0x3, /**< 32-bit */
} trng_data_width_t;
/**
* @brief seed type
*/
typedef enum {
TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */
} trng_seed_type_t;
/**
* @brief TRNG init structure definition
*/
typedef struct {
trng_data_width_t data_width; /**< The width of data */
trng_seed_type_t seed_type; /**< The seed type */
uint32_t seed; /**< The value of seed */
uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
uint8_t adjc; /**< Adjust parameter */
uint8_t posten;
} trng_init_t;
/**
* @brief State type
*/
typedef enum {
TRNG_STATUS_START = (1U << 0), /**< Start state */
TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */
TRNG_STATUS_SERR = (1U << 2), /**< Error state */
} trng_status_t;
/**
* @brief Interrupt type
*/
typedef enum {
TRNG_IT_START = (1U << 0), /**< Start */
TRNG_IT_DAVLD = (1U << 1), /**< Data valid */
TRNG_IT_SERR = (1U << 2), /**< Error */
} trng_it_t;
/**
* @brief Interrupt flag type
*/
typedef enum {
TRNG_IF_START = (1U << 0), /**< Start */
TRNG_IF_DAVLD = (1U << 1), /**< Data valid */
TRNG_IF_SERR = (1U << 2), /**< Error */
} trng_flag_t;
/**
* @}
*/
/**
* @defgroup TRNG_Private_Macros TRNG Private Macros
* @{
*/
#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \
((x) == TRNG_DSEL_8B) || \
((x) == TRNG_DSEL_16B) || \
((x) == TRNG_DSEL_32B))
#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \
((x) == TRNG_SEED_TYPE_1) || \
((x) == TRNG_SEED_TYPE_LAST) || \
((x) == TRNG_SEED_TYPE_SEED))
#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \
((x) == TRNG_STATUS_DAVLD) || \
((x) == TRNG_STATUS_SERR))
#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \
((x) == TRNG_IT_DAVLD) || \
((x) == TRNG_IT_SERR))
#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
#define IS_TRNG_ADJC(x) ((x) < 4)
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions
* @{
*/
/** @addtogroup TRNG_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void trng_init(trng_init_t *init);
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions_Group2
* @{
*/
/* Control functions */
extern uint32_t trng_get_result(void);
extern void trng_interrupt_config(trng_it_t it, type_func_t state);
extern flag_status_t trng_get_status(trng_status_t status);
extern it_status_t trng_get_it_status(trng_it_t it);
extern flag_status_t trng_get_flag_status(trng_flag_t flag);
extern void trng_clear_flag_status(trng_flag_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TRNG_H__ */

461
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h
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@@ -1,461 +0,0 @@
/**
*********************************************************************************
*
* @file ald_uart.h
* @brief Header file of UART module library.
*
* @version V1.0
* @date 21 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_UART_H__
#define __ALD_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup UART
* @{
*/
/**
* @defgroup UART_Public_Macros UART Public Macros
* @{
*/
#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK))
#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK))
#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK))
#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
/**
* @}
*/
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/**
* @brief UART word length
*/
typedef enum {
UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
} uart_word_length_t;
/**
* @brief UART stop bits
*/
typedef enum {
UART_STOP_BITS_1 = 0x0, /**< 1-bits */
UART_STOP_BITS_2 = 0x1, /**< 2-bits */
UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */
UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */
} uart_stop_bits_t;
/**
* @brief UART parity
*/
typedef enum {
UART_PARITY_NONE = 0x0, /**< Not parity */
UART_PARITY_ODD = 0x1, /**< Odd parity */
UART_PARITY_EVEN = 0x3, /**< Even parity */
} uart_parity_t;
/**
* @brief UART mode
*/
typedef enum {
UART_MODE_UART = 0x0, /**< UART */
UART_MODE_LIN = 0x1, /**< LIN */
UART_MODE_IrDA = 0x2, /**< IrDA */
UART_MODE_RS485 = 0x3, /**< RS485 */
UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */
} uart_mode_t;
/**
* @brief UART hardware flow control
*/
typedef enum {
UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */
UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */
} uart_hw_flow_ctl_t;
/**
* @brief ALD UART state
*/
typedef enum {
UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
UART_STATE_TIMEOUT = 0x03, /**< Timeout state */
UART_STATE_ERROR = 0x04, /**< Error */
} uart_state_t;
/**
* @brief UART error codes
*/
typedef enum {
UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
} uart_error_t;
/**
* @brief UART init structure definition
*/
typedef struct {
uint32_t baud; /**< Specifies the uart communication baud rate */
uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
uart_parity_t parity; /**< Specifies the parity mode */
uart_mode_t mode; /**< Specifies uart mode */
uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
} uart_init_t;
/**
* @brief UART handle structure definition
*/
typedef struct uart_handle_s {
UART_TypeDef *perh; /**< UART registers base address */
uart_init_t init; /**< UART communication parameters */
uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */
uint16_t tx_size; /**< UART Tx Transfer size */
uint16_t tx_count; /**< UART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */
uint16_t rx_size; /**< UART Rx Transfer size */
uint16_t rx_count; /**< UART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
uart_state_t state; /**< UART communication state */
uart_error_t err_code; /**< UART Error code */
void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */
} uart_handle_t;
/**
* @brief UART RS485 configure structure definition
*/
typedef struct {
type_func_t normal; /**< Normal mode */
type_func_t dir; /**< Auto-direction mode */
type_func_t invert; /**< Address detection invert */
uint8_t addr; /**< Address for compare */
} uart_rs485_config_t;
/**
* @brief LIN detection break length
*/
typedef enum {
LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */
LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */
} uart_lin_break_len_t;
/**
* @brief UART TXFIFO size
*/
typedef enum {
UART_TXFIFO_EMPTY = 0x0, /**< Empty */
UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */
UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */
UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */
} uart_txfifo_t;
/**
* @brief UART RXFIFO size
*/
typedef enum {
UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
} uart_rxfifo_t;
/**
* @brief UART auto-baud mode
*/
typedef enum {
UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */
UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */
UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */
} uart_auto_baud_mode_t;
/**
* @brief UART status types
*/
typedef enum {
UART_STATUS_DR = (1U << 0), /**< Data ready */
UART_STATUS_OE = (1U << 1), /**< Overrun error */
UART_STATUS_PE = (1U << 2), /**< Parity error */
UART_STATUS_FE = (1U << 3), /**< Framing error */
UART_STATUS_BI = (1U << 4), /**< Break interrupt */
UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */
UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */
UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */
UART_STATUS_BUSY = (1U << 8), /**< UART busy */
UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */
UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */
UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */
UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */
UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */
UART_STATUS_CTS = (1U << 15), /**< Clear to send */
} uart_status_t;
/**
* @brief UART interrupt types
*/
typedef enum {
UART_IT_RXRD = (1U << 0), /**< Receive data available */
UART_IT_TXS = (1U << 1), /**< Tx empty status */
UART_IT_RXS = (1U << 2), /**< Rx line status */
UART_IT_MDS = (1U << 3), /**< Modem status */
UART_IT_RTO = (1U << 4), /**< Receiver timeout */
UART_IT_BZ = (1U << 5), /**< Busy status */
UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IT_LINBK = (1U << 8), /**< Lin break detection */
UART_IT_TC = (1U << 9), /**< Transmission complete */
UART_IT_EOB = (1U << 10), /**< End of block */
UART_IT_CM = (1U << 11), /**< Character match */
} uart_it_t;
/**
* @brief UART flags types
*/
typedef enum {
UART_IF_RXRD = (1U << 0), /**< Receive data available */
UART_IF_TXS = (1U << 1), /**< Tx empty status */
UART_IF_RXS = (1U << 2), /**< Rx line status */
UART_IF_MDS = (1U << 3), /**< Modem status */
UART_IF_RTO = (1U << 4), /**< Receiver timeout */
UART_IF_BZ = (1U << 5), /**< Busy status */
UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IF_LINBK = (1U << 8), /**< Lin break detection */
UART_IF_TC = (1U << 9), /**< Transmission complete */
UART_IF_EOB = (1U << 10), /**< End of block */
UART_IF_CM = (1U << 11), /**< Character match */
} uart_flag_t;
/**
* @}
*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_ALL(x) (((x) == UART0) || \
((x) == UART1) || \
((x) == UART2) || \
((x) == UART3))
#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \
((x) == UART_WORD_LENGTH_6B) || \
((x) == UART_WORD_LENGTH_7B) || \
((x) == UART_WORD_LENGTH_8B))
#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \
((x) == UART_STOP_BITS_2) || \
((x) == UART_STOP_BITS_0_5) || \
((x) == UART_STOP_BITS_1_5))
#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \
((x) == UART_PARITY_ODD) || \
((x) == UART_PARITY_EVEN))
#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \
((x) == UART_MODE_LIN) || \
((x) == UART_MODE_IrDA) || \
((x) == UART_MODE_RS485) || \
((x) == UART_MODE_HDSEL))
#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
(((x) == UART_HW_FLOW_CTL_DISABLE) || \
((x) == UART_HW_FLOW_CTL_ENABLE))
#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \
((x) == LIN_BREAK_LEN_11B))
#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \
((x) == UART_TXFIFO_2BYTE) || \
((x) == UART_TXFIFO_4BYTE) || \
((x) == UART_TXFIFO_8BYTE))
#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \
((x) == UART_RXFIFO_4BYTE) || \
((x) == UART_RXFIFO_8BYTE) || \
((x) == UART_RXFIFO_14BYTE))
#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \
((x) == UART_ABRMOD_1) || \
((x) == UART_ABRMOD_0_TO_1))
#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \
((x) == UART_STATUS_OE) || \
((x) == UART_STATUS_PE) || \
((x) == UART_STATUS_FE) || \
((x) == UART_STATUS_BI) || \
((x) == UART_STATUS_TBEM) || \
((x) == UART_STATUS_TEM) || \
((x) == UART_STATUS_RFE) || \
((x) == UART_STATUS_BUSY) || \
((x) == UART_STATUS_TFNF) || \
((x) == UART_STATUS_TFEM) || \
((x) == UART_STATUS_RFNE) || \
((x) == UART_STATUS_RFF) || \
((x) == UART_STATUS_DCTS) || \
((x) == UART_STATUS_CTS))
#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \
((x) == UART_IT_TXS) || \
((x) == UART_IT_RXS) || \
((x) == UART_IT_MDS) || \
((x) == UART_IT_RTO) || \
((x) == UART_IT_BZ) || \
((x) == UART_IT_ABE) || \
((x) == UART_IT_ABTO) || \
((x) == UART_IT_LINBK) || \
((x) == UART_IT_TC) || \
((x) == UART_IT_EOB) || \
((x) == UART_IT_CM))
#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \
((x) == UART_IF_TXS) || \
((x) == UART_IF_RXS) || \
((x) == UART_IF_MDS) || \
((x) == UART_IF_RTO) || \
((x) == UART_IF_BZ) || \
((x) == UART_IF_ABE) || \
((x) == UART_IF_ABTO) || \
((x) == UART_IF_LINBK) || \
((x) == UART_IF_TC) || \
((x) == UART_IF_EOB) || \
((x) == UART_IF_CM))
#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
#define IS_UART_DATA(x) ((x) <= 0x1FF)
#define UART_STATE_TX_MASK (1U << 4)
#define UART_STATE_RX_MASK (1U << 5)
/**
* @}
*/
/** @addtogroup UART_Public_Functions
* @{
*/
/** @addtogroup UART_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void uart_init(uart_handle_t *hperh);
void uart_reset(uart_handle_t *hperh);
void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t uart_dma_pause(uart_handle_t *hperh);
ald_status_t uart_dma_resume(uart_handle_t *hperh);
ald_status_t uart_dma_stop(uart_handle_t *hperh);
#endif
void uart_irq_handle(uart_handle_t *hperh);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group3
* @{
*/
/* Peripheral Control functions */
void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
void uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void uart_lin_send_break(uart_handle_t *hperh);
void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status);
flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group4
* @{
*/
/* Peripheral State and Errors functions */
uart_state_t uart_get_state(uart_handle_t *hperh);
uint32_t uart_get_error(uart_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_UART_H__ */

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/**
*********************************************************************************
*
* @file ald_acmp.c
* @brief ACMP module driver.
*
* @version V1.0
* @date 13 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_acmp.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup ACMP ACMP
* @brief ACMP module driver
* @{
*/
#ifdef ALD_ACMP
/** @defgroup ACMP_Public_Functions ACMP Public Functions
* @{
*/
/** @defgroup ACMP_Public_Functions_Group1 Initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/**
* @brief Initializes the ACMP mode according to the specified parameters in
* the acmp_init_t and create the associated handle.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t acmp_init(acmp_handle_t *hperh)
{
uint32_t tmp = 0;
if (hperh == NULL)
return ERROR;
if (hperh->init.vdd_level > 63)
return ERROR;
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func));
assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port));
assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port));
assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
__LOCK(hperh);
tmp = hperh->perh->CON;
tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
(hperh->init.inactval << ACMP_CON_INACTV_POS));
hperh->perh->CON = tmp;
tmp = hperh->perh->INPUTSEL;
tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) |
(hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
hperh->perh->INPUTSEL = tmp;
if (hperh->init.warm_func == ACMP_WARM_DISABLE)
CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
else
SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
switch (hperh->init.edge) {
case ACMP_EDGE_NONE:
CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
break;
case ACMP_EDGE_FALL:
SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
break;
case ACMP_EDGE_RISE:
CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
break;
case ACMP_EDGE_ALL:
SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
break;
default:
break;
}
SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0);
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions
* @brief ACMP Interrupt operation functions
* @{
*/
/**
* @brief Enables or disables the specified ACMP interrupts.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @param it: Specifies the ACMP interrupt sources to be enabled or disabled.
* This parameter can be one of the @ref acmp_it_t.
* @param state: New status
* - ENABLE
* - DISABLE
* @retval Status, see @ref ald_status_t.
*/
ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_IT_TYPE(it));
assert_param(IS_FUNC_STATE(state));
__LOCK(hperh);
if (state)
hperh->perh->IES |= it;
else
hperh->perh->IEC |= it;
__UNLOCK(hperh);
return OK;
}
/**
* @brief Checks whether the specified ACMP interrupt has occurred or not.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @param flag: Specifies the ACMP interrupt source to check.
* This parameter can be one of the @ref acmp_it_t.
* @retval it_status_t
* - SET
* - RESET
*/
it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_FLAG_TYPE(flag));
if (hperh->perh->RIF & flag) {
__UNLOCK(hperh);
return SET;
}
return RESET;
}
/** @brief Clear the specified ACMP it flags.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @param flag: specifies the it flag.
* This parameter can be one of the @ref acmp_it_t.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_FLAG_TYPE(flag));
__LOCK(hperh);
hperh->perh->IFC |= flag;
__UNLOCK(hperh);
return OK;
}
/** @brief Set the specified acmp it flags.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified acmp module.
* @param it: specifies the it flag.
* This parameter can be one of the @ref acmp_it_t.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_IT_TYPE(it));
__LOCK(hperh);
hperh->perh->IFM |= it;
__UNLOCK(hperh);
return OK;
}
/** @brief Check whether the specified ACMP flag is set or not.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @param status: specifies the status to check.
* This parameter can be one of the @ref acmp_status_t.
* @retval flag_status_t
* - SET
* - RESET
*/
flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_STATUS_TYPE(status));
if (hperh->perh->STAT & status) {
__UNLOCK(hperh);
return SET;
}
return RESET;
}
/**
* @}
*/
/** @defgroup ACMP_Public_Functions_Group3 Output value functions
* @brief ACMP Output value functions
* @{
*/
/**
* @brief This function handles ACMP interrupt request.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @retval None
*/
void acmp_irq_handle(acmp_handle_t *hperh)
{
if (acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) {
if (hperh->acmp_warmup_cplt_cbk)
hperh->acmp_warmup_cplt_cbk(hperh);
acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
}
if (acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) {
if (hperh->acmp_edge_cplt_cbk)
hperh->acmp_edge_cplt_cbk(hperh);
acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
}
return;
}
/**
* @brief This function config acmp output.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @param config: Pointer to a acmp_output_config_t structure that contains
* the configutation information for acmp output.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config)
{
if (hperh == NULL)
return ERROR;
if (config == NULL)
return ERROR;
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv));
assert_param(IS_ACMP_LOCATION_TYPE(config->location));
assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func));
__LOCK(hperh);
hperh->perh->PORT = config->location;
hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS);
hperh->perh->PORT = config->out_func;
__UNLOCK(hperh);
return OK;
}
/**
* @brief This function output acmp result.
* @param hperh: Pointer to a acmp_handle_t structure that contains
* the configuration information for the specified ACMP module.
* @retval output value.
*/
uint8_t acmp_out_result(acmp_handle_t *hperh)
{
assert_param(IS_ACMP_TYPE(hperh->perh));
return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_ACMP */
/**
* @}
*/
/**
* @}
*/

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/**
*********************************************************************************
*
* @file ald_crc.c
* @brief CRC module driver.
*
* @version V1.0
* @date 6 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_crc.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup CRC CRC
* @brief CRC module driver
* @{
*/
#ifdef ALD_CRC
/** @addtogroup CRC_Private_Functions CRC Private Functions
* @{
*/
void crc_reset(crc_handle_t *hperh);
#ifdef ALD_DMA
static void crc_dma_calculate_cplt(void *arg);
static void crc_dma_error(void *arg);
#endif
/**
* @}
*/
/** @defgroup CRC_Public_Functions CRC Public Functions
* @{
*/
/** @defgroup CRC_Public_Functions_Group1 Initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/**
* @brief Initializes the CRC mode according to the specified parameters in
* the crc_handle_t and create the associated handle.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t crc_init(crc_handle_t *hperh)
{
uint32_t tmp = 0;
if (hperh == NULL)
return ERROR;
assert_param(IS_CRC(hperh->perh));
assert_param(IS_CRC_MODE(hperh->init.mode));
assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
assert_param(IS_FUNC_STATE(hperh->init.data_inv));
assert_param(IS_FUNC_STATE(hperh->init.data_rev));
assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
crc_reset(hperh);
__LOCK(hperh);
CRC_ENABLE(hperh);
tmp = hperh->perh->CR;
tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
(hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
(CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
(1 << CRC_CR_BYTORD_POS));
hperh->perh->CR = tmp;
hperh->perh->SEED = hperh->init.seed;
CRC_RESET(hperh);
hperh->state = CRC_STATE_READY;
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup CRC_Public_Functions_Group2 Calculate functions
* @brief Calculate functions
* @{
*/
/**
* @brief Calculate the crc value of data.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @param buf: Pointer to data buffer
* @param size: The size of data to be calculate
* @retval result, the result of a amount data
*/
uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
{
uint32_t i;
uint32_t ret;
assert_param(IS_CRC(hperh->perh));
if (buf == NULL || size == 0)
return 0;
__LOCK(hperh);
hperh->state = CRC_STATE_BUSY;
for (i = 0; i < size; i++)
CRC->DATA = buf[i];
ret = CRC->CHECKSUM;
hperh->state = CRC_STATE_READY;
__UNLOCK(hperh);
return ret;
}
/**
* @}
*/
#ifdef ALD_DMA
/** @defgroup CRC_Public_Functions_Group3 DMA operation functions
* @brief DMA operation functions
* @{
*/
/**
* @brief Calculate an amount of data used dma channel
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @param buf: Pointer to data buffer
* @param res: Pointer to result
* @param size: Amount of data to be Calculate
* @param channel: DMA channel as CRC transmit
* @retval Status, see @ref ald_status_t.
*/
ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
{
if (hperh->state != CRC_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
__LOCK(hperh);
hperh->state = CRC_STATE_BUSY;
hperh->cal_buf = buf;
hperh->cal_res = res;
if (hperh->hdma.perh == NULL)
hperh->hdma.perh = DMA0;
hperh->hdma.cplt_arg = (void *)hperh;
hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
hperh->hdma.err_arg = (void *)hperh;
hperh->hdma.err_cbk = &crc_dma_error;
dma_config_struct(&(hperh->hdma.config));
hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
hperh->hdma.config.src = (void *)buf;
hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
hperh->hdma.config.size = size;
hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE;
hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
hperh->hdma.config.msel = DMA_MSEL_CRC;
hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
hperh->hdma.config.channel = channel;
dma_config_basic(&(hperh->hdma));
__UNLOCK(hperh);
CRC_DMA_ENABLE(hperh);
return OK;
}
/**
* @brief Pauses the DMA Transfer.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t crc_dma_pause(crc_handle_t *hperh)
{
__LOCK(hperh);
CRC_DMA_DISABLE(hperh);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Resumes the DMA Transfer.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t crc_dma_resume(crc_handle_t *hperh)
{
__LOCK(hperh);
CRC_DMA_ENABLE(hperh);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Stops the DMA Transfer.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t crc_dma_stop(crc_handle_t *hperh)
{
__LOCK(hperh);
CRC_DMA_DISABLE(hperh);
__UNLOCK(hperh);
hperh->state = CRC_STATE_READY;
return OK;
}
/**
* @}
*/
#endif
/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions
* @brief CRC State and Errors functions
* @{
*/
/**
* @brief Returns the CRC state.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval CRC state
*/
crc_state_t crc_get_state(crc_handle_t *hperh)
{
assert_param(IS_CRC(hperh->perh));
return hperh->state;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @brief CRC Private functions
* @{
*/
/**
* @brief Reset the CRC peripheral.
* @param hperh: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval None
*/
void crc_reset(crc_handle_t *hperh)
{
hperh->perh->DATA = 0x0;
hperh->perh->CR = 0x2;
hperh->perh->SEED = 0xFFFFFFFF;
hperh->state = CRC_STATE_READY;
__UNLOCK(hperh);
return;
}
#ifdef ALD_DMA
/**
* @brief DMA CRC calculate process complete callback.
* @param arg: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval None
*/
static void crc_dma_calculate_cplt(void *arg)
{
crc_handle_t *hperh = (crc_handle_t *)arg;
*(hperh->cal_res) = CRC->CHECKSUM;
CRC_DMA_DISABLE(hperh);
hperh->state = CRC_STATE_READY;
if (hperh->cal_cplt_cbk)
hperh->cal_cplt_cbk(hperh);
}
/**
* @brief DMA CRC communication error callback.
* @param arg: Pointer to a crc_handle_t structure that contains
* the configuration information for the specified CRC module.
* @retval None
*/
static void crc_dma_error(void *arg)
{
crc_handle_t *hperh = (crc_handle_t *)arg;
CRC_CLEAR_ERROR_FLAG(hperh);
CRC_DMA_DISABLE(hperh);
hperh->state = CRC_STATE_READY;
if (hperh->err_cplt_cbk)
hperh->err_cplt_cbk(hperh);
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_CRC */
/**
* @}
*/

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/**
*********************************************************************************
*
* @file ald_lcd.c
* @brief LCD module driver.
*
* @version V1.0
* @date 29 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_lcd.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup LCD LCD
* @brief LCD module library
* @{
*/
#ifdef ALD_LCD
/** @defgroup LCD_Public_Functions LCD Public Functions
* @{
*/
/** @defgroup LCD_Public_Functions_Group1 Initialize and Enable functions
* @brief Initialize and Enable Functions
* @{
*/
/**
* @brief Initializes the LCD Peripheral according to the specified parameters.
* @note This function can be used only when the LCD is disabled.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_init(lcd_handle_t *hperh)
{
uint16_t delay = 0;
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps));
assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel));
assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld));
assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd));
assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld));
assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd));
assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld));
assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd));
assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias));
assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty));
assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs));
assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs));
assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div));
assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead));
assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon));
assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs));
__LOCK(hperh);
cmu_lcd_clock_select(hperh->init.clock);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS);
for (delay = 0; delay < 3000; delay++);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS);
MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS);
MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS);
MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Enables or disables the LCD controller.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param state: This parameter can be: ENABLE or DISABLE.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_cmd(lcd_handle_t *hperh, type_func_t state)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_FUNC_STATE(state));
__LOCK(hperh);
MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS);
MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS);
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup LCD_Public_Functions_Group2 Config output functions
* @brief Config output and blink functions
* @{
*/
/**
* @brief Configures the LCD blink mode and blink frequency.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param blink_mode: Specifies the LCD blink mode.
* @param blink_freq: Specifies the LCD blink frequency.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq)
{
uint16_t delay = 0;
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_BLINK_MODE(blink_mode));
assert_param(IS_LCD_BLFRQ_TYPE(blink_freq));
__LOCK(hperh);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS);
for (delay = 0; delay < 3000; delay++);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Control segment port enable or disable
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param seg: Specifies the LCD segment index
* @param seg_data: Specifies LCD segment data to be written to control segment output enable.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_SEG_TYPE(seg));
__LOCK(hperh);
if (seg == SEG_0_TO_31)
WRITE_REG(hperh->perh->SEGCR0, seg_data);
else
WRITE_REG(hperh->perh->SEGCR1, seg_data);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Writes a word in the specific LCD buffer to determine display.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param buf: Specifies the LCD buffer index.
* @param buf_data: Specifies LCD buffer data to be written to control display.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_BUFFER_TYPE(buf));
__LOCK(hperh);
WRITE_REG(hperh->perh->BUF[buf], buf_data);
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup LCD_Public_Functions_Group3 Peripheral State functions
* @brief LCD State functions
* @{
*/
/**
* @brief Checks whether the specified LCD flag is set or not.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param lcd_status: Specifies the flag to check.
* @retval The new state of LCD_STATUS
*/
uint32_t lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_STATUS_TYPE(lcd_status));
if (lcd_status == LCD_STATUS_ALL)
return hperh->perh->SR;
else
return hperh->perh->SR & lcd_status ? 1 : 0;
}
/**
* @}
*/
/** @defgroup LCD_Public_Functions_Group4 Interrupt functions
* @brief LCD Interrupt functions
* @{
*/
/**
* @brief Enable or disable the specified interrupt
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param it: Specifies the interrupt type to be enabled or disabled
* @arg @ref LCD_IT_SOF Start of frame interrupt enable
* @arg @ref LCD_IT_UDD Update display done interrupt
* @param state: New state of the specified interrupt.
* This parameter can be: ENABLE or DISABLE
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_IT_TYPE(it));
assert_param(IS_FUNC_STATE(state));
__LOCK(hperh);
if (state)
SET_BIT(hperh->perh->IE, it);
else
CLEAR_BIT(hperh->perh->IE, it);
__UNLOCK(hperh);
return OK;
}
/**
* @brief Checks whether the specified interrupt has set or not.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param it: Specifies the interrupt type to check
* This parameter can be one of the following values:
* @arg @ref LCD_IT_SOF Start of frame interrupt enable
* @arg @ref LCD_IT_UDD Update display done interrupt
* @retval The new state of the LCD_IT
*/
flag_status_t lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_IT_TYPE(it));
return hperh->perh->IE & it ? SET : RESET;
}
/**
* @brief Checks whether the specified interrupt has occurred or not.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param flag: Specifies the interrupt type to check
* This parameter can be one of the following values:
* @arg @ref LCD_FLAG_SOF Start of frame interrupt enable
* @arg @ref LCD_FLAG_UDD Update display done interrupt
* @retval The new state of the LCD_IT
*/
it_status_t lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_FLAG_TYPE(flag));
return hperh->perh->IF & flag ? SET : RESET;
}
/**
* @brief Clear interrupt state flag
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @param flag: Specifies the interrupt type to clear
* This parameter can be one of the following values:
* @arg @ref LCD_FLAG_SOF Start of frame interrupt enable
* @arg @ref LCD_FLAG_UDD Update display done interrupt
* @retval Status, see @ref ald_status_t.
*/
ald_status_t lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
{
assert_param(IS_LCD_PERH_TYPE(hperh->perh));
assert_param(IS_LCD_FLAG_TYPE(flag));
__LOCK(hperh);
WRITE_REG(hperh->perh->IFCR, flag);
__UNLOCK(hperh);
return OK;
}
/**
* @brief This function handles LCD event interrupt request.
* @param hperh: Pointer to a lcd_handle_t structure that contains
* the configuration information for the specified LCD.
* @retval None
*/
void lcd_irq_handler(lcd_handle_t *hperh)
{
if (lcd_get_flag_status(hperh, LCD_FLAG_UDD)) {
lcd_clear_flag_status(hperh, LCD_FLAG_UDD);
if (hperh->display_cplt_cbk)
hperh->display_cplt_cbk(hperh);
}
if (lcd_get_flag_status(hperh, LCD_FLAG_SOF)) {
lcd_clear_flag_status(hperh, LCD_FLAG_SOF);
if (hperh->frame_start_cbk)
hperh->frame_start_cbk(hperh);
}
return;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_LCD */
/**
* @}
*/
/**
* @}
*/

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/**
*********************************************************************************
*
* @file ald_pis.c
* @brief PIS module driver.
*
* @version V1.0
* @date 27 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_pis.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup PIS PIS
* @brief PIS module driver
* @{
*/
#ifdef ALD_PIS
/** @defgroup PIS_Public_Functions PIS Public Functions
* @{
*/
/** @defgroup PIS_Public_Functions_Group1 Initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/**
* @brief Create the PIS mode according to the specified parameters in
* the pis_handle_t and create the associated handle.
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t pis_create(pis_handle_t *hperh)
{
pis_divide_t temp;
uint8_t clock_menu = 0;
if (hperh == NULL)
return ERROR;
assert_param(IS_PIS_SRC(hperh->init.producer_src));
assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
__LOCK(hperh);
hperh->perh = PIS;
/* get location of consumer in channel and position of con0/con1
* accord to comsumer_trig information */
temp.HalfWord = (hperh->init.consumer_trig);
hperh->consumer_ch = (pis_ch_t)(temp.ch);
hperh->consumer_con = (pis_con_t)(temp.con);
hperh->consumer_pos = (1 << temp.shift);
/* union producer clock and consumer clock */
clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk);
if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
__UNLOCK(hperh);
return BUSY;
}
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
/* configure sync clock, judging by producer clock with consumer clock */
switch (clock_menu) {
case 0x00:
case 0x11:
case 0x22:
case 0x33:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x01:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x02:
case 0x12:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x21:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x30:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x31:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x32:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS);
default:
break;
}
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
/* enable consumer bit, switch pin of consumer */
switch (hperh->consumer_con) {
case PIS_CON_0:
PIS->TAR_CON0 |= hperh->consumer_pos;
break;
case PIS_CON_1:
PIS->TAR_CON1 |= hperh->consumer_pos;
break;
default:
break;
}
__UNLOCK(hperh);
return OK;
}
/**
* @brief Destroy the PIS mode according to the specified parameters in
* the pis_init_t and create the associated handle.
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t pis_destroy(pis_handle_t *hperh)
{
assert_param(IS_PIS(hperh->perh));
if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
return ERROR;
__LOCK(hperh);
CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch));
WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
switch (hperh->consumer_con) {
case PIS_CON_0:
PIS->TAR_CON0 &= ~(hperh->consumer_pos);
break;
case PIS_CON_1:
PIS->TAR_CON1 &= ~(hperh->consumer_pos);
break;
default:
break;
}
hperh->state = PIS_STATE_RESET;
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup PIS_Public_Functions_Group2 Operation functions
* @brief PIS output enable or disable functions
* @{
*/
/**
* @brief Start the PIS output function.
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @param ch: The PIS channel enable output
* This parameter can be one of the following values:
* @arg PIS_OUT_CH_0
* @arg PIS_OUT_CH_1
* @arg PIS_OUT_CH_2
* @arg PIS_OUT_CH_3
* @retval Status, see @ref ald_status_t.
*/
ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
{
assert_param(IS_PIS(hperh->perh));
assert_param(IS_PIS_OUPUT_CH(ch));
__LOCK(hperh);
SET_BIT(PIS->CH_OER, (1 << ch));
__UNLOCK(hperh);
return OK;
}
/**
* @brief Stop the PIS output function.
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @param ch: The PIS channel disable output
* This parameter can be one of the following values:
* @arg PIS_OUT_CH_0
* @arg PIS_OUT_CH_1
* @arg PIS_OUT_CH_2
* @arg PIS_OUT_CH_3
* @retval Status, see @ref ald_status_t.
*/
ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
{
assert_param(IS_PIS(hperh->perh));
assert_param(IS_PIS_OUPUT_CH(ch));
__LOCK(hperh);
CLEAR_BIT(PIS->CH_OER, (1 << ch));
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions
* @brief PIS State and Errors functions
* @{
*/
/**
* @brief Returns the PIS state.
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @retval ALD state
*/
pis_state_t pis_get_state(pis_handle_t *hperh)
{
assert_param(IS_PIS(hperh->perh));
return hperh->state;
}
/**
* @}
*/
/** @defgroup PIS_Public_Functions_Group4 modulate output functions
* @brief PIS modulate output signal functions
* @{
*/
/**
* @brief Config the PIS modulate signal function
* @param hperh: Pointer to a pis_handle_t structure that contains
* the configuration information for the specified PIS module.
* @param config: Pointer to a pis_modulate_config_t structure that
* contains the selected target (UART0,UART1,UART2,UART3 or
* LPUART0) how to modulate the target output signal.
* @retval Status, see @ref ald_status_t.
*/
ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
{
assert_param(IS_PIS(hperh->perh));
assert_param(IS_PIS_MODU_TARGET(config->target));
assert_param(IS_PIS_MODU_LEVEL(config->level));
assert_param(IS_PIS_MODU_SRC(config->src));
assert_param(IS_PIS_MODU_CHANNEL(config->channel));
__LOCK(hperh);
switch (config->target) {
case PIS_UART0_TX:
MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
break;
case PIS_UART1_TX:
MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
break;
case PIS_UART2_TX:
MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
break;
case PIS_UART3_TX:
MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
break;
case PIS_LPUART0_TX:
MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
break;
default:
break;
}
__UNLOCK(hperh);
return OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_PIS */
/**
* @}
*/
/**
* @}
*/

283
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c
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@@ -1,283 +0,0 @@
/**
*********************************************************************************
*
* @file ald_pmu.c
* @brief PMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_pmu.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup PMU PMU
* @brief PMU module driver
* @{
*/
#ifdef ALD_PMU
/** @defgroup PMU_Private_Functions PMU Private Functions
* @{
*/
/**
* @brief PMU module interrupt handler
* @retval None
*/
void LVD_Handler(void)
{
SYSCFG_UNLOCK();
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
SYSCFG_LOCK();
lvd_irq_cbk();
return;
}
/**
* @}
*/
/** @defgroup PMU_Public_Functions PMU Public Functions
* @{
*/
/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode
* @brief Low power mode select functions
*
* @verbatim
==============================================================================
##### Low power mode select functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Enter stop1 mode.
(+) Enter stop2 mode.
(+) Enter standby mode.
(+) Get wakeup status.
(+) Clear wakeup status.
@endverbatim
* @{
*/
/**
* @brief Enter stop1 mode
* @retval None
*/
void pmu_stop1_enter(void)
{
SYSCFG_UNLOCK();
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS);
SYSCFG_LOCK();
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
return;
}
/**
* @brief Enter stop2 mode
* @retval None
*/
void pmu_stop2_enter(void)
{
SYSCFG_UNLOCK();
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS);
SYSCFG_LOCK();
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
return;
}
/**
* @brief Enter standby mode
* @param port: The port whick wake up the standby mode.
* @retval None
*/
void pmu_standby_enter(pmu_standby_wakeup_sel_t port)
{
assert_param(IS_PMU_STANDBY_PORT_SEL(port));
if (port != PMU_STANDBY_PORT_NONE) {
BKPC_UNLOCK();
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
BKPC_LOCK();
SYSCFG_UNLOCK();
MODIFY_REG(PMU->CR, PMU_CR_WKPS_MSK, port << PMU_CR_WKPS_POSS);
SET_BIT(PMU->CR, PMU_CR_WKPEN_MSK);
MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS);
SYSCFG_LOCK();
}
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
return;
}
/**
* @brief Configures low power mode. The system clock must
* be less than 2MHz. Such as: LOSC or LRC.
* @param vol: LDO output voltage select in low power mode.
* @param state: New state, ENABLE/DISABLE;
* @retval None
*/
void pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
{
assert_param(IS_FUNC_STATE(state));
SYSCFG_UNLOCK();
if (state) {
assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS);
SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
}
else {
CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
}
SYSCFG_LOCK();
return;
}
/**
* @brief Get wakup status.
* @param sr: Status bit.
* @retval Status.
*/
flag_status_t pmu_get_status(pmu_status_t sr)
{
assert_param(IS_PMU_STATUS(sr));
if (READ_BIT(PMU->SR, sr))
return SET;
return RESET;
}
/**
* @brief Clear wakup status.
* @param sr: Status bit.
* @retval None
*/
void pmu_clear_status(pmu_status_t sr)
{
assert_param(IS_PMU_STATUS(sr));
SYSCFG_UNLOCK();
if (sr == PMU_SR_WUF)
SET_BIT(PMU->CR, PMU_CR_CWUF_MSK);
else
SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK);
SYSCFG_LOCK();
return;
}
/**
* @}
*/
/** @addtogroup PMU_Public_Functions_Group2 LVD Configure
* @brief LVD configure functions
*
* @verbatim
==============================================================================
##### LVD configure functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure lvd parameters.
(+) Interrupt callback function.
@endverbatim
* @{
*/
/**
* @brief Configure lvd using specified parameters.
* @param sel: LVD threshold voltage.
* @param mode: LVD trigger mode.
* @param state: New state, ENABLE/DISABLE;
* @retval None
*/
void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
{
assert_param(IS_FUNC_STATE(state));
SYSCFG_UNLOCK();
if (state) {
assert_param(IS_PMU_LVD_VOL_SEL(sel));
assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
}
else {
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
}
SYSCFG_LOCK();
return;
}
/**
* @brief Interrupt callback function.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void lvd_irq_cbk(void)
{
return;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_PMU */
/**
* @}
*/
/**
* @}
*/

143
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c
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@@ -1,143 +0,0 @@
/**
*********************************************************************************
*
* @file ald_rmu.c
* @brief RMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_rmu.h"
#include "ald_syscfg.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup RMU RMU
* @brief RMU module driver
* @{
*/
#ifdef ALD_RMU
/** @defgroup RMU_Public_Functions RMU Public Functions
* @{
*/
/**
* @brief Configure BOR parameters.
* @param flt: filter time.
* @param vol: The voltage.
* @param state: The new status: ENABLE/DISABLE.
* @retval None
*/
void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
{
assert_param(IS_FUNC_STATE(state));
SYSCFG_UNLOCK();
if (state) {
assert_param(IS_RMU_BORFLT(flt));
assert_param(IS_RMU_BORVOL(vol));
MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
}
else {
CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
}
SYSCFG_LOCK();
return;
}
/**
* @brief Get specified reset status
* @param state: Speicifies the type of the reset,
* @retval The status: SET/RESET.
*/
flag_status_t rmu_get_reset_status(rmu_state_t state)
{
assert_param(IS_RMU_STATE(state));
if (READ_BIT(RMU->RSTSR, state))
return SET;
return RESET;
}
/**
* @brief Clear the specified reset status
* @param state: Specifies the type of the reset,
* @retval None
*/
void rmu_clear_reset_status(rmu_state_t state)
{
assert_param(IS_RMU_STATE_CLEAR(state));
SYSCFG_UNLOCK();
WRITE_REG(RMU->CRSTSR, state);
SYSCFG_LOCK();
return;
}
/**
* @brief Reset peripheral device
* @param perh: The peripheral device,
* @retval None
*/
void rmu_reset_periperal(rmu_peripheral_t perh)
{
uint32_t idx, pos;
assert_param(IS_RMU_PERH(perh));
idx = (perh >> 27) & 0x7;
pos = perh & ~(0x7 << 27);
SYSCFG_UNLOCK();
switch (idx) {
case 0:
WRITE_REG(RMU->AHB1RSTR, pos);
break;
case 1:
WRITE_REG(RMU->AHB2RSTR, pos);
break;
case 2:
WRITE_REG(RMU->APB1RSTR, pos);
break;
case 4:
WRITE_REG(RMU->APB2RSTR, pos);
break;
default:
break;
}
SYSCFG_LOCK();
return;
}
/**
* @}
*/
#endif /* ALD_RMU */
/**
* @}
*/
/**
* @}
*/

1193
bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c
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