Merge pull request #1985 from Bluebear233/m487

[BSP]add NUVOTON M487 BSP

bsp/nuvoton_m487/.config

@@ -0,0 +1,328 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+# CONFIG_RT_USING_MESSAGEQUEUE is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=1024
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+# CONFIG_DFS_USING_WORKDIR is not set
+CONFIG_DFS_FILESYSTEMS_MAX=1
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=64
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP210 is not set
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=19
+CONFIG_RT_LWIP_PBUF_NUM=0
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=19
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=2920
+CONFIG_RT_LWIP_TCP_WND=2920
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=768
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# system packages
+#
+
+#
+# RT-Thread GUI Engine
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_IPERF is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set

bsp/nuvoton_m487/Kconfig

@@ -0,0 +1,25 @@
+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+source "$BSP_DIR/driver/Kconfig"
+

bsp/nuvoton_m487/README.md

@@ -0,0 +1,66 @@
+# NuMaker-PFM-M487
+
+## 1. 简介
+
+核心板板载主要资源如下：
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| M487JIDAE |
+|CPU| ARM Cortex-M4 |
+|主频| 192MHz |
+|片内SRAM| 160kB |
+|片内Flash| 512kB |
+|SPI FLASH| W25Q32 |
+|PHY| IP101GR |
+|Audio Codec| NAU88L25 |
+
+
+## 2. 编译说明
+
+板级包支持MDK4工程生成、GCC编译器，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本                   |
+| ---------- | ---------------------------- |
+| MDK4       | 4.73                         |
+| GCC        | GCC 5.4.1 20160919 (release) |
+
+使用MDK4打开工程需要安装Nu-Link_Keil_Driver
+
+## 3. 烧写及执行
+
+连接好串口，可以使用115200-N-8-1的配置方式连接到设备上。设备使用的串口引脚是：`[Tx:PB13  Rx:PB12]`
+
+当正确编译产生出rtthread.bin映像文件后，可以使用NU-link或者JLINK下载
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+### 4.1 IO在板级支持包中的映射情况
+
+| IO号 | 板级包中的定义 |
+| -- | -- |
+| PH0 | LED_R |
+| PH1 | LED_Y |
+| PH2 | LED_G |
+| PG15 | KEY2 |
+| PF11| KEY3 |
+
+## 5. 联系人信息
+
+维护人：[bluebear233](https://github.com/bluebear233)
+
+## 6. 参考
+
+* 板子[数据手册][1]
+* 芯片[数据手册][2]
+
+  [1]: http://www.nuvoton.com/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.00.pdf
+  [2]: http://www.nuvoton.com/resource-files/TRM_M480_Series_EN_Rev1.01.pdf

bsp/nuvoton_m487/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/nuvoton_m487/SConstruct

@@ -0,0 +1,35 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-m487.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/nuvoton_m487/applications/SConscript

@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nuvoton_m487/applications/main.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char** argv)
+{
+    printf("Hello RT-Thread!\n");
+
+    return 0;
+}

bsp/nuvoton_m487/applications/mnt.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rtthread.h>
+
+int mnt_init(void)
+{
+    return 0;
+}

bsp/nuvoton_m487/driver/Kconfig

@@ -0,0 +1 @@
+  

bsp/nuvoton_m487/driver/SConscript

@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+''')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nuvoton_m487/driver/board.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#include <rtconfig.h>
+#include <rtthread.h>
+#include <rthw.h>
+#include "NuMicro.h"
+#include "drv_uart.h"
+#include "board.h"
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+extern int __ram_top;
+#endif
+
+/**
+ * This function will initial Clock tree.
+ */
+static void clock_init(void)
+{
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+
+    SystemInit();
+
+    /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
+    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+
+    /* Enable External XTAL (4~24 MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+
+    /* Waiting for 12MHz clock ready */
+    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
+
+    /* Switch HCLK clock source to HXT */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
+
+    /* Set core clock as PLL_CLOCK from PLL */
+    CLK_SetCoreClock(FREQ_192MHZ);
+
+    /* Set both PCLK0 and PCLK1 as HCLK/4 */
+    CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;
+
+    SystemCoreClockUpdate();
+
+    /* Lock protected registers */
+    SYS_LockReg();
+}
+
+/**
+ * This function will initial M487 board.
+ */
+void rt_hw_board_init(void)
+{
+    clock_init();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
+#endif
+#endif /* RT_USING_HEAP */
+
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+	
+	NVIC_SetPriorityGrouping(7);
+	
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_cpu_reset(void)
+{
+    SYS_UnlockReg();
+
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}

bsp/nuvoton_m487/driver/board.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+// <o> Internal SRAM memory size[Kbytes] <8-64>
+#define SRAM_SIZE         (160)
+#define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
+
+#define RT_UART_485_MODE      1
+#define RT_UART_FLOW_CTS_CTRL 2
+#define RT_UART_FLOW_RTS_CTRL 3
+#define RT_UART_CLEAR_BUF     4
+
+void rt_hw_pdma_init(void);
+void rt_hw_uart_handle(void);
+void rt_hw_sc_init(void);
+void rt_hw_usart_init(void);
+void rt_hw_uusart_init(void);
+void rt_hw_io_init(void);
+void phy_error_led(void);
+
+unsigned char *eth_get_default_mac(void);
+void eth_set_mac(const unsigned char * mac);
+void wdt_reload(void);
+unsigned int get_uid(void);
+
+#endif /* BOARD_H_ */

bsp/nuvoton_m487/driver/drv_uart.c

@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+
+#include <rtconfig.h>
+#include <rtdevice.h>
+#include <drv_uart.h>
+#include "NuMicro.h"
+
+/* Private Define ---------------------------------------------------------------*/
+#define USEING_UART0                    //Tx:PB13  Rx:PB12
+
+/* Private Typedef --------------------------------------------------------------*/
+struct usart
+{
+    rt_serial_t dev;
+    UART_T *usart_base;
+};
+typedef struct usart* usart_t;
+
+/* Private functions ------------------------------------------------------------*/
+
+
+static rt_err_t usart_gpio_configure(struct rt_serial_device *serial);
+static rt_err_t usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t usart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int usart_send(struct rt_serial_device *serial, char c);
+static int usart_receive(struct rt_serial_device *serial);
+static void rt_hw_uart_register(usart_t uart, UART_T *uart_base,
+        char *name);
+static void uart_isr(usart_t serial);
+
+/* Private Variables ------------------------------------------------------------*/
+static const struct rt_uart_ops m487_uart_ops =
+{ usart_configure, usart_control, usart_send, usart_receive,
+        RT_NULL };
+
+static const struct serial_configure m487_uart_default_config =
+RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef USEING_UART0
+struct usart uart0;
+#endif
+
+/* Interrupt Handle Funtion  ----------------------------------------------------*/
+#ifdef USEING_UART0
+/* 串口0 中断入口 */
+void UART0_IRQHandler(void)
+{
+    uart_isr(&uart0);
+}
+#endif
+
+/**
+ * 中断处理函数
+ */
+static void uart_isr(usart_t serial)
+{
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    // 获取中断事件
+    uint32_t u32IntSts= uart_base->INTSTS;
+
+    // 接收中断
+    if(u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk))
+    {
+        rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
+    }
+
+}
+
+/**
+ * 串口端口配置
+ */
+static rt_err_t usart_gpio_configure(struct rt_serial_device *serial)
+{
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    switch((uint32_t)uart_base)
+    {
+    case UART0_BASE:
+        SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk);
+        SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_UART0_RXD | SYS_GPB_MFPH_PB13MFP_UART0_TXD);
+        break;
+
+    default:
+        rt_kprintf("unknow uart module\n");
+        RT_ASSERT(0);
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * 串口配置
+ */
+static rt_err_t usart_configure(struct rt_serial_device *serial,
+        struct serial_configure *cfg)
+{
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    uint32_t uart_module = 0;
+    uint32_t uart_word_len = 0;
+    uint32_t uart_stop_bit = 0;
+    uint32_t uart_parity = 0;
+    IRQn_Type uart_irq_channel = 0;
+
+    switch((uint32_t)uart_base)
+    {
+    case UART0_BASE:
+        uart_module = UART0_MODULE;
+        uart_irq_channel = UART0_IRQn;
+        break;
+
+    default:
+        rt_kprintf("unknow uart module\n");
+        RT_ASSERT(0);
+    }
+
+    /* Enable IP clock */
+    CLK_EnableModuleClock(uart_module);
+
+    /* Select IP clock source */
+    CLK_SetModuleClock(uart_module, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
+
+    /* check baudrate */
+    RT_ASSERT(cfg->baud_rate != 0);
+
+    /* check word len */
+    switch(cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        uart_word_len = UART_WORD_LEN_5;
+        break;
+
+    case DATA_BITS_6:
+        uart_word_len = UART_WORD_LEN_6;
+        break;
+
+    case DATA_BITS_7:
+        uart_word_len = UART_WORD_LEN_7;
+        break;
+
+    case DATA_BITS_8:
+        uart_word_len = UART_WORD_LEN_8;
+        break;
+
+    default:
+        rt_kprintf("unsupose data len");
+        RT_ASSERT(0);
+    }
+
+    /* check stop bit */
+    switch(cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart_stop_bit = UART_STOP_BIT_1;
+        break;
+
+    case STOP_BITS_2:
+        uart_stop_bit = UART_STOP_BIT_2;
+        break;
+
+    default:
+        rt_kprintf("unsupose stop bit");
+        RT_ASSERT(0);
+    }
+
+    /* check stop bit */
+    switch(cfg->parity)
+    {
+    case PARITY_NONE:
+        uart_parity = UART_PARITY_NONE;
+        break;
+
+    case PARITY_ODD:
+        uart_parity = UART_PARITY_ODD;
+        break;
+
+    case PARITY_EVEN:
+        uart_parity = UART_PARITY_EVEN;
+        break;
+
+    default:
+        rt_kprintf("unsupose parity");
+        RT_ASSERT(0);
+    }
+
+    /* Open uart */
+    {
+        uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+        uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
+        uint32_t u32Baud_Div = 0ul;
+
+        if(uart_base == (UART_T*)UART0 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+        }
+        else if(uart_base == (UART_T*)UART1 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+        }
+        else if(uart_base == (UART_T*)UART2 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+        }
+        else if(uart_base == (UART_T*)UART3 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+        }
+        else if(uart_base == (UART_T*)UART4 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+        }
+        else if(uart_base == (UART_T*)UART5 )
+        {
+            /* Get UART clock source selection */
+            u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+            /* Get UART clock divider number */
+            u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+        }
+
+        /* Select UART function */
+        uart_base->FUNCSEL = UART_FUNCSEL_UART;
+
+        /* Set UART line configuration */
+        uart_base->LINE = uart_word_len | uart_stop_bit | uart_parity;
+
+        /* Set UART Rx and RTS trigger level */
+        uart_base->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+        /* Get PLL clock frequency if UART clock source selection is PLL */
+        if(u32UartClkSrcSel == 1ul)
+        {
+            u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+        }
+
+        /* Set UART baud rate */
+        if(cfg->baud_rate != 0ul)
+        {
+            u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate);
+
+            if(u32Baud_Div > 0xFFFFul)
+            {
+                uart_base->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate));
+            }
+            else
+            {
+                uart_base->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+            }
+        }
+    }
+
+    /* config nvic */
+    NVIC_EnableIRQ(uart_irq_channel);
+
+    /* config gpio */
+    usart_gpio_configure(serial);
+
+    return RT_EOK;
+}
+
+/**
+ * 串口中断控制
+ */
+static rt_err_t usart_control(struct rt_serial_device *serial,
+        int cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t flag;
+
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    switch ((uint32_t) arg)
+    {
+    case RT_DEVICE_FLAG_INT_RX:
+        flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
+
+        switch (cmd)
+        {
+        case RT_DEVICE_CTRL_CLR_INT:
+            UART_DISABLE_INT(uart_base, flag);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            UART_ENABLE_INT(uart_base, flag);
+            break;
+        default:
+            RT_ASSERT(0);
+        }
+        break;
+// TODO 完善DMA接口
+//    case RT_DEVICE_FLAG_DMA_TX:
+//        USART_DMACmd(dev->usart_base, USART_DMAReq_Tx, ENABLE);
+//        stm32_uart_tx_dma_configure(dev, RT_TRUE);
+//        stm32_uart_tx_dma_nvic(dev, RT_TRUE);
+//        break;
+    default:
+        RT_ASSERT(0)
+        ;
+    }
+
+    return result;
+}
+
+/**
+ * 串口发送函数
+ */
+static int usart_send(struct rt_serial_device *serial, char c)
+{
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    // 等待FIFO 发送
+    while(uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
+
+    // 发送字符
+    uart_base->DAT = c;
+
+    return 1;
+}
+
+/**
+ * 串口接收函数
+ */
+static int usart_receive(struct rt_serial_device *serial)
+{
+    // 获取串口基地址
+    UART_T *uart_base = ((usart_t)serial)->usart_base;
+
+    // 如果FIFO 为空返回
+    if(uart_base->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+    {
+        return -1;
+    }
+
+    return UART_READ(uart_base);
+}
+
+/**
+ * @brief 串口设备注册
+ * @param uart           : UART设备结构体
+ * @param uart_base      : STM32 UART外设基地址
+ * @param name           : STM32 UART设备名
+ * @param tx_dma_channel : STM32 UART TX的DMA通道基地址(可选)
+ */
+static void rt_hw_uart_register(usart_t usart, UART_T * uart_base, char *name)
+{
+    rt_uint32_t flag;
+    RT_ASSERT(usart != RT_NULL);
+    RT_ASSERT(uart_base != RT_NULL);
+
+    // 没有定义对应的硬件I2C
+    if (!(uart_base == UART0 || uart_base == UART1 || uart_base == UART2
+            || uart_base == UART3 || uart_base == UART4 || uart_base == UART5))
+    {
+        RT_ASSERT(0);
+    }
+
+    usart->usart_base = uart_base;
+    usart->dev.ops = &m487_uart_ops;
+    usart->dev.config = m487_uart_default_config;
+
+    flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
+
+    rt_hw_serial_register(&usart->dev, name,
+            flag, RT_NULL);
+}
+
+/**
+ * 硬件串口注册
+ */
+int rt_hw_uart_init(void)
+{
+#ifdef USEING_UART0
+    rt_hw_uart_register(&uart0, UART0, "uart0");
+#endif
+
+    return 0;
+}

bsp/nuvoton_m487/driver/drv_uart.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif /* __DRV_UART_H__ */

bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h

@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/nuvoton_m487/libraries/CMSIS/SConscript

@@ -0,0 +1,16 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+""")
+
+path = [cwd + '/Include',]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h

@@ -0,0 +1,15 @@
+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "M480.h"
+
+#endif  /* __NUMICRO_H__ */
+
+

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h

@@ -0,0 +1,239 @@
+/**************************************************************************//**
+ * @file     acmp_reg.h
+ * @version  V1.00
+ * @brief    ACMP register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ACMP_REG_H__
+#define __ACMP_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup ACMP Analog Comparator Controller(ACMP)
+    Memory Mapped Structure for ACMP Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var ACMP_T::CTL
+     * Offset: 0x00~0x04  Analog Comparator 0/1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPEN    |Comparator Enable Bit
+     * |        |          |0 = Comparator x Disabled.
+     * |        |          |1 = Comparator x Enabled.
+     * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+     * |        |          |0 = Comparator x interrupt Disabled.
+     * |        |          |1 = Comparator x interrupt Enabled
+     * |        |          |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+     * |[3]     |ACMPOINV  |Comparator Output Inverse
+     * |        |          |0 = Comparator x output inverse Disabled.
+     * |        |          |1 = Comparator x output inverse Enabled.
+     * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+     * |        |          |00 = ACMPx_N pin.
+     * |        |          |01 = Internal comparator reference voltage (CRV).
+     * |        |          |10 = Band-gap voltage.
+     * |        |          |11 = DAC output.
+     * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+     * |        |          |00 = Input from ACMPx_P0.
+     * |        |          |01 = Input from ACMPx_P1.
+     * |        |          |10 = Input from ACMPx_P2.
+     * |        |          |11 = Input from ACMPx_P3.
+     * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+     * |        |          |ACMPIFx will be set to 1 when comparator output edge condition is detected.
+     * |        |          |00 = Rising edge or falling edge.
+     * |        |          |01 = Rising edge.
+     * |        |          |10 = Falling edge.
+     * |        |          |11 = Reserved.
+     * |[12]    |OUTSEL    |Comparator Output Select
+     * |        |          |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
+     * |        |          |1 = Comparator x output to ACMPx_O pin is from filter output.
+     * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+     * |        |          |000 = Filter function is Disabled.
+     * |        |          |001 = ACMPx output is sampled 1 consecutive PCLK.
+     * |        |          |010 = ACMPx output is sampled 2 consecutive PCLKs.
+     * |        |          |011 = ACMPx output is sampled 4 consecutive PCLKs.
+     * |        |          |100 = ACMPx output is sampled 8 consecutive PCLKs.
+     * |        |          |101 = ACMPx output is sampled 16 consecutive PCLKs.
+     * |        |          |110 = ACMPx output is sampled 32 consecutive PCLKs.
+     * |        |          |111 = ACMPx output is sampled 64 consecutive PCLKs.
+     * |[16]    |WKEN      |Power-down Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[17]    |WLATEN    |Window Latch Mode Enable Bit
+     * |        |          |0 = Window Latch Mode Disabled.
+     * |        |          |1 = Window Latch Mode Enabled.
+     * |[18]    |WCMPSEL   |Window Compare Mode Selection
+     * |        |          |0 = Window Compare Mode Disabled.
+     * |        |          |1 = Window Compare Mode is Selected.
+     * |[25:24] |HYSSEL    |Hysteresis Mode Selection
+     * |        |          |00 = Hysteresis is 0mV.
+     * |        |          |01 = Hysteresis is 10mV.
+     * |        |          |10 = Hysteresis is 20mV.
+     * |        |          |11 = Hysteresis is 30mV.
+     * |[29:28] |MODESEL   |Propagation Delay Mode Selection
+     * |        |          |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
+     * |        |          |01 = Max propagation delay is 2uS, operation current is 3uA.
+     * |        |          |10 = Max propagation delay is 600nS, operation current is 10uA.
+     * |        |          |11 = Max propagation delay is 200nS, operation current is 75uA.
+     * @var ACMP_T::STATUS
+     * Offset: 0x08  Analog Comparator Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPIF0   |Comparator 0 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8])
+     * |        |          |is detected on comparator 0 output.
+     * |        |          |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |ACMPIF1   |Comparator 1 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8])
+     * |        |          |is detected on comparator 1 output.
+     * |        |          |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |ACMPO0    |Comparator 0 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[5]     |ACMPO1    |Comparator 1 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software.
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[8]     |WKIF0     |Comparator 0 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |WKIF1     |Comparator 1 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |ACMPS0    |Comparator 0 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[13]    |ACMPS1    |Comparator 1 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[16]    |ACMPWO    |Comparator Window Output
+     * |        |          |This bit shows the output status of window compare mode
+     * |        |          |0 = The positive input voltage is outside the window.
+     * |        |          |1 = The positive input voltage is in the window.
+     * @var ACMP_T::VREF
+     * Offset: 0x0C  Analog Comparator Reference Voltage Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CRVCTL    |Comparator Reference Voltage Setting
+     * |        |          |CRV = CRV source voltage * (1/6+CRVCTL/24).
+     * |[6]     |CRVSSEL   |CRV Source Voltage Selection
+     * |        |          |0 = VDDA is selected as CRV source voltage.
+     * |        |          |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+     */
+    __IO uint32_t CTL[2];                /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register                    */
+    __IO uint32_t STATUS;                /*!< [0x0008] Analog Comparator Status Register                                */
+    __IO uint32_t VREF;                  /*!< [0x000c] Analog Comparator Reference Voltage Control Register             */
+
+} ACMP_T;
+
+/**
+    @addtogroup ACMP_CONST ACMP Bit Field Definition
+    Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos              (0)                                               /*!< ACMP_T::CTL: ACMPEN Position           */
+#define ACMP_CTL_ACMPEN_Msk              (0x1ul << ACMP_CTL_ACMPEN_Pos)                    /*!< ACMP_T::CTL: ACMPEN Mask               */
+
+#define ACMP_CTL_ACMPIE_Pos              (1)                                               /*!< ACMP_T::CTL: ACMPIE Position           */
+#define ACMP_CTL_ACMPIE_Msk              (0x1ul << ACMP_CTL_ACMPIE_Pos)                    /*!< ACMP_T::CTL: ACMPIE Mask               */
+
+#define ACMP_CTL_ACMPOINV_Pos            (3)                                               /*!< ACMP_T::CTL: ACMPOINV Position         */
+#define ACMP_CTL_ACMPOINV_Msk            (0x1ul << ACMP_CTL_ACMPOINV_Pos)                  /*!< ACMP_T::CTL: ACMPOINV Mask             */
+
+#define ACMP_CTL_NEGSEL_Pos              (4)                                               /*!< ACMP_T::CTL: NEGSEL Position           */
+#define ACMP_CTL_NEGSEL_Msk              (0x3ul << ACMP_CTL_NEGSEL_Pos)                    /*!< ACMP_T::CTL: NEGSEL Mask               */
+
+#define ACMP_CTL_POSSEL_Pos              (6)                                               /*!< ACMP_T::CTL: POSSEL Position           */
+#define ACMP_CTL_POSSEL_Msk              (0x3ul << ACMP_CTL_POSSEL_Pos)                    /*!< ACMP_T::CTL: POSSEL Mask               */
+
+#define ACMP_CTL_INTPOL_Pos              (8)                                               /*!< ACMP_T::CTL: INTPOL Position           */
+#define ACMP_CTL_INTPOL_Msk              (0x3ul << ACMP_CTL_INTPOL_Pos)                    /*!< ACMP_T::CTL: INTPOL Mask               */
+
+#define ACMP_CTL_OUTSEL_Pos              (12)                                              /*!< ACMP_T::CTL: OUTSEL Position           */
+#define ACMP_CTL_OUTSEL_Msk              (0x1ul << ACMP_CTL_OUTSEL_Pos)                    /*!< ACMP_T::CTL: OUTSEL Mask               */
+
+#define ACMP_CTL_FILTSEL_Pos             (13)                                              /*!< ACMP_T::CTL: FILTSEL Position          */
+#define ACMP_CTL_FILTSEL_Msk             (0x7ul << ACMP_CTL_FILTSEL_Pos)                   /*!< ACMP_T::CTL: FILTSEL Mask              */
+
+#define ACMP_CTL_WKEN_Pos                (16)                                              /*!< ACMP_T::CTL: WKEN Position             */
+#define ACMP_CTL_WKEN_Msk                (0x1ul << ACMP_CTL_WKEN_Pos)                      /*!< ACMP_T::CTL: WKEN Mask                 */
+
+#define ACMP_CTL_WLATEN_Pos              (17)                                              /*!< ACMP_T::CTL: WLATEN Position           */
+#define ACMP_CTL_WLATEN_Msk              (0x1ul << ACMP_CTL_WLATEN_Pos)                    /*!< ACMP_T::CTL: WLATEN Mask               */
+
+#define ACMP_CTL_WCMPSEL_Pos             (18)                                              /*!< ACMP_T::CTL: WCMPSEL Position          */
+#define ACMP_CTL_WCMPSEL_Msk             (0x1ul << ACMP_CTL_WCMPSEL_Pos)                   /*!< ACMP_T::CTL: WCMPSEL Mask              */
+
+#define ACMP_CTL_HYSSEL_Pos              (24)                                              /*!< ACMP_T::CTL: HYSSEL Position           */
+#define ACMP_CTL_HYSSEL_Msk              (0x3ul << ACMP_CTL_HYSSEL_Pos)                    /*!< ACMP_T::CTL: HYSSEL Mask               */
+
+#define ACMP_CTL_MODESEL_Pos             (28)                                              /*!< ACMP_T::CTL: MODESEL Position          */
+#define ACMP_CTL_MODESEL_Msk             (0x3ul << ACMP_CTL_MODESEL_Pos)                   /*!< ACMP_T::CTL: MODESEL Mask              */
+
+#define ACMP_STATUS_ACMPIF0_Pos          (0)                                               /*!< ACMP_T::STATUS: ACMPIF0 Position       */
+#define ACMP_STATUS_ACMPIF0_Msk          (0x1ul << ACMP_STATUS_ACMPIF0_Pos)                /*!< ACMP_T::STATUS: ACMPIF0 Mask           */
+
+#define ACMP_STATUS_ACMPIF1_Pos          (1)                                               /*!< ACMP_T::STATUS: ACMPIF1 Position       */
+#define ACMP_STATUS_ACMPIF1_Msk          (0x1ul << ACMP_STATUS_ACMPIF1_Pos)                /*!< ACMP_T::STATUS: ACMPIF1 Mask           */
+
+#define ACMP_STATUS_ACMPO0_Pos           (4)                                               /*!< ACMP_T::STATUS: ACMPO0 Position        */
+#define ACMP_STATUS_ACMPO0_Msk           (0x1ul << ACMP_STATUS_ACMPO0_Pos)                 /*!< ACMP_T::STATUS: ACMPO0 Mask            */
+
+#define ACMP_STATUS_ACMPO1_Pos           (5)                                               /*!< ACMP_T::STATUS: ACMPO1 Position        */
+#define ACMP_STATUS_ACMPO1_Msk           (0x1ul << ACMP_STATUS_ACMPO1_Pos)                 /*!< ACMP_T::STATUS: ACMPO1 Mask            */
+
+#define ACMP_STATUS_WKIF0_Pos            (8)                                               /*!< ACMP_T::STATUS: WKIF0 Position         */
+#define ACMP_STATUS_WKIF0_Msk            (0x1ul << ACMP_STATUS_WKIF0_Pos)                  /*!< ACMP_T::STATUS: WKIF0 Mask             */
+
+#define ACMP_STATUS_WKIF1_Pos            (9)                                               /*!< ACMP_T::STATUS: WKIF1 Position         */
+#define ACMP_STATUS_WKIF1_Msk            (0x1ul << ACMP_STATUS_WKIF1_Pos)                  /*!< ACMP_T::STATUS: WKIF1 Mask             */
+
+#define ACMP_STATUS_ACMPS0_Pos           (12)                                              /*!< ACMP_T::STATUS: ACMPS0 Position        */
+#define ACMP_STATUS_ACMPS0_Msk           (0x1ul << ACMP_STATUS_ACMPS0_Pos)                 /*!< ACMP_T::STATUS: ACMPS0 Mask            */
+
+#define ACMP_STATUS_ACMPS1_Pos           (13)                                              /*!< ACMP_T::STATUS: ACMPS1 Position        */
+#define ACMP_STATUS_ACMPS1_Msk           (0x1ul << ACMP_STATUS_ACMPS1_Pos)                 /*!< ACMP_T::STATUS: ACMPS1 Mask            */
+
+#define ACMP_STATUS_ACMPWO_Pos           (16)                                              /*!< ACMP_T::STATUS: ACMPWO Position        */
+#define ACMP_STATUS_ACMPWO_Msk           (0x1ul << ACMP_STATUS_ACMPWO_Pos)                 /*!< ACMP_T::STATUS: ACMPWO Mask            */
+
+#define ACMP_VREF_CRVCTL_Pos             (0)                                               /*!< ACMP_T::VREF: CRVCTL Position          */
+#define ACMP_VREF_CRVCTL_Msk             (0xful << ACMP_VREF_CRVCTL_Pos)                   /*!< ACMP_T::VREF: CRVCTL Mask              */
+
+#define ACMP_VREF_CRVSSEL_Pos            (6)                                               /*!< ACMP_T::VREF: CRVSSEL Position         */
+#define ACMP_VREF_CRVSSEL_Msk            (0x1ul << ACMP_VREF_CRVSSEL_Pos)                  /*!< ACMP_T::VREF: CRVSSEL Mask             */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __ACMP_REG_H__ */

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h

@@ -0,0 +1,149 @@
+/**************************************************************************//**
+ * @file     crc_reg.h
+ * @version  V1.00
+ * @brief    CRC register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_REG_H__
+#define __CRC_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var CRC_T::CTL
+     * Offset: 0x00  CRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRCEN     |CRC Channel Enable Bit
+     * |        |          |0 = No effect.
+     * |        |          |1 = CRC operation Enabled.
+     * |[1]     |CHKSINIT  |Checksum Initialization
+     * |        |          |0 = No effect.
+     * |        |          |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
+     * |        |          |Note: This bit will be cleared automatically.
+     * |[24]    |DATREV    |Write Data Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
+     * |        |          |0 = Bit order reversed for CRC write data in Disabled.
+     * |        |          |1 = Bit order reversed for CRC write data in Enabled (per byte).
+     * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+     * |[25]    |CHKSREV   |Checksum Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = Bit order reverse for CRC checksum Disabled.
+     * |        |          |1 = Bit order reverse for CRC checksum Enabled.
+     * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+     * |[26]    |DATFMT    |Write Data 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+     * |        |          |0 = 1's complement for CRC writes data in Disabled.
+     * |        |          |1 = 1's complement for CRC writes data in Enabled.
+     * |[27]    |CHKSFMT   |Checksum 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = 1's complement for CRC checksum Disabled.
+     * |        |          |1 = 1's complement for CRC checksum Enabled.
+     * |[29:28] |DATLEN    |CPU Write Data Length
+     * |        |          |This field indicates the write data length.
+     * |        |          |00 = Data length is 8-bit mode.
+     * |        |          |01 = Data length is 16-bit mode.
+     * |        |          |1x = Data length is 32-bit mode.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+     * |[31:30] |CRCMODE   |CRC Polynomial Mode
+     * |        |          |This field indicates the CRC operation polynomial mode.
+     * |        |          |00 = CRC-CCITT Polynomial mode.
+     * |        |          |01 = CRC-8 Polynomial mode.
+     * |        |          |10 = CRC-16 Polynomial mode.
+     * |        |          |11 = CRC-32 Polynomial mode.
+     * @var CRC_T::DAT
+     * Offset: 0x04  CRC Write Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATA      |CRC Write Data Bits
+     * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+     * @var CRC_T::SEED
+     * Offset: 0x08  CRC Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |CRC Seed Value
+     * |        |          |This field indicates the CRC seed value.
+     * |        |          |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
+     * @var CRC_T::CHECKSUM
+     * Offset: 0x0C  CRC Checksum Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CHECKSUM  |CRC Checksum Results
+     * |        |          |This field indicates the CRC checksum result.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] CRC Control Register                                             */
+    __IO uint32_t DAT;                   /*!< [0x0004] CRC Write Data Register                                          */
+    __IO uint32_t SEED;                  /*!< [0x0008] CRC Seed Register                                                */
+    __I  uint32_t CHECKSUM;              /*!< [0x000c] CRC Checksum Register                                            */
+
+} CRC_T;
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position             */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                 */
+
+#define CRC_CTL_CHKSINIT_Pos             (1)                                               /*!< CRC_T::CTL: CHKSINIT Position          */
+#define CRC_CTL_CHKSINIT_Msk             (0x1ul << CRC_CTL_CHKSINIT_Pos)                   /*!< CRC_T::CTL: CHKSINIT Mask              */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position            */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position           */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask               */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position            */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position           */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask               */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position            */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position           */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask               */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position              */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                  */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position             */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                 */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position     */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask         */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRC_REG_H__ */

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h

@@ -0,0 +1,209 @@
+/**************************************************************************//**
+ * @file     dac_reg.h
+ * @version  V1.00
+ * @brief    DAC register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __DAC_REG_H__
+#define __DAC_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+  @{
+*/
+
+/**
+    @addtogroup DAC Digital to Analog Converter(DAC)
+    Memory Mapped Structure for DAC Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var DAC_T::CTL
+     * Offset: 0x00  DAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DACEN     |DAC Enable Bit
+     * |        |          |0 = DAC is Disabled.
+     * |        |          |1 = DAC is Enabled.
+     * |[1]     |DACIEN    |DAC Interrupt Enable Bit
+     * |        |          |0 = Interrupt is Disabled.
+     * |        |          |1 = Interrupt is Enabled.
+     * |[2]     |DMAEN     |DMA Mode Enable Bit
+     * |        |          |0 = DMA mode Disabled.
+     * |        |          |1 = DMA mode Enabled.
+     * |[3]     |DMAURIEN  |DMA Under-run Interrupt Enable Bit
+     * |        |          |0 = DMA under-run interrupt Disabled.
+     * |        |          |1 = DMA under-run interrupt Enabled.
+     * |[4]     |TRGEN     |Trigger Mode Enable Bit
+     * |        |          |0 = DAC event trigger mode Disabled.
+     * |        |          |1 = DAC event trigger mode Enabled.
+     * |[7:5]   |TRGSEL    |Trigger Source Selection
+     * |        |          |000 = Software trigger.
+     * |        |          |001 = External pin DAC0_ST trigger.
+     * |        |          |010 = Timer 0 trigger.
+     * |        |          |011 = Timer 1 trigger.
+     * |        |          |100 = Timer 2 trigger.
+     * |        |          |101 = Timer 3 trigger.
+     * |        |          |110 = EPWM0 trigger.
+     * |        |          |111 = EPWM1 trigger.
+     * |[8]     |BYPASS    |Bypass Buffer Mode
+     * |        |          |0 = Output voltage buffer Enabled.
+     * |        |          |1 = Output voltage buffer Disabled.
+     * |[10]    |LALIGN    |DAC Data Left-aligned Enabled Control
+     * |        |          |0 = Right alignment.
+     * |        |          |1 = Left alignment.
+     * |[13:12] |ETRGSEL   |External Pin Trigger Selection
+     * |        |          |00 = Low level trigger.
+     * |        |          |01 = High level trigger.
+     * |        |          |10 = Falling edge trigger.
+     * |        |          |11 = Rising edge trigger.
+     * |[15:14] |BWSEL     |DAC Data Bit-width Selection
+     * |        |          |00 = data is 12 bits.
+     * |        |          |01 = data is 8 bits.
+     * |        |          |Others = reserved.
+     * |[16]    |GRPEN     |DAC Group Mode Enable Bit
+     * |        |          |0 = DAC0 and DAC1 are not grouped.
+     * |        |          |1 = DAC0 and DAC1 are grouped.
+     * @var DAC_T::SWTRG
+     * Offset: 0x04  DAC Software Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SWTRG     |Software Trigger
+     * |        |          |0 = Software trigger Disabled.
+     * |        |          |1 = Software trigger Enabled.
+     * |        |          |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+     * @var DAC_T::DAT
+     * Offset: 0x08  DAC Data Holding Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DACDAT    |DAC 12-bit Holding Data
+     * |        |          |These bits are written by user software which specifies 12-bit conversion data for DAC output
+     * |        |          |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+     * |        |          |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+     * |        |          |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+     * @var DAC_T::DATOUT
+     * Offset: 0x0C  DAC Data Output Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DATOUT    |DAC 12-bit Output Data
+     * |        |          |These bits are current digital data for DAC output conversion.
+     * |        |          |It is loaded from DAC_DAT register and user cannot write it directly.
+     * @var DAC_T::STATUS
+     * Offset: 0x10  DAC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FINISH    |DAC Conversion Complete Finish Flag
+     * |        |          |0 = DAC is in conversion state.
+     * |        |          |1 = DAC conversion finish.
+     * |        |          |This bit set to 1 when conversion time counter counts to SETTLET
+     * |        |          |It is cleared to 0 when DAC starts a new conversion
+     * |        |          |User writes 1 to clear this bit to 0.
+     * |[1]     |DMAUDR    |DMA Under-run Interrupt Flag
+     * |        |          |0 = No DMA under-run error condition occurred.
+     * |        |          |1 = DMA under-run error condition occurred.
+     * |        |          |User writes 1 to clear this bit.
+     * |[8]     |BUSY      |DAC Busy Flag (Read Only)
+     * |        |          |0 = DAC is ready for next conversion.
+     * |        |          |1 = DAC is busy in conversion.
+     * |        |          |This is read only bit.
+     * @var DAC_T::TCTL
+     * Offset: 0x14  DAC Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |SETTLET   |DAC Output Settling Time
+     * |        |          |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+     * |        |          |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
+     * |        |          |SELTTLET = DAC controller clock speed x settling time.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] DAC Control Register                                             */
+    __IO uint32_t SWTRG;                 /*!< [0x0004] DAC Software Trigger Control Register                            */
+    __IO uint32_t DAT;                   /*!< [0x0008] DAC Data Holding Register                                        */
+    __I  uint32_t DATOUT;                /*!< [0x000c] DAC Data Output Register                                         */
+    __IO uint32_t STATUS;                /*!< [0x0010] DAC Status Register                                              */
+    __IO uint32_t TCTL;                  /*!< [0x0014] DAC Timing Control Register                                      */
+
+} DAC_T;
+
+/**
+    @addtogroup DAC_CONST DAC Bit Field Definition
+    Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos                (0)                                               /*!< DAC_T::CTL: DACEN Position             */
+#define DAC_CTL_DACEN_Msk                (0x1ul << DAC_CTL_DACEN_Pos)                      /*!< DAC_T::CTL: DACEN Mask                 */
+
+#define DAC_CTL_DACIEN_Pos               (1)                                               /*!< DAC_T::CTL: DACIEN Position            */
+#define DAC_CTL_DACIEN_Msk               (0x1ul << DAC_CTL_DACIEN_Pos)                     /*!< DAC_T::CTL: DACIEN Mask                */
+
+#define DAC_CTL_DMAEN_Pos                (2)                                               /*!< DAC_T::CTL: DMAEN Position             */
+#define DAC_CTL_DMAEN_Msk                (0x1ul << DAC_CTL_DMAEN_Pos)                      /*!< DAC_T::CTL: DMAEN Mask                 */
+
+#define DAC_CTL_DMAURIEN_Pos             (3)                                               /*!< DAC_T::CTL: DMAURIEN Position          */
+#define DAC_CTL_DMAURIEN_Msk             (0x1ul << DAC_CTL_DMAURIEN_Pos)                   /*!< DAC_T::CTL: DMAURIEN Mask              */
+
+#define DAC_CTL_TRGEN_Pos                (4)                                               /*!< DAC_T::CTL: TRGEN Position             */
+#define DAC_CTL_TRGEN_Msk                (0x1ul << DAC_CTL_TRGEN_Pos)                      /*!< DAC_T::CTL: TRGEN Mask                 */
+
+#define DAC_CTL_TRGSEL_Pos               (5)                                               /*!< DAC_T::CTL: TRGSEL Position            */
+#define DAC_CTL_TRGSEL_Msk               (0x7ul << DAC_CTL_TRGSEL_Pos)                     /*!< DAC_T::CTL: TRGSEL Mask                */
+
+#define DAC_CTL_BYPASS_Pos               (8)                                               /*!< DAC_T::CTL: BYPASS Position            */
+#define DAC_CTL_BYPASS_Msk               (0x1ul << DAC_CTL_BYPASS_Pos)                     /*!< DAC_T::CTL: BYPASS Mask                */
+
+#define DAC_CTL_LALIGN_Pos               (10)                                              /*!< DAC_T::CTL: LALIGN Position            */
+#define DAC_CTL_LALIGN_Msk               (0x1ul << DAC_CTL_LALIGN_Pos)                     /*!< DAC_T::CTL: LALIGN Mask                */
+
+#define DAC_CTL_ETRGSEL_Pos              (12)                                              /*!< DAC_T::CTL: ETRGSEL Position           */
+#define DAC_CTL_ETRGSEL_Msk              (0x3ul << DAC_CTL_ETRGSEL_Pos)                    /*!< DAC_T::CTL: ETRGSEL Mask               */
+
+#define DAC_CTL_BWSEL_Pos                (14)                                              /*!< DAC_T::CTL: BWSEL Position             */
+#define DAC_CTL_BWSEL_Msk                (0x3ul << DAC_CTL_BWSEL_Pos)                      /*!< DAC_T::CTL: BWSEL Mask                 */
+
+#define DAC_CTL_GRPEN_Pos                (16)                                              /*!< DAC_T::CTL: GRPEN Position             */
+#define DAC_CTL_GRPEN_Msk                (0x1ul << DAC_CTL_GRPEN_Pos)                      /*!< DAC_T::CTL: GRPEN Mask                 */
+
+#define DAC_SWTRG_SWTRG_Pos              (0)                                               /*!< DAC_T::SWTRG: SWTRG Position           */
+#define DAC_SWTRG_SWTRG_Msk              (0x1ul << DAC_SWTRG_SWTRG_Pos)                    /*!< DAC_T::SWTRG: SWTRG Mask               */
+
+#define DAC_DAT_DACDAT_Pos               (0)                                               /*!< DAC_T::DAT: DACDAT Position            */
+#define DAC_DAT_DACDAT_Msk               (0xfffful << DAC_DAT_DACDAT_Pos)                  /*!< DAC_T::DAT: DACDAT Mask                */
+
+#define DAC_DATOUT_DATOUT_Pos            (0)                                               /*!< DAC_T::DATOUT: DATOUT Position         */
+#define DAC_DATOUT_DATOUT_Msk            (0xffful << DAC_DATOUT_DATOUT_Pos)                /*!< DAC_T::DATOUT: DATOUT Mask             */
+
+#define DAC_STATUS_FINISH_Pos            (0)                                               /*!< DAC_T::STATUS: FINISH Position         */
+#define DAC_STATUS_FINISH_Msk            (0x1ul << DAC_STATUS_FINISH_Pos)                  /*!< DAC_T::STATUS: FINISH Mask             */
+
+#define DAC_STATUS_DMAUDR_Pos            (1)                                               /*!< DAC_T::STATUS: DMAUDR Position         */
+#define DAC_STATUS_DMAUDR_Msk            (0x1ul << DAC_STATUS_DMAUDR_Pos)                  /*!< DAC_T::STATUS: DMAUDR Mask             */
+
+#define DAC_STATUS_BUSY_Pos              (8)                                               /*!< DAC_T::STATUS: BUSY Position           */
+#define DAC_STATUS_BUSY_Msk              (0x1ul << DAC_STATUS_BUSY_Pos)                    /*!< DAC_T::STATUS: BUSY Mask               */
+
+#define DAC_TCTL_SETTLET_Pos             (0)                                               /*!< DAC_T::TCTL: SETTLET Position          */
+#define DAC_TCTL_SETTLET_Msk             (0x3fful << DAC_TCTL_SETTLET_Pos)                 /*!< DAC_T::TCTL: SETTLET Mask              */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __DAC_REG_H__ */

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h

@@ -0,0 +1,428 @@
+/**************************************************************************//**
+ * @file     ebi_reg.h
+ * @version  V1.00
+ * @brief    EBI register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_REG_H__
+#define __EBI_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup EBI External Bus Interface Controller(EBI)
+    Memory Mapped Structure for EBI Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var EBI_T::CTL0
+     * Offset: 0x00  External Bus Interface Bank0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL0
+     * Offset: 0x04  External Bus Interface Bank0 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     * @var EBI_T::CTL1
+     * Offset: 0x10  External Bus Interface Bank1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL1
+     * Offset: 0x14  External Bus Interface Bank1 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     * @var EBI_T::CTL2
+     * Offset: 0x20  External Bus Interface Bank2 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL2
+     * Offset: 0x24  External Bus Interface Bank2 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] External Bus Interface Bank0 Control Register                    */
+    __IO uint32_t TCTL0;                 /*!< [0x0004] External Bus Interface Bank0 Timing Control Register             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL1;                  /*!< [0x0010] External Bus Interface Bank1 Control Register                    */
+    __IO uint32_t TCTL1;                 /*!< [0x0014] External Bus Interface Bank1 Timing Control Register             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL2;                  /*!< [0x0020] External Bus Interface Bank2 Control Register                    */
+    __IO uint32_t TCTL2;                 /*!< [0x0024] External Bus Interface Bank2 Timing Control Register             */
+
+} EBI_T;
+
+/**
+    @addtogroup EBI_CONST EBI Bit Field Definition
+    Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_CTL_EN_Pos                   (0)                                               /*!< EBI_T::CTL: EN Position                */
+#define EBI_CTL_EN_Msk                   (0x1ul << EBI_CTL_EN_Pos)                         /*!< EBI_T::CTL: EN Mask                    */
+
+#define EBI_CTL_DW16_Pos                 (1)                                               /*!< EBI_T::CTL: DW16 Position              */
+#define EBI_CTL_DW16_Msk                 (0x1ul << EBI_CTL_DW16_Pos)                       /*!< EBI_T::CTL: DW16 Mask                  */
+
+#define EBI_CTL_CSPOLINV_Pos             (2)                                               /*!< EBI_T::CTL: CSPOLINV Position          */
+#define EBI_CTL_CSPOLINV_Msk             (0x1ul << EBI_CTL_CSPOLINV_Pos)                   /*!< EBI_T::CTL: CSPOLINV Mask              */
+
+#define EBI_CTL_ADSEPEN_Pos              (3)                                               /*!< EBI_T::CTL: ADSEPEN Position           */
+#define EBI_CTL_ADSEPEN_Msk              (0x1ul << EBI_CTL_ADSEPEN_Pos)                    /*!< EBI_T::CTL: ADSEPEN Mask               */
+
+#define EBI_CTL_CACCESS_Pos              (4)                                               /*!< EBI_T::CTL: CACCESS Position           */
+#define EBI_CTL_CACCESS_Msk              (0x1ul << EBI_CTL_CACCESS_Pos)                    /*!< EBI_T::CTL: CACCESS Mask               */
+
+#define EBI_CTL_MCLKDIV_Pos              (8)                                               /*!< EBI_T::CTL: MCLKDIV Position           */
+#define EBI_CTL_MCLKDIV_Msk              (0x7ul << EBI_CTL_MCLKDIV_Pos)                    /*!< EBI_T::CTL: MCLKDIV Mask               */
+
+#define EBI_CTL_TALE_Pos                 (16)                                              /*!< EBI_T::CTL: TALE Position              */
+#define EBI_CTL_TALE_Msk                 (0x7ul << EBI_CTL_TALE_Pos)                       /*!< EBI_T::CTL: TALE Mask                  */
+
+#define EBI_CTL_WBUFEN_Pos               (24)                                              /*!< EBI_T::CTL: WBUFEN Position            */
+#define EBI_CTL_WBUFEN_Msk               (0x1ul << EBI_CTL_WBUFEN_Pos)                     /*!< EBI_T::CTL: WBUFEN Mask                */
+
+#define EBI_TCTL_TACC_Pos                (3)                                               /*!< EBI_T::TCTL: TACC Position             */
+#define EBI_TCTL_TACC_Msk                (0x1ful << EBI_TCTL_TACC_Pos)                     /*!< EBI_T::TCTL: TACC Mask                 */
+
+#define EBI_TCTL_TAHD_Pos                (8)                                               /*!< EBI_T::TCTL: TAHD Position             */
+#define EBI_TCTL_TAHD_Msk                (0x7ul << EBI_TCTL_TAHD_Pos)                      /*!< EBI_T::TCTL: TAHD Mask                 */
+
+#define EBI_TCTL_W2X_Pos                 (12)                                              /*!< EBI_T::TCTL: W2X Position              */
+#define EBI_TCTL_W2X_Msk                 (0xful << EBI_TCTL_W2X_Pos)                       /*!< EBI_T::TCTL: W2X Mask                  */
+
+#define EBI_TCTL_RAHDOFF_Pos             (22)                                              /*!< EBI_T::TCTL: RAHDOFF Position          */
+#define EBI_TCTL_RAHDOFF_Msk             (0x1ul << EBI_TCTL_RAHDOFF_Pos)                   /*!< EBI_T::TCTL: RAHDOFF Mask              */
+
+#define EBI_TCTL_WAHDOFF_Pos             (23)                                              /*!< EBI_T::TCTL: WAHDOFF Position          */
+#define EBI_TCTL_WAHDOFF_Msk             (0x1ul << EBI_TCTL_WAHDOFF_Pos)                   /*!< EBI_T::TCTL: WAHDOFF Mask              */
+
+#define EBI_TCTL_R2R_Pos                 (24)                                              /*!< EBI_T::TCTL: R2R Position              */
+#define EBI_TCTL_R2R_Msk                 (0xful << EBI_TCTL_R2R_Pos)                       /*!< EBI_T::TCTL: R2R Mask                  */
+
+#define EBI_CTL0_EN_Pos                  (0)                                               /*!< EBI_T::CTL0: EN Position               */
+#define EBI_CTL0_EN_Msk                  (0x1ul << EBI_CTL0_EN_Pos)                        /*!< EBI_T::CTL0: EN Mask                   */
+
+#define EBI_CTL0_DW16_Pos                (1)                                               /*!< EBI_T::CTL0: DW16 Position             */
+#define EBI_CTL0_DW16_Msk                (0x1ul << EBI_CTL0_DW16_Pos)                      /*!< EBI_T::CTL0: DW16 Mask                 */
+
+#define EBI_CTL0_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL0: CSPOLINV Position         */
+#define EBI_CTL0_CSPOLINV_Msk            (0x1ul << EBI_CTL0_CSPOLINV_Pos)                  /*!< EBI_T::CTL0: CSPOLINV Mask             */
+
+#define EBI_CTL0_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL0: ADSEPEN Position          */
+#define EBI_CTL0_ADSEPEN_Msk             (0x1ul << EBI_CTL0_ADSEPEN_Pos)                   /*!< EBI_T::CTL0: ADSEPEN Mask              */
+
+#define EBI_CTL0_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL0: CACCESS Position          */
+#define EBI_CTL0_CACCESS_Msk             (0x1ul << EBI_CTL0_CACCESS_Pos)                   /*!< EBI_T::CTL0: CACCESS Mask              */
+
+#define EBI_CTL0_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL0: MCLKDIV Position          */
+#define EBI_CTL0_MCLKDIV_Msk             (0x7ul << EBI_CTL0_MCLKDIV_Pos)                   /*!< EBI_T::CTL0: MCLKDIV Mask              */
+
+#define EBI_CTL0_TALE_Pos                (16)                                              /*!< EBI_T::CTL0: TALE Position             */
+#define EBI_CTL0_TALE_Msk                (0x7ul << EBI_CTL0_TALE_Pos)                      /*!< EBI_T::CTL0: TALE Mask                 */
+
+#define EBI_CTL0_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL0: WBUFEN Position           */
+#define EBI_CTL0_WBUFEN_Msk              (0x1ul << EBI_CTL0_WBUFEN_Pos)                    /*!< EBI_T::CTL0: WBUFEN Mask               */
+
+#define EBI_TCTL0_TACC_Pos               (3)                                               /*!< EBI_T::TCTL0: TACC Position            */
+#define EBI_TCTL0_TACC_Msk               (0x1ful << EBI_TCTL0_TACC_Pos)                    /*!< EBI_T::TCTL0: TACC Mask                */
+
+#define EBI_TCTL0_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL0: TAHD Position            */
+#define EBI_TCTL0_TAHD_Msk               (0x7ul << EBI_TCTL0_TAHD_Pos)                     /*!< EBI_T::TCTL0: TAHD Mask                */
+
+#define EBI_TCTL0_W2X_Pos                (12)                                              /*!< EBI_T::TCTL0: W2X Position             */
+#define EBI_TCTL0_W2X_Msk                (0xful << EBI_TCTL0_W2X_Pos)                      /*!< EBI_T::TCTL0: W2X Mask                 */
+
+#define EBI_TCTL0_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL0: RAHDOFF Position         */
+#define EBI_TCTL0_RAHDOFF_Msk            (0x1ul << EBI_TCTL0_RAHDOFF_Pos)                  /*!< EBI_T::TCTL0: RAHDOFF Mask             */
+
+#define EBI_TCTL0_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL0: WAHDOFF Position         */
+#define EBI_TCTL0_WAHDOFF_Msk            (0x1ul << EBI_TCTL0_WAHDOFF_Pos)                  /*!< EBI_T::TCTL0: WAHDOFF Mask             */
+
+#define EBI_TCTL0_R2R_Pos                (24)                                              /*!< EBI_T::TCTL0: R2R Position             */
+#define EBI_TCTL0_R2R_Msk                (0xful << EBI_TCTL0_R2R_Pos)                      /*!< EBI_T::TCTL0: R2R Mask                 */
+
+#define EBI_CTL1_EN_Pos                  (0)                                               /*!< EBI_T::CTL1: EN Position               */
+#define EBI_CTL1_EN_Msk                  (0x1ul << EBI_CTL1_EN_Pos)                        /*!< EBI_T::CTL1: EN Mask                   */
+
+#define EBI_CTL1_DW16_Pos                (1)                                               /*!< EBI_T::CTL1: DW16 Position             */
+#define EBI_CTL1_DW16_Msk                (0x1ul << EBI_CTL1_DW16_Pos)                      /*!< EBI_T::CTL1: DW16 Mask                 */
+
+#define EBI_CTL1_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL1: CSPOLINV Position         */
+#define EBI_CTL1_CSPOLINV_Msk            (0x1ul << EBI_CTL1_CSPOLINV_Pos)                  /*!< EBI_T::CTL1: CSPOLINV Mask             */
+
+#define EBI_CTL1_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL1: ADSEPEN Position          */
+#define EBI_CTL1_ADSEPEN_Msk             (0x1ul << EBI_CTL1_ADSEPEN_Pos)                   /*!< EBI_T::CTL1: ADSEPEN Mask              */
+
+#define EBI_CTL1_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL1: CACCESS Position          */
+#define EBI_CTL1_CACCESS_Msk             (0x1ul << EBI_CTL1_CACCESS_Pos)                   /*!< EBI_T::CTL1: CACCESS Mask              */
+
+#define EBI_CTL1_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL1: MCLKDIV Position          */
+#define EBI_CTL1_MCLKDIV_Msk             (0x7ul << EBI_CTL1_MCLKDIV_Pos)                   /*!< EBI_T::CTL1: MCLKDIV Mask              */
+
+#define EBI_CTL1_TALE_Pos                (16)                                              /*!< EBI_T::CTL1: TALE Position             */
+#define EBI_CTL1_TALE_Msk                (0x7ul << EBI_CTL1_TALE_Pos)                      /*!< EBI_T::CTL1: TALE Mask                 */
+
+#define EBI_CTL1_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL1: WBUFEN Position           */
+#define EBI_CTL1_WBUFEN_Msk              (0x1ul << EBI_CTL1_WBUFEN_Pos)                    /*!< EBI_T::CTL1: WBUFEN Mask               */
+
+#define EBI_TCTL1_TACC_Pos               (3)                                               /*!< EBI_T::TCTL1: TACC Position            */
+#define EBI_TCTL1_TACC_Msk               (0x1ful << EBI_TCTL1_TACC_Pos)                    /*!< EBI_T::TCTL1: TACC Mask                */
+
+#define EBI_TCTL1_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL1: TAHD Position            */
+#define EBI_TCTL1_TAHD_Msk               (0x7ul << EBI_TCTL1_TAHD_Pos)                     /*!< EBI_T::TCTL1: TAHD Mask                */
+
+#define EBI_TCTL1_W2X_Pos                (12)                                              /*!< EBI_T::TCTL1: W2X Position             */
+#define EBI_TCTL1_W2X_Msk                (0xful << EBI_TCTL1_W2X_Pos)                      /*!< EBI_T::TCTL1: W2X Mask                 */
+
+#define EBI_TCTL1_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL1: RAHDOFF Position         */
+#define EBI_TCTL1_RAHDOFF_Msk            (0x1ul << EBI_TCTL1_RAHDOFF_Pos)                  /*!< EBI_T::TCTL1: RAHDOFF Mask             */
+
+#define EBI_TCTL1_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL1: WAHDOFF Position         */
+#define EBI_TCTL1_WAHDOFF_Msk            (0x1ul << EBI_TCTL1_WAHDOFF_Pos)                  /*!< EBI_T::TCTL1: WAHDOFF Mask             */
+
+#define EBI_TCTL1_R2R_Pos                (24)                                              /*!< EBI_T::TCTL1: R2R Position             */
+#define EBI_TCTL1_R2R_Msk                (0xful << EBI_TCTL1_R2R_Pos)                      /*!< EBI_T::TCTL1: R2R Mask                 */
+
+#define EBI_CTL2_EN_Pos                  (0)                                               /*!< EBI_T::CTL2: EN Position               */
+#define EBI_CTL2_EN_Msk                  (0x1ul << EBI_CTL2_EN_Pos)                        /*!< EBI_T::CTL2: EN Mask                   */
+
+#define EBI_CTL2_DW16_Pos                (1)                                               /*!< EBI_T::CTL2: DW16 Position             */
+#define EBI_CTL2_DW16_Msk                (0x1ul << EBI_CTL2_DW16_Pos)                      /*!< EBI_T::CTL2: DW16 Mask                 */
+
+#define EBI_CTL2_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL2: CSPOLINV Position         */
+#define EBI_CTL2_CSPOLINV_Msk            (0x1ul << EBI_CTL2_CSPOLINV_Pos)                  /*!< EBI_T::CTL2: CSPOLINV Mask             */
+
+#define EBI_CTL2_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL2: ADSEPEN Position          */
+#define EBI_CTL2_ADSEPEN_Msk             (0x1ul << EBI_CTL2_ADSEPEN_Pos)                   /*!< EBI_T::CTL2: ADSEPEN Mask              */
+
+#define EBI_CTL2_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL2: CACCESS Position          */
+#define EBI_CTL2_CACCESS_Msk             (0x1ul << EBI_CTL2_CACCESS_Pos)                   /*!< EBI_T::CTL2: CACCESS Mask              */
+
+#define EBI_CTL2_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL2: MCLKDIV Position          */
+#define EBI_CTL2_MCLKDIV_Msk             (0x7ul << EBI_CTL2_MCLKDIV_Pos)                   /*!< EBI_T::CTL2: MCLKDIV Mask              */
+
+#define EBI_CTL2_TALE_Pos                (16)                                              /*!< EBI_T::CTL2: TALE Position             */
+#define EBI_CTL2_TALE_Msk                (0x7ul << EBI_CTL2_TALE_Pos)                      /*!< EBI_T::CTL2: TALE Mask                 */
+
+#define EBI_CTL2_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL2: WBUFEN Position           */
+#define EBI_CTL2_WBUFEN_Msk              (0x1ul << EBI_CTL2_WBUFEN_Pos)                    /*!< EBI_T::CTL2: WBUFEN Mask               */
+
+#define EBI_TCTL2_TACC_Pos               (3)                                               /*!< EBI_T::TCTL2: TACC Position            */
+#define EBI_TCTL2_TACC_Msk               (0x1ful << EBI_TCTL2_TACC_Pos)                    /*!< EBI_T::TCTL2: TACC Mask                */
+
+#define EBI_TCTL2_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL2: TAHD Position            */
+#define EBI_TCTL2_TAHD_Msk               (0x7ul << EBI_TCTL2_TAHD_Pos)                     /*!< EBI_T::TCTL2: TAHD Mask                */
+
+#define EBI_TCTL2_W2X_Pos                (12)                                              /*!< EBI_T::TCTL2: W2X Position             */
+#define EBI_TCTL2_W2X_Msk                (0xful << EBI_TCTL2_W2X_Pos)                      /*!< EBI_T::TCTL2: W2X Mask                 */
+
+#define EBI_TCTL2_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL2: RAHDOFF Position         */
+#define EBI_TCTL2_RAHDOFF_Msk            (0x1ul << EBI_TCTL2_RAHDOFF_Pos)                  /*!< EBI_T::TCTL2: RAHDOFF Mask             */
+
+#define EBI_TCTL2_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL2: WAHDOFF Position         */
+#define EBI_TCTL2_WAHDOFF_Msk            (0x1ul << EBI_TCTL2_WAHDOFF_Pos)                  /*!< EBI_T::TCTL2: WAHDOFF Mask             */
+
+#define EBI_TCTL2_R2R_Pos                (24)                                              /*!< EBI_T::TCTL2: R2R Position             */
+#define EBI_TCTL2_R2R_Msk                (0xful << EBI_TCTL2_R2R_Pos)                      /*!< EBI_T::TCTL2: R2R Mask                 */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __EBI_REG_H__ */

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h

@@ -0,0 +1,389 @@
+/**************************************************************************//**
+ * @file     ecap_reg.h
+ * @version  V1.00
+ * @brief    ECAP register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ECAP_REG_H__
+#define __ECAP_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
+    Memory Mapped Structure for ECAP Controller
+@{ */
+
+typedef struct
+{
+
+    /**
+     * @var ECAP_T::CNT
+     * Offset: 0x00  Input Capture Counter (24-bit up counter)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Input Capture Timer/Counter
+     * |        |          |The input Capture Timer/Counter is a 24-bit up-counting counter
+     * |        |          |The clock source for the counter is from the clock divider
+     * @var ECAP_T::HLD0
+     * Offset: 0x04  Input Capture Hold Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD1
+     * Offset: 0x08  Input Capture Hold Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD2
+     * Offset: 0x0C  Input Capture Hold Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::CNTCMP
+     * Offset: 0x10  Input Capture Compare Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNTCMP    |Input Capture Counter Compare Register
+     * |        |          |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
+     * |        |          |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
+     * @var ECAP_T::CTL0
+     * Offset: 0x14  Input Capture Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |NFCLKSEL  |Noise Filter Clock Pre-divide Selection
+     * |        |          |To determine the sampling frequency of the Noise Filter clock
+     * |        |          |000 = CAP_CLK.
+     * |        |          |001 = CAP_CLK/2.
+     * |        |          |010 = CAP_CLK/4.
+     * |        |          |011 = CAP_CLK/16.
+     * |        |          |100 = CAP_CLK/32.
+     * |        |          |101 = CAP_CLK/64.
+     * |[3]     |CAPNFDIS  |Input Capture Noise Filter Disable Control
+     * |        |          |0 = Noise filter of Input Capture Enabled.
+     * |        |          |1 = Noise filter of Input Capture Disabled (Bypass).
+     * |[4]     |IC0EN     |Port Pin IC0 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC0 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC0 input to Input Capture Unit Enabled.
+     * |[5]     |IC1EN     |Port Pin IC1 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC1 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC1 input to Input Capture Unit Enabled.
+     * |[6]     |IC2EN     |Port Pin IC2 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC2 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC2 input to Input Capture Unit Enabled.
+     * |[9:8]   |CAPSEL0   |CAP0 Input Source Selection
+     * |        |          |00 = CAP0 input is from port pin ICAP0.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP0 input is from signal CHA of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[11:10] |CAPSEL1   |CAP1 Input Source Selection
+     * |        |          |00 = CAP1 input is from port pin ICAP1.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP1 input is from signal CHB of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[13:12] |CAPSEL2   |CAP2 Input Source Selection
+     * |        |          |00 = CAP2 input is from port pin ICAP2.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP2 input is from signal CHX of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[16]    |CAPIEN0   |Input Capture Channel 0 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
+     * |[17]    |CAPIEN1   |Input Capture Channel 1 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
+     * |[18]    |CAPIEN2   |Input Capture Channel 2 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
+     * |[20]    |OVIEN     |CAPOVF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
+     * |[21]    |CMPIEN    |CAPCMPF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
+     * |[24]    |CNTEN     |Input Capture Counter Start Counting Control
+     * |        |          |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
+     * |        |          |0 = ECAP_CNT stop counting.
+     * |        |          |1 = ECAP_CNT starts up-counting.
+     * |[25]    |CMPCLREN  |Input Capture Counter Cleared by Compare-match Control
+     * |        |          |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
+     * |        |          |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
+     * |[28]    |CMPEN     |Compare Function Enable Control
+     * |        |          |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
+     * |        |          |0 = The compare function Disabled.
+     * |        |          |1 = The compare function Enabled.
+     * |[29]    |CAPEN     |Input Capture Timer/Counter Enable Control
+     * |        |          |0 = Input Capture function Disabled.
+     * |        |          |1 = Input Capture function Enabled.
+     * @var ECAP_T::CTL1
+     * Offset: 0x18  Input Capture Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |EDGESEL0  |Channel 0 Captured Edge Selection
+     * |        |          |Input capture0 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[3:2]   |EDGESEL1  |Channel 1 Captured Edge Selection
+     * |        |          |Input capture1 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[5:4]   |EDGESEL2  |Channel 2 Captured Edge Selection
+     * |        |          |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[8]     |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE0 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE0 Enabled.
+     * |[9]     |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE1 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE1 Enabled.
+     * |[10]    |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE2 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE2 Enabled.
+     * |[11]    |OVRLDEN   |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
+     * |        |          |0 = The reload triggered by CAPOV Disabled.
+     * |        |          |1 = The reload triggered by CAPOV Enabled.
+     * |[14:12] |CLKSEL    |Capture Timer Clock Divide Selection
+     * |        |          |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
+     * |        |          |000 = CAP_CLK/1.
+     * |        |          |001 = CAP_CLK/4.
+     * |        |          |010 = CAP_CLK/16.
+     * |        |          |011 = CAP_CLK/32.
+     * |        |          |100 = CAP_CLK/64.
+     * |        |          |101 = CAP_CLK/96.
+     * |        |          |110 = CAP_CLK/112.
+     * |        |          |111 = CAP_CLK/128.
+     * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
+     * |        |          |Select the capture timer/counter clock source.
+     * |        |          |00 = CAP_CLK (default).
+     * |        |          |01 = CAP0.
+     * |        |          |10 = CAP1.
+     * |        |          |11 = CAP2.
+     * |[20]    |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
+     * |        |          |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
+     * |[21]    |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
+     * |        |          |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
+     * |[22]    |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
+     * |        |          |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
+     * @var ECAP_T::STATUS
+     * Offset: 0x1C  Input Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPTF0    |Input Capture Channel 0 Triggered Flag
+     * |        |          |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[1]     |CAPTF1    |Input Capture Channel 1 Triggered Flag
+     * |        |          |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[2]     |CAPTF2    |Input Capture Channel 2 Triggered Flag
+     * |        |          |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[4]     |CAPCMPF   |Input Capture Compare-match Flag
+     * |        |          |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
+     * |        |          |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
+     * |        |          |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[5]     |CAPOVF    |Input Capture Counter Overflow Flag
+     * |        |          |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
+     * |        |          |0 = No overflow event has occurred since last clear.
+     * |        |          |1 = Overflow event(s) has/have occurred since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[6]     |CAP0      |Value of Input Channel 0, CAP0 (Read Only)
+     * |        |          |Reflecting the value of input channel 0, CAP0
+     * |        |          |(The bit is read only and write is ignored)
+     * |[7]     |CAP1      |Value of Input Channel 1, CAP1 (Read Only)
+     * |        |          |Reflecting the value of input channel 1, CAP1
+     * |        |          |(The bit is read only and write is ignored)
+     * |[8]     |CAP2      |Value of Input Channel 2, CAP2 (Read Only)
+     * |        |          |Reflecting the value of input channel 2, CAP2.
+     * |        |          |(The bit is read only and write is ignored)
+     */
+    __IO uint32_t CNT;                   /*!< [0x0000] Input Capture Counter                                            */
+    __IO uint32_t HLD0;                  /*!< [0x0004] Input Capture Hold Register 0                                    */
+    __IO uint32_t HLD1;                  /*!< [0x0008] Input Capture Hold Register 1                                    */
+    __IO uint32_t HLD2;                  /*!< [0x000c] Input Capture Hold Register 2                                    */
+    __IO uint32_t CNTCMP;                /*!< [0x0010] Input Capture Compare Register                                   */
+    __IO uint32_t CTL0;                  /*!< [0x0014] Input Capture Control Register 0                                 */
+    __IO uint32_t CTL1;                  /*!< [0x0018] Input Capture Control Register 1                                 */
+    __IO uint32_t STATUS;                /*!< [0x001c] Input Capture Status Register                                    */
+
+} ECAP_T;
+
+/**
+    @addtogroup ECAP_CONST ECAP Bit Field Definition
+    Constant Definitions for ECAP Controller
+@{ */
+
+#define ECAP_CNT_CNT_Pos                 (0)                                               /*!< ECAP_T::CNT: CNT Position              */
+#define ECAP_CNT_CNT_Msk                 (0xfffffful << ECAP_CNT_CNT_Pos)                  /*!< ECAP_T::CNT: CNT Mask                  */
+
+#define ECAP_HLD0_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD0: HOLD Position            */
+#define ECAP_HLD0_HOLD_Msk               (0xfffffful << ECAP_HLD0_HOLD_Pos)                /*!< ECAP_T::HLD0: HOLD Mask                */
+
+#define ECAP_HLD1_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD1: HOLD Position            */
+#define ECAP_HLD1_HOLD_Msk               (0xfffffful << ECAP_HLD1_HOLD_Pos)                /*!< ECAP_T::HLD1: HOLD Mask                */
+
+#define ECAP_HLD2_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD2: HOLD Position            */
+#define ECAP_HLD2_HOLD_Msk               (0xfffffful << ECAP_HLD2_HOLD_Pos)                /*!< ECAP_T::HLD2: HOLD Mask                */
+
+#define ECAP_CNTCMP_CNTCMP_Pos           (0)                                               /*!< ECAP_T::CNTCMP: CNTCMP Position        */
+#define ECAP_CNTCMP_CNTCMP_Msk           (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos)            /*!< ECAP_T::CNTCMP: CNTCMP Mask            */
+
+#define ECAP_CTL0_NFCLKSEL_Pos           (0)                                               /*!< ECAP_T::CTL0: NFCLKSEL Position        */
+#define ECAP_CTL0_NFCLKSEL_Msk           (0x7ul << ECAP_CTL0_NFCLKSEL_Pos)                 /*!< ECAP_T::CTL0: NFCLKSEL Mask            */
+
+#define ECAP_CTL0_CAPNFDIS_Pos           (3)                                               /*!< ECAP_T::CTL0: CAPNFDIS Position        */
+#define ECAP_CTL0_CAPNFDIS_Msk           (0x1ul << ECAP_CTL0_CAPNFDIS_Pos)                 /*!< ECAP_T::CTL0: CAPNFDIS Mask            */
+
+#define ECAP_CTL0_IC0EN_Pos              (4)                                               /*!< ECAP_T::CTL0: IC0EN Position           */
+#define ECAP_CTL0_IC0EN_Msk              (0x1ul << ECAP_CTL0_IC0EN_Pos)                    /*!< ECAP_T::CTL0: IC0EN Mask               */
+
+#define ECAP_CTL0_IC1EN_Pos              (5)                                               /*!< ECAP_T::CTL0: IC1EN Position           */
+#define ECAP_CTL0_IC1EN_Msk              (0x1ul << ECAP_CTL0_IC1EN_Pos)                    /*!< ECAP_T::CTL0: IC1EN Mask               */
+
+#define ECAP_CTL0_IC2EN_Pos              (6)                                               /*!< ECAP_T::CTL0: IC2EN Position           */
+#define ECAP_CTL0_IC2EN_Msk              (0x1ul << ECAP_CTL0_IC2EN_Pos)                    /*!< ECAP_T::CTL0: IC2EN Mask               */
+
+#define ECAP_CTL0_CAPSEL0_Pos            (8)                                               /*!< ECAP_T::CTL0: CAPSEL0 Position         */
+#define ECAP_CTL0_CAPSEL0_Msk            (0x3ul << ECAP_CTL0_CAPSEL0_Pos)                  /*!< ECAP_T::CTL0: CAPSEL0 Mask             */
+
+#define ECAP_CTL0_CAPSEL1_Pos            (10)                                              /*!< ECAP_T::CTL0: CAPSEL1 Position         */
+#define ECAP_CTL0_CAPSEL1_Msk            (0x3ul << ECAP_CTL0_CAPSEL1_Pos)                  /*!< ECAP_T::CTL0: CAPSEL1 Mask             */
+
+#define ECAP_CTL0_CAPSEL2_Pos            (12)                                              /*!< ECAP_T::CTL0: CAPSEL2 Position         */
+#define ECAP_CTL0_CAPSEL2_Msk            (0x3ul << ECAP_CTL0_CAPSEL2_Pos)                  /*!< ECAP_T::CTL0: CAPSEL2 Mask             */
+
+#define ECAP_CTL0_CAPIEN0_Pos            (16)                                              /*!< ECAP_T::CTL0: CAPIEN0 Position         */
+#define ECAP_CTL0_CAPIEN0_Msk            (0x1ul << ECAP_CTL0_CAPIEN0_Pos)                  /*!< ECAP_T::CTL0: CAPIEN0 Mask             */
+
+#define ECAP_CTL0_CAPIEN1_Pos            (17)                                              /*!< ECAP_T::CTL0: CAPIEN1 Position         */
+#define ECAP_CTL0_CAPIEN1_Msk            (0x1ul << ECAP_CTL0_CAPIEN1_Pos)                  /*!< ECAP_T::CTL0: CAPIEN1 Mask             */
+
+#define ECAP_CTL0_CAPIEN2_Pos            (18)                                              /*!< ECAP_T::CTL0: CAPIEN2 Position         */
+#define ECAP_CTL0_CAPIEN2_Msk            (0x1ul << ECAP_CTL0_CAPIEN2_Pos)                  /*!< ECAP_T::CTL0: CAPIEN2 Mask             */
+
+#define ECAP_CTL0_OVIEN_Pos              (20)                                              /*!< ECAP_T::CTL0: OVIEN Position           */
+#define ECAP_CTL0_OVIEN_Msk              (0x1ul << ECAP_CTL0_OVIEN_Pos)                    /*!< ECAP_T::CTL0: OVIEN Mask               */
+
+#define ECAP_CTL0_CMPIEN_Pos             (21)                                              /*!< ECAP_T::CTL0: CMPIEN Position          */
+#define ECAP_CTL0_CMPIEN_Msk             (0x1ul << ECAP_CTL0_CMPIEN_Pos)                   /*!< ECAP_T::CTL0: CMPIEN Mask              */
+
+#define ECAP_CTL0_CNTEN_Pos              (24)                                              /*!< ECAP_T::CTL0: CNTEN Position           */
+#define ECAP_CTL0_CNTEN_Msk              (0x1ul << ECAP_CTL0_CNTEN_Pos)                    /*!< ECAP_T::CTL0: CNTEN Mask               */
+
+#define ECAP_CTL0_CMPCLREN_Pos           (25)                                              /*!< ECAP_T::CTL0: CMPCLREN Position        */
+#define ECAP_CTL0_CMPCLREN_Msk           (0x1ul << ECAP_CTL0_CMPCLREN_Pos)                 /*!< ECAP_T::CTL0: CMPCLREN Mask            */
+
+#define ECAP_CTL0_CMPEN_Pos              (28)                                              /*!< ECAP_T::CTL0: CMPEN Position           */
+#define ECAP_CTL0_CMPEN_Msk              (0x1ul << ECAP_CTL0_CMPEN_Pos)                    /*!< ECAP_T::CTL0: CMPEN Mask               */
+
+#define ECAP_CTL0_CAPEN_Pos              (29)                                              /*!< ECAP_T::CTL0: CAPEN Position           */
+#define ECAP_CTL0_CAPEN_Msk              (0x1ul << ECAP_CTL0_CAPEN_Pos)                    /*!< ECAP_T::CTL0: CAPEN Mask               */
+
+#define ECAP_CTL1_EDGESEL0_Pos           (0)                                               /*!< ECAP_T::CTL1: EDGESEL0 Position        */
+#define ECAP_CTL1_EDGESEL0_Msk           (0x3ul << ECAP_CTL1_EDGESEL0_Pos)                 /*!< ECAP_T::CTL1: EDGESEL0 Mask            */
+
+#define ECAP_CTL1_EDGESEL1_Pos           (2)                                               /*!< ECAP_T::CTL1: EDGESEL1 Position        */
+#define ECAP_CTL1_EDGESEL1_Msk           (0x3ul << ECAP_CTL1_EDGESEL1_Pos)                 /*!< ECAP_T::CTL1: EDGESEL1 Mask            */
+
+#define ECAP_CTL1_EDGESEL2_Pos           (4)                                               /*!< ECAP_T::CTL1: EDGESEL2 Position        */
+#define ECAP_CTL1_EDGESEL2_Msk           (0x3ul << ECAP_CTL1_EDGESEL2_Pos)                 /*!< ECAP_T::CTL1: EDGESEL2 Mask            */
+
+#define ECAP_CTL1_CAP0RLDEN_Pos          (8)                                               /*!< ECAP_T::CTL1: CAP0RLDEN Position       */
+#define ECAP_CTL1_CAP0RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP0RLDEN Mask           */
+
+#define ECAP_CTL1_CAP1RLDEN_Pos          (9)                                               /*!< ECAP_T::CTL1: CAP1RLDEN Position       */
+#define ECAP_CTL1_CAP1RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP1RLDEN Mask           */
+
+#define ECAP_CTL1_CAP2RLDEN_Pos          (10)                                              /*!< ECAP_T::CTL1: CAP2RLDEN Position       */
+#define ECAP_CTL1_CAP2RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP2RLDEN Mask           */
+
+#define ECAP_CTL1_OVRLDEN_Pos            (11)                                              /*!< ECAP_T::CTL1: OVRLDEN Position         */
+#define ECAP_CTL1_OVRLDEN_Msk            (0x1ul << ECAP_CTL1_OVRLDEN_Pos)                  /*!< ECAP_T::CTL1: OVRLDEN Mask             */
+
+#define ECAP_CTL1_CLKSEL_Pos             (12)                                              /*!< ECAP_T::CTL1: CLKSEL Position          */
+#define ECAP_CTL1_CLKSEL_Msk             (0x7ul << ECAP_CTL1_CLKSEL_Pos)                   /*!< ECAP_T::CTL1: CLKSEL Mask              */
+
+#define ECAP_CTL1_CNTSRCSEL_Pos          (16)                                              /*!< ECAP_T::CTL1: CNTSRCSEL Position       */
+#define ECAP_CTL1_CNTSRCSEL_Msk          (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos)                /*!< ECAP_T::CTL1: CNTSRCSEL Mask           */
+
+#define ECAP_CTL1_CAP0CLREN_Pos          (20)                                              /*!< ECAP_T::CTL1: CAP0CLREN Position       */
+#define ECAP_CTL1_CAP0CLREN_Msk          (0x1ul << ECAP_CTL1_CAP0CLREN_Pos)                /*!< ECAP_T::CTL1: CAP0CLREN Mask           */
+
+#define ECAP_CTL1_CAP1CLREN_Pos          (21)                                              /*!< ECAP_T::CTL1: CAP1CLREN Position       */
+#define ECAP_CTL1_CAP1CLREN_Msk          (0x1ul << ECAP_CTL1_CAP1CLREN_Pos)                /*!< ECAP_T::CTL1: CAP1CLREN Mask           */
+
+#define ECAP_CTL1_CAP2CLREN_Pos          (22)                                              /*!< ECAP_T::CTL1: CAP2CLREN Position       */
+#define ECAP_CTL1_CAP2CLREN_Msk          (0x1ul << ECAP_CTL1_CAP2CLREN_Pos)                /*!< ECAP_T::CTL1: CAP2CLREN Mask           */
+
+#define ECAP_STATUS_CAPTF0_Pos           (0)                                               /*!< ECAP_T::STATUS: CAPTF0 Position        */
+#define ECAP_STATUS_CAPTF0_Msk           (0x1ul << ECAP_STATUS_CAPTF0_Pos)                 /*!< ECAP_T::STATUS: CAPTF0 Mask            */
+
+#define ECAP_STATUS_CAPTF1_Pos           (1)                                               /*!< ECAP_T::STATUS: CAPTF1 Position        */
+#define ECAP_STATUS_CAPTF1_Msk           (0x1ul << ECAP_STATUS_CAPTF1_Pos)                 /*!< ECAP_T::STATUS: CAPTF1 Mask            */
+
+#define ECAP_STATUS_CAPTF2_Pos           (2)                                               /*!< ECAP_T::STATUS: CAPTF2 Position        */
+#define ECAP_STATUS_CAPTF2_Msk           (0x1ul << ECAP_STATUS_CAPTF2_Pos)                 /*!< ECAP_T::STATUS: CAPTF2 Mask            */
+
+#define ECAP_STATUS_CAPCMPF_Pos          (4)                                               /*!< ECAP_T::STATUS: CAPCMPF Position       */
+#define ECAP_STATUS_CAPCMPF_Msk          (0x1ul << ECAP_STATUS_CAPCMPF_Pos)                /*!< ECAP_T::STATUS: CAPCMPF Mask           */
+
+#define ECAP_STATUS_CAPOVF_Pos           (5)                                               /*!< ECAP_T::STATUS: CAPOVF Position        */
+#define ECAP_STATUS_CAPOVF_Msk           (0x1ul << ECAP_STATUS_CAPOVF_Pos)                 /*!< ECAP_T::STATUS: CAPOVF Mask            */
+
+#define ECAP_STATUS_CAP0_Pos             (8)                                               /*!< ECAP_T::STATUS: CAP0 Position          */
+#define ECAP_STATUS_CAP0_Msk             (0x1ul << ECAP_STATUS_CAP0_Pos)                   /*!< ECAP_T::STATUS: CAP0 Mask              */
+
+#define ECAP_STATUS_CAP1_Pos             (9)                                               /*!< ECAP_T::STATUS: CAP1 Position          */
+#define ECAP_STATUS_CAP1_Msk             (0x1ul << ECAP_STATUS_CAP1_Pos)                   /*!< ECAP_T::STATUS: CAP1 Mask              */
+
+#define ECAP_STATUS_CAP2_Pos             (10)                                               /*!< ECAP_T::STATUS: CAP2 Position          */
+#define ECAP_STATUS_CAP2_Msk             (0x1ul << ECAP_STATUS_CAP2_Pos)                   /*!< ECAP_T::STATUS: CAP2 Mask              */
+
+/**@}*/ /* ECAP_CONST */
+/**@}*/ /* end of ECAP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __ECAP_REG_H__ */

bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h

@@ -0,0 +1,397 @@
+/**************************************************************************//**
+ * @file     hsotg_reg.h
+ * @version  V1.00
+ * @brief    HSOTG register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HSOTG_REG_H__
+#define __HSOTG_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG)
+    Memory Mapped Structure for HSOTG Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var HSOTG_T::CTL
+     * Offset: 0x00  HSOTG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDROP  |Drop VBUS Control
+     * |        |          |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+     * |        |          |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+     * |        |          |0 = Not drop the VBUS.
+     * |        |          |1 = Drop the VBUS.
+     * |[1]     |BUSREQ    |OTG Bus Request
+     * |        |          |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+     * |        |          |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+     * |        |          |This bit will be cleared when A-device goes to A_wait_vfall state
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+     * |        |          |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+     * |        |          |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+     * |[2]     |HNPREQEN  |OTG HNP Request Enable Bit
+     * |        |          |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+     * |        |          |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+     * |        |          |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+     * |        |          |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+     * |        |          |0 = HNP request Disabled.
+     * |        |          |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+     * |        |          |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+     * |[4]     |OTGEN     |OTG Function Enable Bit
+     * |        |          |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+     * |        |          |When USB frame not configured as OTG device, this bit is must be low.
+     * |        |          |0= OTG function Disabled.
+     * |        |          |1 = OTG function Enabled.
+     * |[5]     |WKEN      |OTG ID Pin Wake-up Enable Bit
+     * |        |          |0 = OTG ID pin status change wake-up function Disabled.
+     * |        |          |1 = OTG ID pin status change wake-up function Enabled.
+     * @var HSOTG_T::PHYCTL
+     * Offset: 0x04  HSOTG PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OTGPHYEN  |OTG PHY Enable
+     * |        |          |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
+     * |        |          |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care".
+     * |        |          |0 = OTG PHY Disabled.
+     * |        |          |1 = OTG PHY Enabled.
+     * |[1]     |IDDETEN   |ID Detection Enable Bit
+     * |        |          |0 = Detect ID pin status Disabled.
+     * |        |          |1 = Detect ID pin status Enabled.
+     * |[4]     |VBENPOL   |Off-chip USB VBUS Power Switch Enable Polarity
+     * |        |          |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+     * |        |          |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+     * |        |          |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The off-chip USB VBUS power switch enable is active high.
+     * |        |          |1 = The off-chip USB VBUS power switch enable is active low.
+     * |[5]     |VBSTSPOL  |Off-chip USB VBUS Power Switch Status Polarity
+     * |        |          |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+     * |        |          |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+     * |        |          |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+     * @var HSOTG_T::INTEN
+     * Offset: 0x08  HSOTG Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[1]     |VBEIEN    |VBUS Error Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+     * |[2]     |SRPFIEN   |SRP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[3]     |HNPFIEN   |HNP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[4]     |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Going to idle state means going to a_idle or b_idle state
+     * |        |          |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+     * |[5]     |IDCHGIEN  |IDSTS Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[6]     |PDEVIEN   |Act As Peripheral Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+     * |        |          |0 = This device as a peripheral interrupt Disabled.
+     * |        |          |1 = This device as a peripheral interrupt Enabled.
+     * |[7]     |HOSTIEN   |Act As Host Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+     * |        |          |0 = This device as a host interrupt Disabled.
+     * |        |          |1 = This device as a host interrupt Enabled.
+     * |[8]     |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[9]     |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[10]    |VBCHGIEN  |VBUSVLD Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[11]    |SECHGIEN  |SESSEND Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[13]    |SRPDETIEN |SRP Detected Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * @var HSOTG_T::INTSTS
+     * Offset: 0x0C  HSOTG Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIF |OTG Role Change Interrupt Status
+     * |        |          |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+     * |        |          |0 = OTG device role not changed.
+     * |        |          |1 = OTG device role changed.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[1]     |VBEIF     |VBUS Error Interrupt Status
+     * |        |          |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+     * |        |          |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+     * |        |          |Note: Write 1 to clear this flag and recover from the VBUS error state.
+     * |[2]     |SRPFIF    |SRP Fail Interrupt Status
+     * |        |          |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+     * |        |          |This flag is set when the OTG B-device does not get VBUS high after this interval.
+     * |        |          |0 = OTG B-device gets VBUS high before this interval.
+     * |        |          |1 = OTG B-device does not get VBUS high before this interval.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[3]     |HNPFIF    |HNP Fail Interrupt Status
+     * |        |          |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+     * |        |          |0 = A-device connects to B-device before specified interval expires.
+     * |        |          |1 = A-device does not connect to B-device before specified interval expires.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[4]     |GOIDLEIF  |OTG Device Goes to IDLE Interrupt Status
+     * |        |          |Flag is set if the OTG device transfers from non-idle state to idle state
+     * |        |          |The OTG device will be neither a host nor a peripheral.
+     * |        |          |0 = OTG device does not go back to idle state (a_idle or b_idle).
+     * |        |          |1 = OTG device goes back to idle state(a_idle or b_idle).
+     * |        |          |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+     * |        |          |Note 2: Write 1 to clear this flag.
+     * |[5]     |IDCHGIF   |ID State Change Interrupt Status
+     * |        |          |0 = IDSTS (OTG_STATUS[1]) not toggled.
+     * |        |          |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[6]     |PDEVIF    |Act As Peripheral Interrupt Status
+     * |        |          |0= This device does not act as a peripheral.
+     * |        |          |1 = This device acts as a peripheral.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[7]     |HOSTIF    |Act As Host Interrupt Status
+     * |        |          |0= This device does not act as a host.
+     * |        |          |1 = This device acts as a host.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[8]     |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+     * |        |          |0 = BVLD (OTG_STATUS[3]) is not toggled.
+     * |        |          |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[9]     |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+     * |        |          |0 = AVLD (OTG_STATUS[4]) not toggled.
+     * |        |          |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[10]    |VBCHGIF   |VBUSVLD State Change Interrupt Status
+     * |        |          |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+     * |        |          |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[11]    |SECHGIF   |SESSEND State Change Interrupt Status
+     * |        |          |0 = SESSEND (OTG_STATUS[2]) not toggled.
+     * |        |          |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[13]    |SRPDETIF  |SRP Detected Interrupt Status
+     * |        |          |0 = SRP not detected.
+     * |        |          |1 = SRP detected.
+     * |        |          |Note: Write 1 to clear this status.
+     * @var HSOTG_T::STATUS
+     * Offset: 0x10  HSOTG Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OVERCUR   |over Current Condition
+     * |        |          |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS successfully.
+     * |        |          |1 = OTG A-device cannot drives VBUS high in this interval.
+     * |[1]     |IDSTS     |USB_ID Pin State of Mini-b/Micro-plug
+     * |        |          |0 = Mini-A/Micro-A plug is attached.
+     * |        |          |1 = Mini-B/Micro-B plug is attached.
+     * |[2]     |SESSEND   |Session End Status
+     * |        |          |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+     * |        |          |Session end means no meaningful power on VBUS.
+     * |        |          |0 = Session is not end.
+     * |        |          |1 = Session is end.
+     * |[3]     |BVLD      |B-device Session Valid Status
+     * |        |          |0 = B-device session is not valid.
+     * |        |          |1 = B-device session is valid.
+     * |[4]     |AVLD      |A-device Session Valid Status
+     * |        |          |0 = A-device session is not valid.
+     * |        |          |1 = A-device session is valid.
+     * |[5]     |VBUSVLD   |VBUS Valid Status
+     * |        |          |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1.
+     * |        |          |0 = VBUS is not valid.
+     * |        |          |1 = VBUS is valid.
+     * |[6]     |ASPERI    |As Peripheral Status
+     * |        |          |When OTG as peripheral, this bit is set.
+     * |        |          |0: OTG not as peripheral
+     * |        |          |1: OTG as peripheral
+     * |[7]     |ASHOST    |As Host Status
+     * |        |          |When OTG as Host, this bit is set.
+     * |        |          |0: OTG not as Host
+     * |        |          |1: OTG as Host
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] HSOTG Control Register                                           */
+    __IO uint32_t PHYCTL;                /*!< [0x0004] HSOTG PHY Control Register                                       */
+    __IO uint32_t INTEN;                 /*!< [0x0008] HSOTG Interrupt Enable Register                                  */
+    __IO uint32_t INTSTS;                /*!< [0x000c] HSOTG Interrupt Status Register                                  */
+    __I  uint32_t STATUS;                /*!< [0x0010] HSOTG Status Register                                            */
+
+} HSOTG_T;
+
+/**
+    @addtogroup HSOTG_CONST HSOTG Bit Field Definition
+    Constant Definitions for HSOTG Controller
+@{ */
+
+#define HSOTG_CTL_VBUSDROP_Pos           (0)                                               /*!< HSOTG_T::CTL: VBUSDROP Position        */
+#define HSOTG_CTL_VBUSDROP_Msk           (0x1ul << HSOTG_CTL_VBUSDROP_Pos)                 /*!< HSOTG_T::CTL: VBUSDROP Mask            */
+
+#define HSOTG_CTL_BUSREQ_Pos             (1)                                               /*!< HSOTG_T::CTL: BUSREQ Position          */
+#define HSOTG_CTL_BUSREQ_Msk             (0x1ul << HSOTG_CTL_BUSREQ_Pos)                   /*!< HSOTG_T::CTL: BUSREQ Mask              */
+
+#define HSOTG_CTL_HNPREQEN_Pos           (2)                                               /*!< HSOTG_T::CTL: HNPREQEN Position        */
+#define HSOTG_CTL_HNPREQEN_Msk           (0x1ul << HSOTG_CTL_HNPREQEN_Pos)                 /*!< HSOTG_T::CTL: HNPREQEN Mask            */
+
+#define HSOTG_CTL_OTGEN_Pos              (4)                                               /*!< HSOTG_T::CTL: OTGEN Position           */
+#define HSOTG_CTL_OTGEN_Msk              (0x1ul << HSOTG_CTL_OTGEN_Pos)                    /*!< HSOTG_T::CTL: OTGEN Mask               */
+
+#define HSOTG_CTL_WKEN_Pos               (5)                                               /*!< HSOTG_T::CTL: WKEN Position            */
+#define HSOTG_CTL_WKEN_Msk               (0x1ul << HSOTG_CTL_WKEN_Pos)                     /*!< HSOTG_T::CTL: WKEN Mask                */
+
+#define HSOTG_PHYCTL_OTGPHYEN_Pos        (0)                                               /*!< HSOTG_T::PHYCTL: OTGPHYEN Position     */
+#define HSOTG_PHYCTL_OTGPHYEN_Msk        (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos)              /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask         */
+
+#define HSOTG_PHYCTL_IDDETEN_Pos         (1)                                               /*!< HSOTG_T::PHYCTL: IDDETEN Position      */
+#define HSOTG_PHYCTL_IDDETEN_Msk         (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos)               /*!< HSOTG_T::PHYCTL: IDDETEN Mask          */
+
+#define HSOTG_PHYCTL_VBENPOL_Pos         (4)                                               /*!< HSOTG_T::PHYCTL: VBENPOL Position      */
+#define HSOTG_PHYCTL_VBENPOL_Msk         (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos)               /*!< HSOTG_T::PHYCTL: VBENPOL Mask          */
+
+#define HSOTG_PHYCTL_VBSTSPOL_Pos        (5)                                               /*!< HSOTG_T::PHYCTL: VBSTSPOL Position     */
+#define HSOTG_PHYCTL_VBSTSPOL_Msk        (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos)              /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask         */
+
+#define HSOTG_INTEN_ROLECHGIEN_Pos       (0)                                               /*!< HSOTG_T::INTEN: ROLECHGIEN Position    */
+#define HSOTG_INTEN_ROLECHGIEN_Msk       (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos)             /*!< HSOTG_T::INTEN: ROLECHGIEN Mask        */
+
+#define HSOTG_INTEN_VBEIEN_Pos           (1)                                               /*!< HSOTG_T::INTEN: VBEIEN Position        */
+#define HSOTG_INTEN_VBEIEN_Msk           (0x1ul << HSOTG_INTEN_VBEIEN_Pos)                 /*!< HSOTG_T::INTEN: VBEIEN Mask            */
+
+#define HSOTG_INTEN_SRPFIEN_Pos          (2)                                               /*!< HSOTG_T::INTEN: SRPFIEN Position       */
+#define HSOTG_INTEN_SRPFIEN_Msk          (0x1ul << HSOTG_INTEN_SRPFIEN_Pos)                /*!< HSOTG_T::INTEN: SRPFIEN Mask           */
+
+#define HSOTG_INTEN_HNPFIEN_Pos          (3)                                               /*!< HSOTG_T::INTEN: HNPFIEN Position       */
+#define HSOTG_INTEN_HNPFIEN_Msk          (0x1ul << HSOTG_INTEN_HNPFIEN_Pos)                /*!< HSOTG_T::INTEN: HNPFIEN Mask           */
+
+#define HSOTG_INTEN_GOIDLEIEN_Pos        (4)                                               /*!< HSOTG_T::INTEN: GOIDLEIEN Position     */
+#define HSOTG_INTEN_GOIDLEIEN_Msk        (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos)              /*!< HSOTG_T::INTEN: GOIDLEIEN Mask         */
+
+#define HSOTG_INTEN_IDCHGIEN_Pos         (5)                                               /*!< HSOTG_T::INTEN: IDCHGIEN Position      */
+#define HSOTG_INTEN_IDCHGIEN_Msk         (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos)               /*!< HSOTG_T::INTEN: IDCHGIEN Mask          */
+
+#define HSOTG_INTEN_PDEVIEN_Pos          (6)                                               /*!< HSOTG_T::INTEN: PDEVIEN Position       */
+#define HSOTG_INTEN_PDEVIEN_Msk          (0x1ul << HSOTG_INTEN_PDEVIEN_Pos)                /*!< HSOTG_T::INTEN: PDEVIEN Mask           */
+
+#define HSOTG_INTEN_HOSTIEN_Pos          (7)                                               /*!< HSOTG_T::INTEN: HOSTIEN Position       */
+#define HSOTG_INTEN_HOSTIEN_Msk          (0x1ul << HSOTG_INTEN_HOSTIEN_Pos)                /*!< HSOTG_T::INTEN: HOSTIEN Mask           */
+
+#define HSOTG_INTEN_BVLDCHGIEN_Pos       (8)                                               /*!< HSOTG_T::INTEN: BVLDCHGIEN Position    */
+#define HSOTG_INTEN_BVLDCHGIEN_Msk       (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos)             /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask        */
+
+#define HSOTG_INTEN_AVLDCHGIEN_Pos       (9)                                               /*!< HSOTG_T::INTEN: AVLDCHGIEN Position    */
+#define HSOTG_INTEN_AVLDCHGIEN_Msk       (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos)             /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask        */
+
+#define HSOTG_INTEN_VBCHGIEN_Pos         (10)                                              /*!< HSOTG_T::INTEN: VBCHGIEN Position      */
+#define HSOTG_INTEN_VBCHGIEN_Msk         (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos)               /*!< HSOTG_T::INTEN: VBCHGIEN Mask          */
+
+#define HSOTG_INTEN_SECHGIEN_Pos         (11)                                              /*!< HSOTG_T::INTEN: SECHGIEN Position      */
+#define HSOTG_INTEN_SECHGIEN_Msk         (0x1ul << HSOTG_INTEN_SECHGIEN_Pos)               /*!< HSOTG_T::INTEN: SECHGIEN Mask          */
+
+#define HSOTG_INTEN_SRPDETIEN_Pos        (13)                                              /*!< HSOTG_T::INTEN: SRPDETIEN Position     */
+#define HSOTG_INTEN_SRPDETIEN_Msk        (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos)              /*!< HSOTG_T::INTEN: SRPDETIEN Mask         */
+
+#define HSOTG_INTSTS_ROLECHGIF_Pos       (0)                                               /*!< HSOTG_T::INTSTS: ROLECHGIF Position    */
+#define HSOTG_INTSTS_ROLECHGIF_Msk       (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos)             /*!< HSOTG_T::INTSTS: ROLECHGIF Mask        */
+
+#define HSOTG_INTSTS_VBEIF_Pos           (1)                                               /*!< HSOTG_T::INTSTS: VBEIF Position        */
+#define HSOTG_INTSTS_VBEIF_Msk           (0x1ul << HSOTG_INTSTS_VBEIF_Pos)                 /*!< HSOTG_T::INTSTS: VBEIF Mask            */
+
+#define HSOTG_INTSTS_SRPFIF_Pos          (2)                                               /*!< HSOTG_T::INTSTS: SRPFIF Position       */
+#define HSOTG_INTSTS_SRPFIF_Msk          (0x1ul << HSOTG_INTSTS_SRPFIF_Pos)                /*!< HSOTG_T::INTSTS: SRPFIF Mask           */
+
+#define HSOTG_INTSTS_HNPFIF_Pos          (3)                                               /*!< HSOTG_T::INTSTS: HNPFIF Position       */
+#define HSOTG_INTSTS_HNPFIF_Msk          (0x1ul << HSOTG_INTSTS_HNPFIF_Pos)                /*!< HSOTG_T::INTSTS: HNPFIF Mask           */
+
+#define HSOTG_INTSTS_GOIDLEIF_Pos        (4)                                               /*!< HSOTG_T::INTSTS: GOIDLEIF Position     */
+#define HSOTG_INTSTS_GOIDLEIF_Msk        (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos)              /*!< HSOTG_T::INTSTS: GOIDLEIF Mask         */
+
+#define HSOTG_INTSTS_IDCHGIF_Pos         (5)                                               /*!< HSOTG_T::INTSTS: IDCHGIF Position      */
+#define HSOTG_INTSTS_IDCHGIF_Msk         (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos)               /*!< HSOTG_T::INTSTS: IDCHGIF Mask          */
+
+#define HSOTG_INTSTS_PDEVIF_Pos          (6)                                               /*!< HSOTG_T::INTSTS: PDEVIF Position       */
+#define HSOTG_INTSTS_PDEVIF_Msk          (0x1ul << HSOTG_INTSTS_PDEVIF_Pos)                /*!< HSOTG_T::INTSTS: PDEVIF Mask           */
+
+#define HSOTG_INTSTS_HOSTIF_Pos          (7)                                               /*!< HSOTG_T::INTSTS: HOSTIF Position       */
+#define HSOTG_INTSTS_HOSTIF_Msk          (0x1ul << HSOTG_INTSTS_HOSTIF_Pos)                /*!< HSOTG_T::INTSTS: HOSTIF Mask           */
+
+#define HSOTG_INTSTS_BVLDCHGIF_Pos       (8)                                               /*!< HSOTG_T::INTSTS: BVLDCHGIF Position    */
+#define HSOTG_INTSTS_BVLDCHGIF_Msk       (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos)             /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask        */
+
+#define HSOTG_INTSTS_AVLDCHGIF_Pos       (9)                                               /*!< HSOTG_T::INTSTS: AVLDCHGIF Position    */
+#define HSOTG_INTSTS_AVLDCHGIF_Msk       (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos)             /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask        */
+
+#define HSOTG_INTSTS_VBCHGIF_Pos         (10)                                              /*!< HSOTG_T::INTSTS: VBCHGIF Position      */
+#define HSOTG_INTSTS_VBCHGIF_Msk         (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos)               /*!< HSOTG_T::INTSTS: VBCHGIF Mask          */
+
+#define HSOTG_INTSTS_SECHGIF_Pos         (11)                                              /*!< HSOTG_T::INTSTS: SECHGIF Position      */
+#define HSOTG_INTSTS_SECHGIF_Msk         (0x1ul << HSOTG_INTSTS_SECHGIF_Pos)               /*!< HSOTG_T::INTSTS: SECHGIF Mask          */
+
+#define HSOTG_INTSTS_SRPDETIF_Pos        (13)                                              /*!< HSOTG_T::INTSTS: SRPDETIF Position     */
+#define HSOTG_INTSTS_SRPDETIF_Msk        (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos)              /*!< HSOTG_T::INTSTS: SRPDETIF Mask         */
+
+#define HSOTG_STATUS_OVERCUR_Pos         (0)                                               /*!< HSOTG_T::STATUS: OVERCUR Position      */
+#define HSOTG_STATUS_OVERCUR_Msk         (0x1ul << HSOTG_STATUS_OVERCUR_Pos)               /*!< HSOTG_T::STATUS: OVERCUR Mask          */
+
+#define HSOTG_STATUS_IDSTS_Pos           (1)                                               /*!< HSOTG_T::STATUS: IDSTS Position        */
+#define HSOTG_STATUS_IDSTS_Msk           (0x1ul << HSOTG_STATUS_IDSTS_Pos)                 /*!< HSOTG_T::STATUS: IDSTS Mask            */
+
+#define HSOTG_STATUS_SESSEND_Pos         (2)                                               /*!< HSOTG_T::STATUS: SESSEND Position      */
+#define HSOTG_STATUS_SESSEND_Msk         (0x1ul << HSOTG_STATUS_SESSEND_Pos)               /*!< HSOTG_T::STATUS: SESSEND Mask          */
+
+#define HSOTG_STATUS_BVLD_Pos            (3)                                               /*!< HSOTG_T::STATUS: BVLD Position         */
+#define HSOTG_STATUS_BVLD_Msk            (0x1ul << HSOTG_STATUS_BVLD_Pos)                  /*!< HSOTG_T::STATUS: BVLD Mask             */
+
+#define HSOTG_STATUS_AVLD_Pos            (4)                                               /*!< HSOTG_T::STATUS: AVLD Position         */
+#define HSOTG_STATUS_AVLD_Msk            (0x1ul << HSOTG_STATUS_AVLD_Pos)                  /*!< HSOTG_T::STATUS: AVLD Mask             */
+
+#define HSOTG_STATUS_VBUSVLD_Pos         (5)                                               /*!< HSOTG_T::STATUS: VBUSVLD Position      */
+#define HSOTG_STATUS_VBUSVLD_Msk         (0x1ul << HSOTG_STATUS_VBUSVLD_Pos)               /*!< HSOTG_T::STATUS: VBUSVLD Mask          */
+
+#define HSOTG_STATUS_ASPERI_Pos          (6)                                               /*!< HSOTG_T::STATUS: ASPERI Position       */
+#define HSOTG_STATUS_ASPERI_Msk          (0x1ul << HSOTG_STATUS_ASPERI_Pos)                /*!< HSOTG_T::STATUS: ASPERI Mask           */
+
+#define HSOTG_STATUS_ASHOST_Pos          (7)                                               /*!< HSOTG_T::STATUS: ASHOST Position       */
+#define HSOTG_STATUS_ASHOST_Msk          (0x1ul << HSOTG_STATUS_ASHOST_Pos)                /*!< HSOTG_T::STATUS: ASHOST Mask           */
+
+/**@}*/ /* HSOTG_CONST */
+/**@}*/ /* end of HSOTG register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __HSOTG_REG_H__ */