Merge pull request #1985 from Bluebear233/m487

[BSP]add NUVOTON M487 BSP
2026-11-09 20:45:41 +08:00 · 2018-11-20 18:16:01 +08:00
commit 6b6d122e36
@@ -0,0 +1,25 @@
+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+source "$BSP_DIR/driver/Kconfig"
+
@@ -0,0 +1,66 @@
+# NuMaker-PFM-M487
+
+## 1. 简介
+
+核心板板载主要资源如下：
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| M487JIDAE |
+|CPU| ARM Cortex-M4 |
+|主频| 192MHz |
+|片内SRAM| 160kB |
+|片内Flash| 512kB |
+|SPI FLASH| W25Q32 |
+|PHY| IP101GR |
+|Audio Codec| NAU88L25 |
+
+
+## 2. 编译说明
+
+板级包支持MDK4工程生成、GCC编译器，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本                   |
+| ---------- | ---------------------------- |
+| MDK4       | 4.73                         |
+| GCC        | GCC 5.4.1 20160919 (release) |
+
+使用MDK4打开工程需要安装Nu-Link_Keil_Driver
+
+## 3. 烧写及执行
+
+连接好串口，可以使用115200-N-8-1的配置方式连接到设备上。设备使用的串口引脚是：`[Tx:PB13  Rx:PB12]`
+
+当正确编译产生出rtthread.bin映像文件后，可以使用NU-link或者JLINK下载
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+### 4.1 IO在板级支持包中的映射情况
+
+| IO号 | 板级包中的定义 |
+| -- | -- |
+| PH0 | LED_R |
+| PH1 | LED_Y |
+| PH2 | LED_G |
+| PG15 | KEY2 |
+| PF11| KEY3 |
+
+## 5. 联系人信息
+
+维护人：[bluebear233](https://github.com/bluebear233)
+
+## 6. 参考
+
+* 板子[数据手册][1]
+* 芯片[数据手册][2]
+
+  [1]: http://www.nuvoton.com/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.00.pdf
+  [2]: http://www.nuvoton.com/resource-files/TRM_M480_Series_EN_Rev1.01.pdf
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,35 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-m487.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char** argv)
+{
+    printf("Hello RT-Thread!\n");
+
+    return 0;
+}
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rtthread.h>
+
+int mnt_init(void)
+{
+    return 0;
+}
@@ -0,0 +1 @@
+  
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+''')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#include <rtconfig.h>
+#include <rtthread.h>
+#include <rthw.h>
+#include "NuMicro.h"
+#include "drv_uart.h"
+#include "board.h"
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+extern int __ram_top;
+#endif
+
+/**
+ * This function will initial Clock tree.
+ */
+static void clock_init(void)
+{
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+
+    SystemInit();
+
+    /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
+    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+
+    /* Enable External XTAL (4~24 MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+
+    /* Waiting for 12MHz clock ready */
+    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
+
+    /* Switch HCLK clock source to HXT */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
+
+    /* Set core clock as PLL_CLOCK from PLL */
+    CLK_SetCoreClock(FREQ_192MHZ);
+
+    /* Set both PCLK0 and PCLK1 as HCLK/4 */
+    CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;
+
+    SystemCoreClockUpdate();
+
+    /* Lock protected registers */
+    SYS_LockReg();
+}
+
+/**
+ * This function will initial M487 board.
+ */
+void rt_hw_board_init(void)
+{
+    clock_init();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
+#endif
+#endif /* RT_USING_HEAP */
+
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+	
+	NVIC_SetPriorityGrouping(7);
+	
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_cpu_reset(void)
+{
+    SYS_UnlockReg();
+
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+// <o> Internal SRAM memory size[Kbytes] <8-64>
+#define SRAM_SIZE         (160)
+#define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
+
+#define RT_UART_485_MODE      1
+#define RT_UART_FLOW_CTS_CTRL 2
+#define RT_UART_FLOW_RTS_CTRL 3
+#define RT_UART_CLEAR_BUF     4
+
+void rt_hw_pdma_init(void);
+void rt_hw_uart_handle(void);
+void rt_hw_sc_init(void);
+void rt_hw_usart_init(void);
+void rt_hw_uusart_init(void);
+void rt_hw_io_init(void);
+void phy_error_led(void);
+
+unsigned char *eth_get_default_mac(void);
+void eth_set_mac(const unsigned char * mac);
+void wdt_reload(void);
+unsigned int get_uid(void);
+
+#endif /* BOARD_H_ */
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-16    bluebear233   first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif /* __DRV_UART_H__ */
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
@@ -0,0 +1,16 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+""")
+
+path = [cwd + '/Include',]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,15 @@
+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "M480.h"
+
+#endif  /* __NUMICRO_H__ */
+
+
@@ -0,0 +1,149 @@
+/**************************************************************************//**
+ * @file     crc_reg.h
+ * @version  V1.00
+ * @brief    CRC register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_REG_H__
+#define __CRC_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var CRC_T::CTL
+     * Offset: 0x00  CRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRCEN     |CRC Channel Enable Bit
+     * |        |          |0 = No effect.
+     * |        |          |1 = CRC operation Enabled.
+     * |[1]     |CHKSINIT  |Checksum Initialization
+     * |        |          |0 = No effect.
+     * |        |          |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
+     * |        |          |Note: This bit will be cleared automatically.
+     * |[24]    |DATREV    |Write Data Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
+     * |        |          |0 = Bit order reversed for CRC write data in Disabled.
+     * |        |          |1 = Bit order reversed for CRC write data in Enabled (per byte).
+     * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+     * |[25]    |CHKSREV   |Checksum Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = Bit order reverse for CRC checksum Disabled.
+     * |        |          |1 = Bit order reverse for CRC checksum Enabled.
+     * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+     * |[26]    |DATFMT    |Write Data 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+     * |        |          |0 = 1's complement for CRC writes data in Disabled.
+     * |        |          |1 = 1's complement for CRC writes data in Enabled.
+     * |[27]    |CHKSFMT   |Checksum 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = 1's complement for CRC checksum Disabled.
+     * |        |          |1 = 1's complement for CRC checksum Enabled.
+     * |[29:28] |DATLEN    |CPU Write Data Length
+     * |        |          |This field indicates the write data length.
+     * |        |          |00 = Data length is 8-bit mode.
+     * |        |          |01 = Data length is 16-bit mode.
+     * |        |          |1x = Data length is 32-bit mode.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+     * |[31:30] |CRCMODE   |CRC Polynomial Mode
+     * |        |          |This field indicates the CRC operation polynomial mode.
+     * |        |          |00 = CRC-CCITT Polynomial mode.
+     * |        |          |01 = CRC-8 Polynomial mode.
+     * |        |          |10 = CRC-16 Polynomial mode.
+     * |        |          |11 = CRC-32 Polynomial mode.
+     * @var CRC_T::DAT
+     * Offset: 0x04  CRC Write Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATA      |CRC Write Data Bits
+     * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+     * @var CRC_T::SEED
+     * Offset: 0x08  CRC Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |CRC Seed Value
+     * |        |          |This field indicates the CRC seed value.
+     * |        |          |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
+     * @var CRC_T::CHECKSUM
+     * Offset: 0x0C  CRC Checksum Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CHECKSUM  |CRC Checksum Results
+     * |        |          |This field indicates the CRC checksum result.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] CRC Control Register                                             */
+    __IO uint32_t DAT;                   /*!< [0x0004] CRC Write Data Register                                          */
+    __IO uint32_t SEED;                  /*!< [0x0008] CRC Seed Register                                                */
+    __I  uint32_t CHECKSUM;              /*!< [0x000c] CRC Checksum Register                                            */
+
+} CRC_T;
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position             */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                 */
+
+#define CRC_CTL_CHKSINIT_Pos             (1)                                               /*!< CRC_T::CTL: CHKSINIT Position          */
+#define CRC_CTL_CHKSINIT_Msk             (0x1ul << CRC_CTL_CHKSINIT_Pos)                   /*!< CRC_T::CTL: CHKSINIT Mask              */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position            */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position           */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask               */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position            */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position           */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask               */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position            */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position           */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask               */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position              */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                  */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position             */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                 */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position     */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask         */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRC_REG_H__ */
@@ -0,0 +1,66 @@
+/**************************************************************************//**
+ * @file     system_M480.h
+ * @version  V1.00
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M480_H__
+#define __SYSTEM_M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define __HSI       (12000000UL)    /*!< PLL default output is 50MHz */
+#define __HXT       (12000000UL)    /*!< External Crystal Clock Frequency     */
+#define __LXT       (32768UL)       /*!< External Crystal Clock Frequency 32.768KHz */
+#define __HIRC      (12000000UL)    /*!< Internal 12M RC Oscillator Frequency */
+#define __LIRC      (10000UL)       /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+
+#define __SYSTEM_CLOCK    (1UL*__HXT)
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t CyclesPerUs;         /*!< Cycles per micro second              */
+extern uint32_t PllClock;            /*!< PLL Output Clock Frequency           */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the micro controller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M480_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
@@ -0,0 +1,182 @@
+/**************************************************************************//**
+ * @file     wdt_reg.h
+ * @version  V1.00
+ * @brief    WDT register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_REG_H__
+#define __WDT_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup WDT Watch Dog Timer Controller(WDT)
+    Memory Mapped Structure for WDT Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var WDT_T::CTL
+     * Offset: 0x00  WDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RSTCNT    |Reset WDT Up Counter (Write Protect)
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the internal 18-bit WDT up counter value.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit will be automatically cleared by hardware.
+     * |[1]     |RSTEN     |WDT Time-out Reset Enable Control (Write Protect)
+     * |        |          |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+     * |        |          |0 = WDT time-out reset function Disabled.
+     * |        |          |1 = WDT time-out reset function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |RSTF      |WDT Time-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by WDT time-out reset or not.
+     * |        |          |0 = WDT time-out reset did not occur.
+     * |        |          |1 = WDT time-out reset occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |IF        |WDT Time-out Interrupt Flag
+     * |        |          |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+     * |        |          |0 = WDT time-out interrupt did not occur.
+     * |        |          |1 = WDT time-out interrupt occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[4]     |WKEN      |WDT Time-out Wake-up Function Control (Write Protect)
+     * |        |          |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
+     * |        |          |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
+     * |        |          |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
+     * |[5]     |WKF       |WDT Time-out Wake-up Flag (Write Protect)
+     * |        |          |This bit indicates the interrupt wake-up flag status of WDT
+     * |        |          |0 = WDT does not cause chip wake-up.
+     * |        |          |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[6]     |INTEN     |WDT Time-out Interrupt Enable Control (Write Protect)
+     * |        |          |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WDT time-out interrupt Disabled.
+     * |        |          |1 = WDT time-out interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |WDTEN     |WDT Enable Control (Write Protect)
+     * |        |          |0 = WDT Disabled (This action will reset the internal up counter value).
+     * |        |          |1 = WDT Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
+     * |[10:8]  |TOUTSEL   |WDT Time-out Interval Selection (Write Protect)
+     * |        |          |These three bits select the time-out interval period for the WDT.
+     * |        |          |000 = 24 * WDT_CLK.
+     * |        |          |001 = 26 * WDT_CLK.
+     * |        |          |010 = 28 * WDT_CLK.
+     * |        |          |011 = 210 * WDT_CLK.
+     * |        |          |100 = 212 * WDT_CLK.
+     * |        |          |101 = 214 * WDT_CLK.
+     * |        |          |110 = 216 * WDT_CLK.
+     * |        |          |111 = 218 * WDT_CLK.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[30]    |SYNC      |WDT Enable Control SYNC Flag Indicator (Read Only)
+     * |        |          |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
+     * |        |          |0 = Set WDTEN bit is completed.
+     * |        |          |1 = Set WDTEN bit is synchronizing and not become active yet..
+     * |        |          |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement affects WDT counting.
+     * |        |          |WDT up counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |WDT up counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var WDT_T::ALTCTL
+     * Offset: 0x04  WDT Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RSTDSEL   |WDT Reset Delay Selection (Write Protect)
+     * |        |          |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened
+     * |        |          |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
+     * |        |          |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+     * |        |          |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+     * |        |          |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+     * |        |          |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This register will be reset to 0 if WDT time-out reset happened.
+     * @var WDT_T::RSTCNT
+     * Offset: 0x08  WDT Reset Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RSTCNT    |WDT Reset Counter Register
+     * |        |          |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
+     * |        |          |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
+     * |        |          |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit
+     * |        |          |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] WDT Control Register                                             */
+    __IO uint32_t ALTCTL;                /*!< [0x0004] WDT Alternative Control Register                                 */
+    __O  uint32_t RSTCNT;                /*!< [0x0008] WDT Reset Counter Register                                       */
+
+} WDT_T;
+
+/**
+    @addtogroup WDT_CONST WDT Bit Field Definition
+    Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_RSTCNT_Pos               (0)                                               /*!< WDT_T::CTL: RSTCNT Position            */
+#define WDT_CTL_RSTCNT_Msk               (0x1ul << WDT_CTL_RSTCNT_Pos)                     /*!< WDT_T::CTL: RSTCNT Mask                */
+
+#define WDT_CTL_RSTEN_Pos                (1)                                               /*!< WDT_T::CTL: RSTEN Position             */
+#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)                      /*!< WDT_T::CTL: RSTEN Mask                 */
+
+#define WDT_CTL_RSTF_Pos                 (2)                                               /*!< WDT_T::CTL: RSTF Position              */
+#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)                       /*!< WDT_T::CTL: RSTF Mask                  */
+
+#define WDT_CTL_IF_Pos                   (3)                                               /*!< WDT_T::CTL: IF Position                */
+#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)                         /*!< WDT_T::CTL: IF Mask                    */
+
+#define WDT_CTL_WKEN_Pos                 (4)                                               /*!< WDT_T::CTL: WKEN Position              */
+#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)                       /*!< WDT_T::CTL: WKEN Mask                  */
+
+#define WDT_CTL_WKF_Pos                  (5)                                               /*!< WDT_T::CTL: WKF Position               */
+#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)                        /*!< WDT_T::CTL: WKF Mask                   */
+
+#define WDT_CTL_INTEN_Pos                (6)                                               /*!< WDT_T::CTL: INTEN Position             */
+#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)                      /*!< WDT_T::CTL: INTEN Mask                 */
+
+#define WDT_CTL_WDTEN_Pos                (7)                                               /*!< WDT_T::CTL: WDTEN Position             */
+#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)                      /*!< WDT_T::CTL: WDTEN Mask                 */
+
+#define WDT_CTL_TOUTSEL_Pos              (8)                                               /*!< WDT_T::CTL: TOUTSEL Position           */
+#define WDT_CTL_TOUTSEL_Msk              (0x7ul << WDT_CTL_TOUTSEL_Pos)                    /*!< WDT_T::CTL: TOUTSEL Mask               */
+
+#define WDT_CTL_SYNC_Pos                 (30)                                              /*!< WDT_T::CTL: SYNC Position              */
+#define WDT_CTL_SYNC_Msk                 (0x1ul << WDT_CTL_SYNC_Pos)                       /*!< WDT_T::CTL: SYNC Mask                  */
+
+#define WDT_CTL_ICEDEBUG_Pos             (31)                                              /*!< WDT_T::CTL: ICEDEBUG Position          */
+#define WDT_CTL_ICEDEBUG_Msk             (0x1ul << WDT_CTL_ICEDEBUG_Pos)                   /*!< WDT_T::CTL: ICEDEBUG Mask              */
+
+#define WDT_ALTCTL_RSTDSEL_Pos           (0)                                               /*!< WDT_T::ALTCTL: RSTDSEL Position        */
+#define WDT_ALTCTL_RSTDSEL_Msk           (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)                 /*!< WDT_T::ALTCTL: RSTDSEL Mask            */
+
+#define WDT_RSTCNT_RSTCNT_Pos            (0)                                               /*!< WDT_T::RSTCNT: RSTCNT Position         */
+#define WDT_RSTCNT_RSTCNT_Msk            (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos)           /*!< WDT_T::RSTCNT: RSTCNT Mask             */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __WDT_REG_H__ */
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file     wwdt_reg.h
+ * @version  V1.00
+ * @brief    WWDT register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_REG_H__
+#define __WWDT_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup WWDT Window Watchdog Timer(WWDT)
+    Memory Mapped Structure for WWDT Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var WWDT_T::RLDCNT
+     * Offset: 0x00  WWDT Reload Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RLDCNT    |WWDT Reload Counter Register
+     * |        |          |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
+     * |        |          |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
+     * @var WWDT_T::CTL
+     * Offset: 0x04  WWDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTEN    |WWDT Enable Control Bit
+     * |        |          |Set this bit to enable WWDT counter counting.
+     * |        |          |0 = WWDT counter is stopped.
+     * |        |          |1 = WWDT counter is starting counting.
+     * |[1]     |INTEN     |WWDT Interrupt Enable Control Bit
+     * |        |          |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WWDT counter compare match interrupt Disabled.
+     * |        |          |1 = WWDT counter compare match interrupt Enabled.
+     * |[11:8]  |PSCSEL    |WWDT Counter Prescale Period Selection
+     * |        |          |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
+     * |        |          |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
+     * |        |          |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
+     * |        |          |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
+     * |        |          |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
+     * |        |          |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
+     * |        |          |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
+     * |        |          |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
+     * |        |          |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
+     * |        |          |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
+     * |        |          |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
+     * |        |          |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
+     * |        |          |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
+     * |        |          |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
+     * |        |          |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
+     * |        |          |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
+     * |[21:16] |CMPDAT    |WWDT Window Compare Register
+     * |        |          |Set this register to adjust the valid reload window.
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
+     * |        |          |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+     * |        |          |0 = ICE debug mode acknowledgement effects WWDT counting.
+     * |        |          |WWDT down counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |WWDT down counter will keep going no matter CPU is held by ICE or not.
+     * @var WWDT_T::STATUS
+     * Offset: 0x08  WWDT Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTIF    |WWDT Compare Match Interrupt Flag
+     * |        |          |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+     * |        |          |0 = No effect.
+     * |        |          |1 = WWDT counter value matches CMPDAT.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |WWDTRF    |WWDT Timer-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by WWDT time-out reset or not.
+     * |        |          |0 = WWDT time-out reset did not occur.
+     * |        |          |1 = WWDT time-out reset occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var WWDT_T::CNT
+     * Offset: 0x0C  WWDT Counter Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CNTDAT    |WWDT Counter Value
+     * |        |          |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+     */
+    __O  uint32_t RLDCNT;                /*!< [0x0000] WWDT Reload Counter Register                                     */
+    __IO uint32_t CTL;                   /*!< [0x0004] WWDT Control Register                                            */
+    __IO uint32_t STATUS;                /*!< [0x0008] WWDT Status Register                                             */
+    __I  uint32_t CNT;                   /*!< [0x000c] WWDT Counter Value Register                                      */
+
+} WWDT_T;
+
+/**
+    @addtogroup WWDT_CONST WWDT Bit Field Definition
+    Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLDCNT_RLDCNT_Pos           (0)                                               /*!< WWDT_T::RLDCNT: RLDCNT Position        */
+#define WWDT_RLDCNT_RLDCNT_Msk           (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)          /*!< WWDT_T::RLDCNT: RLDCNT Mask            */
+
+#define WWDT_CTL_WWDTEN_Pos              (0)                                               /*!< WWDT_T::CTL: WWDTEN Position           */
+#define WWDT_CTL_WWDTEN_Msk              (0x1ul << WWDT_CTL_WWDTEN_Pos)                    /*!< WWDT_T::CTL: WWDTEN Mask               */
+
+#define WWDT_CTL_INTEN_Pos               (1)                                               /*!< WWDT_T::CTL: INTEN Position            */
+#define WWDT_CTL_INTEN_Msk               (0x1ul << WWDT_CTL_INTEN_Pos)                     /*!< WWDT_T::CTL: INTEN Mask                */
+
+#define WWDT_CTL_PSCSEL_Pos              (8)                                               /*!< WWDT_T::CTL: PSCSEL Position           */
+#define WWDT_CTL_PSCSEL_Msk              (0xful << WWDT_CTL_PSCSEL_Pos)                    /*!< WWDT_T::CTL: PSCSEL Mask               */
+
+#define WWDT_CTL_CMPDAT_Pos              (16)                                              /*!< WWDT_T::CTL: CMPDAT Position           */
+#define WWDT_CTL_CMPDAT_Msk              (0x3ful << WWDT_CTL_CMPDAT_Pos)                   /*!< WWDT_T::CTL: CMPDAT Mask               */
+
+#define WWDT_CTL_ICEDEBUG_Pos            (31)                                              /*!< WWDT_T::CTL: ICEDEBUG Position         */
+#define WWDT_CTL_ICEDEBUG_Msk            (0x1ul << WWDT_CTL_ICEDEBUG_Pos)                  /*!< WWDT_T::CTL: ICEDEBUG Mask             */
+
+#define WWDT_STATUS_WWDTIF_Pos           (0)                                               /*!< WWDT_T::STATUS: WWDTIF Position        */
+#define WWDT_STATUS_WWDTIF_Msk           (0x1ul << WWDT_STATUS_WWDTIF_Pos)                 /*!< WWDT_T::STATUS: WWDTIF Mask            */
+
+#define WWDT_STATUS_WWDTRF_Pos           (1)                                               /*!< WWDT_T::STATUS: WWDTRF Position        */
+#define WWDT_STATUS_WWDTRF_Msk           (0x1ul << WWDT_STATUS_WWDTRF_Pos)                 /*!< WWDT_T::STATUS: WWDTRF Mask            */
+
+#define WWDT_CNT_CNTDAT_Pos              (0)                                               /*!< WWDT_T::CNT: CNTDAT Position           */
+#define WWDT_CNT_CNTDAT_Msk              (0x3ful << WWDT_CNT_CNTDAT_Pos)                   /*!< WWDT_T::CNT: CNTDAT Mask               */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __WWDT_REG_H__ */
@@ -0,0 +1,195 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000   /* 512k */
+  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x28000   /* 160k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
@@ -0,0 +1,195 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000   /* 512k */
+  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x20000   /* 128k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
@@ -0,0 +1,116 @@
+
+#ifndef ARM_SEMIHOSTING_H_
+#define ARM_SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum OperationNumber
+{
+    // Regular operations
+    SEMIHOSTING_EnterSVC = 0x17,
+    SEMIHOSTING_ReportException = 0x18,
+    SEMIHOSTING_SYS_CLOSE = 0x02,
+    SEMIHOSTING_SYS_CLOCK = 0x10,
+    SEMIHOSTING_SYS_ELAPSED = 0x30,
+    SEMIHOSTING_SYS_ERRNO = 0x13,
+    SEMIHOSTING_SYS_FLEN = 0x0C,
+    SEMIHOSTING_SYS_GET_CMDLINE = 0x15,
+    SEMIHOSTING_SYS_HEAPINFO = 0x16,
+    SEMIHOSTING_SYS_ISERROR = 0x08,
+    SEMIHOSTING_SYS_ISTTY = 0x09,
+    SEMIHOSTING_SYS_OPEN = 0x01,
+    SEMIHOSTING_SYS_READ = 0x06,
+    SEMIHOSTING_SYS_READC = 0x07,
+    SEMIHOSTING_SYS_REMOVE = 0x0E,
+    SEMIHOSTING_SYS_RENAME = 0x0F,
+    SEMIHOSTING_SYS_SEEK = 0x0A,
+    SEMIHOSTING_SYS_SYSTEM = 0x12,
+    SEMIHOSTING_SYS_TICKFREQ = 0x31,
+    SEMIHOSTING_SYS_TIME = 0x11,
+    SEMIHOSTING_SYS_TMPNAM = 0x0D,
+    SEMIHOSTING_SYS_WRITE = 0x05,
+    SEMIHOSTING_SYS_WRITEC = 0x03,
+    SEMIHOSTING_SYS_WRITE0 = 0x04,
+
+    // Codes returned by SEMIHOSTING_ReportException
+    ADP_Stopped_ApplicationExit = ((2 << 16) + 38),
+    ADP_Stopped_RunTimeError = ((2 << 16) + 35),
+
+};
+
+// ----------------------------------------------------------------------------
+
+// SWI numbers and reason codes for RDI (Angel) monitors.
+#define AngelSWI_ARM                    0x123456
+#ifdef __thumb__
+#define AngelSWI                        0xAB
+#else
+#define AngelSWI                        AngelSWI_ARM
+#endif
+// For thumb only architectures use the BKPT instruction instead of SWI.
+#if defined(__ARM_ARCH_7M__)     \
+    || defined(__ARM_ARCH_7EM__) \
+    || defined(__ARM_ARCH_6M__)
+#define AngelSWIInsn                    "bkpt"
+#define AngelSWIAsm                     bkpt
+#else
+#define AngelSWIInsn                    "swi"
+#define AngelSWIAsm                     swi
+#endif
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+// Testing the local semihosting handler cannot use another BKPT, since this
+// configuration cannot trigger HaedFault exceptions while the debugger is
+// connected, so we use an illegal op code, that will trigger an
+// UsageFault exception.
+#define AngelSWITestFault       "setend be"
+#define AngelSWITestFaultOpCode (0xB658)
+#endif
+
+static inline int
+__attribute__ ((always_inline))
+call_host (int reason, void* arg)
+{
+    int value;
+    asm volatile (
+
+        " mov r0, %[rsn]  \n"
+        " mov r1, %[arg]  \n"
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+        " " AngelSWITestFault " \n"
+#else
+        " " AngelSWIInsn " %[swi] \n"
+#endif
+        " mov %[val], r0"
+
+        : [val] "=r" (value) /* Outputs */
+        : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */
+        : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
+        // Clobbers r0 and r1, and lr if in supervisor mode
+    );
+
+    // Accordingly to page 13-77 of ARM DUI 0040D other registers
+    // can also be clobbered. Some memory positions may also be
+    // changed by a system call, so they should not be kept in
+    // registers. Note: we are assuming the manual is right and
+    // Angel is respecting the APCS.
+    return value;
+}
+
+// ----------------------------------------------------------------------------
+
+// Function used in _exit() to return the status code as Angel exception.
+static inline void
+__attribute__ ((always_inline,noreturn))
+report_exception (int reason)
+{
+    call_host (SEMIHOSTING_ReportException, (void*) reason);
+
+    for (;;)
+        ;
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // ARM_SEMIHOSTING_H_
@@ -0,0 +1,109 @@
+/**************************************************************************//**
+ * @file     system_M480.c
+ * @version  V1.000
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock  = __SYSTEM_CLOCK;    /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs      = (__HSI / 1000000UL); /* Cycles per micro second */
+uint32_t PllClock         = __HSI;             /*!< PLL Output Clock Frequency         */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+    uint32_t u32Freq, u32ClkSrc;
+    uint32_t u32HclkDiv;
+
+    /* Update PLL Clock */
+    PllClock = CLK_GetPLLClockFreq();
+
+    u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+    if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
+    {
+        /* Use PLL clock */
+        u32Freq = PllClock;
+    }
+    else
+    {
+        /* Use the clock sources directly */
+        u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+    }
+
+    u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
+
+    /* Update System Core Clock */
+    SystemCoreClock = u32Freq / u32HclkDiv;
+
+
+    //if(SystemCoreClock == 0)
+    //    __BKPT(0);
+
+    CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+/**
+  * @brief      Set PF.2 and PF.3 to input mode
+  * @param      None
+  * @return     None
+  * @details    GPIO default state could be configured as input or quasi through user config.
+  *             To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
+  *             PF.2 and PF.3 to input mode no matter which mode they are working at.
+  */
+static __INLINE void HXTInit(void)
+{
+    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+
+}
+
+/**
+ * @brief  Initialize the System
+ *
+ * @param  none
+ * @return none
+ */
+void SystemInit (void)
+{
+    /* Add your system initialize code here.
+       Do not use global variables because this function is called before
+       reaching pre-main. RW section maybe overwritten afterwards.          */
+
+
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+#endif
+
+    /* Set access cycle for CPU @ 192MHz */
+    FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
+    /* Configure power down bias, must set 1 before entering power down mode.
+       So set it at the very beginning */
+    CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
+    /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
+    CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+    RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
+                       RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
+    RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
+                       RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
+    CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+    HXTInit();
+
+}
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
@@ -0,0 +1,25 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+Nuvoton/M480/Source/system_M480.c
+""")
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['Nuvoton/M480/Source/GCC/startup.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['Nuvoton/M480/Source/ARM/startup_M480.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['Nuvoton/M480/Source/IAR/startup_M480.s']
+
+path = [cwd + '/Nuvoton/M480/Include',]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*src/*.c') + Glob('src/*.cpp')
+CPPPATH = [cwd + '/inc']
+
+group = DefineGroup('M487_StdPeriph', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,191 @@
+/**************************************************************************//**
+ * @file     can.h
+ * @version  V2.00
+ * @brief    M480 Series CAN Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_NORMAL_MODE   0ul    /*!< CAN select normal mode \hideinitializer */
+#define    CAN_BASIC_MODE    1ul    /*!< CAN select basic mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_STD_ID    0ul    /*!< CAN select standard ID \hideinitializer */
+#define    CAN_EXT_ID    1ul    /*!< CAN select extended ID \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_REMOTE_FRAME    0ul    /*!< CAN frame select remote frame \hideinitializer */
+#define    CAN_DATA_FRAME    1ul      /*!< CAN frame select data frame \hideinitializer */
+
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
+  @{
+*/
+/**
+  * @details    CAN message structure
+  */
+typedef struct
+{
+    uint32_t  IdType;       /*!< ID type */
+    uint32_t  FrameType;    /*!< Frame type */
+    uint32_t  Id;           /*!< Message ID */
+    uint8_t   DLC;          /*!< Data length */
+    uint8_t   Data[8];      /*!< Data */
+} STR_CANMSG_T;
+
+/**
+  * @details    CAN mask message structure
+  */
+typedef struct
+{
+    uint8_t   u8Xtd;      /*!< Extended ID */
+    uint8_t   u8Dir;      /*!< Direction */
+    uint32_t  u32Id;      /*!< Message ID */
+    uint8_t   u8IdType;   /*!< ID type*/
+} STR_CANMASK_T;
+
+/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */
+
+/** @cond HIDDEN_SYMBOLS */
+#define MSG(id)  (id)
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ *          EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ *          with the highest priority, disregarding their chronological order.
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details  The macro is used to disable wake-up function.
+ * \hideinitializer
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * \hideinitializer
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ *          or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ * \hideinitializer
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
+void CAN_WaitMsg(CAN_T *tCAN);
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg);
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CAN_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
@@ -0,0 +1,112 @@
+/**************************************************************************//**
+ * @file     crc.h
+ * @version  V1.00
+ * @brief    M480 series CRC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CRC Polynomial Mode Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT           (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
+#define CRC_8               (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
+#define CRC_16              (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
+#define CRC_32              (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Checksum, Write data Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CHECKSUM_COM    (CRC_CTL_CHKSFMT_Msk)       /*!<CRC Checksum Complement \hideinitializer */
+#define CRC_CHECKSUM_RVS    (CRC_CTL_CHKSREV_Msk)       /*!<CRC Checksum Reverse \hideinitializer */
+#define CRC_WDATA_COM       (CRC_CTL_DATFMT_Msk)        /*!<CRC Write Data Complement \hideinitializer */
+#define CRC_WDATA_RVS       (CRC_CTL_DATREV_Msk)        /*!<CRC Write Data Reverse \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CPU Write Data Length Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CPU_WDATA_8     (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 8-bit \hideinitializer */
+#define CRC_CPU_WDATA_16    (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 16-bit \hideinitializer */
+#define CRC_CPU_WDATA_32    (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 32-bit \hideinitializer */
+
+/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set CRC Seed Value
+  *
+  * @param[in]  u32Seed     Seed value
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set CRC seed value.
+  *
+  * @note       User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
+  *             to CRC controller.
+  * \hideinitializer
+  */
+#define CRC_SET_SEED(u32Seed)   do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
+
+/**
+ * @brief       Get CRC Seed Value
+ *
+  * @param      None
+ *
+ * @return      CRC seed value
+ *
+ * @details     This macro gets the current CRC seed value.
+ * \hideinitializer
+ */
+#define CRC_GET_SEED()          (CRC->SEED)
+
+/**
+ * @brief       CRC Write Data
+ *
+ * @param[in]   u32Data     Write data
+ *
+ * @return      None
+ *
+ * @details    User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ * \hideinitializer
+ */
+#define CRC_WRITE_DATA(u32Data)   (CRC->DAT = (u32Data))
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
@@ -0,0 +1,184 @@
+/**************************************************************************//**
+ * @file     emac.h
+ * @version  V1.00
+ * @brief    M480 EMAC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __EMAC_H__
+#define __EMAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EMAC_Driver EMAC Driver
+  @{
+*/
+
+/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+  @{
+*/
+
+#define EMAC_PHY_ADDR     1UL    /*!<  PHY address, this address is board dependent \hideinitializer */
+#define EMAC_RX_DESC_SIZE 4UL    /*!<  Number of Rx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_TX_DESC_SIZE 4UL    /*!<  Number of Tx Descriptors, should be 2 at least \hideinitializer */
+
+#define EMAC_LINK_DOWN    0UL    /*!<  Ethernet link is down \hideinitializer */
+#define EMAC_LINK_100F    1UL    /*!<  Ethernet link is 100Mbps full duplex \hideinitializer */
+#define EMAC_LINK_100H    2UL    /*!<  Ethernet link is 100Mbps half duplex \hideinitializer */
+#define EMAC_LINK_10F     3UL    /*!<  Ethernet link is 10Mbps full duplex \hideinitializer */
+#define EMAC_LINK_10H     4UL    /*!<  Ethernet link is 10Mbps half duplex \hideinitializer */
+
+/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Enable EMAC Tx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Enable EMAC Rx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
+
+/**
+  * @brief  Disable EMAC Tx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Disable EMAC Rx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
+
+/**
+  * @brief  Enable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
+
+/**
+  * @brief  Enable EMAC to receive broadcast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Disable EMAC to receive broadcast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Enable EMAC to receive multicast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Check if EMAC time stamp alarm interrupt occurred or not
+  * @param  None
+  * @return If time stamp alarm interrupt occurred or not
+  * @retval 0 Alarm interrupt does not occur
+  * @retval 1 Alarm interrupt occurred
+  * \hideinitializer
+  */
+#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
+
+/**
+  * @brief  Clear EMAC time stamp alarm interrupt flag
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
+
+
+void EMAC_Open(uint8_t *pu8MacAddr);
+void EMAC_Close(void);
+void EMAC_SetMacAddr(uint8_t *pu8MacAddr);
+void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]);
+void EMAC_DisableCamEntry(uint32_t u32Entry);
+
+uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size);
+uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_RecvPktDone(void);
+
+uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size);
+uint32_t EMAC_SendPktDone(void);
+uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+
+void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableTS(void);
+void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableAlarm(void);
+
+uint32_t EMAC_CheckLinkStatus(void);
+
+/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EMAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/