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https://github.com/RT-Thread/rt-thread.git
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modify for STM32 FW library 3.1.0.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@52 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong committed
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@@ -10,6 +10,7 @@
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2009-09-27 Bernard add protect when contex switch occurs
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; */
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;/**
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@@ -53,18 +54,28 @@ rt_hw_interrupt_enable:
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; * r0 --> from
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; * r1 --> to
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; */
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EXPORT rt_hw_context_switch_interrupt
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EXPORT rt_hw_context_switch
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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LDR r2, =rt_interrupt_from_thread
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STR r0, [r2]
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LDR r2, =rt_interrupt_to_thread
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STR r1, [r2]
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; set rt_thread_switch_interrput_flag to 1
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1
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STR r3, [r2]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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CPSIE I ; enable interrupts at processor level
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BX LR
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; r0 --> swith from thread stack
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@@ -72,6 +83,16 @@ rt_hw_context_switch:
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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EXPORT rt_hw_pend_sv
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rt_hw_pend_sv:
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; disable interrupt to protect context switch
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MRS r2, PRIMASK
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CPSID I
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; clear rt_thread_switch_interrput_flag to 0
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LDR r0, =rt_thread_switch_interrput_flag
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MOV r1, #0x00
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STR r1, [r0]
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LDR r0, =rt_interrupt_from_thread
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LDR r1, [r0]
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CBZ r1, swtich_to_thread ; skip register save at the first time
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@@ -89,6 +110,9 @@ swtich_to_thread
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LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
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MSR psp, r1 ; update stack pointer
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; restore interrupt
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MSR PRIMASK, r2
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ORR lr, lr, #0x04
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BX lr
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@@ -119,52 +143,9 @@ rt_hw_context_switch_to:
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; never reach here!
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)
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; * {
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; * if (rt_thread_switch_interrput_flag == 1)
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; * {
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; * rt_interrupt_to_thread = to;
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; * }
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; * else
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; * {
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; * rt_thread_switch_interrput_flag = 1;
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; * rt_interrupt_from_thread = from;
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; * rt_interrupt_to_thread = to;
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; * }
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; * }
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; */
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EXPORT rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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; compatible with old version
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EXPORT rt_hw_interrupt_thread_switch
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rt_hw_interrupt_thread_switch:
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LDR r0, =rt_thread_switch_interrput_flag
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LDR r1, [r0]
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CBZ r1, _no_switch
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; clear rt_thread_switch_interrput_flag to 0
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MOV r1, #0x00
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STR r1, [r0]
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; trigger context switch
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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_no_switch:
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BX lr
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END
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END
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@@ -0,0 +1,34 @@
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;/*
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; * File : context.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; */
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_hw_hard_fault_exception
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EXPORT rt_hw_hard_fault
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rt_hw_hard_fault:
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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END
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@@ -12,22 +12,24 @@
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; * 2009-01-17 Bernard first version
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; */
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AREA |.text|, CODE, READONLY, ALIGN=2
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THUMB
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REQUIRE8
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PRESERVE8
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AREA |.text|, CODE, READONLY, ALIGN=2
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_hw_hard_fault_exception
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IMPORT rt_hw_hard_fault_exception
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rt_hw_hard_fault PROC
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EXPORT rt_hw_hard_fault
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rt_hw_hard_fault PROC
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EXPORT rt_hw_hard_fault
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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BL rt_hw_hard_fault_exception
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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ORR lr, lr, #0x04
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BX lr
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ENDP
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END
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+587
-586
File diff suppressed because it is too large.
Load diff
@@ -5,7 +5,7 @@
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#include <rtthread.h>
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/* STM32F10x library definitions */
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#include <stm32f10x_lib.h>
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#include <stm32f10x.h>
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#define UART_DMA_RX_DESCRIPTOR 2
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#define UART_DMA_RX_BUFFER_SIZE 16
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@@ -1,176 +0,0 @@
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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32f10x_vector.c
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* Author : MCD Application Team
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* Version : V2.0.3
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* Date : 09/22/2008
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* Description : STM32F10x vector table for EWARM5.x toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == __iar_program_start,
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure external SRAM mounted on STM3210E-EVAL board
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* to be used as data memory (optional, to be enabled by user)
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* After Reset the Cortex-M3 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_lib.h"
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#include "stm32f10x_it.h"
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/* Private typedef -----------------------------------------------------------*/
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typedef void( *intfunc )( void );
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typedef union { intfunc __fun; void * __ptr; } intvec_elem;
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/* Private define ------------------------------------------------------------*/
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/* Uncomment the following line if you need to use external SRAM mounted on
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STM3210E-EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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#pragma language=extended
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#pragma segment="CSTACK"
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void __iar_program_start( void );
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#pragma location = ".intvec"
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/* STM32F10x Vector Table entries */
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const intvec_elem __vector_table[] =
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{
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{ .__ptr = __sfe( "CSTACK" ) },
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__iar_program_start,
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NMIException,
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HardFaultException,
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MemManageException,
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BusFaultException,
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UsageFaultException,
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0, 0, 0, 0, /* Reserved */
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SVCHandler,
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DebugMonitor,
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0, /* Reserved */
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rt_hw_pend_sv,
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SysTickHandler,
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WWDG_IRQHandler,
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PVD_IRQHandler,
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TAMPER_IRQHandler,
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RTC_IRQHandler,
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FLASH_IRQHandler,
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RCC_IRQHandler,
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EXTI0_IRQHandler,
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EXTI1_IRQHandler,
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EXTI2_IRQHandler,
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EXTI3_IRQHandler,
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EXTI4_IRQHandler,
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DMA1_Channel1_IRQHandler,
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DMA1_Channel2_IRQHandler,
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DMA1_Channel3_IRQHandler,
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DMA1_Channel4_IRQHandler,
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DMA1_Channel5_IRQHandler,
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DMA1_Channel6_IRQHandler,
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DMA1_Channel7_IRQHandler,
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ADC1_2_IRQHandler,
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USB_HP_CAN_TX_IRQHandler,
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USB_LP_CAN_RX0_IRQHandler,
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CAN_RX1_IRQHandler,
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CAN_SCE_IRQHandler,
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EXTI9_5_IRQHandler,
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TIM1_BRK_IRQHandler,
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TIM1_UP_IRQHandler,
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TIM1_TRG_COM_IRQHandler,
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TIM1_CC_IRQHandler,
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TIM2_IRQHandler,
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TIM3_IRQHandler,
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TIM4_IRQHandler,
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I2C1_EV_IRQHandler,
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I2C1_ER_IRQHandler,
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I2C2_EV_IRQHandler,
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I2C2_ER_IRQHandler,
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SPI1_IRQHandler,
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SPI2_IRQHandler,
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USART1_IRQHandler,
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USART2_IRQHandler,
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USART3_IRQHandler,
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EXTI15_10_IRQHandler,
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RTCAlarm_IRQHandler,
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USBWakeUp_IRQHandler,
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TIM8_BRK_IRQHandler,
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TIM8_UP_IRQHandler,
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TIM8_TRG_COM_IRQHandler,
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TIM8_CC_IRQHandler,
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ADC3_IRQHandler,
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FSMC_IRQHandler,
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SDIO_IRQHandler,
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TIM5_IRQHandler,
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SPI3_IRQHandler,
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UART4_IRQHandler,
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UART5_IRQHandler,
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TIM6_IRQHandler,
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TIM7_IRQHandler,
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DMA2_Channel1_IRQHandler,
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DMA2_Channel2_IRQHandler,
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DMA2_Channel3_IRQHandler,
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DMA2_Channel4_5_IRQHandler,
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};
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#ifdef DATA_IN_ExtSRAM
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#pragma language=extended
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__interwork int __low_level_init(void);
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#pragma location="ICODE"
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__interwork int __low_level_init(void)
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{
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/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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required, then adjust the Register Addresses*/
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/* Enable FSMC clock */
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*(vu32 *)0x40021014 = 0x00000114;
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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*(vu32 *)0x40021018 = 0x000001E0;
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/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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/*---------------- SRAM Address lines configuration -------------------------*/
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/*---------------- NOE and NWE configuration --------------------------------*/
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/*---------------- NE3 configuration ----------------------------------------*/
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/*---------------- NBL0, NBL1 configuration ---------------------------------*/
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*(vu32 *)0x40011400 = 0x44BB44BB;
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*(vu32 *)0x40011404 = 0xBBBBBBBB;
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*(vu32 *)0x40011800 = 0xB44444BB;
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*(vu32 *)0x40011804 = 0xBBBBBBBB;
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*(vu32 *)0x40011C00 = 0x44BBBBBB;
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*(vu32 *)0x40011C04 = 0xBBBB4444;
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*(vu32 *)0x40012000 = 0x44BBBBBB;
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*(vu32 *)0x40012004 = 0x44444B44;
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/*---------------- FSMC Configuration ---------------------------------------*/
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/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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*(vu32 *)0xA0000010 = 0x00001011;
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*(vu32 *)0xA0000014 = 0x00000200;
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return (1);
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}
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#endif /*DATA_IN_ExtSRAM*/
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/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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File diff suppressed because it is too large.
Load diff
+120
-103
File diff suppressed because it is too large.
Load diff
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