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https://github.com/RT-Thread/rt-thread.git
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[bsp][nuvoton_m487]Add EMAC drive
This commit is contained in:
Bluebear233
@@ -42,6 +42,7 @@
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| 驱动 | 支持情况 | 备注 |
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| ------ | ---- | :------: |
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| UART | 支持 | UART0|
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| EMAC | 支持 | EH0|
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### 4.1 IO在板级支持包中的映射情况
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@@ -1,4 +1,4 @@
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# RT-Thread building script for component
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# RT-Thread building script for component
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from building import *
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@@ -6,6 +6,7 @@ cwd = GetCurrentDir()
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src = Split('''
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board.c
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drv_uart.c
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drv_emac.c
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''')
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CPPPATH = [cwd]
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@@ -8,9 +8,7 @@
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* 2018-11-16 bluebear233 first version
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*/
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#include <rtconfig.h>
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#include <rtthread.h>
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#include <rthw.h>
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#include "NuMicro.h"
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#include "drv_uart.h"
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#include "board.h"
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@@ -15,22 +15,7 @@
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#define SRAM_SIZE (160)
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#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
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#define RT_UART_485_MODE 1
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#define RT_UART_FLOW_CTS_CTRL 2
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#define RT_UART_FLOW_RTS_CTRL 3
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#define RT_UART_CLEAR_BUF 4
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void rt_hw_pdma_init(void);
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void rt_hw_uart_handle(void);
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void rt_hw_sc_init(void);
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void rt_hw_usart_init(void);
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void rt_hw_uusart_init(void);
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void rt_hw_io_init(void);
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void phy_error_led(void);
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unsigned char *eth_get_default_mac(void);
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void eth_set_mac(const unsigned char * mac);
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void wdt_reload(void);
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unsigned int get_uid(void);
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void rt_hw_board_init(void);
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void rt_hw_cpu_reset(void);
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#endif /* BOARD_H_ */
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733
bsp/nuvoton_m487/driver/drv_emac.c
Normal file
733
bsp/nuvoton_m487/driver/drv_emac.c
Normal file
File diff suppressed because it is too large
Load Diff
126
bsp/nuvoton_m487/driver/drv_emac.h
Normal file
126
bsp/nuvoton_m487/driver/drv_emac.h
Normal file
@@ -0,0 +1,126 @@
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/*
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* Copyright (c) 2016 Nuvoton Technology Corp.
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* Description: M480 EMAC driver header file
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*/
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#include "NuMicro.h"
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#ifndef _M480_ETH_
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#define _M480_ETH_
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/* Generic MII registers. */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* Basic mode control register. */
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#define BMCR_RESV 0x007f /* Unused... */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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/* Basic mode status register. */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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#define BMSR_RFAULT 0x0010 /* Remote fault detected */
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#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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#define BMSR_RESV 0x07c0 /* Unused... */
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#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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/* Advertisement control register. */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_RESV 0x1c00 /* Unused... */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define RX_DESCRIPTOR_NUM 4 // Max Number of Rx Frame Descriptors
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#define TX_DESCRIPTOR_NUM 2 // Max number of Tx Frame Descriptors
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#define PACKET_BUFFER_SIZE 1520
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#define CONFIG_PHY_ADDR 1
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// Frame Descriptor's Owner bit
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#define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
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//#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
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// Rx Frame Descriptor Status
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#define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
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#define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
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// Tx Frame Descriptor's Control bits
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#define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
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#define TXFD_INTEN 0x04 // Interrupt Enable
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#define TXFD_CRCAPP 0x02 // Append CRC
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#define TXFD_PADEN 0x01 // Padding Enable
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// Tx Frame Descriptor Status
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#define TXFD_TXCP 0x00080000 // Transmission Completion
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#define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
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// Tx/Rx buffer descriptor structure
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struct eth_descriptor;
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struct eth_descriptor
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{
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uint32_t status1;
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uint8_t *buf;
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uint32_t status2;
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struct eth_descriptor *next;
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#ifdef TIME_STAMPING
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u32_t backup1;
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u32_t backup2;
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u32_t reserved1;
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u32_t reserved2;
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#endif
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};
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#ifdef TIME_STAMPING
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#define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)
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#define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)
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s32_t ETH_settime(u32_t sec, u32_t nsec);
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s32_t ETH_gettime(u32_t *sec, u32_t *nsec);
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s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);
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s32_t ETH_adjtimex(int ppm);
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void ETH_setinc(void);
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#endif
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#endif /* _M480_ETH_ */
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@@ -315,11 +315,6 @@ static rt_err_t usart_control(struct rt_serial_device *serial,
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}
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break;
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// TODO 完善DMA接口
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// case RT_DEVICE_FLAG_DMA_TX:
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// USART_DMACmd(dev->usart_base, USART_DMAReq_Tx, ENABLE);
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// stm32_uart_tx_dma_configure(dev, RT_TRUE);
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// stm32_uart_tx_dma_nvic(dev, RT_TRUE);
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// break;
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default:
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RT_ASSERT(0)
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;
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@@ -365,9 +360,9 @@ static int usart_receive(struct rt_serial_device *serial)
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/**
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* @brief 串口设备注册
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* @param uart : UART设备结构体
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* @param uart_base : STM32 UART外设基地址
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* @param name : STM32 UART设备名
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* @param tx_dma_channel : STM32 UART TX的DMA通道基地址(可选)
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* @param uart_base : UART外设基地址
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* @param name : UART设备名
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* @param tx_dma_channel : UART TX的DMA通道基地址(可选)
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*/
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static void rt_hw_uart_register(usart_t usart, UART_T * uart_base, char *name)
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{
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@@ -36,6 +36,7 @@
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#define RT_USING_CONSOLE
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart0"
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#define RT_VER_NUM 0x40000
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/* RT-Thread Components */
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@@ -147,11 +148,6 @@
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/* RT-Thread online packages */
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/* system packages */
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/* RT-Thread GUI Engine */
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/* IoT - internet of things */
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@@ -163,6 +159,9 @@
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/* Wiced WiFi */
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/* IoT Cloud */
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/* security packages */
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@@ -175,10 +174,16 @@
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/* tools packages */
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/* system packages */
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/* peripheral libraries and drivers */
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/* miscellaneous packages */
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/* example package: hello */
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/* samples: kernel and components samples */
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#endif
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