[bluetrum] add sound and romfs support

This commit is contained in:
greedyhao committed 2020-12-19 10:45:03 +08:00
1 parent a9d7e7021e
commit 67bf5cea1f
17 files changed
+692 -39

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+25 -7
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@@ -19,10 +19,10 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=1024
CONFIG_IDLE_THREAD_STACK_SIZE=512
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_TIMER_THREAD_STACK_SIZE=256
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -96,7 +96,7 @@ CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_THREAD_STACK_SIZE=2048
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
@@ -107,7 +107,18 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
@@ -134,7 +145,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
CONFIG_RT_USING_AUDIO=y
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=1024
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=512
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
@@ -153,6 +167,7 @@ CONFIG_RT_USING_PIN=y
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
# CONFIG_RT_USING_MODULE is not set
#
@@ -325,6 +340,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
#
# system packages
@@ -419,6 +436,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
#
# miscellaneous packages
@@ -430,8 +448,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_MULTIBUTTON_V102 is not set
# CONFIG_PKG_USING_MULTIBUTTON_LATEST_VERSION is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
@@ -484,6 +500,8 @@ CONFIG_BSP_USING_USB_TO_USART=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_USING_AUDIO=y
CONFIG_BSP_USING_AUDIO_PLAY=y
#
# Board extended module Drivers
+3 -1
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@@ -102,7 +102,9 @@ msh >
## 注意事项
波特率默认为 1.5M,需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片
波特率默认为 1.5M,需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片,需要编译后自动下载,需要在 `Downloader` 中的下载的下拉窗中选择 `自动`;目前暂时屏蔽 uart1 打印
使用 `romfs` 时,需要自己生成 `romfs.c` 进行替换,操作参考[使用 RomFS](https://www.rt-thread.org/document/site/tutorial/qemu-network/filesystems/filesystems/#romfs)
编译报错的时候,如果出现重复定义的报错,可能需要在 `cconfig.h` 中手动添加以下配置
@@ -0,0 +1,21 @@
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_fs.h>
#include "dfs_romfs.h"
int mnt_init(void)
{
if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
{
rt_kprintf("ROM file system initializated!\n");
}
else
{
rt_kprintf("ROM file system initializate failed!\n");
}
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
@@ -0,0 +1,17 @@
/* Generated by mkromfs. Edit with caution. */
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_romfs.h>
static const struct romfs_dirent _romfs_root[] = {
{ROMFS_DIRENT_FILE, "ab32vg1", RT_NULL, 0}
};
const struct romfs_dirent romfs_root = {
ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root)/sizeof(_romfs_root[0])
};
#endif
+15 -4
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@@ -8,14 +8,25 @@ menu "Onboard Peripheral Drivers"
select BSP_USING_UART0
default y
menuconfig BSP_USING_AUDIO
bool "Enable Audio Device"
select RT_USING_AUDIO
default n
if BSP_USING_AUDIO
config BSP_USING_AUDIO_PLAY
bool "Enable Audio Play"
default y
endif
endmenu
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART0
bool "Enable UART0"
select RT_USING_SERIAL
default y
menuconfig BSP_USING_UART0
bool "Enable UART0"
select RT_USING_SERIAL
default y
endmenu
@@ -9,6 +9,9 @@ ab32vg1_hal_msp.c
''')
CPPPATH = [cwd]
if GetDepend(['RT_USING_AUDIO']):
src += Glob('ports/audio/drv_sound.c')
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
objs = [group]
File diff suppressed because it is too large. Load diff
Binary file not shown.
+18 -13
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@@ -1,12 +1,16 @@
/* Define the flash max size */
__max_flash_size = 768k;
__comm_ram_size = 104k;
__heap_ram_size = 14k;
__data_ram_size = 5k;
__stack_ram_size = 4k;
__comm_ram_size = 86k;
__heap_ram_size = 29k;
__base = 0x10000000;
__comm_vma = 0x12800;
__data_vma = 0x11000;
__stack_vma = __data_vma + __data_ram_size;
__comm_vma = __stack_vma + __stack_ram_size;
__heap_vma = __comm_vma + __comm_ram_size;
__ram1_vma = 0x50000;
@@ -17,8 +21,8 @@ MEMORY
flash(rx) : org = __base + 512, len = __max_flash_size
comm(rx) : org = __comm_vma, len = __comm_ram_size
data : org = 0x11000, len = 5k
stack : org = 0x12400, len = 1k
data : org = __data_vma, len = __data_ram_size
stack : org = __stack_vma, len = __stack_ram_size
heap : org = __heap_vma, len = __heap_ram_size
ram1(rx) : org = __ram1_vma, len = 0x7a00
}
@@ -30,11 +34,10 @@ SECTIONS
} > init
.ram1 __ram1_vma : {
/*board\\ports\\*.o(.text*)*/
*hal_drivers\\*.o(.text*)
*hal_libraries\\ab32vg1_hal\\*.o(.text*)
*components\\drivers\\*.o(.text* .rodata*)
*components\\libc\\*.o(.text*)
*hal_drivers**.o(.text*)
*hal_libraries*ab32vg1_hal**.o(.text*)
*components*drivers**.o(.text* .rodata*)
*components*libc**.o(.text*)
*ab32vg1_hal_msp.o(.text*)
*components.o(.text* .rodata*)
*ipc.o(.text* .rodata*)
@@ -63,8 +66,8 @@ SECTIONS
.comm : {
KEEP(*(.vector))
*(.text*)
*(.rodata*)
EXCLUDE_FILE (*romfs.o *lib_a**.o) *(.text*)
EXCLUDE_FILE (*romfs.o *lib_a**.o) *(.rodata*)
*(.srodata*)
*(.rela*)
*(.data*)
@@ -73,6 +76,8 @@ SECTIONS
} > comm AT > flash
.flash : {
*romfs.o *(.text* .rodata*)
*lib_a**.o *(.text* .rodata*)
. = ALIGN(512);
} > flash
@@ -89,7 +94,7 @@ SECTIONS
.stack (NOLOAD) : {
__irq_stack_start = .;
. = 0x400;
. = __stack_ram_size;
__irq_stack = .;
} > stack
__irq_stack_size = __irq_stack - __irq_stack_start;
+15 -3
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@@ -15,10 +15,10 @@
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define IDLE_THREAD_STACK_SIZE 512
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 256
#define RT_DEBUG
/* Inter-Thread communication */
@@ -64,7 +64,7 @@
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 2048
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
@@ -72,6 +72,12 @@
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_ROMFS
/* Device Drivers */
@@ -80,6 +86,10 @@
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 1024
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 512
/* Using USB */
@@ -163,6 +173,8 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_UART0
#define BSP_USING_AUDIO
#define BSP_USING_AUDIO_PLAY
/* Board extended module Drivers */
@@ -58,6 +58,7 @@ if PLATFORM == 'gcc':
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION += './riscv32-elf-xmaker -b rtthread.xm\n'
POST_ACTION += './riscv32-elf-xmaker -b download.xm\n'
def dist_handle(BSP_ROOT, dist_dir):
import sys
+17 -4
View File
@@ -13,8 +13,8 @@
#include <rthw.h>
#include "ab32vgx.h"
uint32_t irq_mask AT(.bss.irq_tbl);
void *tbl_irq_vector[IRQ_TOTAL_NUM] AT(.bss.irq_tbl);
uint32_t irq_mask;
void *tbl_irq_vector[IRQ_TOTAL_NUM];
void (*cpu_irq_comm_hook)(void);
void set_cpu_irq_comm(void (*irq_hook)(void))
@@ -22,7 +22,6 @@ void set_cpu_irq_comm(void (*irq_hook)(void))
cpu_irq_comm_hook = irq_hook;
}
AT(.com_text.irq)
void cpu_irq_comm_do(void)
{
void (*pfnct)(void);
@@ -37,6 +36,20 @@ void cpu_irq_comm_do(void)
}
}
void rt_hw_irq_enable(int vector)
{
if (vector < IRQ_TOTAL_NUM) {
PICEN |= BIT(vector);
}
}
void rt_hw_irq_disable(int vector)
{
if (vector < IRQ_TOTAL_NUM) {
PICEN &= ~BIT(vector);
}
}
void rt_hw_interrupt_init(void)
{
}
@@ -58,7 +71,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector,
rt_isr_handler_t old_handler = RT_NULL;
if (vector < IRQ_TOTAL_NUM) {
uint32_t cpu_ie = PICCON&BIT(0);
uint32_t cpu_ie = PICCON & BIT(0);
PICCON &= ~BIT(0);
old_handler = tbl_irq_vector[vector];
tbl_irq_vector[vector] = handler;
+7
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@@ -0,0 +1,7 @@
#ifndef INTERRUPT_H__
#define INTERRUPT_H__
void rt_hw_irq_enable(int vector);
void rt_hw_irq_disable(int vector);
#endif
@@ -136,8 +136,8 @@ static int ab32_getc(struct rt_serial_device *serial)
ch = -1;
if(hal_uart_getflag(uart->handle.instance, UART_FLAG_RXPND) != HAL_RESET) {
hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
ch = hal_uart_read(uart->handle.instance);
hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
}
return ch;
@@ -156,10 +156,10 @@ static void uart_isr(int vector, void *param)
{
rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
}
if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
}
// if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
// {
// rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
// }
rt_interrupt_leave();
}
@@ -2,8 +2,6 @@
static uint32_t hw_ticks = 0;
void timer0_cfg(uint32_t ticks);
static void (*tick_cfg_hook)(uint32_t ticks) = HAL_NULL;
void hal_set_tick_hook(void (*hook)(uint32_t ticks))
@@ -133,8 +133,29 @@ typedef enum
#define TMR2CNT SFR_RW (SFR0_BASE + 0x3c*4)
#define TMR2PR SFR_RW (SFR0_BASE + 0x3d*4)
//------------------------- SFR Group1 ---------------------------------------//
#define AUBUFDATA SFR_RW (SFR1_BASE + 0x01*4)
#define AUBUFCON SFR_RW (SFR1_BASE + 0x02*4)
#define AUBUFSTARTADDR SFR_RW (SFR1_BASE + 0x03*4)
#define AUBUFSIZE SFR_RW (SFR1_BASE + 0x04*4)
#define AUBUFFIFOCNT SFR_RW (SFR1_BASE + 0x05*4)
#define AUBUF1DATA SFR_RW (SFR1_BASE + 0x06*4)
#define AUBUF1CON SFR_RW (SFR1_BASE + 0x07*4)
#define AUBUF1STARTADDR SFR_RW (SFR1_BASE + 0x08*4)
#define AUBUF1SIZE SFR_RW (SFR1_BASE + 0x09*4)
#define AUBUF1FIFOCNT SFR_RW (SFR1_BASE + 0x0a*4)
#define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4)
#define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4)
#define AU0LMIXCOEF SFR_RW (SFR1_BASE + 0x12*4)
#define AU0RMIXCOEF SFR_RW (SFR1_BASE + 0x13*4)
#define AU1LMIXCOEF SFR_RW (SFR1_BASE + 0x14*4)
#define AU1RMIXCOEF SFR_RW (SFR1_BASE + 0x15*4)
#define AUANGCON0 SFR_RW (SFR1_BASE + 0x3c*4)
#define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4)
#define AUANGCON2 SFR_RW (SFR1_BASE + 0x3e*4)
#define AUANGCON3 SFR_RW (SFR1_BASE + 0x3f*4)
#define USBCON0 SFR_RW (SFR3_BASE + 0x00*4)
#define USBCON1 SFR_RW (SFR3_BASE + 0x01*4)
@@ -148,6 +169,7 @@ typedef enum
#define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4)
#define PLL0CON SFR_RW (SFR3_BASE + 0x26*4)
#define PLL1CON SFR_RW (SFR3_BASE + 0x27*4)
#define PLL2CON SFR_RW (SFR3_BASE + 0x28*4)
#define XO26MCON SFR_RW (SFR3_BASE + 0x29*4)
#define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4)
#define CLKGAT0 SFR_RW (SFR3_BASE + 0x2c*4)
@@ -174,6 +196,7 @@ typedef enum
#define PICPR SFR_RW (SFR5_BASE + 0x12*4)
#define PICADR SFR_RW (SFR5_BASE + 0x13*4)
#define PICPND SFR_RW (SFR5_BASE + 0x14*4)
#define EPICCON SFR_RW (SFR5_BASE + 0x1e*4)
#define EPC SFR_RW (SFR5_BASE + 0x1f*4)
#define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4)
@@ -56,6 +56,43 @@ _start:
jal x0, low_prio_irq
mret
.org 0x80
#define METHOD 1
#if METHOD == 1
addi sp, sp, -6*4
lw a0, PICEN(zero)
lw a1, EPC(zero)
lw a2, EPICCON(zero)
sw a0, 3*4(sp)
sw a1, 4*4(sp)
sw a2, 5*4(sp)
andi a0, a0, 1
sw a0, PICEN(zero)
la a0, 0f
sw a0, EPC(zero)
j 0x84020
0:
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
lw a0, 3*4(sp)
lw a1, 4*4(sp)
lw a2, 5*4(sp)
sw a0, PICEN(zero)
sw a1, EPC(zero)
sw a2, EPICCON(zero)
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
addi sp, sp, 6*4
mret
.align 4
1: .word 0, 0
j 0x84020
#endif
.global cpu_irq_comm
cpu_irq_comm:
la a5, __irq_stack