mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-11-08 14:43:04 +08:00
[bluetrum] add sound and romfs support
This commit is contained in:
1 parent
a9d7e7021e
commit
67bf5cea1f
17 files changed
+692
-39
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@@ -19,10 +19,10 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=1024
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CONFIG_IDLE_THREAD_STACK_SIZE=512
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CONFIG_RT_USING_TIMER_SOFT=y
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CONFIG_RT_TIMER_THREAD_PRIO=4
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CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
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CONFIG_RT_TIMER_THREAD_STACK_SIZE=256
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CONFIG_RT_DEBUG=y
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# CONFIG_RT_DEBUG_COLOR is not set
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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@@ -96,7 +96,7 @@ CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_THREAD_STACK_SIZE=2048
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CONFIG_FINSH_CMD_SIZE=80
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_USING_MSH=y
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@@ -107,7 +107,18 @@ CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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# CONFIG_RT_USING_DFS is not set
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=2
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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# CONFIG_RT_USING_DFS_ELMFAT is not set
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# CONFIG_RT_USING_DFS_DEVFS is not set
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CONFIG_RT_USING_DFS_ROMFS=y
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# CONFIG_RT_USING_DFS_RAMFS is not set
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# CONFIG_RT_USING_DFS_UFFS is not set
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# CONFIG_RT_USING_DFS_JFFS2 is not set
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#
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# Device Drivers
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@@ -134,7 +145,10 @@ CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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CONFIG_RT_USING_AUDIO=y
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CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=1024
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CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
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CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=512
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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# CONFIG_RT_USING_HWCRYPTO is not set
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@@ -153,6 +167,7 @@ CONFIG_RT_USING_PIN=y
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#
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CONFIG_RT_USING_LIBC=y
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# CONFIG_RT_USING_PTHREADS is not set
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# CONFIG_RT_USING_POSIX is not set
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# CONFIG_RT_USING_MODULE is not set
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#
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@@ -325,6 +340,8 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_UMCN is not set
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# CONFIG_PKG_USING_LWRB2RTT is not set
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# CONFIG_PKG_USING_CPU_USAGE is not set
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# CONFIG_PKG_USING_GBK2UTF8 is not set
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# CONFIG_PKG_USING_VCONSOLE is not set
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#
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# system packages
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@@ -419,6 +436,7 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_SSD1306 is not set
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# CONFIG_PKG_USING_QKEY is not set
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# CONFIG_PKG_USING_RS485 is not set
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# CONFIG_PKG_USING_NES is not set
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#
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# miscellaneous packages
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@@ -430,8 +448,6 @@ CONFIG_RT_USING_LIBC=y
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# CONFIG_PKG_USING_QUICKLZ is not set
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# CONFIG_PKG_USING_LZMA is not set
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# CONFIG_PKG_USING_MULTIBUTTON is not set
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# CONFIG_PKG_USING_MULTIBUTTON_V102 is not set
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# CONFIG_PKG_USING_MULTIBUTTON_LATEST_VERSION is not set
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# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
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# CONFIG_PKG_USING_CANFESTIVAL is not set
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# CONFIG_PKG_USING_ZLIB is not set
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@@ -484,6 +500,8 @@ CONFIG_BSP_USING_USB_TO_USART=y
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# On-chip Peripheral Drivers
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#
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CONFIG_BSP_USING_UART0=y
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CONFIG_BSP_USING_AUDIO=y
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CONFIG_BSP_USING_AUDIO_PLAY=y
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#
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# Board extended module Drivers
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@@ -102,7 +102,9 @@ msh >
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## 注意事项
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波特率默认为 1.5M,需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片
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波特率默认为 1.5M,需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片,需要编译后自动下载,需要在 `Downloader` 中的下载的下拉窗中选择 `自动`;目前暂时屏蔽 uart1 打印
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使用 `romfs` 时,需要自己生成 `romfs.c` 进行替换,操作参考[使用 RomFS](https://www.rt-thread.org/document/site/tutorial/qemu-network/filesystems/filesystems/#romfs)
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编译报错的时候,如果出现重复定义的报错,可能需要在 `cconfig.h` 中手动添加以下配置
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@@ -0,0 +1,21 @@
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#include <rtthread.h>
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#ifdef RT_USING_DFS
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#include <dfs_fs.h>
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#include "dfs_romfs.h"
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int mnt_init(void)
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{
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if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
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{
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rt_kprintf("ROM file system initializated!\n");
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}
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else
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{
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rt_kprintf("ROM file system initializate failed!\n");
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}
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return 0;
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}
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INIT_ENV_EXPORT(mnt_init);
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#endif
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@@ -0,0 +1,17 @@
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/* Generated by mkromfs. Edit with caution. */
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#include <rtthread.h>
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#ifdef RT_USING_DFS
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#include <dfs_romfs.h>
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static const struct romfs_dirent _romfs_root[] = {
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{ROMFS_DIRENT_FILE, "ab32vg1", RT_NULL, 0}
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};
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const struct romfs_dirent romfs_root = {
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ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root)/sizeof(_romfs_root[0])
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};
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#endif
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@@ -8,14 +8,25 @@ menu "Onboard Peripheral Drivers"
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select BSP_USING_UART0
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default y
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menuconfig BSP_USING_AUDIO
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bool "Enable Audio Device"
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select RT_USING_AUDIO
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default n
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if BSP_USING_AUDIO
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config BSP_USING_AUDIO_PLAY
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bool "Enable Audio Play"
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default y
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endif
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endmenu
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menu "On-chip Peripheral Drivers"
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menuconfig BSP_USING_UART0
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bool "Enable UART0"
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select RT_USING_SERIAL
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default y
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menuconfig BSP_USING_UART0
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bool "Enable UART0"
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select RT_USING_SERIAL
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default y
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endmenu
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@@ -9,6 +9,9 @@ ab32vg1_hal_msp.c
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''')
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CPPPATH = [cwd]
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if GetDepend(['RT_USING_AUDIO']):
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src += Glob('ports/audio/drv_sound.c')
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group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
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objs = [group]
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File diff suppressed because it is too large.
Load diff
Binary file not shown.
@@ -1,12 +1,16 @@
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/* Define the flash max size */
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__max_flash_size = 768k;
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__comm_ram_size = 104k;
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__heap_ram_size = 14k;
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__data_ram_size = 5k;
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__stack_ram_size = 4k;
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__comm_ram_size = 86k;
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__heap_ram_size = 29k;
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__base = 0x10000000;
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__comm_vma = 0x12800;
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__data_vma = 0x11000;
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__stack_vma = __data_vma + __data_ram_size;
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__comm_vma = __stack_vma + __stack_ram_size;
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__heap_vma = __comm_vma + __comm_ram_size;
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__ram1_vma = 0x50000;
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@@ -17,8 +21,8 @@ MEMORY
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flash(rx) : org = __base + 512, len = __max_flash_size
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comm(rx) : org = __comm_vma, len = __comm_ram_size
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data : org = 0x11000, len = 5k
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stack : org = 0x12400, len = 1k
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data : org = __data_vma, len = __data_ram_size
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stack : org = __stack_vma, len = __stack_ram_size
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heap : org = __heap_vma, len = __heap_ram_size
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ram1(rx) : org = __ram1_vma, len = 0x7a00
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}
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@@ -30,11 +34,10 @@ SECTIONS
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} > init
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.ram1 __ram1_vma : {
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/*board\\ports\\*.o(.text*)*/
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*hal_drivers\\*.o(.text*)
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*hal_libraries\\ab32vg1_hal\\*.o(.text*)
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*components\\drivers\\*.o(.text* .rodata*)
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*components\\libc\\*.o(.text*)
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*hal_drivers**.o(.text*)
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*hal_libraries*ab32vg1_hal**.o(.text*)
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*components*drivers**.o(.text* .rodata*)
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*components*libc**.o(.text*)
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*ab32vg1_hal_msp.o(.text*)
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*components.o(.text* .rodata*)
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*ipc.o(.text* .rodata*)
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@@ -63,8 +66,8 @@ SECTIONS
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.comm : {
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KEEP(*(.vector))
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*(.text*)
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*(.rodata*)
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EXCLUDE_FILE (*romfs.o *lib_a**.o) *(.text*)
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EXCLUDE_FILE (*romfs.o *lib_a**.o) *(.rodata*)
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*(.srodata*)
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*(.rela*)
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*(.data*)
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@@ -73,6 +76,8 @@ SECTIONS
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} > comm AT > flash
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.flash : {
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*romfs.o *(.text* .rodata*)
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*lib_a**.o *(.text* .rodata*)
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. = ALIGN(512);
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} > flash
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@@ -89,7 +94,7 @@ SECTIONS
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.stack (NOLOAD) : {
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__irq_stack_start = .;
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. = 0x400;
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. = __stack_ram_size;
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__irq_stack = .;
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} > stack
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__irq_stack_size = __irq_stack - __irq_stack_start;
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@@ -15,10 +15,10 @@
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#define RT_USING_HOOK
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#define RT_USING_IDLE_HOOK
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#define RT_IDLE_HOOK_LIST_SIZE 4
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#define IDLE_THREAD_STACK_SIZE 1024
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#define IDLE_THREAD_STACK_SIZE 512
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#define RT_USING_TIMER_SOFT
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#define RT_TIMER_THREAD_PRIO 4
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#define RT_TIMER_THREAD_STACK_SIZE 512
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#define RT_TIMER_THREAD_STACK_SIZE 256
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#define RT_DEBUG
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/* Inter-Thread communication */
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@@ -64,7 +64,7 @@
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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#define FINSH_THREAD_PRIORITY 20
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#define FINSH_THREAD_STACK_SIZE 4096
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#define FINSH_THREAD_STACK_SIZE 2048
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#define FINSH_CMD_SIZE 80
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#define FINSH_USING_MSH
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#define FINSH_USING_MSH_DEFAULT
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@@ -72,6 +72,12 @@
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/* Device virtual file system */
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#define RT_USING_DFS
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#define DFS_USING_WORKDIR
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#define DFS_FILESYSTEMS_MAX 2
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#define DFS_FILESYSTEM_TYPES_MAX 2
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#define DFS_FD_MAX 16
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#define RT_USING_DFS_ROMFS
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/* Device Drivers */
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@@ -80,6 +86,10 @@
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#define RT_USING_SERIAL
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#define RT_SERIAL_RB_BUFSZ 64
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#define RT_USING_PIN
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#define RT_USING_AUDIO
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#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 1024
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#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
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#define RT_AUDIO_RECORD_PIPE_SIZE 512
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/* Using USB */
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@@ -163,6 +173,8 @@
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/* On-chip Peripheral Drivers */
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#define BSP_USING_UART0
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#define BSP_USING_AUDIO
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#define BSP_USING_AUDIO_PLAY
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/* Board extended module Drivers */
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@@ -58,6 +58,7 @@ if PLATFORM == 'gcc':
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DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
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POST_ACTION += './riscv32-elf-xmaker -b rtthread.xm\n'
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POST_ACTION += './riscv32-elf-xmaker -b download.xm\n'
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def dist_handle(BSP_ROOT, dist_dir):
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import sys
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@@ -13,8 +13,8 @@
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#include <rthw.h>
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#include "ab32vgx.h"
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uint32_t irq_mask AT(.bss.irq_tbl);
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void *tbl_irq_vector[IRQ_TOTAL_NUM] AT(.bss.irq_tbl);
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uint32_t irq_mask;
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void *tbl_irq_vector[IRQ_TOTAL_NUM];
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void (*cpu_irq_comm_hook)(void);
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void set_cpu_irq_comm(void (*irq_hook)(void))
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@@ -22,7 +22,6 @@ void set_cpu_irq_comm(void (*irq_hook)(void))
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cpu_irq_comm_hook = irq_hook;
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}
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AT(.com_text.irq)
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void cpu_irq_comm_do(void)
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{
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void (*pfnct)(void);
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@@ -37,6 +36,20 @@ void cpu_irq_comm_do(void)
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}
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}
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void rt_hw_irq_enable(int vector)
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{
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if (vector < IRQ_TOTAL_NUM) {
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PICEN |= BIT(vector);
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}
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}
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void rt_hw_irq_disable(int vector)
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{
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if (vector < IRQ_TOTAL_NUM) {
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PICEN &= ~BIT(vector);
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}
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}
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void rt_hw_interrupt_init(void)
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{
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}
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@@ -58,7 +71,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector,
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < IRQ_TOTAL_NUM) {
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uint32_t cpu_ie = PICCON&BIT(0);
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uint32_t cpu_ie = PICCON & BIT(0);
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PICCON &= ~BIT(0);
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old_handler = tbl_irq_vector[vector];
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tbl_irq_vector[vector] = handler;
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@@ -0,0 +1,7 @@
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#ifndef INTERRUPT_H__
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#define INTERRUPT_H__
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void rt_hw_irq_enable(int vector);
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void rt_hw_irq_disable(int vector);
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#endif
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@@ -136,8 +136,8 @@ static int ab32_getc(struct rt_serial_device *serial)
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ch = -1;
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if(hal_uart_getflag(uart->handle.instance, UART_FLAG_RXPND) != HAL_RESET) {
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hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
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ch = hal_uart_read(uart->handle.instance);
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hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
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}
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return ch;
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@@ -156,10 +156,10 @@ static void uart_isr(int vector, void *param)
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{
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rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
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}
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if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
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{
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rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
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}
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// if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
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// {
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// rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
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// }
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rt_interrupt_leave();
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}
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@@ -2,8 +2,6 @@
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||||
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||||
static uint32_t hw_ticks = 0;
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||||
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void timer0_cfg(uint32_t ticks);
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static void (*tick_cfg_hook)(uint32_t ticks) = HAL_NULL;
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void hal_set_tick_hook(void (*hook)(uint32_t ticks))
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@@ -133,8 +133,29 @@ typedef enum
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#define TMR2CNT SFR_RW (SFR0_BASE + 0x3c*4)
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#define TMR2PR SFR_RW (SFR0_BASE + 0x3d*4)
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//------------------------- SFR Group1 ---------------------------------------//
|
||||
#define AUBUFDATA SFR_RW (SFR1_BASE + 0x01*4)
|
||||
#define AUBUFCON SFR_RW (SFR1_BASE + 0x02*4)
|
||||
#define AUBUFSTARTADDR SFR_RW (SFR1_BASE + 0x03*4)
|
||||
#define AUBUFSIZE SFR_RW (SFR1_BASE + 0x04*4)
|
||||
#define AUBUFFIFOCNT SFR_RW (SFR1_BASE + 0x05*4)
|
||||
#define AUBUF1DATA SFR_RW (SFR1_BASE + 0x06*4)
|
||||
#define AUBUF1CON SFR_RW (SFR1_BASE + 0x07*4)
|
||||
#define AUBUF1STARTADDR SFR_RW (SFR1_BASE + 0x08*4)
|
||||
#define AUBUF1SIZE SFR_RW (SFR1_BASE + 0x09*4)
|
||||
#define AUBUF1FIFOCNT SFR_RW (SFR1_BASE + 0x0a*4)
|
||||
|
||||
#define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4)
|
||||
#define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4)
|
||||
#define AU0LMIXCOEF SFR_RW (SFR1_BASE + 0x12*4)
|
||||
#define AU0RMIXCOEF SFR_RW (SFR1_BASE + 0x13*4)
|
||||
#define AU1LMIXCOEF SFR_RW (SFR1_BASE + 0x14*4)
|
||||
#define AU1RMIXCOEF SFR_RW (SFR1_BASE + 0x15*4)
|
||||
|
||||
#define AUANGCON0 SFR_RW (SFR1_BASE + 0x3c*4)
|
||||
#define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4)
|
||||
#define AUANGCON2 SFR_RW (SFR1_BASE + 0x3e*4)
|
||||
#define AUANGCON3 SFR_RW (SFR1_BASE + 0x3f*4)
|
||||
|
||||
#define USBCON0 SFR_RW (SFR3_BASE + 0x00*4)
|
||||
#define USBCON1 SFR_RW (SFR3_BASE + 0x01*4)
|
||||
@@ -148,6 +169,7 @@ typedef enum
|
||||
#define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4)
|
||||
#define PLL0CON SFR_RW (SFR3_BASE + 0x26*4)
|
||||
#define PLL1CON SFR_RW (SFR3_BASE + 0x27*4)
|
||||
#define PLL2CON SFR_RW (SFR3_BASE + 0x28*4)
|
||||
#define XO26MCON SFR_RW (SFR3_BASE + 0x29*4)
|
||||
#define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4)
|
||||
#define CLKGAT0 SFR_RW (SFR3_BASE + 0x2c*4)
|
||||
@@ -174,6 +196,7 @@ typedef enum
|
||||
#define PICPR SFR_RW (SFR5_BASE + 0x12*4)
|
||||
#define PICADR SFR_RW (SFR5_BASE + 0x13*4)
|
||||
#define PICPND SFR_RW (SFR5_BASE + 0x14*4)
|
||||
#define EPICCON SFR_RW (SFR5_BASE + 0x1e*4)
|
||||
#define EPC SFR_RW (SFR5_BASE + 0x1f*4)
|
||||
|
||||
#define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4)
|
||||
|
||||
@@ -56,6 +56,43 @@ _start:
|
||||
jal x0, low_prio_irq
|
||||
mret
|
||||
|
||||
.org 0x80
|
||||
#define METHOD 1
|
||||
#if METHOD == 1
|
||||
addi sp, sp, -6*4
|
||||
lw a0, PICEN(zero)
|
||||
lw a1, EPC(zero)
|
||||
lw a2, EPICCON(zero)
|
||||
sw a0, 3*4(sp)
|
||||
sw a1, 4*4(sp)
|
||||
sw a2, 5*4(sp)
|
||||
andi a0, a0, 1
|
||||
sw a0, PICEN(zero)
|
||||
la a0, 0f
|
||||
sw a0, EPC(zero)
|
||||
j 0x84020
|
||||
0:
|
||||
sw a0, 0(sp)
|
||||
sw a1, 4(sp)
|
||||
sw a2, 8(sp)
|
||||
|
||||
lw a0, 3*4(sp)
|
||||
lw a1, 4*4(sp)
|
||||
lw a2, 5*4(sp)
|
||||
sw a0, PICEN(zero)
|
||||
sw a1, EPC(zero)
|
||||
sw a2, EPICCON(zero)
|
||||
|
||||
lw a0, 0(sp)
|
||||
lw a1, 4(sp)
|
||||
lw a2, 8(sp)
|
||||
addi sp, sp, 6*4
|
||||
mret
|
||||
.align 4
|
||||
1: .word 0, 0
|
||||
j 0x84020
|
||||
#endif
|
||||
|
||||
.global cpu_irq_comm
|
||||
cpu_irq_comm:
|
||||
la a5, __irq_stack
|
||||
|
||||
Reference in new issue
Block a user