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add apm32 rtt sdio/flash/sdram driver (#7065)

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* add rtt sdio/flash/sdram driver

* formatting rtt drivers
This commit is contained in:
luobeihai authored and GitHub committed 2023-03-20 00:04:18 -04:00
1 parent 4b8f518c48
commit 674c4d4ebc
85 files changed
+3588 -1335
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bsp/apm32/apm32f051r8-evalboard/README.md
+1 -1
View File
@@ -15,7 +15,7 @@
APM32F051R8 EVAL BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
![image-20230114161253327](../../../../../abc/rt-thread/bsp/apm32/apm32f051r8-evalboard/figures/APM32F051R8-EVAL.png)
![APM32F051R8-EVAL](figures/APM32F051R8-EVAL.png)
- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)
bsp/apm32/apm32f072vb-miniboard/.config
+16 -6
View File
@@ -58,6 +58,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
@@ -207,6 +208,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -302,6 +304,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -378,12 +381,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -398,6 +395,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -505,6 +503,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
#
# peripheral libraries and drivers
@@ -576,6 +575,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -714,6 +714,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -903,6 +904,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -932,10 +934,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -978,6 +987,7 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#
bsp/apm32/apm32f072vb-miniboard/board/Kconfig
+4
View File
@@ -199,6 +199,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
bsp/apm32/apm32f072vb-miniboard/board/SConscript
+1
View File
@@ -12,6 +12,7 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
bsp/apm32/apm32f072vb-miniboard/board/board.h
+6
View File
@@ -41,6 +41,12 @@
#include "apm32f0xx_iwdt.h"
#include "apm32f0xx_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f0xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f0xx_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f072vb-miniboard/board/ports/fal_cfg.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 112 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 112 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f072vb-miniboard/project.uvoptx
+2 -2
View File
@@ -356,7 +356,7 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -472,7 +472,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
bsp/apm32/apm32f072vb-miniboard/project.uvprojx
+1 -1
View File
@@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F072xB</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension;.;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\ipc;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;board;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;applications;..\libraries\Drivers;board\ports;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\..\..\libcpu\arm\common;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
bsp/apm32/apm32f072vb-miniboard/rtconfig.h
+2 -3
View File
@@ -34,6 +34,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@@ -140,9 +141,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -215,6 +213,7 @@
/* Other */
/* Signal IO */
bsp/apm32/apm32f091vc-miniboard/.config
+15 -16
View File
@@ -146,13 +146,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -214,6 +208,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -386,12 +381,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -406,6 +395,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -585,6 +575,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -723,6 +714,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -912,6 +904,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -941,10 +934,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -984,11 +984,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_I2C is not set
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI1=y
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#
bsp/apm32/apm32f091vc-miniboard/board/Kconfig
+4
View File
@@ -199,6 +199,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
bsp/apm32/apm32f091vc-miniboard/board/SConscript
+1
View File
@@ -12,6 +12,7 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
bsp/apm32/apm32f091vc-miniboard/board/board.h
+6
View File
@@ -41,6 +41,12 @@
#include "apm32f0xx_iwdt.h"
#include "apm32f0xx_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f0xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f0xx_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f091vc-miniboard/board/ports/fal_cfg.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f091vc-miniboard/project.uvoptx
+102 -170
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/apm32f091vc-miniboard/project.uvprojx
+1 -31
View File
@@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, APM32F091xC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F0xx_Library\CMSIS\Include;..\libraries\Drivers\config;board;..\..\..\components\finsh;..\..\..\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\stdio;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\..\..\components\drivers\include;..\libraries\Drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\libcpu\arm\common;applications;..\..\..\components\libc\compilers\common\extension;.;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\utilities\libadt</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;board\ports;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\Drivers;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\..\..\components\libc\compilers\common\include;..\..\..\include;..\..\..\libcpu\arm\common;..\libraries\APM32F0xx_Library\CMSIS\Include;applications;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -380,16 +380,6 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>ADT</GroupName>
<Files>
<File>
<FileName>avl.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\utilities\libadt\avl.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Applications</GroupName>
<Files>
@@ -518,16 +508,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
<File>
<FileName>spi_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
</File>
<File>
<FileName>spi_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
</File>
</Files>
</Group>
<Group>
@@ -553,11 +533,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_spi.c</FilePath>
</File>
<File>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
@@ -668,11 +643,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_eint.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_spi.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_misc.c</FileName>
<FileType>1</FileType>
bsp/apm32/apm32f091vc-miniboard/rtconfig.h
+1 -6
View File
@@ -80,7 +80,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SPI
/* Using USB */
@@ -142,9 +141,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -217,6 +213,7 @@
/* Other */
/* Signal IO */
@@ -236,8 +233,6 @@
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_SPI
#define BSP_USING_SPI1
/* Board extended module Drivers */
bsp/apm32/apm32f103vb-miniboard/.config
+13 -6
View File
@@ -210,6 +210,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -382,12 +383,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -402,6 +397,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -581,6 +577,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -719,6 +716,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -908,6 +906,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -937,10 +936,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -979,4 +985,5 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
bsp/apm32/apm32f103vb-miniboard/board/Kconfig
+4
View File
@@ -184,6 +184,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
bsp/apm32/apm32f103vb-miniboard/board/SConscript
+5 -4
View File
@@ -12,20 +12,21 @@ board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.S']
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.S']
# APM32F10X_LD || APM32F10X_MD || APM32F10X_HD || APM32F10X_CL
# You can select chips from the list above
CPPDEFINES = ['APM32F10X_MD']
CPPDEFINES = ['APM32F10X_HD']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/apm32/apm32f103vb-miniboard/board/board.h
+6
View File
@@ -41,6 +41,12 @@
#include "apm32f10x_iwdt.h"
#include "apm32f10x_wwdt.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f103vb-miniboard/board/ports/fal_cfg.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f103vb-miniboard/project.uvoptx
+17 -5
View File
@@ -183,7 +183,7 @@
<Group>
<GroupName>Applications</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -363,7 +363,7 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -479,7 +479,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -502,8 +502,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_md.s</PathWithFileName>
<FilenameWithoutPath>startup_apm32f10x_md.s</FilenameWithoutPath>
<PathWithFileName>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</PathWithFileName>
<FilenameWithoutPath>startup_apm32f10x_hd.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@@ -843,6 +843,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</PathWithFileName>
<FilenameWithoutPath>apm32f10x_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>
bsp/apm32/apm32f103vb-miniboard/project.uvprojx
+9 -4
View File
@@ -337,9 +337,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>APM32F10X_MD, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F10X_HD</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;board;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\components\drivers\include;.</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\libcpu\arm\cortex-m3;board;..\..\..\components\libc\compilers\common\extension;.;board\ports;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -519,9 +519,9 @@
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>startup_apm32f10x_md.s</FileName>
<FileName>startup_apm32f10x_hd.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_md.s</FilePath>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
@@ -668,6 +668,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath>
</File>
<File>
<FileName>apm32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>
bsp/apm32/apm32f103vb-miniboard/rtconfig.h
+1 -3
View File
@@ -144,9 +144,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -219,6 +216,7 @@
/* Other */
/* Signal IO */
bsp/apm32/apm32f103xe-minibroard/.config
+52 -10
View File
@@ -60,6 +60,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
@@ -122,7 +123,29 @@ CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
@@ -158,7 +181,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=512
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@@ -221,6 +250,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -316,6 +346,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -392,12 +423,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -412,6 +437,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -519,6 +545,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
#
# peripheral libraries and drivers
@@ -590,6 +617,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -728,6 +756,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -917,6 +946,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -946,10 +976,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -974,6 +1011,11 @@ CONFIG_SOC_SERIES_APM32F1=y
#
CONFIG_SOC_APM32F103ZE=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
@@ -984,10 +1026,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_RTC_USING_LSE is not set
# CONFIG_BSP_RTC_USING_LSI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
bsp/apm32/apm32f103xe-minibroard/board/Kconfig
+21
View File
@@ -7,6 +7,17 @@ config SOC_APM32F103ZE
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
@@ -170,6 +181,16 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
bsp/apm32/apm32f103xe-minibroard/board/SConscript
+4
View File
@@ -11,7 +11,11 @@ src = Split('''
board.c
''')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
bsp/apm32/apm32f103xe-minibroard/board/board.c
+20
View File
@@ -43,3 +43,23 @@ void apm32_usart_init(void)
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
#endif
}
void apm32_msp_sdio_init(void *Instance)
{
GPIO_Config_T GPIO_InitStructure;
/* Enable the GPIO and DMA2 Clock */
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC | RCM_APB2_PERIPH_GPIOD);
/* Enable the SDIO Clock */
RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_SDIO);
/* Configure the GPIO pin */
GPIO_InitStructure.pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
GPIO_InitStructure.mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.pin = GPIO_PIN_2;
GPIO_Config(GPIOD, &GPIO_InitStructure);
}
bsp/apm32/apm32f103xe-minibroard/board/board.h
+13
View File
@@ -21,6 +21,7 @@
#include "apm32f10x_rcm.h"
#include "apm32f10x_eint.h"
#include "apm32f10x_usart.h"
#include "apm32f10x_dma.h"
#if defined(RT_USING_ADC)
#include "apm32f10x_adc.h"
@@ -42,6 +43,18 @@
#include "apm32f10x_iwdt.h"
#include "apm32f10x_wwdt.h"
#endif
#if defined(BSP_USING_SDCARD)
#include "apm32f10x_sdio.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#if defined(BSP_USING_SDRAM)
#include "apm32f10x_dmc.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f103xe-minibroard/board/ports/fal_cfg.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 496 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 496* 1024 , 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f103xe-minibroard/board/ports/sdcard_port.c
+66
View File
@@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int apm32_sdcard_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
return RT_EOK;
}
INIT_APP_EXPORT(apm32_sdcard_mount);
#endif /* BSP_USING_SDCARD */
bsp/apm32/apm32f103xe-minibroard/project.uvoptx
+4 -735
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/apm32f103xe-minibroard/project.uvprojx
+226 -63
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/apm32f103xe-minibroard/rtconfig.h
+26 -3
View File
@@ -36,6 +36,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@@ -78,6 +79,21 @@
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* Device Drivers */
@@ -88,6 +104,12 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 512
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@@ -149,9 +171,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -224,6 +243,7 @@
/* Other */
/* Signal IO */
@@ -236,6 +256,9 @@
#define SOC_APM32F103ZE
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
bsp/apm32/apm32f107vc-evalboard/.config
+13 -6
View File
@@ -212,6 +212,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -384,12 +385,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -404,6 +399,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -583,6 +579,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -721,6 +718,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -910,6 +908,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -939,10 +938,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -988,6 +994,7 @@ CONFIG_BSP_USING_UART4=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
#
bsp/apm32/apm32f107vc-evalboard/board/Kconfig
+4
View File
@@ -214,6 +214,10 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
bsp/apm32/apm32f107vc-evalboard/board/board.c
+1 -1
View File
@@ -150,7 +150,7 @@ void phy_reset(void)
/*
* GPIO Configuration for ETH
*/
void ETH_GPIO_Configuration(void)
void apm32_msp_eth_init(void *instance)
{
#ifdef BSP_USING_ETH
GPIO_Config_T GPIO_ConfigStruct;
bsp/apm32/apm32f107vc-evalboard/board/board.h
+6
View File
@@ -44,6 +44,12 @@
#if defined(BSP_USING_ETH)
#include "apm32f10x_eth.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f10x_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f10x_can.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f107vc-evalboard/board/ports/fal_cfg.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev apm32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 240 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 240 * 1024, 16 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f107vc-evalboard/project.uvoptx
+113 -121
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/apm32f107vc-evalboard/project.uvprojx
+6 -11
View File
@@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>APM32F10X_CL, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\Drivers\config;board\ports;..\..\..\components\finsh;..\..\..\include;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;.;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\libraries\Drivers;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;board;applications;..\..\..\libcpu\arm\cortex-m3;..\..\..\libcpu\arm\common;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\utilities\libadt</IncludePath>
<IncludePath>..\..\..\components\libc\posix\ipc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;.;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\drivers\include;board;applications;board\ports;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -380,16 +380,6 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>ADT</GroupName>
<Files>
<File>
<FileName>avl.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\utilities\libadt\avl.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Applications</GroupName>
<Files>
@@ -678,6 +668,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</FilePath>
</File>
<File>
<FileName>apm32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>
bsp/apm32/apm32f107vc-evalboard/rtconfig.h
+1 -3
View File
@@ -147,9 +147,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -222,6 +219,7 @@
/* Other */
/* Signal IO */
bsp/apm32/apm32f407zg-evalboard/.config
+17 -6
View File
@@ -212,6 +212,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
@@ -384,12 +385,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -405,6 +400,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -584,6 +580,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
@@ -722,6 +719,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -911,6 +909,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
@@ -940,10 +939,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -973,6 +979,8 @@ CONFIG_SOC_APM32F407ZG=y
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_ETH is not set
#
@@ -989,7 +997,10 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_DMC is not set
#
# Board extended module Drivers
bsp/apm32/apm32f407zg-evalboard/board/Kconfig
+26
View File
@@ -23,6 +23,18 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_SFDP
default n
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
select BSP_USING_DMC
default n
config BSP_USING_ETH
bool "Enable Ethernet"
default n
@@ -242,11 +254,25 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_DMC
bool
default n
endmenu
menu "Board extended module Drivers"
bsp/apm32/apm32f407zg-evalboard/board/SConscript
+6
View File
@@ -14,6 +14,12 @@ board.c
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash_init.c')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
if GetDepend(['BSP_USING_SDRAM']):
src += Glob('ports/drv_sdram.c')
path = [cwd]
path += [cwd + '/ports']
bsp/apm32/apm32f407zg-evalboard/board/board.c
+36 -1
View File
@@ -149,7 +149,7 @@ void phy_reset(void)
/*
* GPIO Configuration for ETH
*/
void ETH_GPIO_Configuration(void)
void apm32_msp_eth_init(void *instance)
{
#ifdef BSP_USING_ETH
GPIO_Config_T GPIO_ConfigStruct;
@@ -202,3 +202,38 @@ void ETH_GPIO_Configuration(void)
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_7, GPIO_AF_ETH);
#endif
}
void apm32_msp_sdio_init(void *Instance)
{
GPIO_Config_T GPIO_InitStructure;
/* Enable the GPIO Clock */
RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOC | RCM_AHB1_PERIPH_GPIOD);
/* Enable the SDIO Clock */
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SDIO);
/* Enable the SDIO peripheral reset */
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SDIO);
/* Configure the GPIO pin */
GPIO_InitStructure.pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
GPIO_InitStructure.mode = GPIO_MODE_AF;
GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
GPIO_InitStructure.otype = GPIO_OTYPE_PP;
GPIO_InitStructure.pupd = GPIO_PUPD_UP;
GPIO_Config(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.pin = GPIO_PIN_2;
GPIO_Config(GPIOD, &GPIO_InitStructure);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_8, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_9, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_10, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_11, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOC,GPIO_PIN_SOURCE_12, GPIO_AF_SDIO);
GPIO_ConfigPinAF(GPIOD,GPIO_PIN_SOURCE_2, GPIO_AF_SDIO);
/* Disable the SDIO peripheral reset */
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SDIO);
}
bsp/apm32/apm32f407zg-evalboard/board/board.h
+13
View File
@@ -21,6 +21,7 @@
#include "apm32f4xx_rcm.h"
#include "apm32f4xx_eint.h"
#include "apm32f4xx_usart.h"
#include "apm32f4xx_dma.h"
#if defined(RT_USING_ADC)
#include "apm32f4xx_adc.h"
@@ -45,6 +46,18 @@
#if defined(BSP_USING_ETH)
#include "apm32f4xx_eth.h"
#endif
#if defined(BSP_USING_SDCARD)
#include "apm32f4xx_sdio.h"
#endif
#if defined(BSP_USING_ON_CHIP_FLASH)
#include "apm32f4xx_fmc.h"
#endif
#if defined(RT_USING_CAN)
#include "apm32f4xx_can.h"
#endif
#if defined(BSP_USING_SDRAM)
#include "apm32f4xx_dmc.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
bsp/apm32/apm32f407zg-evalboard/board/ports/drv_sdram.c
+245
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/apm32f407zg-evalboard/board/ports/drv_sdram.h
+41
View File
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#ifndef __DRV_SDRAM_H__
#define __DRV_SDRAM_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* apm32f407 Bank Addr: 0x60000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0x60000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers */
#define SDRAM_COLUMN_BITS DMC_COL_WIDTH_8
/* row bit numbers */
#define SDRAM_ROW_BITS DMC_ROW_WIDTH_11
#define SDRAM_SIZE ((uint32_t)0x200000)
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif
bsp/apm32/apm32f407zg-evalboard/board/ports/fal_cfg.h
+49
View File
@@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024)
#define FLASH_SIZE_GRANULARITY_64K (64 * 1024)
#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024)
#define APM32_FLASH_START_ADRESS_16K APM32_FLASH_START_ADRESS
#define APM32_FLASH_START_ADRESS_64K (APM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K)
#define APM32_FLASH_START_ADRESS_128K (APM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K)
extern const struct fal_flash_dev apm32_onchip_flash_16k;
extern const struct fal_flash_dev apm32_onchip_flash_64k;
extern const struct fal_flash_dev apm32_onchip_flash_128k;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&apm32_onchip_flash_16k, \
&apm32_onchip_flash_64k, \
&apm32_onchip_flash_128k, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
bsp/apm32/apm32f407zg-evalboard/board/ports/sdcard_port.c
+66
View File
@@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-18 luobeihai first version
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int apm32_sdcard_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
return RT_EOK;
}
INIT_APP_EXPORT(apm32_sdcard_mount);
#endif /* BSP_USING_SDCARD */
bsp/apm32/apm32f407zg-evalboard/project.uvoptx
+15 -3
View File
@@ -807,6 +807,18 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_dma.c</PathWithFileName>
<FilenameWithoutPath>apm32f4xx_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c</PathWithFileName>
<FilenameWithoutPath>apm32f4xx_eint.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@@ -814,7 +826,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>49</FileNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -826,7 +838,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>50</FileNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -838,7 +850,7 @@
</File>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileNumber>52</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
bsp/apm32/apm32f407zg-evalboard/project.uvprojx
+7 -2
View File
@@ -10,7 +10,7 @@
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
@@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\io\poll;.;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F4xx_Library\CMSIS\Include;board;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;applications;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;board\ports;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc</IncludePath>
<IncludePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\libraries\Drivers;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\drivers\include;board\ports;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;.;applications;..\..\..\include;..\..\..\libcpu\arm\common;board;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\poll</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -653,6 +653,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c</FilePath>
</File>
<File>
<FileName>apm32f4xx_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_dma.c</FilePath>
</File>
<File>
<FileName>apm32f4xx_eint.c</FileName>
<FileType>1</FileType>
bsp/apm32/apm32f407zg-evalboard/rtconfig.h
+1 -3
View File
@@ -147,9 +147,6 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@@ -222,6 +219,7 @@
/* Other */
/* Signal IO */
bsp/apm32/libraries/APM32F0xx_Library/SConscript
+3
View File
@@ -39,6 +39,9 @@ if GetDepend(['RT_USING_WDT']):
if GetDepend(['RT_USING_CAN']):
src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_fmc.c']
path = [cwd + '/Device/Geehy/APM32F0xx/Include',
cwd + '/APM32F0xx_StdPeriphDriver/inc',
cwd + '/CMSIS/Include']
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c
+2 -2
View File
@@ -75,7 +75,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
uint32_t PCLK1 = 8000000, PCLK2 = 0;
uint16_t result = 0x04;
i2c->SWITCH = 0;
i2c->I2C_SWITCH = 0;
/* I2C CTRL2 Configuration */
RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
@@ -399,7 +399,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
case I2C_REGISTER_RISETMAX:
return i2c->RISETMAX;
case I2C_REGISTER_SWITCH:
return i2c->SWITCH;
return i2c->I2C_SWITCH;
default:
return 0;
}
bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h
+4 -4
View File
@@ -3351,11 +3351,11 @@ typedef struct
/* @brief I2C Switching register */
union
{
__IOM uint32_t SWITCH;
__IOM uint32_t I2C_SWITCH;
struct
{
__IOM uint32_t SWITCH : 1;
__IOM uint32_t I2C_SWITCH : 1;
__IM uint32_t RESERVED1 : 31;
} SWITCH_B;
};
@@ -6111,11 +6111,11 @@ typedef struct
/* @brief Buffer table address register */
union
{
__IOM uint32_t SWITCH;
__IOM uint32_t USB_SWITCH;
struct
{
__IOM uint32_t SWITCH : 1;
__IOM uint32_t USB_SWITCH : 1;
__IM uint32_t RESERVED : 31;
} SWITCH_B;
};
bsp/apm32/libraries/APM32F10x_Library/SConscript
+13
View File
@@ -13,6 +13,7 @@ APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c
APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c
APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c
APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c
APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c
""")
if GetDepend(['RT_USING_ADC']):
@@ -35,6 +36,18 @@ if GetDepend(['RT_USING_WDT']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c']
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c']
if GetDepend(['RT_USING_CAN']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_can.c']
if GetDepend(['RT_USING_SDIO']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c']
if GetDepend(['BSP_USING_SDRAM']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c']
if GetDepend(['BSP_USING_ETH']):
src += ['APM32F10x_ETH_Driver/src/apm32f10x_eth.c']
bsp/apm32/libraries/APM32F4xx_Library/SConscript
+17
View File
@@ -14,6 +14,7 @@ APM32F4xx_StdPeriphDriver/src/apm32f4xx_misc.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_rcm.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_usart.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_eint.c
APM32F4xx_StdPeriphDriver/src/apm32f4xx_dma.c
""")
if GetDepend(['RT_USING_ADC']):
@@ -36,6 +37,18 @@ if GetDepend(['RT_USING_WDT']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_wwdt.c']
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_iwdt.c']
if GetDepend(['RT_USING_CAN']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_can.c']
if GetDepend(['RT_USING_SDIO']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_sdio.c']
if GetDepend(['BSP_USING_SDRAM']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_dmc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_fmc.c']
if GetDepend(['BSP_USING_ETH']):
src += ['APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c']
@@ -45,6 +58,10 @@ path = [cwd + '/Device/Geehy/APM32F4xx/Include',
cwd + '/APM32F4xx_ETH_Driver/inc']
CPPDEFINES = ['USE_STDPERIPH_DRIVER']
if GetDepend(['BSP_USING_SDRAM']):
CPPDEFINES += ['DATA_IN_ExtSRAM']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/apm32/libraries/Drivers/SConscript
+15
View File
@@ -45,11 +45,26 @@ if GetDepend(['BSP_USING_WDT']):
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['BSP_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F0']):
src += ['drv_flash/drv_flash_f0.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F1']):
src += ['drv_flash/drv_flash_f1.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_APM32F4']):
src += ['drv_flash/drv_flash_f4.c']
src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [cwd + '/drv_flash']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
bsp/apm32/libraries/Drivers/drv_adc.c
+7 -14
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -53,7 +53,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC2
@@ -73,7 +72,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC3
@@ -92,7 +90,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(F, 6),
GET_PIN(F, 7), GET_PIN(F, 8), GET_PIN(F, 9), GET_PIN(F, 10)
},
RT_NULL
},
#endif
};
@@ -117,7 +114,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC2
@@ -138,7 +134,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
#ifdef BSP_USING_ADC3
@@ -159,7 +154,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(F, 7), GET_PIN(F, 8), GET_PIN(F, 9), GET_PIN(F, 10), GET_PIN(F, 3),
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3)
},
RT_NULL
},
#endif
};
@@ -184,7 +178,6 @@ static struct apm32_adc adc_config[] =
GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4),
GET_PIN(C, 5)
},
RT_NULL
},
#endif
};
@@ -338,7 +331,7 @@ static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t ch
{
return -RT_ERROR;
}
#if defined(SOC_SERIES_APM32F1)
ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_13CYCLES5);
@@ -353,7 +346,7 @@ static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t ch
}
ADC_EnableSoftwareStartConv(adc_cfg->adc);
while (!ADC_ReadStatusFlag(adc_cfg->adc, ADC_FLAG_EOC))
{
if (++counter > DRV_ADC_TIME_OUT)
@@ -365,7 +358,7 @@ static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t ch
#elif defined(SOC_SERIES_APM32F4)
ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_15CYCLES);
ADC_SoftwareStartConv(adc_cfg->adc);
while (!ADC_ReadStatusFlag(adc_cfg->adc, ADC_FLAG_EOC))
{
if (++counter > DRV_ADC_TIME_OUT)
@@ -376,9 +369,9 @@ static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t ch
*value = ADC_ReadConversionValue(adc_cfg->adc);
#elif defined(SOC_SERIES_APM32F0)
ADC_ConfigChannel((uint16_t)(1u << ((channel) & 0xFu)), ADC_SAMPLE_TIME_239_5);
ADC_StartConversion();
while (!ADC_ReadStatusFlag(ADC_FLAG_CC))
{
if (++counter > DRV_ADC_TIME_OUT)
@@ -388,7 +381,7 @@ static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t ch
}
*value = ADC_ReadConversionValue();
#endif
return RT_EOK;
}
bsp/apm32/libraries/Drivers/drv_common.c
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_common.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_dac.c
+2 -4
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -15,7 +15,7 @@
#if defined(BSP_USING_DAC1)
#define DBG_TAG "drv.dac"
#define DBG_LVL DBG_LOG//DBG_INFO
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
struct apm32_dac
@@ -40,7 +40,6 @@ static struct apm32_dac dac_config[] =
DAC_WAVE_GENERATION_NONE,
DAC_TRIANGLEAMPLITUDE_4095,
},
RT_NULL,
#elif defined (SOC_SERIES_APM32F1) || defined (SOC_SERIES_APM32F4)
"dac1",
DAC,
@@ -50,7 +49,6 @@ static struct apm32_dac dac_config[] =
DAC_WAVE_GENERATION_NONE,
DAC_TRIANGLE_AMPLITUDE_4095,
},
RT_NULL,
#endif
}
#endif
bsp/apm32/libraries/Drivers/drv_eth.c
+6 -4
View File
@@ -471,7 +471,7 @@ rt_err_t rt_apm32_eth_tx( rt_device_t dev, struct pbuf* p)
/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
to = (uint8_t*)((DMATxDescToSet->Buffer1Addr) + offset);
memcpy(to, q->payload, q->len);
SMEMCPY(to, q->payload, q->len);
offset += q->len;
}
#ifdef ETH_TX_DUMP
@@ -552,7 +552,7 @@ struct pbuf *rt_apm32_eth_rx(rt_device_t dev)
for (q = p; q != RT_NULL; q= q->next)
{
/* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
memcpy(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len);
SMEMCPY(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len);
offset += q->len;
}
#ifdef ETH_RX_DUMP
@@ -724,11 +724,13 @@ static void phy_monitor_thread_entry(void *parameter)
static int rt_hw_apm32_eth_init(void)
{
/* reset phy */
extern void phy_reset(void);
phy_reset();
void ETH_GPIO_Configuration(void);
ETH_GPIO_Configuration();
/* apm32 eth gpio init */
extern void apm32_msp_eth_init(void *instance);
apm32_msp_eth_init(RT_NULL);
apm32_eth_device.ETH_Speed = ETH_SPEED_100M;
apm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
bsp/apm32/libraries/Drivers/drv_eth.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_flash/drv_flash.h
+31
View File
@@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-16 luobeihai first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int apm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int apm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int apm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f0.c
+212
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f1.c
+212
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/libraries/Drivers/drv_flash/drv_flash_f4.c
+384
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/libraries/Drivers/drv_gpio.c
+13 -12
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -8,6 +8,7 @@
* 2020-08-20 Abbcc first version
* 2022-07-15 Aligagago add apm32F4 serie MCU support
* 2022-12-26 luobeihai add apm32F0 serie MCU support
* 2022-03-18 luobeihai fix warning about incompatible function pointer types
*/
#include <board.h>
@@ -71,7 +72,7 @@ static const struct pin_irq_map pin_irq_map[] =
{GPIO_PIN_12, EINT4_15_IRQn},
{GPIO_PIN_13, EINT4_15_IRQn},
{GPIO_PIN_14, EINT4_15_IRQn},
{GPIO_PIN_15, EINT4_15_IRQn},
{GPIO_PIN_15, EINT4_15_IRQn},
#else
{GPIO_PIN_0, EINT0_IRQn},
{GPIO_PIN_1, EINT1_IRQn},
@@ -152,7 +153,7 @@ static rt_base_t apm32_pin_get(const char *name)
return pin;
}
static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
{
GPIO_T *gpio_port;
uint16_t gpio_pin;
@@ -169,7 +170,7 @@ static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
}
}
static int apm32_pin_read(rt_device_t dev, rt_base_t pin)
static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_T *gpio_port;
uint16_t gpio_pin;
@@ -185,7 +186,7 @@ static int apm32_pin_read(rt_device_t dev, rt_base_t pin)
return value;
}
static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
GPIO_Config_T gpioConfig;
@@ -325,8 +326,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
return &pin_irq_map[mapindex];
};
static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
rt_uint8_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
@@ -365,7 +366,7 @@ static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
return RT_EOK;
}
static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
@@ -397,7 +398,7 @@ static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
}
static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
rt_uint8_t enabled)
{
const struct pin_irq_map *irqmap;
rt_base_t level;
@@ -481,7 +482,7 @@ static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
#endif
}
GPIO_Config(PIN_APMPORT(pin), &gpioConfig);
#if defined(SOC_SERIES_APM32F0)
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
SYSCFG_EINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex);
@@ -496,7 +497,7 @@ static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
eintConfig.mode = EINT_MODE_INTERRUPT;
eintConfig.lineCmd = ENABLE;
EINT_Config(&eintConfig);
#if defined(SOC_SERIES_APM32F0)
NVIC_EnableIRQRequest(irqmap->irqno, 5);
#else
@@ -517,7 +518,7 @@ static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
level = rt_hw_interrupt_disable();
pin_irq_enable_mask &= ~irqmap->pinbit;
#if defined(SOC_SERIES_APM32F0)
if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1))
{
bsp/apm32/libraries/Drivers/drv_gpio.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_hwtimer.c
+7 -7
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -139,7 +139,7 @@ static struct apm32_timer tmr_config[] =
TMR6,
#if defined(SOC_SERIES_APM32F1) || defined(APM32F030) || defined(APM32F070)
TMR6_IRQn,
#elif defined(SOC_SERIES_APM32F4)
#elif defined(SOC_SERIES_APM32F4)
TMR6_DAC_IRQn
#elif defined(SOC_SERIES_APM32F0) && !defined(APM32F030) && !defined(APM32F070)
TMR6_DAC_IRQn
@@ -237,9 +237,9 @@ static rt_uint32_t apm32_hwtimer_clock_get(TMR_T *tmr)
{
#if defined(SOC_SERIES_APM32F0)
uint32_t pclk1;
pclk1 = RCM_ReadPCLKFreq();
return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1));
#else
uint32_t pclk1, pclk2;
@@ -327,9 +327,9 @@ static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t stat
if (state)
{
timer_config = (struct apm32_timer *)timer->parent.user_data;
apm32_hwtimer_enable_clock();
prescaler = (uint32_t)(apm32_hwtimer_clock_get(timer_config->tmr) / 10000) - 1;
base_config.period = 10000 - 1;
@@ -358,7 +358,7 @@ static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t stat
#endif
base_config.repetitionCounter = 0;
TMR_ConfigTimeBase(timer_config->tmr, &base_config);
#if defined(SOC_SERIES_APM32F0)
/* set the TIMx priority */
NVIC_EnableIRQRequest(timer_config->irqn, 3);
bsp/apm32/libraries/Drivers/drv_log.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_pwm.c
+11 -11
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -308,17 +308,17 @@ static rt_err_t apm32_pwm_hw_init(struct apm32_pwm *device)
{
rt_err_t result = RT_EOK;
TMR_T *tmr = RT_NULL;
RT_ASSERT(device != RT_NULL);
tmr = (TMR_T *)device->tmr;
/* Init timer gpio and enable clock */
apm32_msp_timer_init(tmr);
#if defined(SOC_SERIES_APM32F0)
TMR_TimeBase_T base_config;
TMR_OCConfig_T oc_config;
/* configure the tmrer to pwm mode */
base_config.div = 0;
base_config.counterMode = TMR_COUNTER_MODE_UP;
@@ -412,9 +412,9 @@ static rt_uint32_t timer_clock_get(TMR_T *tmr)
{
#if defined(SOC_SERIES_APM32F0)
uint32_t pclk1;
pclk1 = RCM_ReadPCLKFreq();
return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1));
#else
uint32_t pclk1, pclk2;
@@ -488,7 +488,7 @@ static rt_err_t drv_pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configurati
rt_uint32_t timer_reload, timer_psc;
timer_clock = timer_clock_get(tmr);
#if defined(SOC_SERIES_APM32F0)
if (tmr->CTRL1_B.CLKDIV == TMR_CKD_DIV2)
#else
@@ -505,7 +505,7 @@ static rt_err_t drv_pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configurati
{
timer_clock = timer_clock / 4;
}
uint32_t temp;
temp = (uint32_t)tmr;
temp += (uint32_t)(0x34 + channel);
@@ -516,7 +516,7 @@ static rt_err_t drv_pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configurati
timer_psc = tmr->PSC;
configuration->period = (timer_reload + 1) * (timer_psc + 1) * 1000UL / timer_clock;
configuration->pulse = ((*(__IO uint32_t *)temp) + 1) * (timer_psc + 1) * 1000UL / timer_clock;
return RT_EOK;
}
@@ -526,7 +526,7 @@ static rt_err_t drv_pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configurati
rt_uint64_t timer_clock, psc;
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
uint32_t temp = (uint32_t)tmr;
timer_clock = timer_clock_get(tmr);
/* Convert nanosecond to frequency and duty cycle. */
bsp/apm32/libraries/Drivers/drv_rtc.c
+21 -19
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -8,6 +8,7 @@
* 2022-03-04 stevetong459 first version
* 2022-07-15 Aligagago add apm32F4 serie MCU support
* 2022-12-26 luobeihai add apm32F0 serie MCU support
* 2023-03-18 luobeihai fix RT-Thread Studio compile error bug
*/
#include "board.h"
@@ -39,14 +40,14 @@ static rt_uint8_t rtc_init_flag = RESET;
static rt_err_t apm32_rtc_init(void)
{
volatile rt_uint32_t counter = 0;
/* Enable RTC Clock */
#if defined(SOC_SERIES_APM32F1)
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU | RCM_APB1_PERIPH_BAKR);
#elif defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4)
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU);
#endif
PMU_EnableBackupAccess();
/* Config RTC clock */
@@ -101,12 +102,12 @@ static rt_err_t apm32_rtc_init(void)
RTC_Config_T rtcConfig;
RTC_ConfigStructInit(&rtcConfig);
RTC_Config(&rtcConfig);
#elif defined(SOC_SERIES_APM32F0)
RTC_EnableInit();
RTC_Config_T rtcConfig;
RTC_ConfigStructInit(&rtcConfig);
#ifdef BSP_RTC_USING_LSI
rtcConfig.AsynchPrediv = 0x63;
rtcConfig.SynchPrediv = 0x18F;
@@ -131,7 +132,7 @@ static rt_err_t apm32_rtc_init(void)
*
* @return RT_EOK indicates successful initialize, other value indicates failed;
*/
static rt_err_t apm32_rtc_get_secs(time_t *sec)
static rt_err_t apm32_rtc_get_secs(void *args)
{
volatile rt_uint32_t counter = 0;
@@ -143,12 +144,12 @@ static rt_err_t apm32_rtc_get_secs(time_t *sec)
}
}
*(timer_t *) sec = RTC_ReadCounter();
*(rt_uint32_t *) args = RTC_ReadCounter();
return RT_EOK;
}
static rt_err_t apm32_rtc_set_secs(time_t *sec)
static rt_err_t apm32_rtc_set_secs(void *args)
{
volatile rt_uint32_t counter = 0;
@@ -165,13 +166,15 @@ static rt_err_t apm32_rtc_set_secs(time_t *sec)
}
}
RTC_ConfigCounter(*(rt_uint32_t *)sec);
RTC_ConfigCounter(*(rt_uint32_t *)args);
return RT_EOK;
}
#elif defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4)
static rt_err_t apm32_rtc_get_timeval(struct timeval *tv)
static rt_err_t apm32_rtc_get_timeval(void *args)
{
struct timeval *tv = (struct timeval *) args;
#if defined(SOC_SERIES_APM32F0)
RTC_TIME_T timeConfig;
RTC_DATE_T dateConfig;
@@ -179,7 +182,7 @@ static rt_err_t apm32_rtc_get_timeval(struct timeval *tv)
RTC_TimeConfig_T timeConfig;
RTC_DateConfig_T dateConfig;
#endif
struct tm tm_new = {0};
RTC_ReadTime(RTC_FORMAT_BIN, &timeConfig);
@@ -191,9 +194,9 @@ static rt_err_t apm32_rtc_get_timeval(struct timeval *tv)
tm_new.tm_mday = dateConfig.date;
tm_new.tm_mon = dateConfig.month - 1;
tm_new.tm_year = dateConfig.year + 100;
tv->tv_sec = timegm(&tm_new);
return RT_EOK;
}
@@ -232,11 +235,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
dateConfig.weekday = tm.tm_wday + 1;
#endif
dateConfig.year = tm.tm_year - 100;
RTC_ConfigTime(RTC_FORMAT_BIN, &timeConfig);
RTC_ConfigDate(RTC_FORMAT_BIN, &dateConfig);
/* wait for set time completed */
for (int i = 0; i < 0xFFFF; i++);
@@ -248,20 +250,20 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
*
* @return RT_EOK indicates successful initialize, other value indicates failed;
*/
static rt_err_t apm32_rtc_get_secs(time_t *sec)
static rt_err_t apm32_rtc_get_secs(void *args)
{
struct timeval tv;
apm32_rtc_get_timeval(&tv);
*(time_t *) sec = tv.tv_sec;
*(rt_uint32_t *) args = tv.tv_sec;
return RT_EOK;
}
static rt_err_t apm32_rtc_set_secs(time_t *sec)
static rt_err_t apm32_rtc_set_secs(void *args)
{
rt_err_t result = RT_EOK;
if (set_rtc_time_stamp(*sec))
if (set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
bsp/apm32/libraries/Drivers/drv_sdio.c
+882
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/libraries/Drivers/drv_sdio.h
+228
View File
File diff suppressed because it is too large. Load diff
bsp/apm32/libraries/Drivers/drv_soft_i2c.c
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_spi.c
+18 -18
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -46,7 +46,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
struct rt_spi_device *spi_device;
struct apm32_spi_cs *cs_pin;
GPIO_Config_T GPIO_InitStructure;
/* initialize the cs pin && select the slave */
#if defined(SOC_SERIES_APM32F0)
GPIO_ConfigStructInit(&GPIO_InitStructure);
@@ -100,18 +100,18 @@ static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
SPI_Config_T hw_spi_config;
struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus;
struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data;
SPI_T *spi = spi_device->config->spi_x;
uint32_t hw_spi_apb_clock;
#if (DBG_LVL == DBG_LOG)
uint32_t hw_spi_sys_clock = RCM_ReadSYSCLKFreq();
#endif
/* apm32 spi gpio init and enable clock */
extern void apm32_msp_spi_init(void *Instance);
apm32_msp_spi_init(spi);
@@ -128,7 +128,7 @@ static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_
hw_spi_config.nss = (cfg->mode & RT_SPI_NO_CS) ? SPI_NSS_HARD : SPI_NSS_SOFT;
hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRSTBIT_MSB : SPI_FIRSTBIT_LSB;
#endif
if (cfg->data_width == 8)
{
hw_spi_config.length = SPI_DATA_LENGTH_8B;
@@ -191,28 +191,28 @@ static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
hw_spi_sys_clock, hw_spi_apb_clock, cfg->max_hz, hw_spi_config.baudrateDiv);
#if defined(SOC_SERIES_APM32F0)
SPI_DisableCRC(spi);
SPI_EnableSSoutput(spi);
SPI_ConfigFIFOThreshold(spi, SPI_RXFIFO_QUARTER);
#endif
SPI_Config(spi, &hw_spi_config);
SPI_Enable(spi);
return RT_EOK;
}
static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
static rt_ssize_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
struct rt_spi_configuration *config = &device->config;
struct apm32_spi_cs *cs = device->parent.user_data;
struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus;
struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data;
SPI_T *spi = spi_device->config->spi_x;
@@ -249,7 +249,7 @@ static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
/* Wait until the transmit buffer is empty */
while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
SPI_TxData8(spi, data);
/* Wait until a data is received */
while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
data = SPI_RxData8(spi);
@@ -262,7 +262,7 @@ static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
data = SPI_I2S_RxData(spi);
#endif
if (recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
@@ -284,12 +284,12 @@ static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
{
data = *send_ptr++;
}
#if defined(SOC_SERIES_APM32F0)
/* Wait until the transmit buffer is empty */
while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET);
SPI_I2S_TxData16(spi, data);
/* Wait until a data is received */
while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET);
data = SPI_I2S_RxData16(spi);
@@ -304,7 +304,7 @@ static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
/* Get the received data */
data = SPI_I2S_RxData(spi);
#endif
if (recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
@@ -335,7 +335,7 @@ static const struct rt_spi_ops apm32_spi_ops =
static int rt_hw_spi_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
bsp/apm32/libraries/Drivers/drv_spi.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_usart.c
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -111,7 +111,7 @@ static rt_err_t apm32_uart_configure(struct rt_serial_device *serial, struct ser
USART_ConfigStruct.baudRate = cfg->baud_rate;
USART_ConfigStruct.mode = USART_MODE_TX_RX;
USART_ConfigStruct.parity = USART_PARITY_NONE;
#if defined(SOC_SERIES_APM32F0)
switch (cfg->flowcontrol)
{
bsp/apm32/libraries/Drivers/drv_usart.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/apm32/libraries/Drivers/drv_wdt.c
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -67,15 +67,15 @@ static rt_err_t apm32_iwdt_init(rt_watchdog_t *wdt)
return -RT_ERROR;
}
}
IWDT_EnableWriteAccess();
#if defined(SOC_SERIES_APM32F0)
IWDT_ConfigDivider(IWDT_DIV_256);
#else
IWDT_ConfigDivider(IWDT_DIVIDER_256);
#endif
IWDT_DisableWriteAccess();
return RT_EOK;