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Merge pull request #5727 from rtthread-bot/rtt_bot

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guo
2022-03-29 07:09:08 +08:00
committed by GitHub
parent 84e18bb2d5 6330720b5c
commit 66d5101bfd
90 changed files with 28793 additions and 2 deletions
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6
bsp/v85xxp/.ignore_format.yml Normal file
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# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- Libraries/VangoV85xxP_standard_peripheral

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bsp/v85xxp/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_V85XXP
bool
default y
config SOC_V85XXP
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_V85XXP
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
config BSP_USING_UART5
bool "using uart5"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu

46
bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_CodeRAM.h Normal file
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/**
******************************************************************************
* @file lib_CodeRAM.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CODERAM_H
#define __LIB_CODERAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#ifndef __GNUC__
#ifdef __ICCARM__ /* EWARM */
#define __RAM_FUNC __ramfunc
#endif
#ifdef __CC_ARM /* MDK-ARM */
#define __RAM_FUNC __attribute__((used))
#endif
/* Exported Functions ------------------------------------------------------- */
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CODERAM_H */
/*********************************** END OF FILE ******************************/

235
bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_LoadNVR.h Normal file
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/**
******************************************************************************
* @file lib_LoadNVR.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LOADNVR_H
#define __LIB_LOADNVR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
/* Power Measure Result */
typedef struct
{
uint32_t AVCCMEAResult; // LDO33 Measure Result
uint32_t DVCCMEAResult; // LDO15 Measure Result
uint32_t BGPMEAResult; // BGP Measure Result
uint32_t RCLMEAResult; // RCL Measure Result
uint32_t RCHMEAResult; // RCH Measure Result
} NVR_MISCGain;
/* Chip ID */
typedef struct
{
uint32_t ChipID0; // ID word 0
uint32_t ChipID1; // ID word 1
} NVR_CHIPID;
/* Temperature information */
typedef struct
{
float TempOffset;
} NVR_TEMPINFO;
/* LCD information */
typedef struct
{
uint32_t MEALCDLDO; // Measure LCD LDO pre trim value
uint32_t MEALCDVol; // VLCD setting
} NVR_LCDINFO;
/* RTC(temp) information */
typedef struct
{
int16_t RTCTempP0; //P0
int16_t RTCTempP1; //P1
int32_t RTCTempP2; //P2
int16_t RTCTempP4; //P4
int16_t RTCTempP5; //P5
int16_t RTCTempP6; //P6
int16_t RTCTempP7; //P7
int16_t RTCTempK0; //K0
int16_t RTCTempK1; //K1
int16_t RTCTempK2; //K2
int16_t RTCTempK3; //K3
int16_t RTCTempK4; //K4
int16_t RTCACTI; //Center temperature
uint32_t RTCACKTemp; //section X temperature
int32_t RTCTempDelta; //Temperature delta
uint32_t RTCACF200; //RTC_ACF200
} NVR_RTCINFO;
/* RTC(temp) information */
typedef struct
{
int16_t RTCTempP0; //P0
int16_t RTCTempP1; //P1
int32_t RTCTempP2; //P2
} NVR_TempParams;
/* ADC Voltage Parameters */
typedef struct
{
float aParameter;
float bParameter;
float OffsetParameter;
} NVR_ADCVOLPARA;
//Mode
#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define NVR_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define NVR_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define NVR_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define NVR_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_3V_BAT1_RESDIV) ||\
((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_5V_BAT1_RESDIV) ||\
((__MODE__) == NVR_5V_BATRTC_RESDIV))
//VOLMode
#define NVR_MEARES_3V 0
#define NVR_MEARES_5V 1
#define IS_MEARES(__VOLMODE__) (((__VOLMODE__) == NVR_MEARES_3V) ||\
((__VOLMODE__) == NVR_MEARES_5V))
/********** NVR Address **********/
//ADC Voltage Parameters
#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x80C48)
#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x80C6C)
#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x80C00)
#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x80C24)
//RTC DATA
//P4
#define NVR_RTC1_P4 (__IO uint32_t *)(0x80800)
#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x80804)
#define NVR_RTC2_P4 (__IO uint32_t *)(0x80808)
#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x8080C)
//ACK1~ACK5
#define NVR_RTC1_ACK0 (__IO uint32_t *)(0x80810)
#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x80814)
#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x80818)
#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x8081C)
#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x80820)
#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x80824)
#define NVR_RTC2_ACK0 (__IO uint32_t *)(0x80828)
#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x8082C)
#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x80830)
#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x80834)
#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x80838)
#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x8083C)
//ACTI
#define NVR_RTC1_ACTI (__IO uint32_t *)(0x80840)
#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x80844)
#define NVR_RTC2_ACTI (__IO uint32_t *)(0x80848)
#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x8084C)
//ACKTEMP
#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x80850)
#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x80854)
#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x80858)
#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x8085C)
//Analog trim data
#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x80DC0)
#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x80DC4)
#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x80DC8)
#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x80DCC)
#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x80DD0)
#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x80DD4)
#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x80DD8)
#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x80DDC)
#define NVR_ANA1_REG10 (__IO uint32_t *)(0x80DE0)
#define NVR_ANA1_REG10_CHKSUM (__IO uint32_t *)(0x80DE4)
#define NVR_ANA2_REG10 (__IO uint32_t *)(0x80DE8)
#define NVR_ANA2_REG10_CHKSUM (__IO uint32_t *)(0x80DEC)
//ADC_CHx
#define NVR_5VADCCHx_NODIV1 (__IO uint32_t *)(0x80C90)
#define NVR_5VADCCHx_RESDIV1 (__IO uint32_t *)(0x80C94)
#define NVR_5VADCCHx_NODIV2 (__IO uint32_t *)(0x80CA4)
#define NVR_5VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CA8)
#define NVR_3VADCCHx_NODIV1 (__IO uint32_t *)(0x80CB8)
#define NVR_3VADCCHx_RESDIV1 (__IO uint32_t *)(0x80CBC)
#define NVR_3VADCCHx_NODIV2 (__IO uint32_t *)(0x80CCC)
#define NVR_3VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CD0)
//BAT Measure Result
#define NVR_5VBAT1 (__IO uint32_t *)(0x80C98)
#define NVR_5VBATRTC1 (__IO uint32_t *)(0x80C9C)
#define NVR_5VBATCHKSUM1 (__IO uint32_t *)(0x80CA0)
#define NVR_5VBAT2 (__IO uint32_t *)(0x80CAC)
#define NVR_5VBATRTC2 (__IO uint32_t *)(0x80CB0)
#define NVR_5VBATCHKSUM2 (__IO uint32_t *)(0x80CB4)
#define NVR_3VBAT1 (__IO uint32_t *)(0x80CC0)
#define NVR_3VBATRTC1 (__IO uint32_t *)(0x80CC4)
#define NVR_3VBATCHKSUM1 (__IO uint32_t *)(0x80CC8)
#define NVR_3VBAT2 (__IO uint32_t *)(0x80CD4)
#define NVR_3VBATRTC2 (__IO uint32_t *)(0x80CD8)
#define NVR_3VBATCHKSUM2 (__IO uint32_t *)(0x80CDC)
//RTC AutoCal Px pramameters
#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x80D10)
#define NVR_RTC1_P2 (__IO uint32_t *)(0x80D14)
#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x80D18)
#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x80D1C)
#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x80D20)
#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x80D24)
#define NVR_RTC2_P2 (__IO uint32_t *)(0x80D28)
#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x80D2C)
#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x80D30)
#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x80D34)
//Power Measure Result
#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x80D38)
#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x80D3C)
#define NVR_BGP_MEA1 (__IO uint32_t *)(0x80D40)
#define NVR_RCL_MEA1 (__IO uint32_t *)(0x80D44)
#define NVR_RCH_MEA1 (__IO uint32_t *)(0x80D48)
#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x80D4C)
#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x80D50)
#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x80D54)
#define NVR_BGP_MEA2 (__IO uint32_t *)(0x80D58)
#define NVR_RCL_MEA2 (__IO uint32_t *)(0x80D5C)
#define NVR_RCH_MEA2 (__IO uint32_t *)(0x80D60)
#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x80D64)
//Chip ID
#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x80D68)
#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x80D6C)
#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x80D70)
#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x80D74)
#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x80D78)
#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x80D7C)
//Temperature information
#define NVR_REALTEMP1 (__IO uint32_t *)(0x80D80)
#define NVR_MEATEMP1 (__IO uint32_t *)(0x80D84)
#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x80D88)
#define NVR_REALTEMP2 (__IO uint32_t *)(0x80D9C)
#define NVR_MEATEMP2 (__IO uint32_t *)(0x80D90)
#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x80D94)
uint32_t NVR_LoadANADataManual(void);
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource);
uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams);
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LOADNVR_H */
/*********************************** END OF FILE ******************************/

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bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_conf.h Normal file
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/**
******************************************************************************
* @file lib_conf.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Dirver configuration.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CONF_H
#define __LIB_CONF_H
/* ########################## Assert Selection ############################## */
//#define ASSERT_NDEBUG 1
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#include "lib_ana.h"
#include "lib_adc.h"
#include "lib_adc_tiny.h"
#include "lib_clk.h"
#include "lib_cmp.h"
#include "lib_crypt.h"
#include "lib_dma.h"
#include "lib_flash.h"
#include "lib_gpio.h"
#include "lib_i2c.h"
#include "lib_iso7816.h"
#include "lib_lcd.h"
#include "lib_misc.h"
#include "lib_pmu.h"
#include "lib_pwm.h"
#include "lib_rtc.h"
#include "lib_spi.h"
#include "lib_tmr.h"
#include "lib_u32k.h"
#include "lib_uart.h"
#include "lib_version.h"
#include "lib_wdt.h"
#include "lib_LoadNVR.h"
#include "lib_CodeRAM.h"
#include "lib_cortex.h"
/* Exported macro ------------------------------------------------------------*/
#ifndef ASSERT_NDEBUG
#define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_errhandler(uint8_t* file, uint32_t line);
#else
#define assert_parameters(expr) ((void)0U)
#endif /* ASSERT_NDEBUG */
#endif
/*********************************** END OF FILE ******************************/

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bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_cortex.h Normal file
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/**
******************************************************************************
* @file lib_Cortex.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CORTEX_H
#define __LIB_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
/* Exported Functions ------------------------------------------------------- */
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_SystemReset(void);
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
void CORTEX_Delay_nSysClock(__IO uint32_t nClock);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CORTEX_H */
/*********************************** END OF FILE ******************************/

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bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/system_target.h Normal file
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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __SYSTEM_TARGET_H
#define __SYSTEM_TARGET_H
#ifdef __cplusplus
extern "C" {
#endif
#include "type_def.h"
extern void SystemInit(void);
extern void SystemUpdate(void);
#ifdef USE_TARGET_DRIVER
#include "lib_conf.h"
#endif /* USE_TARGET_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_TARGET_H */
/*********************************** END OF FILE ******************************/

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bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/type_def.h Normal file
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/**
******************************************************************************
* @file type_def.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Typedef file
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __TYPE_DEF_H
#define __TYPE_DEF_H
#define ENABLE 1
#define DISABLE 0
#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
#define BIT_BAND(addr, bitnum) *((volatile unsigned long *)((((uint32_t)addr) & 0xF0000000) + \
0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2)))
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#endif /* __TYPE_DEF_H */
/*********************************** END OF FILE ******************************/

478
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;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.equ __CHIPINITIAL, 1
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/*************************************************************************
* Chip init.
* 1. Load flash configuration
* 2. Load ANA_REG(B/C/D/E) information
* 3. Load ANA_REG10 information
**************************************************************************/
.if (__CHIPINITIAL != 0)
.section .chipinit_section.__CHIP_INIT
__CHIP_INIT:
CONFIG1_START:
/*-------------------------------*/
/* 1. Load flash configuration */
/* Unlock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
/* Load configure word 0 to 7
Compare bit[7:0] */
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1:
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1:
/* Load configure word 8 to 11
Compare bit 31,24,23:16,8,7:0 */
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2:
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2:
/* Lock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
/*-------------------------------*/
/* 2. Load ANA_REG(B/C/D/E) information */
CONFIG2_START:
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR:
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR:
B ANADAT_CHECKSUM2_ERR
/*-------------------------------*/
/* 3. Load ANA_REG10 information */
CONFIG3_START:
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR:
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR:
B ANADAT10_CHECKSUM2_ERR
.size __CHIP_INIT, .-__CHIP_INIT
.endif
.if (__CHIPINITIAL != 0)
.global __CHIP_INIT
.section .chipinit_section.Reset_Handler
.else
.section .text.Reset_Handler
.endif
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.if (__CHIPINITIAL != 0)
/* Chip Initiliazation */
bl __CHIP_INIT
/* System Initiliazation */
bl SystemInit
.endif
/* set stack pointer */
ldr r0, =_estack
mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word PMU_IRQHandler /* 0: PMU */
.word RTC_IRQHandler /* 1: RTC */
.word U32K0_IRQHandler /* 2: U32K0 */
.word U32K1_IRQHandler /* 3: U32K1 */
.word I2C_IRQHandler /* 4: I2C */
.word SPI1_IRQHandler /* 5: SPI1 */
.word UART0_IRQHandler /* 6: UART0 */
.word UART1_IRQHandler /* 7: UART1 */
.word UART2_IRQHandler /* 8: UART2 */
.word UART3_IRQHandler /* 9: UART3 */
.word UART4_IRQHandler /* 10: UART4 */
.word UART5_IRQHandler /* 11: UART5 */
.word ISO78160_IRQHandler /* 12: ISO78160 */
.word ISO78161_IRQHandler /* 13: ISO78161 */
.word TMR0_IRQHandler /* 14: TMR0 */
.word TMR1_IRQHandler /* 15: TMR1 */
.word TMR2_IRQHandler /* 16: TMR2 */
.word TMR3_IRQHandler /* 17: TMR3 */
.word PWM0_IRQHandler /* 18: PWM0 */
.word PWM1_IRQHandler /* 19: PWM1 */
.word PWM2_IRQHandler /* 20: PWM2 */
.word PWM3_IRQHandler /* 21: PWM3 */
.word DMA_IRQHandler /* 22: DMA */
.word FLASH_IRQHandler /* 23: FLASH */
.word ANA_IRQHandler /* 24: ANA */
.word 0 /* 25: Reserved */
.word 0 /* 26: Reserved */
.word SPI2_IRQHandler /* 27: SPI2 */
.word SPI3_IRQHandler /* 28: SPI3 */
.word 0 /* 29: Reserved */
.word 0 /* 30: Reserved */
.word 0 /* 31: Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak PMU_IRQHandler
.thumb_set PMU_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak U32K0_IRQHandler
.thumb_set U32K0_IRQHandler,Default_Handler
.weak U32K1_IRQHandler
.thumb_set U32K1_IRQHandler,Default_Handler
.weak I2C_IRQHandler
.thumb_set I2C_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak ISO78160_IRQHandler
.thumb_set ISO78160_IRQHandler,Default_Handler
.weak ISO78161_IRQHandler
.thumb_set ISO78161_IRQHandler,Default_Handler
.weak TMR0_IRQHandler
.thumb_set TMR0_IRQHandler,Default_Handler
.weak TMR1_IRQHandler
.thumb_set TMR1_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Default_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Default_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Default_Handler
.weak PWM3_IRQHandler
.thumb_set PWM3_IRQHandler,Default_Handler
.weak DMA_IRQHandler
.thumb_set DMA_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak ANA_IRQHandler
.thumb_set ANA_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler

450
bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S Normal file
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;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
__CHIPINITIAL EQU 1
Stack_Size EQU 0x000001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PMU_IRQHandler ; 0: PMU
DCD RTC_IRQHandler ; 1: RTC
DCD U32K0_IRQHandler ; 2: U32K0
DCD U32K1_IRQHandler ; 3: U32K1
DCD I2C_IRQHandler ; 4: I2C
DCD SPI1_IRQHandler ; 5: SPI1
DCD UART0_IRQHandler ; 6: UART0
DCD UART1_IRQHandler ; 7: UART1
DCD UART2_IRQHandler ; 8: UART2
DCD UART3_IRQHandler ; 9: UART3
DCD UART4_IRQHandler ; 10: UART4
DCD UART5_IRQHandler ; 11: UART5
DCD ISO78160_IRQHandler ; 12: ISO78160
DCD ISO78161_IRQHandler ; 13: ISO78161
DCD TMR0_IRQHandler ; 14: TMR0
DCD TMR1_IRQHandler ; 15: TMR1
DCD TMR2_IRQHandler ; 16: TMR2
DCD TMR3_IRQHandler ; 17: TMR3
DCD PWM0_IRQHandler ; 18: PWM0
DCD PWM1_IRQHandler ; 19: PWM1
DCD PWM2_IRQHandler ; 20: PWM2
DCD PWM3_IRQHandler ; 21: PWM3
DCD DMA_IRQHandler ; 22: DMA
DCD FLASH_IRQHandler ; 23: FLASH
DCD ANA_IRQHandler ; 24: ANA
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD SPI2_IRQHandler ; 27: SPI2
DCD SPI3_IRQHandler ; 28: SPI3
DCD 0 ; 29: Reserved
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
ELSE
AREA |.text|, CODE, READONLY
ENDIF
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IF (__CHIPINITIAL != 0)
LDR R0, =__CHIP_INIT
BLX R0
ENDIF
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
AREA |.text|, CODE, READONLY
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PMU_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT U32K0_IRQHandler [WEAK]
EXPORT U32K1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT ISO78160_IRQHandler [WEAK]
EXPORT ISO78161_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT ANA_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
PMU_IRQHandler
RTC_IRQHandler
U32K0_IRQHandler
U32K1_IRQHandler
I2C_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
ISO78160_IRQHandler
ISO78161_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PWM0_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
PWM3_IRQHandler
DMA_IRQHandler
FLASH_IRQHandler
ANA_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Chip init.
;; 1. Load flash configuration
;; 2. Load ANA_REG(B/C/D/E) information
;; 3. Load ANA_REG10 information
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
__CHIP_INIT PROC
CONFIG1_START
;-------------------------------;
;; 1. Load flash configuration
; Unlock flash
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
; Load configure word 0 to 7
; Compare bit[7:0]
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1
; Load configure word 8 to 11
; Compare bit 31,24,23:16,8,7:0
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2
; Lock flash
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
;-------------------------------;
;; 2. Load ANA_REG(B/C/D/E) information
CONFIG2_START
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR
B ANADAT_CHECKSUM2_ERR
;-------------------------------;
;; 2. Load ANA_REG10 information
CONFIG3_START
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR
B ANADAT10_CHECKSUM2_ERR
NOP
ENDP
ENDIF
END
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_CodeRAM.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_CodeRAM.h"
#ifndef __GNUC__
/**
* @brief Enter idle mode with flash deep standby.
* @note This function is executed in RAM.
* @param None
* @retval None
*/
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
{
/* Flash deep standby */
FLASH->PASS = 0x55AAAA55;
FLASH->DSTB = 0xAA5555AA;
/* Enter Idle mode */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
__WFI();
}
#endif
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_cortex.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_cortex.h"
#include "core_cm0.h"
/**
* @brief 1. Clears Pending of a device specific External Interrupt.
* 2. Sets Priority of a device specific External Interrupt.
* 3. Enables a device specific External Interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Clear Pending Interrupt */
NVIC_ClearPendingIRQ(IRQn);
/* Set Interrupt Priority */
NVIC_SetPriority(IRQn, Priority);
/* Enable Interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly before calling it.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt in NVIC */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void CORTEX_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Gets the Pending bit of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval 0 Interrupt status is not pending.
1 Interrupt status is pending.
*/
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Clear interrupt pending */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval Interrupt Priority. Value is aligned automatically to the implemented
* priority bits of the microcontroller.
*/
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
{
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPriority(IRQn);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Get priority for Cortex-M0 system or device specific interrupts */
NVIC_SetPriority(IRQn, Priority);
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
{
return SysTick_Config(TicksNum);
}
/**
* @brief Delay N system-clock cycle.
* @param nClock < 0x1000000
* @retval None
*/
void CORTEX_Delay_nSysClock(__IO uint32_t nClock)
{
uint32_t tmp;
SysTick->LOAD = nClock - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \
|SysTick_CTRL_ENABLE_Msk;
do
{
tmp = SysTick->CTRL;
}
while (!(tmp & SysTick_CTRL_COUNTFLAG_Msk));
SysTick->CTRL = 0;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "target.h"
/**
* @brief Setup the microcontroller system
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
volatile uint32_t i;
uint32_t tmp[3];
ANA->REG0 = 0x30;
ANA->REG4 = 0x04;
ANA->REG7 = 0x84;
ANA->REGA = 0x02;
while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
ANA->ADCCTRL0 = 0x300000;
ANA->ADCCTRL1 = 0xC2;
ANA->ADCCTRL2 = 0x8014;
LCD->CTRL = 0x84;
tmp[0] = 0x599A599A;
tmp[1] = 0x78000000;
tmp[2] = 0x80000000;
RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
}
/**
* @brief Initializes registers.
* @param None
* @retval None
*/
void SystemUpdate(void)
{
uint32_t tmp[3];
ANA->REG0 &= ~0xCE;
ANA->REG0 |= 0x30;
ANA->REG1 &= ~0x7F;
ANA->REG2 &= ~0xC0;
ANA->REG3 &= ~0x01;
ANA->REG4 |= 0x04;
ANA->REG4 &= ~0xFB;
ANA->REG5 &= ~0xB0;
ANA->REG6 &= ~0x3E;
ANA->REG7 |= 0x84;
ANA->REG7 &= ~0x7B;
ANA->REG8 &= ~0x0C;
ANA->REGA |= 0x02;
ANA->REGA &= ~0x7D;
tmp[0] = 0x599A599A;
tmp[1] = RTC->ADCMACTL;
tmp[1] &= ~0XFF080000;
tmp[1] |= 0x78000000;
tmp[2] = 0x80000000;
RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
}
/*********************************** END OF FILE ******************************/

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('VangoV85xxP_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/Vango/V85xxP/Source/system_target.c']
src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c']
src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_cortex.c']
src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S']
if rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S']
path = [
cwd + '/CMSIS/Vango/V85xxP/Include',
cwd + '/CMSIS',
cwd + '/VangoV85xxP_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85XXP','USE_TARGET_DRIVER']
group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/**
******************************************************************************
* @file lib_adc.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief ADC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_H
#define __LIB_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Mode;
uint32_t ClockSource;
uint32_t ClockFrq;
uint32_t SkipSample;
uint32_t AverageSample;
uint32_t TriggerSource;
uint32_t Channel;
uint32_t ResDivEnable;
uint32_t AverageEnable;
} ADC_InitType;
typedef struct
{
uint32_t THDChannel;
uint8_t UpperTHD;
uint8_t LowerTHD;
uint32_t TriggerSel;
uint32_t THDSource;
} ADCTHD_InitType;
/* Exported constants --------------------------------------------------------*/
//Mode
#define ADC_MODE_DC (0UL)
#define ADC_MODE_AC (1UL)
#define ADC_MODE_TEMP (2UL)
#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_DC) ||\
((__MODE__) == ADC_MODE_AC) ||\
((__MODE__) == ADC_MODE_TEMP))
//ClockSource
#define ADC_CLKSRC_RCH (0)
#define ADC_CLKSRC_PLLL ANA_ADCCTRL0_CLKSRCSEL
#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\
((__CLKSRC__) == ADC_CLKSRC_PLLL))
//ClockFrq
#define ADC_CLKFRQ_HIGH (0UL)
#define ADC_CLKFRQ_LOW (1UL)
#define IS_ADC_CLKFRQ(__CLKFRQ__) (((__CLKFRQ__) == ADC_CLKFRQ_HIGH) ||\
((__CLKFRQ__) == ADC_CLKFRQ_LOW))
//SkipSample
#define ADC_SKIP_0 (0x0UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
#define ADC_SKIP_4 (0x4UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
#define ADC_SKIP_8 (0x7UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
#define ADC_SKIP_12 (0x12UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos)
#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_0) ||\
((__SKIP__) == ADC_SKIP_4) ||\
((__SKIP__) == ADC_SKIP_8) ||\
((__SKIP__) == ADC_SKIP_12))
//AverageSample
#define ADC_AVERAGE_2 (0x0UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define ADC_AVERAGE_4 (0x1UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define ADC_AVERAGE_8 (0x2UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define ADC_AVERAGE_16 (0x3UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define ADC_AVERAGE_32 (0x4UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define ADC_AVERAGE_64 (0x5UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos)
#define IS_ADC_AVERAG(__AVERAG__) (((__AVERAG__) == ADC_AVERAGE_2) ||\
((__AVERAG__) == ADC_AVERAGE_4) ||\
((__AVERAG__) == ADC_AVERAGE_8) ||\
((__AVERAG__) == ADC_AVERAGE_16) ||\
((__AVERAG__) == ADC_AVERAGE_32) ||\
((__AVERAG__) == ADC_AVERAGE_64))
//TriggerSource
#define ADC_TRIGSOURCE_OFF (0x0UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_ITVSITV (0x1UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_WKUSEC (0x2UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_ALARM (0x3UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_TMR0 (0x4UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_TMR1 (0x5UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_TMR2 (0x6UL << ANA_ADCCTRL0_AEN_Pos)
#define ADC_TRIGSOURCE_TMR3 (0x7UL << ANA_ADCCTRL0_AEN_Pos)
#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_ITVSITV) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_WKUSEC) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_ALARM) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR0) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR1) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR2) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR3))
//Channel
#define ADC_CHANNEL_NONE (0 << 0UL)
#define ADC_CHANNEL_GND0 (1 << 0UL)
#define ADC_CHANNEL_BAT1 (1 << 1UL)
#define ADC_CHANNEL_BATRTC (1 << 2UL)
#define ADC_CHANNEL_CH3 (1 << 3UL)
#define ADC_CHANNEL_CH4 (1 << 4UL)
#define ADC_CHANNEL_CH5 (1 << 5UL)
#define ADC_CHANNEL_CH6 (1 << 6UL)
#define ADC_CHANNEL_CH7 (1 << 7UL)
#define ADC_CHANNEL_CH8 (1 << 8UL)
#define ADC_CHANNEL_CH9 (1 << 9UL)
#define ADC_CHANNEL_TEMP (1 << 10UL)
#define ADC_CHANNEL_CH11 (1 << 11UL)
#define ADC_CHANNEL_DVCC (1 << 12UL)
#define ADC_CHANNEL_GND13 (1 << 13UL)
#define ADC_CHANNEL_GND14 (1 << 14UL)
#define ADC_CHANNEL_GND15 (1 << 15UL)
#define ADC_CHANNEL_DC_Msk (0xFBFFUL)
#define ADC_CHANNEL_DC_ALL ADC_CHANNEL_DC_Msk
#define ADC_CHANNEL_AC_Msk (0x0BF8UL)
#define ADC_CHANNEL_AC_ALL ADC_CHANNEL_AC_Msk
#define IS_ADC_CHANNEL_GETDATA(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_GND0) ||\
((__CHANNEL__) == ADC_CHANNEL_BAT1) ||\
((__CHANNEL__) == ADC_CHANNEL_BATRTC) ||\
((__CHANNEL__) == ADC_CHANNEL_CH3) ||\
((__CHANNEL__) == ADC_CHANNEL_CH4) ||\
((__CHANNEL__) == ADC_CHANNEL_CH5) ||\
((__CHANNEL__) == ADC_CHANNEL_CH6) ||\
((__CHANNEL__) == ADC_CHANNEL_CH7) ||\
((__CHANNEL__) == ADC_CHANNEL_CH8) ||\
((__CHANNEL__) == ADC_CHANNEL_CH9) ||\
((__CHANNEL__) == ADC_CHANNEL_TEMP) ||\
((__CHANNEL__) == ADC_CHANNEL_CH11) ||\
((__CHANNEL__) == ADC_CHANNEL_DVCC) ||\
((__CHANNEL__) == ADC_CHANNEL_GND13) ||\
((__CHANNEL__) == ADC_CHANNEL_GND14) ||\
((__CHANNEL__) == ADC_CHANNEL_GND15))
#define IS_ADC_CHANNEL_AC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) &&\
(((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL))
#define IS_ADC_CHANNEL_DC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) &&\
(((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL))
#define IS_ADC_CHANNEL_TEMP(__CHANNEL__) ((__CHANNEL__) == ADC_CHANNEL_TEMP)
#define IS_ADC_CHANNEL_EN_DC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) ||\
((__CHANNEL__) == ADC_CHANNEL_NONE))
#define IS_ADC_CHANNEL_EN_AC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) ||\
((__CHANNEL__) == ADC_CHANNEL_NONE))
#define ADC_CHANNEL_Pos (0UL)
#define ADC_CHANNEL_SHIFT (ANA_ADCCTRL2_SCAN_CHx_Pos - ADC_CHANNEL_Pos)
#define ADC_AVERAGECH_SHIFT (RTC_ADCMACTL_AVERAGE_CHx_Pos - ADC_CHANNEL_Pos)
#define ADC_RESDIVCH_SHIFT (ANA_ADCCTRL1_RESDIV_CHx_Pos - ADC_CHANNEL_Pos)
//THDChannel
#define ADC_THDCHANNEL0 (0UL)
#define ADC_THDCHANNEL1 (1UL)
#define ADC_THDCHANNEL2 (2UL)
#define ADC_THDCHANNEL3 (3UL)
#define IS_ADC_THDCHANNEL(THDCHANNEL) (((THDCHANNEL) == ADC_THDCHANNEL0) ||\
((THDCHANNEL) == ADC_THDCHANNEL1) ||\
((THDCHANNEL) == ADC_THDCHANNEL2) ||\
((THDCHANNEL) == ADC_THDCHANNEL3))
//TriggerSel
#define ADC_THDSEL_HIGH (0UL)
#define ADC_THDSEL_RISING (1UL)
#define ADC_THDSEL_FALLING (2UL)
#define ADC_THDSEL_BOTH (3UL)
#define IS_ADC_THDSEL(__THDSEL__) (((__THDSEL__) == ADC_THDSEL_HIGH) ||\
((__THDSEL__) == ADC_THDSEL_RISING) ||\
((__THDSEL__) == ADC_THDSEL_FALLING) ||\
((__THDSEL__) == ADC_THDSEL_BOTH))
//INTMask
#define ADC_INT_UPPER_TH3 ANA_INTEN_INTEN21
#define ADC_INT_LOWER_TH3 ANA_INTEN_INTEN20
#define ADC_INT_UPPER_TH2 ANA_INTEN_INTEN19
#define ADC_INT_LOWER_TH2 ANA_INTEN_INTEN18
#define ADC_INT_UPPER_TH1 ANA_INTEN_INTEN17
#define ADC_INT_LOWER_TH1 ANA_INTEN_INTEN16
#define ADC_INT_UPPER_TH0 ANA_INTEN_INTEN15
#define ADC_INT_LOWER_TH0 ANA_INTEN_INTEN14
#define ADC_INT_AUTODONE ANA_INTEN_INTEN1
#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0
#define ADC_INT_Msk (0x3FC003UL)
#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0UL) &&\
(((__INT__) & ~ADC_INT_Msk) == 0UL))
//INTSTS
#define ADC_INTSTS_UPPER_TH3 ANA_INTSTS_INTSTS21
#define ADC_INTSTS_LOWER_TH3 ANA_INTSTS_INTSTS20
#define ADC_INTSTS_UPPER_TH2 ANA_INTSTS_INTSTS19
#define ADC_INTSTS_LOWER_TH2 ANA_INTSTS_INTSTS18
#define ADC_INTSTS_UPPER_TH1 ANA_INTSTS_INTSTS17
#define ADC_INTSTS_LOWER_TH1 ANA_INTSTS_INTSTS16
#define ADC_INTSTS_UPPER_TH0 ANA_INTSTS_INTSTS15
#define ADC_INTSTS_LOWER_TH0 ANA_INTSTS_INTSTS14
#define ADC_INTSTS_AUTODONE ANA_INTSTS_INTSTS1
#define ADC_INTSTS_MANUALDONE ANA_INTSTS_INTSTS0
#define ADC_INTSTS_Msk (0x3FC003UL)
#define IS_ADC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & ADC_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~ADC_INTSTS_Msk) == 0U))
#define IS_ADC_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == ADC_INTSTS_UPPER_TH3) ||\
((__INTFLAGR__) == ADC_INTSTS_LOWER_TH3) ||\
((__INTFLAGR__) == ADC_INTSTS_UPPER_TH2) ||\
((__INTFLAGR__) == ADC_INTSTS_LOWER_TH2) ||\
((__INTFLAGR__) == ADC_INTSTS_UPPER_TH1) ||\
((__INTFLAGR__) == ADC_INTSTS_LOWER_TH1) ||\
((__INTFLAGR__) == ADC_INTSTS_UPPER_TH0) ||\
((__INTFLAGR__) == ADC_INTSTS_LOWER_TH0) ||\
((__INTFLAGR__) == ADC_INTSTS_AUTODONE) ||\
((__INTFLAGR__) == ADC_INTSTS_MANUALDONE))
#define ADC_FLAG_CONV_ERR (0x1U << ANA_ADCCTRL2_CONV_ERR_Pos)
#define ADC_FLAG_CAL_ERR (0x1U << ANA_ADCCTRL2_CAL_ERR_Pos)
#define ADC_FLAG_CAL_DONE (0x1U << ANA_ADCCTRL2_RTC_CAL_DONE_Pos)
#define ADC_FLAG_BUSY (0x1U << ANA_ADCCTRL2_BUSY_Pos)
#define IS_ADC_ADCFLAG(__ADCFLAG__) (((__ADCFLAG__) == ADC_FLAG_CONV_ERR) ||\
((__ADCFLAG__) == ADC_FLAG_CAL_ERR) ||\
((__ADCFLAG__) == ADC_FLAG_CAL_DONE) ||\
((__ADCFLAG__) == ADC_FLAG_BUSY))
#define ADC_FLAG_RCMsk (ADC_FLAG_CONV_ERR|ADC_FLAG_CAL_ERR)
#define IS_ADC_ADCFLAGC(__ADCFLAG__) ((((__ADCFLAG__) & ADC_FLAG_RCMsk) != 0U) &&\
(((__ADCFLAG__) & ~ADC_FLAG_RCMsk) == 0U))
//THDFlag
#define ADC_THDFLAG_UPPER3 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos)
#define ADC_THDFLAG_LOWER3 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos)
#define ADC_THDFLAG_UPPER2 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos)
#define ADC_THDFLAG_LOWER2 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos)
#define ADC_THDFLAG_UPPER1 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos)
#define ADC_THDFLAG_LOWER1 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos)
#define ADC_THDFLAG_UPPER0 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos)
#define ADC_THDFLAG_LOWER0 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos)
#define IS_ADC_THDFLAG(__THDFLAG__) (((__THDFLAG__) == ADC_THDFLAG_UPPER3) ||\
((__THDFLAG__) == ADC_THDFLAG_LOWER3) ||\
((__THDFLAG__) == ADC_THDFLAG_UPPER2) ||\
((__THDFLAG__) == ADC_THDFLAG_LOWER2) ||\
((__THDFLAG__) == ADC_THDFLAG_UPPER1) ||\
((__THDFLAG__) == ADC_THDFLAG_LOWER1) ||\
((__THDFLAG__) == ADC_THDFLAG_UPPER0) ||\
((__THDFLAG__) == ADC_THDFLAG_LOWER0))
#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\
((__BATDIV__) == ADC_BAT_RESDIV))
/* ADC_GetVoltage */
//Mode
#define ADC_3V_ADCCHx_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define ADC_3V_ADCCHx_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define ADC_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define ADC_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_5V_ADCCHx_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define ADC_5V_ADCCHx_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define ADC_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define ADC_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_TEMP (0x1000UL) // Temperature ; Channel: ADC_CHANNEL_TEMP
#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_ADCCHx_NODIV) ||\
((__MODE__) == ADC_3V_ADCCHx_RESDIV) ||\
((__MODE__) == ADC_3V_BAT1_RESDIV) ||\
((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_5V_ADCCHx_NODIV) ||\
((__MODE__) == ADC_5V_ADCCHx_RESDIV) ||\
((__MODE__) == ADC_5V_BAT1_RESDIV) ||\
((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_TEMP))
/* Exported Functions ------------------------------------------------------- */
/* ADC Exported Functions Group1:
(De)Initialization -------------------------*/
void ADC_DeInit(void);
void ADC_StructInit(ADC_InitType* ADC_InitStruct);
void ADC_Init(ADC_InitType* ADC_InitStruct);
/* ADC Exported Functions Group2:
ADC Configuration --------------*/
void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct);
void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct);
void ADC_Calibration(void);
/* ADC Exported Functions Group3:
Get NVR Info, Calculate datas --------------*/
uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value);
/* ADC Exported Functions Group4:
Interrupt (flag) ---------------------------*/
int16_t ADC_GetADCConversionValue(uint32_t Channel);
void ADC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t ADC_GetFlag(uint32_t FlagMask);
void ADC_ClearFlag(uint32_t FlagMask);
uint8_t ADC_GetINTStatus(uint32_t INTMask);
void ADC_ClearINTStatus(uint32_t INTMask);
uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask);
/* ADC Exported Functions Group5:
MISC Configuration -------------------------*/
void ADC_Cmd(uint32_t NewState);
void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState);
void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState);
void ADC_StartManual(void);
void ADC_WaitForManual(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc_tiny.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_TINY_H
#define __LIB_ADC_TINY_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SignalSel;
uint32_t ADTREF1;
uint32_t ADTREF2;
uint32_t ADTREF3;
} TADCInitType;
//SelADT
#define ADCTINY_SIGNALSEL_IOE6 0
#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_ADTSEL
#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
//ADTREF1
#define ADCTINY_REF1_0_9 0
#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL
#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
((__ADTREF1__) == ADCTINY_REF1_0_7))
//ADTREF2
#define ADCTINY_REF2_1_8 0
#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL
#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
((__ADTREF2__) == ADCTINY_REF2_1_6))
//ADTREF3
#define ADCTINY_REF3_2_7 0
#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL
#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
((__ADTREF3__) == ADCTINY_REF3_2_5))
//THSel
#define ADCTINY_THSEL_0 (0x00UL << ANA_MISC_TADCTH_Pos)
#define ADCTINY_THSEL_1 (0x01UL << ANA_MISC_TADCTH_Pos)
#define ADCTINY_THSEL_2 (0x02UL << ANA_MISC_TADCTH_Pos)
#define ADCTINY_THSEL_3 (0x03UL << ANA_MISC_TADCTH_Pos)
#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\
((__THSEL__) == ADCTINY_THSEL_1) ||\
((__THSEL__) == ADCTINY_THSEL_2) ||\
((__THSEL__) == ADCTINY_THSEL_3))
/* Exported Functions ------------------------------------------------------- */
void TADC_DeInit(void);
void TADC_StructInit(TADCInitType* TADC_InitStruct);
void TADC_Init(TADCInitType* TADC_InitStruct);
void TADC_Cmd(uint32_t NewState);
uint8_t TADC_GetOutput(void);
void TADC_IntTHConfig(uint32_t THSel);
void TADC_INTConfig(uint32_t NewState);
uint8_t TADC_GetINTStatus(void);
void TADC_ClearINTStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_TINY_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
#ifndef __LIB_ANA_H
#define __LIB_ANA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/***** StatusMask (ANA_GetStatus) *****/
#define ANA_STATUS_AVCCLV ANA_CMPOUT_AVCCLV
#define ANA_STATUS_VDCINDROP ANA_CMPOUT_VDCINDROP
#define ANA_STATUS_VDDALARM ANA_CMPOUT_VDDALARM
#define ANA_STATUS_COMP2 ANA_CMPOUT_CMP2
#define ANA_STATUS_COMP1 ANA_CMPOUT_CMP1
#define ANA_STATUS_LOCKL ANA_CMPOUT_LOCKL
#define ANA_STATUS_LOCKH ANA_CMPOUT_LOCKH
/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/
#define ANA_INT_UPPER_TH3 ANA_INTEN_INTEN21
#define ANA_INT_LOWER_TH3 ANA_INTEN_INTEN20
#define ANA_INT_UPPER_TH2 ANA_INTEN_INTEN19
#define ANA_INT_LOWER_TH2 ANA_INTEN_INTEN18
#define ANA_INT_UPPER_TH1 ANA_INTEN_INTEN17
#define ANA_INT_LOWER_TH1 ANA_INTEN_INTEN16
#define ANA_INT_UPPER_TH0 ANA_INTEN_INTEN15
#define ANA_INT_LOWER_TH0 ANA_INTEN_INTEN14
#define ANA_INT_TADC_OVER ANA_INTEN_INTEN13
#define ANA_INT_REGERR ANA_INTEN_INTEN12
#define ANA_INT_SLPFAIL_VDCIN ANA_INTEN_INTEN11
#define ANA_INT_AVCCLV ANA_INTEN_INTEN10
#define ANA_INT_VDCINDROP ANA_INTEN_INTEN8
#define ANA_INT_VDDALARM ANA_INTEN_INTEN7
#define ANA_INT_COMP2 ANA_INTEN_INTEN3
#define ANA_INT_COMP1 ANA_INTEN_INTEN2
#define ANA_INT_ADCA ANA_INTEN_INTEN1
#define ANA_INT_ADCM ANA_INTEN_INTEN0
#define ANA_INT_Msk (ANA_INTSTS_INTSTS21 \
|ANA_INTSTS_INTSTS20 \
|ANA_INTSTS_INTSTS19 \
|ANA_INTSTS_INTSTS18 \
|ANA_INTSTS_INTSTS17 \
|ANA_INTSTS_INTSTS16 \
|ANA_INTSTS_INTSTS15 \
|ANA_INTSTS_INTSTS14 \
|ANA_INTSTS_INTSTS13 \
|ANA_INTSTS_INTSTS12 \
|ANA_INTSTS_INTSTS11 \
|ANA_INTSTS_INTSTS10 \
|ANA_INTSTS_INTSTS8 \
|ANA_INTSTS_INTSTS7 \
|ANA_INTSTS_INTSTS3 \
|ANA_INTSTS_INTSTS2 \
|ANA_INTSTS_INTSTS1 \
|ANA_INTSTS_INTSTS0)
/****************************** ANA Instances *********************************/
#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA)
/* Private macros ------------------------------------------------------------*/
#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\
((__STATUS__) == ANA_STATUS_VDCINDROP) ||\
((__STATUS__) == ANA_STATUS_VDDALARM) ||\
((__STATUS__) == ANA_STATUS_COMP2) ||\
((__STATUS__) == ANA_STATUS_COMP1) ||\
((__STATUS__) == ANA_STATUS_LOCKL) ||\
((__STATUS__) == ANA_STATUS_LOCKH))
#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_UPPER_TH3) ||\
((__INTSTSR__) == ANA_INT_LOWER_TH3) ||\
((__INTSTSR__) == ANA_INT_UPPER_TH2) ||\
((__INTSTSR__) == ANA_INT_LOWER_TH2) ||\
((__INTSTSR__) == ANA_INT_UPPER_TH1) ||\
((__INTSTSR__) == ANA_INT_LOWER_TH1) ||\
((__INTSTSR__) == ANA_INT_UPPER_TH0) ||\
((__INTSTSR__) == ANA_INT_LOWER_TH0) ||\
((__INTSTSR__) == ANA_INT_TADC_OVER) ||\
((__INTSTSR__) == ANA_INT_REGERR) ||\
((__INTSTSR__) == ANA_INT_SLPFAIL_VDCIN) ||\
((__INTSTSR__) == ANA_INT_AVCCLV) ||\
((__INTSTSR__) == ANA_INT_VDCINDROP) ||\
((__INTSTSR__) == ANA_INT_VDDALARM) ||\
((__INTSTSR__) == ANA_INT_COMP2) ||\
((__INTSTSR__) == ANA_INT_COMP1) ||\
((__INTSTSR__) == ANA_INT_ADCA) ||\
((__INTSTSR__) == ANA_INT_ADCM))
#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\
(((__INTSTSC__) & ~ANA_INT_Msk) == 0U))
#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__)
/* Exported Functions ------------------------------------------------------- */
uint8_t ANA_GetStatus(uint32_t StatusMask);
uint8_t ANA_GetINTStatus(uint32_t IntMask);
void ANA_ClearINTStatus(uint32_t IntMask);
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ANA_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_clk.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Clock library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CLK_H
#define __LIB_CLK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* PLLL Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLL_ConfTypeDef;
/* PLLH Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLH_ConfTypeDef;
/* RCH Configure */
typedef struct
{
uint32_t State;
} RCH_ConfTypeDef;
/* XTALH Configure */
typedef struct
{
uint32_t State;
} XTALH_ConfTypeDef;
/* RTCCLK Configure */
typedef struct
{
uint32_t Source;
uint32_t Divider;
} RTCCLK_ConfTypeDef;
/* HCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} HCLK_ConfTypeDef;
/* PCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} PCLK_ConfTypeDef;
/* Clock Configure */
typedef struct
{
uint32_t ClockType; /* The clock to be configured */
uint32_t AHBSource;
PLLL_ConfTypeDef PLLL;
PLLH_ConfTypeDef PLLH;
XTALH_ConfTypeDef XTALH;
RTCCLK_ConfTypeDef RTCCLK;
HCLK_ConfTypeDef HCLK;
PCLK_ConfTypeDef PCLK;
} CLK_InitTypeDef;
/************** Bits definition for ANA_REG9 register ******************/
#define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos)
#define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos)
#define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos)
/************** Bits definition for MISC2_CLKSEL register ******************/
#define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */
#define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */
#define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */
#define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */
#define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */
/***** ClockType *****/
#define CLK_TYPE_MSk (0xFFUL)
#define CLK_TYPE_ALL CLK_TYPE_MSk
#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */
#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */
#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */
#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */
#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */
#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */
#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */
/***** AHBSource *****/
#define CLK_AHBSEL_6_5MRC (0x0U << MISC2_CLKSEL_CLKSEL_Pos)
#define CLK_AHBSEL_6_5MXTAL (0x1U << MISC2_CLKSEL_CLKSEL_Pos)
#define CLK_AHBSEL_HSPLL (0x2U << MISC2_CLKSEL_CLKSEL_Pos)
#define CLK_AHBSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos)
#define CLK_AHBSEL_LSPLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos)
/***** PLLL_ConfTypeDef PLLL *****/
/* PLLL.Source */
#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL
#define CLK_PLLLSRC_XTALL (0)
/* PLLL.State */
#define CLK_PLLL_ON ANA_REG3_PLLLPDN
#define CLK_PLLL_OFF (0)
/* PLLL.Frequency */
#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M
#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M
#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M
#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M
#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K
#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K
#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K
/***** PLLH_ConfTypeDef PLLH *****/
/* PLLH.Source */
#define CLK_PLLHSRC_RCH (0)
#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL
/* PLLH.State */
#define CLK_PLLH_ON ANA_REG3_PLLHPDN
#define CLK_PLLH_OFF (0)
/* PLLH.Frequency */
#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2
#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5
#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3
#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5
#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4
#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5
#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5
#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6
#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5
#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7
#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5
/* XTALH_ConfTypeDef XTALH */
/* XTALH.State */
#define CLK_XTALH_ON ANA_REG3_XOHPDN
#define CLK_XTALH_OFF (0)
/* RTCCLK Configure */
/* RTCCLK.Source */
#define CLK_RTCCLKSRC_XTALL (0)
#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCCLK_SEL)
/* RTCCLK.Divider */
#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0)
#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1)
//AHB Periphral
#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA
#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO
#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD
#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT
#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_LCD \
|MISC2_HCLKEN_CRYPT)
//APB Periphral
#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA
#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C
#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1
#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0
#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1
#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2
#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3
#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4
#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5
#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160
#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161
#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER
#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC
#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2
#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU
#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC
#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA
#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0
#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1
#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2
#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160 \
|MISC2_PCLKEN_ISO78161 \
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC1 \
|MISC2_PCLKEN_MISC2 \
|MISC2_PCLKEN_PMU \
|MISC2_PCLKEN_RTC \
|MISC2_PCLKEN_ANA \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2 \
|MISC2_PCLKEN_SPI3)
/***** PLLStatus (CLK_GetPLLLockStatus) *****/
#define CLK_STATUS_LOCKL ANA_CMPOUT_LOCKL
#define CLK_STATUS_LOCKH ANA_CMPOUT_LOCKH
/* Private macros ------------------------------------------------------------*/
#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_MSk) != 0UL) &&\
(((__TYPE__) & ~CLK_TYPE_MSk) == 0UL))
#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\
((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\
((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\
((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\
((__AHBSRC__) == CLK_AHBSEL_LSPLL))
#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\
((__PLLLSRC__) == CLK_PLLLSRC_XTALL))
#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\
((__PLLLSTA__) == CLK_PLLL_OFF))
#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_2048MHz))
#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\
((__PLLHSRC__) == CLK_PLLHSRC_XTALH))
#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\
((__PLLHSTA__) == CLK_PLLH_OFF))
#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\
((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\
((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\
((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\
((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\
((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\
((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\
((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\
((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\
((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\
((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\
((__PLLHSRC__) == CLK_PLLH_49_152MHz))
#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\
((__XTALHSTA__) == CLK_XTALH_OFF))
#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\
((__RTCSRC__) == CLK_RTCCLKSRC_RCL))
#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\
((__RTCDIV__) == CLK_RTCCLKDIV_4))
#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\
((__HCLKDIV__) < 257UL))
#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\
((__PCLKDIV__) < 257UL))
#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\
(((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\
(((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_CMPOUT_LOCKL) ||\
((__PLLLOCK__) == ANA_CMPOUT_LOCKH))
/* Exported Functions ------------------------------------------------------- */
/* CLK Exported Functions Group1:
Initialization and functions ---------------*/
void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
/* CLK Exported Functions Group2:
Peripheral Control -------------------------*/
void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
/* CLK Exported Functions Group3:
Get clock/configuration information --------*/
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetPCLKFreq(void);
uint32_t CLK_GetPLLLFreq(void);
void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
uint8_t CLK_GetXTALHStatus(void);
uint8_t CLK_GetXTALLStatus(void);
uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CLK_H */
/*********************************** END OF FILE ******************************/

205
bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_cmp.h Normal file
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@@ -0,0 +1,205 @@
/**
******************************************************************************
* @file lib_cmp.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief CMP library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CMP_H
#define __LIB_CMP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* CMP Time struct */
typedef struct
{
uint32_t DebSel;
uint32_t SignalSourceSel;
uint32_t BiasSel;
} CMP_TypeDef;
typedef struct
{
uint32_t ModeSel;
uint32_t CheckPeriod;
uint32_t CheckNum;
} CMP_CountTypeDef;
typedef struct
{
uint32_t DebSel;
uint32_t OutputSel;
} CMP_OutputTypeDef;
typedef struct
{
uint32_t INTNumSel;
uint32_t SubSel;
uint32_t THRNum;
} CMP_INTTypeDef;
/* Macros --------------------------------------------------------------------*/
/***** CMP_DEBConfig *****/
//CMPx
#define CMP_1 (0x00U)
#define CMP_2 (0x02U)
#define IS_CMP(__CMP__) (((__CMP__) == CMP_1) || ((__CMP__) == CMP_2))
/************** Bits definition for ANA_REG2 register ******************/
#define ANA_REG2_CMP1SEL_0 (0x0U << ANA_REG2_CMP1SEL_Pos)
#define ANA_REG2_CMP1SEL_1 (0x1U << ANA_REG2_CMP1SEL_Pos)
#define ANA_REG2_CMP1SEL_2 (0x2U << ANA_REG2_CMP1SEL_Pos)
#define ANA_REG2_CMP1SEL_3 (0x3U << ANA_REG2_CMP1SEL_Pos)
#define ANA_REG2_CMP2SEL_0 (0x0U << ANA_REG2_CMP2SEL_Pos)
#define ANA_REG2_CMP2SEL_1 (0x1U << ANA_REG2_CMP2SEL_Pos)
#define ANA_REG2_CMP2SEL_2 (0x2U << ANA_REG2_CMP2SEL_Pos)
#define ANA_REG2_CMP2SEL_3 (0x3U << ANA_REG2_CMP2SEL_Pos)
/************** Bits definition for ANA_REG5 register ******************/
#define ANA_REG5_CMP1IT_0 (0x0U << ANA_REG5_CMP1IT_Pos)
#define ANA_REG5_CMP1IT_1 (0x1U << ANA_REG5_CMP1IT_Pos)
#define ANA_REG5_CMP1IT_2 (0x2U << ANA_REG5_CMP1IT_Pos)
#define ANA_REG5_CMP1IT_3 (0x3U << ANA_REG5_CMP1IT_Pos)
#define ANA_REG5_CMP2IT_0 (0x0U << ANA_REG5_CMP2IT_Pos)
#define ANA_REG5_CMP2IT_1 (0x1U << ANA_REG5_CMP2IT_Pos)
#define ANA_REG5_CMP2IT_2 (0x2U << ANA_REG5_CMP2IT_Pos)
#define ANA_REG5_CMP2IT_3 (0x3U << ANA_REG5_CMP2IT_Pos)
/************** Bits definition for ANA_CTRL register ******************/
//Debounce
#define CMP_DEB_NONE (0x0U)
#define CMP_DEB_RTCCLK_2 (0x1U)
#define CMP_DEB_RTCCLK_3 (0x2U)
#define CMP_DEB_RTCCLK_4 (0x3U)
#define IS_CMP_DEB(__DEB__) (((__DEB__) == CMP_DEB_NONE) ||\
((__DEB__) == CMP_DEB_RTCCLK_2) ||\
((__DEB__) == CMP_DEB_RTCCLK_3) ||\
((__DEB__) == CMP_DEB_RTCCLK_4))
/***** SourceSelect (CMP_ConfigSignalSource) *****/
#define CMP_SIGNALSRC_PPIN_TO_VREF 0x00
#define CMP_SIGNALSRC_PPIN_TO_BGPREF 0x01
#define CMP_SIGNALSRC_PBAT_TO_VREF 0x80
#define CMP_SIGNALSRC_PBAT_TO_BGPREF 0x81
#define CMP_SIGNALSRC_NPIN_TO_VREF 0x10
#define CMP_SIGNALSRC_NPIN_TO_BGPREF 0x11
#define CMP_SIGNALSRC_PPIN_TO_NPIN 0x20
#define CMP_SIGNALSRC_PBAT_TO_NPIN 0xA0
#define IS_CMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_VREF) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_BGPREF) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_NPIN) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_NPIN) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_VREF) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_BGPREF) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_VREF) ||\
((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_BGPREF))
/***** BiasSel (CMP_BiasConfig) *****/
#define CMP_BIAS_20nA (0x0U)
#define CMP_BIAS_100nA (0x1U)
#define CMP_BIAS_500nA (0x2U)
#define IS_CMP_BIAS(__BIAS__) (((__BIAS__) == CMP_BIAS_20nA) ||\
((__BIAS__) == CMP_BIAS_100nA) ||\
((__BIAS__) == CMP_BIAS_500nA))
/***** CheckPeriod (CMP_CheckFrequecnyConfig) *****/
#define CMP_PERIOD_30US 0
#define CMP_PERIOD_7_8125MS 1
#define CMP_PERIOD_125MS 2
#define CMP_PERIOD_250MS 3
#define CMP_PERIOD_500MS 4
#define IS_CMP_CHECKPERIOD(__CHECKPERIOD__) (((__CHECKPERIOD__) == CMP_PERIOD_30US) ||\
((__CHECKPERIOD__) == CMP_PERIOD_7_8125MS)||\
((__CHECKPERIOD__) == CMP_PERIOD_125MS) ||\
((__CHECKPERIOD__) == CMP_PERIOD_250MS) ||\
((__CHECKPERIOD__) == CMP_PERIOD_500MS))
/***** Mode (CMP_ModeConfig) *****/
#define CMP_MODE_OFF (0x0U)
#define CMP_MODE_RISING (0x1U)
#define CMP_MODE_FALLING (0x2U)
#define CMP_MODE_BOTH (0x3U)
#define IS_CMP_MODE(__MODE__) (((__MODE__) == CMP_MODE_OFF) ||\
((__MODE__) == CMP_MODE_RISING) ||\
((__MODE__) == CMP_MODE_FALLING) ||\
((__MODE__) == CMP_MODE_BOTH))
//CountSel
#define CMP_COUNT_NOSUB 0
#define CMP_COUNT_SUB 1
#define IS_CMP_COUNT(__COUNT__) (((__COUNT__) == CMP_COUNT_NOSUB) ||\
((__COUNT__) == CMP_COUNT_SUB))
//SubSel
#define CMP_INTNUM_EVERY 0
#define CMP_INTNUM_1 1
#define IS_CMP_INTNUM(__INTNUM__) (((__INTNUM__) == CMP_INTNUM_EVERY) ||\
((__INTNUM__) == CMP_INTNUM_1))
//THRNum
#define IS_CMP_THRNUM(__THRNUM__) ((__THRNUM__) < 65536UL)
#define CMP_CHKNUM_1 0
#define CMP_CHKNUM_2 1
#define CMP_CHKNUM_3 2
#define CMP_CHKNUM_4 3
#define CMP_CHKNUM_5 4
#define CMP_CHKNUM_6 5
#define CMP_CHKNUM_7 6
#define CMP_CHKNUM_8 7
#define CMP_CHKNUM_9 8
#define CMP_CHKNUM_10 9
#define CMP_CHKNUM_11 10
#define CMP_CHKNUM_12 11
#define CMP_CHKNUM_13 12
#define CMP_CHKNUM_14 13
#define CMP_CHKNUM_15 14
#define CMP_CHKNUM_16 15
#define IS_CMP_CHKNUM(__CHKNUM__) (__CHKNUM__ < 16)
//DebSel
//SubSel
#define CMP_OUTPUT_DEB 0
#define CMP_OUTPUT_NODEB 1
#define IS_CMP_OUTPUTDEB(__OUTPUTDEB__) (((__OUTPUTDEB__) == CMP_OUTPUT_DEB) ||\
((__OUTPUTDEB__) == CMP_OUTPUT_NODEB))
/* Exported Functions ------------------------------------------------------- */
/* CMP Exported Functions Group1:
(De)Initialization ------------------------*/
void CMP_DeInit(uint32_t CMPx);
void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct);
void CMP_StructInit(CMP_TypeDef *InitStruct);
void CMP_CountStructInit(CMP_CountTypeDef *InitStruct);
void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct);
void CMP_INTStructInit(CMP_INTTypeDef *InitStruct);
void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct);
void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct);
void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct);
/* CMP Exported Functions Group2:
Interrupt (flag) --------------------------*/
void CMP_INTConfig(uint32_t CMPx, uint32_t NewState);
uint8_t CMP_GetINTStatus(uint32_t CMPx);
void CMP_ClearINTStatus(uint32_t CMPx);
/* CMP Exported Functions Group3:
MISC Configuration ------------------------*/
void CMP_Cmd(uint32_t CMPx, uint32_t NewState);
uint32_t CMP_GetCNTValue(uint32_t CMPx);
void CMP_ClearCNTValue(uint32_t CMPx);
uint8_t CMP_GetOutputValue(uint32_t CMPx);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CMP_H */
/*********************************** END OF FILE ******************************/

107
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/**
******************************************************************************
* @file lib_crypt.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief CRYPT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CRYPT_H
#define __LIB_CRYPT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/************** Bits definition for CRYPT_CTRL register ******************/
#define CRYPT_CTRL_MODE_MULTIPLY (0x0U << CRYPT_CTRL_MODE_Pos)
#define CRYPT_CTRL_MODE_ADD (0x1U << CRYPT_CTRL_MODE_Pos)
#define CRYPT_CTRL_MODE_SUB (0x2U << CRYPT_CTRL_MODE_Pos)
#define CRYPT_CTRL_MODE_RSHIFT1 (0x3U << CRYPT_CTRL_MODE_Pos)
#define CRYPT_CTRL_LENGTH_32 (0x0U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_64 (0x1U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_96 (0x2U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_128 (0x3U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_160 (0x4U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_192 (0x5U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_224 (0x6U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_256 (0x7U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_288 (0x8U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_320 (0x9U << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_352 (0xAU << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_384 (0xBU << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_416 (0xCU << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_448 (0xDU << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_480 (0xEU << CRYPT_CTRL_LENGTH_Pos)
#define CRYPT_CTRL_LENGTH_512 (0xFU << CRYPT_CTRL_LENGTH_Pos)
//Length
#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32
#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64
#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96
#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128
#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160
#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192
#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224
#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256
#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288
#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320
#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352
#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384
#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416
#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448
#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480
#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512
//Nostop
#define CRYPT_STOPCPU (0)
#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP
/* Private macros ------------------------------------------------------------*/
#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) & 0x3U) == 0U)
#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_64) ||\
((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_96) ||\
((__LENGTH__) == CRYPT_LENGTH_128) ||\
((__LENGTH__) == CRYPT_LENGTH_160) ||\
((__LENGTH__) == CRYPT_LENGTH_192) ||\
((__LENGTH__) == CRYPT_LENGTH_224) ||\
((__LENGTH__) == CRYPT_LENGTH_256) ||\
((__LENGTH__) == CRYPT_LENGTH_288) ||\
((__LENGTH__) == CRYPT_LENGTH_320) ||\
((__LENGTH__) == CRYPT_LENGTH_352) ||\
((__LENGTH__) == CRYPT_LENGTH_384) ||\
((__LENGTH__) == CRYPT_LENGTH_416) ||\
((__LENGTH__) == CRYPT_LENGTH_448) ||\
((__LENGTH__) == CRYPT_LENGTH_480) ||\
((__LENGTH__) == CRYPT_LENGTH_512))
#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU))
/****************************** CRYPT Instances *******************************/
#define IS_CRYPT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRYPT)
/* Exported Functions ------------------------------------------------------- */
void CRYPT_AddressAConfig(uint16_t AddrA);
void CRYPT_AddressBConfig(uint16_t AddrB);
void CRYPT_AddressOConfig(uint16_t AddrO);
uint8_t CRYPT_GetCarryBorrowBit(void);
void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop);
void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop);
void CRYPT_StartSub(uint32_t Length, uint32_t Nostop);
void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop);
void CRYPT_WaitForLastOperation(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CRYPT_H */
/*********************************** END OF FILE ******************************/

267
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/**
******************************************************************************
* @file lib_dma.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief DMA library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_DMA_H
#define __LIB_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//Channel
#define DMA_CHANNEL_0 (0)
#define DMA_CHANNEL_1 (1)
#define DMA_CHANNEL_2 (2)
#define DMA_CHANNEL_3 (3)
typedef struct
{
uint32_t DestAddr; /* destination address */
uint32_t SrcAddr; /* source address */
uint8_t FrameLen; /* Frame length */
uint8_t PackLen; /* Package length */
uint32_t ContMode; /* Continuous mode */
uint32_t TransMode; /* Transfer mode */
uint32_t ReqSrc; /* DMA request source */
uint32_t DestAddrMode; /* Destination address mode */
uint32_t SrcAddrMode; /* Source address mode */
uint32_t TransSize; /* Transfer size mode */
} DMA_InitType;
/************** Bits definition for DMA_CxCTL register ******************/
/************** Bits definition for DMA_AESCTL register ******************/
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA)
//ContMode
#define DMA_CONTMODE_ENABLE DMA_CCTL_CONT
#define DMA_CONTMODE_DISABLE 0
#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\
((__CONTMOD__) == DMA_CONTMODE_DISABLE))
//TransMode
#define DMA_TRANSMODE_SINGLE 0
#define DMA_TRANSMODE_PACK DMA_CCTL_TMODE
#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\
((__TRANSMOD__) == DMA_TRANSMODE_PACK))
//ReqSrc
#define DMA_REQSRC_SOFT (0x0U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000000 */
#define DMA_REQSRC_ADC (0x1U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000080 */
#define DMA_REQSRC_UART0TX (0x2U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000100 */
#define DMA_REQSRC_UART0RX (0x3U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000180 */
#define DMA_REQSRC_UART1TX (0x4U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000200 */
#define DMA_REQSRC_UART1RX (0x5U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000280 */
#define DMA_REQSRC_UART2TX (0x6U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000300 */
#define DMA_REQSRC_UART2RX (0x7U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000380 */
#define DMA_REQSRC_UART3TX (0x8U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000400 */
#define DMA_REQSRC_UART3RX (0x9U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000480 */
#define DMA_REQSRC_UART4TX (0xAU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000500 */
#define DMA_REQSRC_UART4RX (0xBU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000580 */
#define DMA_REQSRC_UART5TX (0xCU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000600 */
#define DMA_REQSRC_UART5RX (0xDU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000680 */
#define DMA_REQSRC_ISO78160TX (0xEU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000700 */
#define DMA_REQSRC_ISO78160RX (0xFU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000780 */
#define DMA_REQSRC_ISO78161TX (0x10U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000800 */
#define DMA_REQSRC_ISO78161RX (0x11U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000880 */
#define DMA_REQSRC_TIMER0 (0x12U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000900 */
#define DMA_REQSRC_TIMER1 (0x13U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000980 */
#define DMA_REQSRC_TIMER2 (0x14U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A00 */
#define DMA_REQSRC_TIMER3 (0x15U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A80 */
#define DMA_REQSRC_SPI1TX (0x16U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B00 */
#define DMA_REQSRC_SPI1RX (0x17U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B80 */
#define DMA_REQSRC_U32K0 (0x18U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C00 */
#define DMA_REQSRC_U32K1 (0x19U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C80 */
#define DMA_REQSRC_CMP1 (0x1AU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D00 */
#define DMA_REQSRC_CMP2 (0x1BU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D80 */
#define DMA_REQSRC_SPI3TX (0x1CU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E00 */
#define DMA_REQSRC_SPI3RX (0x1DU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E80 */
#define DMA_REQSRC_SPI2TX (0x1EU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F00 */
#define DMA_REQSRC_SPI2RX (0x1FU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F80 */
#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\
((__REQSRC__) == DMA_REQSRC_ADC) ||\
((__REQSRC__) == DMA_REQSRC_UART0TX) ||\
((__REQSRC__) == DMA_REQSRC_UART0RX) ||\
((__REQSRC__) == DMA_REQSRC_UART1TX) ||\
((__REQSRC__) == DMA_REQSRC_UART1RX) ||\
((__REQSRC__) == DMA_REQSRC_UART2TX) ||\
((__REQSRC__) == DMA_REQSRC_UART2RX) ||\
((__REQSRC__) == DMA_REQSRC_UART3TX) ||\
((__REQSRC__) == DMA_REQSRC_UART3RX) ||\
((__REQSRC__) == DMA_REQSRC_UART4TX) ||\
((__REQSRC__) == DMA_REQSRC_UART4RX) ||\
((__REQSRC__) == DMA_REQSRC_UART5TX) ||\
((__REQSRC__) == DMA_REQSRC_UART5RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\
((__REQSRC__) == DMA_REQSRC_TIMER0) ||\
((__REQSRC__) == DMA_REQSRC_TIMER1) ||\
((__REQSRC__) == DMA_REQSRC_TIMER2) ||\
((__REQSRC__) == DMA_REQSRC_TIMER3) ||\
((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\
((__REQSRC__) == DMA_REQSRC_U32K0) ||\
((__REQSRC__) == DMA_REQSRC_U32K1) ||\
((__REQSRC__) == DMA_REQSRC_CMP1) ||\
((__REQSRC__) == DMA_REQSRC_CMP2) ||\
((__REQSRC__) == DMA_REQSRC_SPI3TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI3RX) ||\
((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI2RX))
//DestAddrMode
#define DMA_DESTADDRMODE_FIX (0x0U << DMA_CCTL_DMODE_Pos) /*!< 0x00000000 */
#define DMA_DESTADDRMODE_PEND (0x1U << DMA_CCTL_DMODE_Pos) /*!< 0x00000020 */
#define DMA_DESTADDRMODE_FEND (0x2U << DMA_CCTL_DMODE_Pos) /*!< 0x00000040 */
#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\
((__DAM__) == DMA_DESTADDRMODE_PEND) ||\
((__DAM__) == DMA_DESTADDRMODE_FEND))
//SrcAddrMode
#define DMA_SRCADDRMODE_FIX (0x0U << DMA_CCTL_SMODE_Pos) /*!< 0x00000000 */
#define DMA_SRCADDRMODE_PEND (0x1U << DMA_CCTL_SMODE_Pos) /*!< 0x00000008 */
#define DMA_SRCADDRMODE_FEND (0x2U << DMA_CCTL_SMODE_Pos) /*!< 0x00000010 */
#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\
((__SAM__) == DMA_SRCADDRMODE_PEND) ||\
((__SAM__) == DMA_SRCADDRMODE_FEND))
//TransSize
#define DMA_TRANSSIZE_BYTE (0x0U << DMA_CCTL_SIZE_Pos)
#define DMA_TRANSSIZE_HWORD (0x1U << DMA_CCTL_SIZE_Pos)
#define DMA_TRANSSIZE_WORD (0x2U << DMA_CCTL_SIZE_Pos)
#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\
((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\
((__TSIZE__) == DMA_TRANSSIZE_WORD))
#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U)
#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U)
typedef struct
{
uint32_t Mode; /* AES mode */
uint32_t Direction; /* Direction */
uint32_t *KeyStr; /* AES key */
} DMA_AESInitType;
//AES MODE
#define DMA_AESMODE_128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */
#define DMA_AESMODE_192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */
#define DMA_AESMODE_256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */
#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\
((__AESMOD__) == DMA_AESMODE_192) ||\
((__AESMOD__) == DMA_AESMODE_256))
//AES Direction
#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC
#define DMA_AESDIRECTION_DECODE 0
#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\
((__AESDIR__) == DMA_AESDIRECTION_DECODE))
//INT
#define DMA_INT_C3DA DMA_IE_C3DAIE
#define DMA_INT_C2DA DMA_IE_C2DAIE
#define DMA_INT_C1DA DMA_IE_C1DAIE
#define DMA_INT_C0DA DMA_IE_C0DAIE
#define DMA_INT_C3FE DMA_IE_C3FEIE
#define DMA_INT_C2FE DMA_IE_C2FEIE
#define DMA_INT_C1FE DMA_IE_C1FEIE
#define DMA_INT_C0FE DMA_IE_C0FEIE
#define DMA_INT_C3PE DMA_IE_C3PEIE
#define DMA_INT_C2PE DMA_IE_C2PEIE
#define DMA_INT_C1PE DMA_IE_C1PEIE
#define DMA_INT_C0PE DMA_IE_C0PEIE
#define DMA_INT_Msk (0xFFFUL)
#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\
(((__INT__) & ~DMA_INT_Msk) == 0U))
//INTSTS
#define DMA_INTSTS_C3DA DMA_STS_C3DA
#define DMA_INTSTS_C2DA DMA_STS_C2DA
#define DMA_INTSTS_C1DA DMA_STS_C1DA
#define DMA_INTSTS_C0DA DMA_STS_C0DA
#define DMA_INTSTS_C3FE DMA_STS_C3FE
#define DMA_INTSTS_C2FE DMA_STS_C2FE
#define DMA_INTSTS_C1FE DMA_STS_C1FE
#define DMA_INTSTS_C0FE DMA_STS_C0FE
#define DMA_INTSTS_C3PE DMA_STS_C3PE
#define DMA_INTSTS_C2PE DMA_STS_C2PE
#define DMA_INTSTS_C1PE DMA_STS_C1PE
#define DMA_INTSTS_C0PE DMA_STS_C0PE
#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY
#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY
#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY
#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY
#define DMA_INTSTS_Msk (0xFFF0UL)
#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C0BUSY))
#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U))
#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\
((__CH__) == DMA_CHANNEL_1) ||\
((__CH__) == DMA_CHANNEL_2) ||\
((__CH__) == DMA_CHANNEL_3))
/* Exported Functions ------------------------------------------------------- */
/* DMA Exported Functions Group1:
(De)Initialization ------------------------*/
void DMA_DeInit(uint32_t Channel);
void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel);
void DMA_StructInit(DMA_InitType *InitStruct);
void DMA_ASEDeInit(void);
void DMA_AESInit(DMA_AESInitType *InitStruct);
/* DMA Exported Functions Group2:
Interrupt (flag) --------------------------*/
void DMA_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t DMA_GetINTStatus(uint32_t INTMask);
void DMA_ClearINTStatus(uint32_t INTMask);
/* DMA Exported Functions Group3:
MISC Configuration ------------------------*/
void DMA_Cmd(uint32_t Channel, uint32_t NewState);
void DMA_AESCmd(uint32_t NewState);
void DMA_StopTransmit(uint32_t Channel, uint32_t NewState);
uint8_t DMA_GetFrameLenTransferred(uint32_t Channel);
uint8_t DMA_GetPackLenTransferred(uint32_t Channel);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_DMA_H */
/*********************************** END OF FILE ******************************/

159
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/**
******************************************************************************
* @file lib_flash.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief FLASH library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_FLASH_H
#define __LIB_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define FLASH_BLOCK_0 (0x00000001UL)
#define FLASH_BLOCK_1 (0x00000002UL)
#define FLASH_BLOCK_2 (0x00000004UL)
#define FLASH_BLOCK_3 (0x00000008UL)
#define FLASH_BLOCK_4 (0x00000010UL)
#define FLASH_BLOCK_5 (0x00000020UL)
#define FLASH_BLOCK_6 (0x00000040UL)
#define FLASH_BLOCK_7 (0x00000080UL)
#define FLASH_BLOCK_8 (0x00000100UL)
#define FLASH_BLOCK_9 (0x00000200UL)
#define FLASH_BLOCK_10 (0x00000400UL)
#define FLASH_BLOCK_11 (0x00000800UL)
#define FLASH_BLOCK_12 (0x00001000UL)
#define FLASH_BLOCK_13 (0x00002000UL)
#define FLASH_BLOCK_14 (0x00004000UL)
#define FLASH_BLOCK_15 (0x00008000UL)
#define FLASH_BLOCK_16 (0x00010000UL)
#define FLASH_BLOCK_17 (0x00020000UL)
#define FLASH_BLOCK_18 (0x00040000UL)
#define FLASH_BLOCK_19 (0x00080000UL)
#define FLASH_BLOCK_20 (0x00100000UL)
#define FLASH_BLOCK_21 (0x00200000UL)
#define FLASH_BLOCK_22 (0x00400000UL)
#define FLASH_BLOCK_23 (0x00800000UL)
#define FLASH_BLOCK_24 (0x01000000UL)
#define FLASH_BLOCK_25 (0x02000000UL)
#define FLASH_BLOCK_26 (0x04000000UL)
#define FLASH_BLOCK_27 (0x08000000UL)
#define FLASH_BLOCK_28 (0x10000000UL)
#define FLASH_BLOCK_29 (0x20000000UL)
#define FLASH_BLOCK_30 (0x40000000UL)
#define FLASH_BLOCK_31 (0x80000000UL)
#define FLASH_BLOCK_Msk (0xFFFFFFFFUL)
#define FLASH_BLOCK_ALL FLASH_BLOCK_Msk
#define IS_FLASH_RWBLOCK(__BLOCK__) ((((__BLOCK__) & FLASH_BLOCK_Msk) != 0UL) &&\
(((__BLOCK__) & ~FLASH_BLOCK_Msk) == 0UL))
#define IS_FLASH_BLOCK(__BLOCK__) (((__BLOCK__) == FLASH_BLOCK_0) ||\
((__BLOCK__) == FLASH_BLOCK_1) ||\
((__BLOCK__) == FLASH_BLOCK_2) ||\
((__BLOCK__) == FLASH_BLOCK_3) ||\
((__BLOCK__) == FLASH_BLOCK_4) ||\
((__BLOCK__) == FLASH_BLOCK_5) ||\
((__BLOCK__) == FLASH_BLOCK_6) ||\
((__BLOCK__) == FLASH_BLOCK_7) ||\
((__BLOCK__) == FLASH_BLOCK_8) ||\
((__BLOCK__) == FLASH_BLOCK_9) ||\
((__BLOCK__) == FLASH_BLOCK_10) ||\
((__BLOCK__) == FLASH_BLOCK_11) ||\
((__BLOCK__) == FLASH_BLOCK_12) ||\
((__BLOCK__) == FLASH_BLOCK_13) ||\
((__BLOCK__) == FLASH_BLOCK_14) ||\
((__BLOCK__) == FLASH_BLOCK_15) ||\
((__BLOCK__) == FLASH_BLOCK_16) ||\
((__BLOCK__) == FLASH_BLOCK_17) ||\
((__BLOCK__) == FLASH_BLOCK_18) ||\
((__BLOCK__) == FLASH_BLOCK_19) ||\
((__BLOCK__) == FLASH_BLOCK_20) ||\
((__BLOCK__) == FLASH_BLOCK_21) ||\
((__BLOCK__) == FLASH_BLOCK_22) ||\
((__BLOCK__) == FLASH_BLOCK_23) ||\
((__BLOCK__) == FLASH_BLOCK_24) ||\
((__BLOCK__) == FLASH_BLOCK_25) ||\
((__BLOCK__) == FLASH_BLOCK_26) ||\
((__BLOCK__) == FLASH_BLOCK_27) ||\
((__BLOCK__) == FLASH_BLOCK_28) ||\
((__BLOCK__) == FLASH_BLOCK_29) ||\
((__BLOCK__) == FLASH_BLOCK_30) ||\
((__BLOCK__) == FLASH_BLOCK_31))
#define FLASH_READ (0)
#define FLASH_WRITE (1)
#define IS_FLASH_OPERATION(__OPERATION__) (((__OPERATION__) == FLASH_READ) ||\
((__OPERATION__) == FLASH_WRITE))
/************** Bits definition for FLASH_CTRL register ******************/
#define FLASH_CTRL_CSMODE_DISABLE (0x0U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000000 */
#define FLASH_CTRL_CSMODE_ALWAYSON (0x1U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000001 */
#define FLASH_CTRL_CSMODE_TIM2OV (0x2U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000002 */
#define FLASH_CTRL_CSMODE_RTC (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */
//CSMode
#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE
#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON
#define FLASH_CSMODE_TMR2OF FLASH_CTRL_CSMODE_TIM2OV
#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC
#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\
((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\
((__CSMODE__) == FLASH_CSMODE_TMR2OF) ||\
((__CSMODE__) == FLASH_CSMODE_RTC))
//INT
#define FLASH_INT_CS FLASH_CTRL_CSINTEN
#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS)
//WriteStatus
#define FLASH_WSTA_BUSY 0
#define FLASH_WRITE_FINISH 1
#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH
#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x80000UL)
#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x80000UL) &&\
(((__ADDRW__) & 0x3U) == 0U))
#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x80000UL) &&\
(((__ADDRHW__) & 0x1U) == 0U))
#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x80000) && ((__ADDRESS2__) < 0x80000) && ((__ADDRESS1__) < (__ADDRESS2__)))
/* Exported Functions ------------------------------------------------------- */
void FLASH_Init(uint32_t CSMode);
void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState);
void FLASH_CycleInit(void);
void FLASH_SectorErase(uint32_t SectorAddr);
void FLASH_ChipErase(void);
void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length);
void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length);
void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length);
void FLASH_SetReadProtection(uint32_t Block);
void FLASH_WriteProtection(uint32_t Block, uint32_t NewState);
void FLASH_ICEProtection(uint32_t NewState);
uint8_t FLASH_GetProtectionStatus(uint32_t Block, uint32_t Operation);
uint32_t FLASH_GetAllProtectionStatus(uint32_t Operation);
void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd);
void FLASH_SetCheckSumCompValue(uint32_t Checksum);
uint32_t FLASH_GetCheckSum(void);
uint8_t FLASH_GetINTStatus(uint32_t IntMask);
void FLASH_ClearINTStatus(uint32_t IntMask);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_FLASH_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_gpio.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief GPIO library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_GPIO_H
#define __LIB_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define GET_BITBAND_ADDR(addr, bitnum) ((((uint32_t)addr) & 0xF0000000) + \
0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2))
typedef struct
{
uint32_t GPIO_Pin;
uint32_t GPIO_Mode;
} GPIO_InitType;
typedef struct
{
__IO uint32_t DATBitBand[16];
} GPIO_DATInitType;
/**
* @brief Bit_State_enumeration
*/
typedef enum {
Bit_RESET = 0,
Bit_SET
} BitState;
#define GPIO_A ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40014018,0)))
#define GPIO_B ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000028,0)))
#define GPIO_C ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000048,0)))
#define GPIO_D ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000068,0)))
#define GPIO_E ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000088,0)))
#define GPIO_F ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x400000A8,0)))
#define IS_GPIO_DAT(__GPIODAT__) (((__GPIODAT__) == GPIO_A) ||\
((__GPIODAT__) == GPIO_B) ||\
((__GPIODAT__) == GPIO_C) ||\
((__GPIODAT__) == GPIO_D) ||\
((__GPIODAT__) == GPIO_E) ||\
((__GPIODAT__) == GPIO_F))
#define IS_GPIO_PINNUM(__PINNUM__) ((__PINNUM__) < 16U)
#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U))
//GPIO_Pin
#define GPIO_Pin_0 ((uint16_t)0x0001)
#define GPIO_Pin_1 ((uint16_t)0x0002)
#define GPIO_Pin_2 ((uint16_t)0x0004)
#define GPIO_Pin_3 ((uint16_t)0x0008)
#define GPIO_Pin_4 ((uint16_t)0x0010)
#define GPIO_Pin_5 ((uint16_t)0x0020)
#define GPIO_Pin_6 ((uint16_t)0x0040)
#define GPIO_Pin_7 ((uint16_t)0x0080)
#define GPIO_Pin_8 ((uint16_t)0x0100)
#define GPIO_Pin_9 ((uint16_t)0x0200)
#define GPIO_Pin_10 ((uint16_t)0x0400)
#define GPIO_Pin_11 ((uint16_t)0x0800)
#define GPIO_Pin_12 ((uint16_t)0x1000)
#define GPIO_Pin_13 ((uint16_t)0x2000)
#define GPIO_Pin_14 ((uint16_t)0x4000)
#define GPIO_Pin_15 ((uint16_t)0x8000)
#define GPIO_Pin_All ((uint16_t)0xFFFF)
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\
(((__PIN__) & ~GPIO_Pin_All) == 0UL))
#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\
((__PINR__) == GPIO_Pin_1) ||\
((__PINR__) == GPIO_Pin_2) ||\
((__PINR__) == GPIO_Pin_3) ||\
((__PINR__) == GPIO_Pin_4) ||\
((__PINR__) == GPIO_Pin_5) ||\
((__PINR__) == GPIO_Pin_6) ||\
((__PINR__) == GPIO_Pin_7) ||\
((__PINR__) == GPIO_Pin_8) ||\
((__PINR__) == GPIO_Pin_9) ||\
((__PINR__) == GPIO_Pin_10) ||\
((__PINR__) == GPIO_Pin_11) ||\
((__PINR__) == GPIO_Pin_12) ||\
((__PINR__) == GPIO_Pin_13) ||\
((__PINR__) == GPIO_Pin_14) ||\
((__PINR__) == GPIO_Pin_15))
//GPIO_Mode
#define GPIO_MODE_INPUT (0xCU)
#define GPIO_MODE_OUTPUT_CMOS (0x2U)
#define GPIO_MODE_OUTPUT_OD (0x3U)
#define GPIO_MODE_INOUT_OD (0xBU)
#define GPIO_MODE_INOUT_CMOS (0xAU)
#define GPIO_MODE_FORBIDDEN (0x4U)
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_CMOS) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_INOUT_OD) ||\
((__MODE__) == GPIO_MODE_INOUT_CMOS) ||\
((__MODE__) == GPIO_MODE_FORBIDDEN))
/************** Bits definition for IO_MISC register ******************/
#define IO_MISC_PLLHDIV_1 (0x0U << GPIOAF_IO_MISC_PLLHDIV_Pos)
#define IO_MISC_PLLHDIV_2 (0x1U << GPIOAF_IO_MISC_PLLHDIV_Pos)
#define IO_MISC_PLLHDIV_4 (0x2U << GPIOAF_IO_MISC_PLLHDIV_Pos)
#define IO_MISC_PLLHDIV_8 (0x3U << GPIOAF_IO_MISC_PLLHDIV_Pos)
#define IO_MISC_PLLHDIV_16 (0x4U << GPIOAF_IO_MISC_PLLHDIV_Pos)
//GPIO AF
#define GPIOB_AF_PLLHDIV GPIOAF_IOB_SEL_SEL1
#define GPIOB_AF_PLLLOUT GPIOAF_IOB_SEL_SEL2
#define GPIOB_AF_OSC GPIOAF_IOB_SEL_SEL6
#define GPIOE_AF_CMP1O GPIOAF_IOE_SEL_SEL7
#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\
((__GPIOAF__) == GPIOB_AF_OSC) ||\
((__GPIOAF__) == GPIOE_AF_CMP1O))
#define IS_GPIOB_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\
((__GPIOAF__) == GPIOB_AF_OSC))
#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O)
//PMUIO AF
#define PMUIO7_AF_PLLDIV GPIOA_SEL_SEL7
#define PMUIO6_AF_CMP2O GPIOA_SEL_SEL6
#define PMUIO3_AF_PLLDIV GPIOA_SEL_SEL3
#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO6_AF_CMP2O | PMUIO3_AF_PLLDIV)
//GPIO pin remap
#define GPIO_REMAP_I2C GPIOAF_IO_MISC_I2CIOC
#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
//PLLDIV
#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1
#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2
#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4
#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8
#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16
#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
((__PLLDIV__) == GPIO_PLLDIV_2) ||\
((__PLLDIV__) == GPIO_PLLDIV_4) ||\
((__PLLDIV__) == GPIO_PLLDIV_8) ||\
((__PLLDIV__) == GPIO_PLLDIV_16))
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF))
#define IS_PMUIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPIOA)
#define IS_GPIOAF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOE))
#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O)
#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\
(((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U))
#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
((__PLLDIV__) == GPIO_PLLDIV_2) ||\
((__PLLDIV__) == GPIO_PLLDIV_4) ||\
((__PLLDIV__) == GPIO_PLLDIV_8) ||\
((__PLLDIV__) == GPIO_PLLDIV_16))
/* Exported Functions ------------------------------------------------------- */
/* GPIO Exported Functions Group1:
Initialization and functions --------------*/
void GPIOBToF_Init(GPIO_Type *GPIOx, GPIO_InitType *InitStruct);
void GPIOA_Init(GPIOA_Type *GPIOx, GPIO_InitType *InitStruct);
/* GPIO Exported Functions Group2:
Read input data ---------------------------*/
uint8_t GPIOBToF_ReadInputDataBit(GPIO_Type *GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadInputDataBit(GPIOA_Type *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadInputData(GPIO_Type* GPIOx);
uint16_t GPIOA_ReadInputData(GPIOA_Type* GPIOx);
/* GPIO Exported Functions Group3:
Read output data --------------------------*/
uint8_t GPIOBToF_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadOutputDataBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadOutputData(GPIO_Type* GPIOx);
uint16_t GPIOA_ReadOutputData(GPIOA_Type* GPIOx);
/* GPIO Exported Functions Group4:
Write output data -------------------------*/
void GPIO_WriteBit(GPIO_DATInitType* DATx, uint8_t PinNum, uint8_t val);
void GPIOBToF_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOA_WriteBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOBToF_Write(GPIO_Type* GPIOx, uint16_t val);
void GPIOA_Write(GPIOA_Type* GPIOx, uint16_t val);
/* GPIO Exported Functions Group5:
IO AF configure ---------------------------*/
void GPIOBToF_AFConfig(GPIO_Type* GPIOx, uint32_t GPIO_AFx, uint8_t NewState);
void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState);
/* GPIO Exported Functions Group6:
IO Remap configure ------------------------*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState);
/* GPIO Exported Functions Group7:
Others ------------------------------------*/
void GPIO_PLLDIVConfig(uint32_t Divider);
void GPIOA_DeGlitchCmd( uint16_t GPIO_Pin, uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_GPIO_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_i2c.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief IIC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_I2C_H
#define __LIB_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SlaveAddr;
uint32_t GeneralCallAck;
uint32_t AssertAcknowledge;
uint32_t ClockSource;
} I2C_InitType;
/************** Bits definition for I2C_CTRL register ******************/
#define I2C_CTRL_CR_0 (0x0U << I2C_CTRL_CR0_Pos) /*!< 0x0000000 */
#define I2C_CTRL_CR_1 (0x1U << I2C_CTRL_CR0_Pos) /*!< 0x0000001 */
#define I2C_CTRL_CR_2 (0x2U << I2C_CTRL_CR0_Pos) /*!< 0x0000002 */
#define I2C_CTRL_CR_3 (0x3U << I2C_CTRL_CR0_Pos) /*!< 0x0000003 */
#define I2C_CTRL_CR_4 (0x80U << I2C_CTRL_CR0_Pos) /*!< 0x0000080 */
#define I2C_CTRL_CR_5 (0x81U << I2C_CTRL_CR0_Pos) /*!< 0x0000081 */
#define I2C_CTRL_CR_6 (0x82U << I2C_CTRL_CR0_Pos) /*!< 0x0000082 */
#define I2C_CTRL_CR_7 (0x83U << I2C_CTRL_CR0_Pos) /*!< 0x0000083 */
/************** Bits definition for I2C_STS register ******************/
#define I2C_STS_STS_0x00 (0x0U << I2C_STS_STS_Pos) /*!< 0x0000000 */
#define I2C_STS_STS_0x08 (0x1U << I2C_STS_STS_Pos) /*!< 0x0000008 */
#define I2C_STS_STS_0x10 (0x2U << I2C_STS_STS_Pos) /*!< 0x0000010 */
#define I2C_STS_STS_0x18 (0x3U << I2C_STS_STS_Pos) /*!< 0x0000018 */
#define I2C_STS_STS_0x20 (0x4U << I2C_STS_STS_Pos) /*!< 0x0000020 */
#define I2C_STS_STS_0x28 (0x5U << I2C_STS_STS_Pos) /*!< 0x0000028 */
#define I2C_STS_STS_0x30 (0x6U << I2C_STS_STS_Pos) /*!< 0x0000030 */
#define I2C_STS_STS_0x38 (0x7U << I2C_STS_STS_Pos) /*!< 0x0000038 */
#define I2C_STS_STS_0x40 (0x8U << I2C_STS_STS_Pos) /*!< 0x0000040 */
#define I2C_STS_STS_0x48 (0x9U << I2C_STS_STS_Pos) /*!< 0x0000048 */
#define I2C_STS_STS_0x50 (0xAU << I2C_STS_STS_Pos) /*!< 0x0000050 */
#define I2C_STS_STS_0x58 (0xBU << I2C_STS_STS_Pos) /*!< 0x0000058 */
#define I2C_STS_STS_0x60 (0xCU << I2C_STS_STS_Pos) /*!< 0x0000060 */
#define I2C_STS_STS_0x68 (0xDU << I2C_STS_STS_Pos) /*!< 0x0000068 */
#define I2C_STS_STS_0x70 (0xEU << I2C_STS_STS_Pos) /*!< 0x0000070 */
#define I2C_STS_STS_0x78 (0xFU << I2C_STS_STS_Pos) /*!< 0x0000078 */
#define I2C_STS_STS_0x80 (0x10U << I2C_STS_STS_Pos) /*!< 0x0000080 */
#define I2C_STS_STS_0x88 (0x11U << I2C_STS_STS_Pos) /*!< 0x0000088 */
#define I2C_STS_STS_0x90 (0x12U << I2C_STS_STS_Pos) /*!< 0x0000090 */
#define I2C_STS_STS_0x98 (0x13U << I2C_STS_STS_Pos) /*!< 0x0000098 */
#define I2C_STS_STS_0xA0 (0x14U << I2C_STS_STS_Pos) /*!< 0x00000A0 */
#define I2C_STS_STS_0xA8 (0x15U << I2C_STS_STS_Pos) /*!< 0x00000A8 */
#define I2C_STS_STS_0xB0 (0x16U << I2C_STS_STS_Pos) /*!< 0x00000B0 */
#define I2C_STS_STS_0xB8 (0x17U << I2C_STS_STS_Pos) /*!< 0x00000B8 */
#define I2C_STS_STS_0xC0 (0x18U << I2C_STS_STS_Pos) /*!< 0x00000C0 */
#define I2C_STS_STS_0xC8 (0x19U << I2C_STS_STS_Pos) /*!< 0x00000C8 */
#define I2C_STS_STS_0xF8 (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */
//GeneralCallAck
#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC
#define I2C_GENERALCALLACK_DISABLE 0
//AssertAcknowledge
#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA
#define I2C_ASSERTACKNOWLEDGE_DISABLE 0
//ClockSource
#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0
#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1
#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2
#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3
#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4
#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5
#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6
#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7
#define I2C_CTRL_CR (0x83)
typedef struct
{
uint16_t SlaveAddr;
uint8_t SubAddrType;
uint32_t PageRange;
uint32_t SubAddress;
uint8_t *pBuffer;
uint32_t Length;
} I2C_WRType;
//SubAddrType
#define I2C_SUBADDR_1BYTE (1)
#define I2C_SUBADDR_2BYTE (2)
#define I2C_SUBADDR_OTHER (3)
//remap
#define I2C_REMAP_ENABLE (1)
#define I2C_REMAP_DISABLE (0)
/* Private macros ------------------------------------------------------------*/
#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\
((__GC__) == I2C_GENERALCALLACK_DISABLE))
#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\
((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE))
#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8))
#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\
((__TYPE__) == I2C_SUBADDR_2BYTE) ||\
((__TYPE__) == I2C_SUBADDR_OTHER))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C)
/* Exported Functions ------------------------------------------------------- */
/* I2C Exported Functions Group1:
(De)Initialization ------------------------*/
void I2C_DeInit(uint32_t remap);
void I2C_StructInit(I2C_InitType *InitStruct);
void I2C_Init(I2C_InitType *InitStruct);
/* I2C Exported Functions Group2:
Interrupt ---------------------------------*/
void I2C_INTConfig(uint32_t NewState);
uint8_t I2C_GetINTStatus(void);
void I2C_ClearINTStatus(void);
/* I2C Exported Functions Group3:
Transfer datas ----------------------------*/
uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct);
uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct);
/* I2C Exported Functions Group4:
MISC Configuration ------------------------*/
void I2C_Cmd(uint32_t NewState);
/* I2C Exported Functions Group5:
Others ------------------------------------*/
void I2C_AssertAcknowledgeConfig(uint32_t NewState);
uint8_t I2C_ReceiveData(void);
void I2C_SendData(uint8_t Dat);
void I2C_GenerateSTART(uint32_t NewState);
void I2C_GenerateSTOP(uint32_t NewState);
uint8_t I2C_GetStatusCode(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_I2C_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_iso7816.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief ISO7816 library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ISO7816_H
#define __LIB_ISO7816_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t FirstBit;
uint32_t Parity;
uint32_t Baudrate;
uint32_t TXRetry;
uint32_t RXACKLength;
uint32_t TXNACKLength;
} ISO7816_InitType;
//FirstBit
#define ISO7816_FIRSTBIT_MSB (0UL)
#define ISO7816_FIRSTBIT_LSB ISO7816_CFG_LSB
#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB) ||\
((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB))
//Parity
#define ISO7816_PARITY_EVEN (0UL)
#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP
#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) ||\
((__PARITY__) == ISO7816_PARITY_ODD))
//Baudrate
#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((200UL <= (__BAUDRATE__)) &&\
((__BAUDRATE__) <= 2625000UL))
//TXRetry
#define ISO7816_TXRTY_0 ((0x00U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_1 ((0x01U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_2 ((0x02U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_3 ((0x03U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_4 ((0x04U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_5 ((0x05U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_6 ((0x06U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_7 ((0x07U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_8 ((0x08U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_9 ((0x09U << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_10 ((0x0AU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_11 ((0x0BU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_12 ((0x0CU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_13 ((0x0DU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_14 ((0x0EU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define ISO7816_TXRTY_15 ((0x0FU << ISO7816_CFG_TXRTYCNT_Pos) \
| (1U << 10))
#define IS_ISO7816_TXRTY(__TXRTY__) (((__TXRTY__) == ISO7816_TXRTY_0) || \
((__TXRTY__) == ISO7816_TXRTY_1) || \
((__TXRTY__) == ISO7816_TXRTY_2) || \
((__TXRTY__) == ISO7816_TXRTY_3) || \
((__TXRTY__) == ISO7816_TXRTY_4) || \
((__TXRTY__) == ISO7816_TXRTY_5) || \
((__TXRTY__) == ISO7816_TXRTY_6) || \
((__TXRTY__) == ISO7816_TXRTY_7) || \
((__TXRTY__) == ISO7816_TXRTY_8) || \
((__TXRTY__) == ISO7816_TXRTY_9) || \
((__TXRTY__) == ISO7816_TXRTY_10) || \
((__TXRTY__) == ISO7816_TXRTY_11) || \
((__TXRTY__) == ISO7816_TXRTY_12) || \
((__TXRTY__) == ISO7816_TXRTY_13) || \
((__TXRTY__) == ISO7816_TXRTY_14) || \
((__TXRTY__) == ISO7816_TXRTY_15))
//RXACKLength
#define ISO7816_RXACKLEN_2 (0UL)
#define ISO7816_RXACKLEN_1 (ISO7816_CFG_RXACKSET)
#define IS_ISO7816_RXACKLEN(__RXACKLEN__) (((__RXACKLEN__) == ISO7816_RXACKLEN_2) ||\
((__RXACKLEN__) == ISO7816_RXACKLEN_1))
//TXNACKLength
#define ISO7816_TXNACKLEN_0 (0UL)
#define ISO7816_TXNACKLEN_1 (ISO7816_CFG_AUTORXACK)
#define ISO7816_TXNACKLEN_2 (ISO7816_CFG_AUTORXACK | ISO7816_CFG_ACKLEN)
#define IS_ISO7816_TXNACKLEN(__TXNACKLEN__) (((__TXNACKLEN__) == ISO7816_TXNACKLEN_0) ||\
((__TXNACKLEN__) == ISO7816_TXNACKLEN_1) ||\
((__TXNACKLEN__) == ISO7816_TXNACKLEN_2))
#define IS_ISO7816_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x80)
//interrupt
#define ISO7816_INT_TXRTYERR ISO7816_CFG_TXRTYERRIE
#define ISO7816_INT_RXOV ISO7816_CFG_RXOVIE
#define ISO7816_INT_TXDONE ISO7816_CFG_TXDONEIE
#define ISO7816_INT_RX ISO7816_CFG_RXIE
#define ISO7816_INT_RXERR ISO7816_CFG_RXERRIE
#define ISO7816_INT_Msk (ISO7816_INT_TXRTYERR \
|ISO7816_INT_RXOV \
|ISO7816_INT_TXDONE \
|ISO7816_INT_RX \
|ISO7816_INT_RXERR)
#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\
(((__INT__) & ~ISO7816_INT_Msk) == 0U))
//INTStatus
#define ISO7816_INTSTS_TXRTYERR ISO7816_INFO_TXRTYERRIF
#define ISO7816_INTSTS_RXOV ISO7816_INFO_RXOVIF
#define ISO7816_INTSTS_TXDONE ISO7816_INFO_TXDONEIF
#define ISO7816_INTSTS_RX ISO7816_INFO_RXIF
#define ISO7816_INTSTS_RXERR ISO7816_INFO_RXERRIF
#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_TXRTYERR \
|ISO7816_INTSTS_RXOV \
|ISO7816_INTSTS_TXDONE \
|ISO7816_INTSTS_RX \
|ISO7816_INTSTS_RXERR)
#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_TXRTYERR) ||\
((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\
((__INTFLAG__) == ISO7816_INTSTS_TXDONE) ||\
((__INTFLAG__) == ISO7816_INTSTS_RX) ||\
((__INTFLAG__) == ISO7816_INTSTS_RXERR))
#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\
(((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U))
//status
#define ISO7816_FLAG_DMATXDONE ISO7816_INFO_DMATXDONE
#define IS_ISO7816_FLAGR(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE)
#define IS_ISO7816_FLAGC(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE)
/****************************** ISO7816 Instances *****************************/
#define IS_ISO7816_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ISO78160) || \
((INSTANCE) == ISO78161))
/* Exported Functions ------------------------------------------------------- */
void ISO7816_DeInit(ISO7816_Type *ISO7816x);
void ISO7816_StructInit(ISO7816_InitType *InitStruct);
void ISO7816_Init(ISO7816_Type *ISO7816x, ISO7816_InitType *Init_Struct);
void ISO7816_Cmd(ISO7816_Type *ISO7816x, uint32_t NewState);
void ISO7816_BaudrateConfig(ISO7816_Type *ISO7816x, uint32_t BaudRate);
void ISO7816_CLKDIVConfig(ISO7816_Type *ISO7816x, uint32_t Prescaler);
void ISO7816_CLKOutputCmd(ISO7816_Type *ISO7816x, uint32_t NewState);
void ISO7816_SendData(ISO7816_Type *ISO7816x, uint8_t ch);
uint8_t ISO7816_ReceiveData(ISO7816_Type *ISO7816x);
void ISO7816_INTConfig(ISO7816_Type *ISO7816x, uint32_t INTMask, uint8_t NewState);
uint8_t ISO7816_GetINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask);
void ISO7816_ClearINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask);
uint8_t ISO7816_GetFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask);
void ISO7816_ClearFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask);
uint8_t ISO7816_GetLastTransmitACK(ISO7816_Type *ISO7816x);
uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_Type *ISO7816x);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ISO7816_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_lcd.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief LCD library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LCD_H
#define __LIB_LCD_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* LCD COMx IO typedef */
typedef struct
{
__IO uint32_t *GPIO;
uint16_t Pin;
}LCD_COMIO;
typedef struct
{
uint32_t Type;
uint32_t Drv;
uint32_t FRQ;
uint32_t SWPR;
uint32_t FBMODE;
uint32_t BKFILL;
} LCD_InitType;
typedef struct
{
uint32_t SegCtrl0;
uint32_t SegCtrl1;
uint16_t SegCtrl2;
uint32_t COMMode;
} LCD_IOInitType;
/************** Bits definition for ANA_REG6 register ******************/
#define ANA_REG6_VLCD_0 (0x0U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_1 (0x1U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_2 (0x2U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_3 (0x3U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_4 (0x4U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_5 (0x5U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_6 (0x6U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_7 (0x7U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_8 (0x8U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_9 (0x9U << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_A (0xAU << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_B (0xBU << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_C (0xCU << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_D (0xDU << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_E (0xEU << ANA_REG6_VLCD_Pos)
#define ANA_REG6_VLCD_F (0xFU << ANA_REG6_VLCD_Pos)
/************** Bits definition for LCD_CTRL register ******************/
/************** Bits definition for LCD_CTRL2 register ******************/
//Type
#define LCD_TYPE_4COM (0x0U << LCD_CTRL_TYPE_Pos) /*!< 0x00000000 */
#define LCD_TYPE_6COM (0x1U << LCD_CTRL_TYPE_Pos) /*!< 0x00000010 */
#define LCD_TYPE_8COM (0x2U << LCD_CTRL_TYPE_Pos) /*!< 0x00000020 */
#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\
((__TYPE__) == LCD_TYPE_6COM) ||\
((__TYPE__) == LCD_TYPE_8COM))
//DrivingRes
#define LCD_DRV_300 (0x0U << LCD_CTRL_DRV_Pos) /*!< 0x00000000 */
#define LCD_DRV_600 (0x1U << LCD_CTRL_DRV_Pos) /*!< 0x00000004 */
#define LCD_DRV_150 (0x2U << LCD_CTRL_DRV_Pos) /*!< 0x00000008 */
#define LCD_DRV_200 (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */
#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\
((__DRV__) == LCD_DRV_600) ||\
((__DRV__) == LCD_DRV_150) ||\
((__DRV__) == LCD_DRV_200))
//ScanFRQ
#define LCD_FRQ_64H (0x0U << LCD_CTRL_FRQ_Pos) /*!< 0x00000000 */
#define LCD_FRQ_128H (0x1U << LCD_CTRL_FRQ_Pos) /*!< 0x00000001 */
#define LCD_FRQ_256H (0x2U << LCD_CTRL_FRQ_Pos) /*!< 0x00000002 */
#define LCD_FRQ_512H (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */
#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\
((__FRQ__) == LCD_FRQ_128H) ||\
((__FRQ__) == LCD_FRQ_256H) ||\
((__FRQ__) == LCD_FRQ_512H))
#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL)
//SwitchMode
#define LCD_FBMODE_BUFA (0x0U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000000 */
#define LCD_FBMODE_BUFAB (0x1U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000040 */
#define LCD_FBMODE_BUFABLANK (0x2U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000080 */
#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\
((__FBMODE__) == LCD_FBMODE_BUFAB) ||\
((__FBMODE__) == LCD_FBMODE_BUFABLANK))
//BlankFill
#define LCD_BKFILL_1 LCD_CTRL2_BKFILL
#define LCD_BKFILL_0 0
#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0))
//ComMode
#define LCD_COMMOD_4COM 1
#define LCD_COMMOD_6COM 3
#define LCD_COMMOD_8COM 7
#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\
((__COMMOD__) == LCD_COMMOD_6COM) ||\
((__COMMOD__) == LCD_COMMOD_8COM))
//BiasSelection
#define LCD_BMODE_DIV3 0
#define LCD_BMODE_DIV4 ANA_REG6_LCDBMODE
#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\
((__BMODE__) == LCD_BMODE_DIV4))
/****************************** LCD Instances *********************************/
#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
/* Exported Functions ------------------------------------------------------- */
/* LCD Exported Functions Group1:
(De)Initialization -------------------------*/
void LCD_DeInit(void);
void LCD_StructInit(LCD_InitType *LCD_InitStruct);
void LCD_Init(LCD_InitType *InitStruct);
/* LCD Exported Functions Group1:
MISC Configuration -------------------------*/
void LCD_Cmd(LCD_IOInitType *IOInitType, uint32_t NewState);
void LCD_BiasModeConfig(uint32_t BiasSelection);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LCD_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_misc.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief MISC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_MISC_H
#define __LIB_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//FlagMask
#define MISC_FLAG_LOCKUP MISC1_SRAMINT_LOCKUP
#define MISC_FLAG_PIAC MISC1_SRAMINT_PIAC
#define MISC_FLAG_HIAC MISC1_SRAMINT_HIAC
#define MISC_FLAG_PERR MISC1_SRAMINT_PERR
#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR)
//MISC interrupt
#define MISC_INT_LOCK MISC1_SRAMINIT_LOCKIE
#define MISC_INT_PIAC MISC1_SRAMINIT_PIACIE
#define MISC_INT_HIAC MISC1_SRAMINIT_HIACIE
#define MISC_INT_PERR MISC1_SRAMINIT_PERRIE
#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR)
//IR
#define MISC_IREN_TX0 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_TX1 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_TX2 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_TX3 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_TX4 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_TX5 (0x1U << MISC1_IREN_IREN_Pos)
#define MISC_IREN_Msk (0x3FUL)
/* Private macros ------------------------------------------------------------*/
#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\
((__FLAGR__) == MISC_FLAG_PIAC) ||\
((__FLAGR__) == MISC_FLAG_HIAC) ||\
((__FLAGR__) == MISC_FLAG_PERR))
#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\
(((__FLAGC__) & ~MISC_FLAG_Msk) == 0U))
#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\
(((__INT__) &~MISC_INT_Msk) == 0U))
#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\
(((__IREN__) & ~MISC_IREN_Msk) == 0U))
/****************************** MISC Instances ********************************/
#define IS_MISC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC1)
#define IS_MISC2_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC2)
/* Exported Functions ------------------------------------------------------- */
uint8_t MISC_GetFlag(uint32_t FlagMask);
void MISC_ClearFlag(uint32_t FlagMask);
void MISC_INTConfig(uint32_t INTMask, uint32_t NewState);
void MISC_SRAMParityCmd(uint32_t NewState);
uint32_t MISC_GetSRAMPEAddr(void);
uint32_t MISC_GetAPBErrAddr(void);
uint32_t MISC_GetAHBErrAddr(void);
void MISC_IRCmd(uint32_t IRx, uint32_t NewState);
void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow);
void MISC_HardFaultCmd(uint32_t NewState);
void MISC_LockResetCmd(uint32_t NewState);
void MISC_IRQLATConfig(uint8_t Latency);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_MISC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pmu.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief PMU library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PMU_H
#define __LIB_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/**
* Deep-sleep low-power configuration
*/
typedef struct
{
uint32_t COMP1Power; /* Comparator 1 power control */
uint32_t COMP2Power; /* Comparator 2 power control */
uint32_t TADCPower; /* Tiny ADC power control */
uint32_t BGPPower; /* BGP power control */
uint32_t AVCCPower; /* AVCC power control */
// uint32_t LCDPower; /* LCD controller power control */
uint32_t VDCINDetector; /* VDCIN detector control */
uint32_t VDDDetector; /* VDD detector control */
uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */
uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */
} PMU_LowPWRTypeDef;
/************** Bits definition for ANA_REG8 register ******************/
#define ANA_REG8_VDDPVDSEL_0 (0x0UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_1 (0x1UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_2 (0x2UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_3 (0x3UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_4 (0x4UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_5 (0x5UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_6 (0x6UL << ANA_REG8_VDDPVDSEL_Pos)
#define ANA_REG8_VDDPVDSEL_7 (0x7UL << ANA_REG8_VDDPVDSEL_Pos)
/****************************** PMU Instances *********************************/
#define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU)
/****************************** PMU_RETRAM Instances **************************/
#define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM)
/* COMP1Power */
#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN)
#define PMU_COMP1PWR_OFF (0UL)
#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\
((__COMP1PWR__) == PMU_COMP1PWR_OFF))
/* COMP2Power */
#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN)
#define PMU_COMP2PWR_OFF (0UL)
#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\
((__COMP2PWR__) == PMU_COMP2PWR_OFF))
/* TADCPower */
#define PMU_TADCPWR_ON (ANA_REGF_ADTPDN)
#define PMU_TADCPWR_OFF (0UL)
#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\
((__TADCPWR__) == PMU_TADCPWR_OFF))
/* BGPPower */
#define PMU_BGPPWR_ON (0UL)
#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD)
#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\
((__BGPPWR__) == PMU_BGPPWR_OFF))
/* AVCCPower */
#define PMU_AVCCPWR_ON (0UL)
#define PMU_AVCCPWR_OFF (ANA_REG8_AVCCLDOPD)
#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\
((__AVCCPWR__) == PMU_AVCCPWR_OFF))
/* VDCINDetector */
#define PMU_VDCINDET_ENABLE (0UL)
#define PMU_VDCINDET_DISABLE (ANA_REGA_VDCINDETPD)
#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\
((__VDCINDET__) == PMU_VDCINDET_DISABLE))
/* VDDDetector */
#define PMU_VDDDET_ENABLE (0UL)
#define PMU_VDDDET_DISABLE (ANA_REG9_VDDDETPD)
#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\
((__VDDDET__) == PMU_VDDDET_DISABLE))
#define PMU_APB_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160 \
|MISC2_PCLKEN_ISO78161 \
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC1 \
|MISC2_PCLKEN_MISC2 \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2 \
|MISC2_PCLKEN_SPI3)
#define PMU_APB_DMA MISC2_PCLKEN_DMA
#define PMU_APB_I2C MISC2_PCLKEN_I2C
#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1
#define PMU_APB_UART0 MISC2_PCLKEN_UART0
#define PMU_APB_UART1 MISC2_PCLKEN_UART1
#define PMU_APB_UART2 MISC2_PCLKEN_UART2
#define PMU_APB_UART3 MISC2_PCLKEN_UART3
#define PMU_APB_UART4 MISC2_PCLKEN_UART4
#define PMU_APB_UART5 MISC2_PCLKEN_UART5
#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160
#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161
#define PMU_APB_TIMER MISC2_PCLKEN_TIMER
#define PMU_APB_MISC1 MISC2_PCLKEN_MISC1
#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0
#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1
#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2
#define PMU_APB_SPI3 MISC2_PCLKEN_SPI3
#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_CRYPT)
// |MISC2_HCLKEN_LCD
#define PMU_AHB_DMA MISC2_HCLKEN_DMA
#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO
//#define PMU_AHB_LCD MISC2_HCLKEN_LCD
#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT
//PMU interrupt
#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN
#define PMU_INT_32K PMU_CONTROL_INT_32K_EN
#define PMU_INT_6M PMU_CONTROL_INT_6M_EN
#define PMU_INT_Msk (PMU_INT_IOAEN \
|PMU_INT_32K \
|PMU_INT_6M)
#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0UL) &&\
(((__INT__)&(~PMU_INT_Msk)) == 0UL))
//INTStatus
#define PMU_INTSTS_32K PMU_STS_INT_32K
#define PMU_INTSTS_6M PMU_STS_INT_6M
#define PMU_INTSTS_Msk (PMU_INTSTS_32K \
|PMU_INTSTS_6M)
#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\
((__INTFLAG__) == PMU_INTSTS_6M))
#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0UL) &&\
(((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0UL))
/***** Reset Source Status *****/
#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST
#define PMU_RSTSRC_PORST PMU_STS_PORST
#define PMU_RSTSRC_DPORST PMU_STS_DPORST
#define PMU_RSTSRC_WDTRST PMU_STS_WDTRST
#define PMU_RSTSRC_SFTRST PMU_STS_SFTRST
#define PMU_RSTSRC_MODERST PMU_STS_MODERST
#define PMU_RSTSRC_Msk (PMU_RSTSRC_EXTRST |\
PMU_RSTSRC_PORST |\
PMU_RSTSRC_DPORST |\
PMU_RSTSRC_WDTRST |\
PMU_RSTSRC_SFTRST |\
PMU_RSTSRC_MODERST)
#define PMU_RSTSRC_ALL PMU_RSTSRC_Msk
#define PMU_RESETSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\
((__RSTSRC__) == PMU_RSTSRC_PORST) ||\
((__RSTSRC__) == PMU_RSTSRC_DPORST) ||\
((__RSTSRC__) == PMU_RSTSRC_WDTRST) ||\
((__RSTSRC__) == PMU_RSTSRC_SFTRST) ||\
((__RSTSRC__) == PMU_RSTSRC_MODERST))
#define PMU_RESETSRC_CLR(__RSTSRC__) ((((__RSTSRC__) & PMU_RSTSRC_Msk) != 0UL) &&\
(((__RSTSRC__) & (~PMU_RSTSRC_Msk)) == 0UL))
/***** DeepSleep wakeup Source Status *****/
#define PMU_DSLEEPWKUSRC_MODE PMU_STS_WKUMODE
#define PMU_DSLEEPWKUSRC_XTAL PMU_STS_WKUXTAL
#define PMU_DSLEEPWKUSRC_U32K PMU_STS_WKUU32K
#define PMU_DSLEEPWKUSRC_ANA PMU_STS_WKUANA
#define PMU_DSLEEPWKUSRC_RTC PMU_STS_WKURTC
#define PMU_DSLEEPWKUSRC_IOA PMU_STS_WKUIOA
#define PMU_DSLEEPWKUSRC_Msk (PMU_DSLEEPWKUSRC_MODE |\
PMU_DSLEEPWKUSRC_XTAL |\
PMU_DSLEEPWKUSRC_U32K |\
PMU_DSLEEPWKUSRC_ANA |\
PMU_DSLEEPWKUSRC_RTC |\
PMU_DSLEEPWKUSRC_IOA)
#define IS_PMU_DSLEEPWKUSRC(__SRC__) (((__SRC__) == PMU_DSLEEPWKUSRC_MODE) ||\
((__SRC__) == PMU_DSLEEPWKUSRC_XTAL) ||\
((__SRC__) == PMU_DSLEEPWKUSRC_U32K) ||\
((__SRC__) == PMU_DSLEEPWKUSRC_ANA) ||\
((__SRC__) == PMU_DSLEEPWKUSRC_RTC) ||\
((__SRC__) == PMU_DSLEEPWKUSRC_IOA))
//Status
#define PMU_STS_32K PMU_STS_EXIST_32K
#define PMU_STS_6M PMU_STS_EXIST_6M
#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M))
//Wakeup_Event
#define IOA_DISABLE (0UL)
#define IOA_RISING (1UL)
#define IOA_FALLING (2UL)
#define IOA_HIGH (3UL)
#define IOA_LOW (4UL)
#define IOA_EDGEBOTH (5UL)
#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\
((__WAKEUP__) == IOA_RISING) ||\
((__WAKEUP__) == IOA_FALLING) ||\
((__WAKEUP__) == IOA_HIGH) ||\
((__WAKEUP__) == IOA_LOW) ||\
((__WAKEUP__) == IOA_EDGEBOTH))
/***** Wakeup_Event (PMU_SleepWKUSRCConfig_RTC) *****/
#define PMU_RTCEVT_ALARM RTC_INTSTS_INTSTS10
#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6
#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5
#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4
#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3
#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2
#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1
#define PMU_RTCEVT_ITVSITV RTC_INTSTS_INTSTS0
#define PMU_RTCEVT_Msk (PMU_RTCEVT_WKUCNT \
|PMU_RTCEVT_MIDNIGHT \
|PMU_RTCEVT_WKUHOUR \
|PMU_RTCEVT_WKUMIN \
|PMU_RTCEVT_WKUSEC \
|PMU_RTCEVT_TIMEILLE \
|PMU_RTCEVT_ITVSITV \
|PMU_RTCEVT_ALARM)
#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0UL) &&\
(((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0UL))
/***** BATRTCDisc (PMU_BATDischargeConfig) *****/
#define PMU_BAT1 ANA_REG6_BAT1DISC
#define PMU_BATRTC ANA_REG6_BATRTCDISC
#define IS_PMU_BATRTCDISC(__BATRTCDISC__) (((__BATRTCDISC__) == PMU_BAT1) || ((__BATRTCDISC__) == PMU_BATRTC))
/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/
#define PMU_VDDALARM_4_5V ANA_REG8_VDDPVDSEL_0
#define PMU_VDDALARM_4_2V ANA_REG8_VDDPVDSEL_1
#define PMU_VDDALARM_3_9V ANA_REG8_VDDPVDSEL_2
#define PMU_VDDALARM_3_6V ANA_REG8_VDDPVDSEL_3
#define PMU_VDDALARM_3_2V ANA_REG8_VDDPVDSEL_4
#define PMU_VDDALARM_2_9V ANA_REG8_VDDPVDSEL_5
#define PMU_VDDALARM_2_6V ANA_REG8_VDDPVDSEL_6
#define PMU_VDDALARM_2_3V ANA_REG8_VDDPVDSEL_7
#define IS_PMU_VDDALARM_THR(__VDDALARM__) (((__VDDALARM__) == PMU_VDDALARM_4_5V) ||\
((__VDDALARM__) == PMU_VDDALARM_4_2V) ||\
((__VDDALARM__) == PMU_VDDALARM_3_9V) ||\
((__VDDALARM__) == PMU_VDDALARM_3_6V) ||\
((__VDDALARM__) == PMU_VDDALARM_3_2V) ||\
((__VDDALARM__) == PMU_VDDALARM_2_9V) ||\
((__VDDALARM__) == PMU_VDDALARM_2_6V) ||\
((__VDDALARM__) == PMU_VDDALARM_2_3V))
/***** RTCLDOSel (PMU_RTCLDOConfig) *****/
#define PMU_RTCLDO_1_5 (0UL)
#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL
/***** StatusMask (PMU_GetPowerStatus) *****/
#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV
#define PMU_PWRSTS_VDCINDROP ANA_CMPOUT_VDCINDROP
#define PMU_PWRSTS_VDDALARM ANA_CMPOUT_VDDALARM
/***** PMU_PDNDSleepConfig *****/
//VDCIN_PDNS
#define PMU_VDCINPDNS_0 (0UL)
#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS)
#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\
((__VDCINPDNS__) == PMU_VDCINPDNS_1))
//VDD_PDNS
#define PMU_VDDPDNS_0 (0UL)
#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2)
#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\
((__VDDPDNS__) == PMU_VDDPDNS_1))
#define PMU_VDDALARM_CHKFRE_NOCHECK (0x0UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos)
#define PMU_VDDALARM_CHKFRE_30US (0x1UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos)
#define IS_PMU_VDDALARM_CHKFRE(__CHKFRE__) (((__CHKFRE__) == PMU_VDDALARM_CHKFRE_NOCHECK) ||\
((__CHKFRE__) == PMU_VDDALARM_CHKFRE_30US))
#define IS_PMU_PWR_DEBSEL(__DEBSEL__) ((__DEBSEL__) < 256UL)
/* Exported Functions ------------------------------------------------------- */
uint32_t PMU_EnterDSleepMode(void);
void PMU_EnterIdleMode(void);
uint32_t PMU_EnterSleepMode(void);
void PMU_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t PMU_GetINTStatus(uint32_t INTMask);
void PMU_ClearINTStatus(uint32_t INTMask);
uint8_t PMU_GetCrystalStatus(uint32_t Mask);
uint16_t PMU_GetIOAAllINTStatus(void);
uint8_t PMU_GetIOAINTStatus(uint16_t INTMask);
void PMU_ClearIOAINTStatus(uint16_t INTMask);
void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event);
uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
#ifndef __GNUC__
void PMU_EnterIdle_LowPower(void);
#endif
void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority);
void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority);
void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event);
void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event);
void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS);
/***** BGP functions *****/
void PMU_BGPCmd(uint32_t NewState);
/***** VDD functions *****/
void PMU_VDDAlarmConfig(uint32_t CheckTHR, uint32_t CheckFrequency);
uint8_t PMU_GetVDDAlarmStatus(void);
/***** AVCC functions *****/
void PMU_AVCCCmd(uint32_t NewState);
void PMU_AVCCOutputCmd(uint32_t NewState);
void PMU_AVCCLVDetectorCmd(uint32_t NewState);
uint8_t PMU_GetAVCCLVStatus(void);
/***** VDCIN functions *****/
void PMU_VDCINDetectorCmd(uint32_t NewState);
uint8_t PMU_GetVDCINDropStatus(void);
void PMU_PWRDEBSel(uint32_t DEBSel);
/***** BAT functions *****/
void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState);
/***** Other functions *****/
uint8_t PMU_GetModeStatus(void);
uint8_t PMU_GetPowerStatus(uint32_t StatusMask);
uint8_t PMU_GetResetSource(uint32_t Mask);
void PMU_ClearResetSource(uint32_t Mask);
uint32_t PMU_GetAllResetSource(void);
uint8_t PMU_GetDSleepWKUSource(uint32_t Mask);
uint32_t PMU_GetAllDSleepWKUSource(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PMU_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pwm.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief PWM library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PWM_H
#define __LIB_PWM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t ClockDivision;
uint32_t Mode;
uint32_t ClockSource;
} PWM_BaseInitType;
/************** Bits definition for PWMx_CTL register ******************/
#define PWM_CTL_TESL_APBDIV128 (0x0U << PWM_CTL_TSEL_Pos) /*!< 0x00000000 */
#define PWM_CTL_TESL_APBDIV1 (0x1U << PWM_CTL_TSEL_Pos) /*!< 0x00000008 */
#define PWM_CTL_MC_STOP (0x0U << PWM_CTL_MC_Pos) /*!< 0x00000000 */
#define PWM_CTL_MC_UP (0x1U << PWM_CTL_MC_Pos) /*!< 0x00000010 */
#define PWM_CTL_MC_CONTINUE (0x2U << PWM_CTL_MC_Pos) /*!< 0x00000020 */
#define PWM_CTL_MC_UPDOWN (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */
#define PWM_CTL_ID_DIV2 (0x0U << PWM_CTL_ID_Pos) /*!< 0x00000000 */
#define PWM_CTL_ID_DIV4 (0x1U << PWM_CTL_ID_Pos) /*!< 0x00000040 */
#define PWM_CTL_ID_DIV8 (0x2U << PWM_CTL_ID_Pos) /*!< 0x00000080 */
#define PWM_CTL_ID_DIV16 (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */
/************** Bits definition for PWMx_TAR register ******************/
/************** Bits definition for PWMx_CCTLy register ******************/
////////////#define PWM_CCTL_OUTMOD_CONST (0x00UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_SET (0x01UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_TOGGLE_RESET (0x02UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_SET_RESET (0x03UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_TOGGLE (0x04UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_RESET (0x05UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_TOGGLE_SET (0x06UL << PWM_CCTL_OUTMOD_Pos)
#define PWM_CCTL_OUTMOD_RESET_SET (0x07UL << PWM_CCTL_OUTMOD_Pos)
////////////////////
//ClockDivision
#define PWM_CLKDIV_2 (0x0U << PWM_CTL_ID_Pos)
#define PWM_CLKDIV_4 (0x1U << PWM_CTL_ID_Pos)
#define PWM_CLKDIV_8 (0x2U << PWM_CTL_ID_Pos)
#define PWM_CLKDIV_16 (0x3U << PWM_CTL_ID_Pos)
#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\
((__CLKDIV__) == PWM_CLKDIV_4) ||\
((__CLKDIV__) == PWM_CLKDIV_8) ||\
((__CLKDIV__) == PWM_CLKDIV_16))
//Mode
#define PWM_MODE_STOP (0x0U << PWM_CTL_MC_Pos)
#define PWM_MODE_UPCOUNT (0x1U << PWM_CTL_MC_Pos)
#define PWM_MODE_CONTINUOUS (0x2U << PWM_CTL_MC_Pos)
#define PWM_MODE_UPDOWN (0x3U << PWM_CTL_MC_Pos)
#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\
((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\
((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\
((__CNTMODE__) == PWM_MODE_UPDOWN))
//ClockSource
#define PWM_CLKSRC_APB (0x1U << PWM_CTL_TSEL_Pos)
#define PWM_CLKSRC_APBD128 (0x0U << PWM_CTL_TSEL_Pos)
#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\
((__CLKSRC__) == PWM_CLKSRC_APBD128))
typedef struct
{
uint32_t Channel;
uint32_t Period;
uint32_t OutMode;
} PWM_OCInitType;
typedef struct
{
uint32_t Channel;
uint32_t CaptureMode;
} PWM_ICInitType;
//Channel
#define PWM_CHANNEL_0 (0UL)
#define PWM_CHANNEL_1 (1UL)
#define PWM_CHANNEL_2 (2UL)
#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\
((__CHANNEL__) == PWM_CHANNEL_1) ||\
((__CHANNEL__) == PWM_CHANNEL_2))
//OutMode
#define PWM_OUTMOD_CONST (0x0U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_SET (0x1U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_TOGGLE_RESET (0x2U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_SET_RESET (0x3U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_TOGGLE (0x4U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_RESET (0x5U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_TOGGLE_SET (0x6U << PWM_CCTL_OUTMOD_Pos)
#define PWM_OUTMOD_RESET_SET (0x7U << PWM_CCTL_OUTMOD_Pos)
#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\
((__OUTMODE__) == PWM_OUTMOD_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET_SET))
//CaptureMode
#define PWM_CM_DISABLE (0x0U << PWM_CCTL_CM_Pos)
#define PWM_CM_RISING (0x1U << PWM_CCTL_CM_Pos)
#define PWM_CM_FALLING (0x2U << PWM_CCTL_CM_Pos)
#define PWM_CM_BOTH (0x3U << PWM_CCTL_CM_Pos)
#define IS_PWM_CAPMODE(__CAPMODE__) (((__CAPMODE__) == PWM_CM_DISABLE) ||\
((__CAPMODE__) == PWM_CM_RISING) ||\
((__CAPMODE__) == PWM_CM_FALLING) ||\
((__CAPMODE__) == PWM_CM_BOTH))
//Interrupt
#define PWM_INT_CCIFG PWM_CCTL_CCIFG
#define PWM_INT_COV PWM_CCTL_COV
#define PWM_INT_Msk (PWM_INT_CCIFG | PWM_INT_COV)
#define IS_PWM_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == PWM_INT_CCIFG) ||\
((__INTFLAGR__) == PWM_INT_COV))
#define IS_PWM_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & PWM_INT_Msk) != 0U) &&\
(((__INTFLAGC__) & ~PWM_INT_Msk) == 0U))
//PWM output selection
#define PWM0_OUT0 0
#define PWM0_OUT1 1
#define PWM0_OUT2 2
#define PWM1_OUT0 4
#define PWM1_OUT1 5
#define PWM1_OUT2 6
#define PWM2_OUT0 8
#define PWM2_OUT1 9
#define PWM2_OUT2 10
#define PWM3_OUT0 12
#define PWM3_OUT1 13
#define PWM3_OUT2 14
#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\
((__OUTSEL__) == PWM0_OUT1) ||\
((__OUTSEL__) == PWM0_OUT2) ||\
((__OUTSEL__) == PWM1_OUT0) ||\
((__OUTSEL__) == PWM1_OUT1) ||\
((__OUTSEL__) == PWM1_OUT2) ||\
((__OUTSEL__) == PWM2_OUT0) ||\
((__OUTSEL__) == PWM2_OUT1) ||\
((__OUTSEL__) == PWM2_OUT2) ||\
((__OUTSEL__) == PWM3_OUT0) ||\
((__OUTSEL__) == PWM3_OUT1) ||\
((__OUTSEL__) == PWM3_OUT2))
//outline
#define PWM_OLINE_0 1
#define PWM_OLINE_1 2
#define PWM_OLINE_2 4
#define PWM_OLINE_3 8
#define PWM_OLINE_Msk 0xF
#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\
(((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U))
//inline
#define PWM_ILINE_0 0
#define PWM_ILINE_1 1
#define PWM_ILINE_2 2
#define PWM_ILINE_3 3
#define IS_PWM_INLINE(__INLINE__) (((__INLINE__) == PWM_ILINE_0) ||\
((__INLINE__) == PWM_ILINE_1) ||\
((__INLINE__) == PWM_ILINE_2) ||\
((__INLINE__) == PWM_ILINE_3))
//PWM input selection
#define PWM1_IN2 0x014
#define PWM1_IN1 0x012
#define PWM1_IN0 0x010
#define PWM0_IN2 0x004
#define PWM0_IN1 0x002
#define PWM0_IN0 0x000
#define PWM3_IN2 0x114
#define PWM3_IN1 0x112
#define PWM3_IN0 0x110
#define PWM2_IN2 0x104
#define PWM2_IN1 0x102
#define PWM2_IN0 0x100
#define IS_PWM_INSEL(__INSEL__) (((__INSEL__) == PWM1_IN2) ||\
((__INSEL__) == PWM1_IN1) ||\
((__INSEL__) == PWM1_IN0) ||\
((__INSEL__) == PWM0_IN2) ||\
((__INSEL__) == PWM0_IN1) ||\
((__INSEL__) == PWM0_IN0) ||\
((__INSEL__) == PWM3_IN2) ||\
((__INSEL__) == PWM3_IN1) ||\
((__INSEL__) == PWM3_IN0) ||\
((__INSEL__) == PWM2_IN2) ||\
((__INSEL__) == PWM2_IN1) ||\
((__INSEL__) == PWM2_IN0))
//Level
#define PWM_LEVEL_HIGH (0x1U << PWM_CCTL_OUT_Pos)
#define PWM_LEVEL_LOW 0
#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\
((__OUTLVL__) == PWM_LEVEL_LOW))
#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U)
/****************************** PWM Instances *********************************/
#define IS_PWM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PWM0) || \
((INSTANCE) == PWM1) || \
((INSTANCE) == PWM2) || \
((INSTANCE) == PWM3))
#define IS_PWMMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWMMUX)
/* Exported Functions ------------------------------------------------------- */
/* PWM Exported Functions Group1:
Initialization ----------------------------*/
void PWM_BaseInit(PWM_Type *PWMx, PWM_BaseInitType *InitStruct);
void PWM_BaseStructInit(PWM_BaseInitType *InitStruct);
void PWM_OCStructInit(PWM_OCInitType *OCInitType);
void PWM_OCInit(PWM_Type *PWMx, PWM_OCInitType *OCInitType);
void PWM_ICStructInit(PWM_ICInitType *ICInitType);
void PWM_ICInit(PWM_Type *PWMx, PWM_ICInitType *ICInitType);
/* PWM Exported Functions Group2:
Interrupt ---------------------------------*/
void PWM_BaseINTConfig(PWM_Type *PWMx, uint32_t NewState);
uint8_t PWM_GetBaseINTStatus(PWM_Type *PWMx);
void PWM_ClearBaseINTStatus(PWM_Type *PWMx);
void PWM_ChannelINTConfig(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState);
uint8_t PWM_GetChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask);
void PWM_ClearChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask);
/* PWM Exported Functions Group3:
MISC --------------------------------------*/
void PWM_ClearCounter(PWM_Type *PWMx);
void PWM_CCRConfig(PWM_Type *PWMx, uint32_t Channel, uint16_t Period);
//Compare output
void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine);
void PWM_OutputCmd(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState);
void PWM_SetOutLevel(PWM_Type *PWMx, uint32_t Channel, uint32_t Level);
void PWM_ILineConfig(uint32_t InSelection, uint32_t ILine);
uint8_t PWM_GetSCCI(PWM_Type *PWMx, uint32_t Channel);
uint32_t PWM_GetCapture(PWM_Type *PWMx, uint32_t Channel);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PWM_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_rtc.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief RTC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_RTC_H
#define __LIB_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* RTC Time struct */
typedef struct
{
uint32_t Year;
uint32_t Month;
uint32_t Date;
uint32_t WeekDay;
uint32_t Hours;
uint32_t Minutes;
uint32_t Seconds;
uint32_t SubSeconds;
} RTC_TimeTypeDef;
/* RTC Alarm Time struct */
typedef struct
{
uint32_t AlarmHours;
uint32_t AlarmMinutes;
uint32_t AlarmSeconds;
uint32_t AlarmSubSeconds;
}RTC_AlarmTypeDef;
#define RTC_ACCURATE 0
#define RTC_INACCURATE 1
#define IS_RTC_ACCURATESEL(__ACCURATESEL__) (((__ACCURATESEL__) == RTC_ACCURATE) ||\
((__ACCURATESEL__) == RTC_INACCURATE))
/************** Bits definition for RTC_WKUCNT register ******************/
#define RTC_WKUCNT_CNTSEL_0 (0x0U << RTC_WKUCNT_CNTSEL_Pos)
#define RTC_WKUCNT_CNTSEL_1 (0x1U << RTC_WKUCNT_CNTSEL_Pos)
#define RTC_WKUCNT_CNTSEL_2 (0x2U << RTC_WKUCNT_CNTSEL_Pos)
#define RTC_WKUCNT_CNTSEL_3 (0x3U << RTC_WKUCNT_CNTSEL_Pos)
/************** Bits definition for RTC_PSCA register ******************/
#define RTC_PSCA_PSCA_0 (0x0U << RTC_PSCA_PSCA_Pos)
#define RTC_PSCA_PSCA_1 (0x1U << RTC_PSCA_PSCA_Pos)
//#define RTC_PSCA_PSCA_2 (0x2U << RTC_PSCA_PSCA_Pos)
//#define RTC_PSCA_PSCA_3 (0x3U << RTC_PSCA_PSCA_Pos)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
//INT
#define RTC_INT_ALARM RTC_INTSTS_INTSTS10
#define RTC_INT_CEILLE RTC_INTSTS_INTSTS8
#define RTC_INT_WKUCNT RTC_INTSTS_INTSTS6
#define RTC_INT_MIDNIGHT RTC_INTSTS_INTSTS5
#define RTC_INT_WKUHOUR RTC_INTSTS_INTSTS4
#define RTC_INT_WKUMIN RTC_INTSTS_INTSTS3
#define RTC_INT_WKUSEC RTC_INTSTS_INTSTS2
#define RTC_INT_TIMEILLE RTC_INTSTS_INTSTS1
#define RTC_INT_ITVSITV RTC_INTSTS_INTSTS0
#define RTC_INT_Msk (0x57FUL)
//INTSTS
#define RTC_INTSTS_ALARM RTC_INTSTS_INTSTS10
#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8
#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6
#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5
#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4
#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3
#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2
#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1
#define RTC_INTSTS_ITVSITV RTC_INTSTS_INTSTS0
#define RTC_INTSTS_Msk (0x57FUL)
//CNTCLK
#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0
#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1
#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2
#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3
//Prescaler
#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0
#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1
//PLLDIVSOUCE
#define RTC_PLLDIVSOURCE_PCLK 0
#define RTC_PLLDIVSOURCE_PLLL (0x1U << RTC_CTL_RTCPLLCLKSEL_Pos)
//RTC_ITV
#define RTC_ITV_SEC (0x80)
#define RTC_ITV_MIN (1 << RTC_ITV_ITV_Pos)
#define RTC_ITV_HOUR (2 << RTC_ITV_ITV_Pos)
#define RTC_ITV_DAY (3 << RTC_ITV_ITV_Pos)
#define RTC_ITV_500MS (4 << RTC_ITV_ITV_Pos)
#define RTC_ITV_250MS (5 << RTC_ITV_ITV_Pos)
#define RTC_ITV_125MS (6 << RTC_ITV_ITV_Pos)
#define RTC_ITV_62MS (7 << RTC_ITV_ITV_Pos)
#define RTC_ITV_SITVSEC (7 << RTC_ITV_ITV_Pos)
//RTC_SITV
#define RTC_SITV_EN (1 << RTC_SITV_SITVEN_Pos) //Control Multi Second interval.1:enable; 0:disable.
/* Private macros ------------------------------------------------------------*/
#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U)
/* Year 0 ~ 99 */
#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU)
/* Month 1 ~ 12 */
#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U))
/* Date 1 ~ 31 */
#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32U))
/* Weekday 0 ~ 6 */
#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U)
/* Hours 0 ~ 23 */
#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24U)
/* Minutes 0 ~ 59 */
#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5AU)
/* Seconds 0 ~ 59 */
#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5AU)
/* SubSeconds 0 ~ 0x999 */
#define IS_RTC_TIME_SubSECS(__SubSECS__) ((__SubSECS__) < 0x1000U)
/* Alarm time 0 ~ 0x999 */
#define IS_RTC_ALARMTIME(__ALARMTIME__) ((__ALARMTIME__) < 0x1E0000U)
#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\
(((__INT__) & ~RTC_INT_Msk) == 0U))
#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\
((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\
((__INTFLAGR_) == RTC_INTSTS_ALARM) ||\
((__INTFLAGR_) == RTC_INTSTS_TIMEILLE) ||\
((__INTFLAGR_) == RTC_INTSTS_ITVSITV))
#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U))
#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) ((__PERIOD__) < 0x41U)
#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) ((__PERIOD__) < 0x41U)
#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) ((__PERIOD__) < 0x21U)
#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) ((__PERIOD__) < 0x1000001U)
#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\
((__CNTSEL__) == RTC_WKUCNT_2048) ||\
((__CNTSEL__) == RTC_WKUCNT_512) ||\
((__CNTSEL__) == RTC_WKUCNT_128))
#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\
((__CLKDIV__) == RTC_CLKDIV_4))
#define IS_RTC_PLLDIVSOURCE(__PLLDIVSOURCE__) (((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PCLK) ||\
((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PLLL))
#define IS_RTC_ITV(__ITV__) (((__ITV__) == RTC_ITV_SEC) ||\
((__ITV__) == RTC_ITV_MIN) ||\
((__ITV__) == RTC_ITV_HOUR) ||\
((__ITV__) == RTC_ITV_DAY) ||\
((__ITV__) == RTC_ITV_500MS) ||\
((__ITV__) == RTC_ITV_250MS) ||\
((__ITV__) == RTC_ITV_125MS) ||\
((__ITV__) == RTC_ITV_62MS) ||\
((__ITV__) == RTC_ITV_SITVSEC))
#define IS_RTC_SITV(__SITV__) ((__SITV__) < 64U)
/* Exported Functions ------------------------------------------------------- */
/* RTC Exported Functions Group1:
Time functions -----------------------------*/
void RTC_SetTime(RTC_TimeTypeDef *sTime, uint32_t AccurateSel);
void RTC_GetTime(RTC_TimeTypeDef *gTime, uint32_t AccurateSel);
void RTC_SubSecondCmd(uint32_t NewState);
/* RTC Exported Functions Group2:
Alarms configuration functions -------------*/
void RTC_SetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel);
void RTC_GetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel);
void RTC_AlarmCmd(uint32_t NewState);
void RTC_AlarmAccurateCmd(uint32_t NewState);
/* RTC Exported Functions Group3:
Registers operation functions --------------*/
void RTC_WriteProtection(uint32_t NewState);
void RTC_WaitForSynchro(void);
void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len);
void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len);
/* RTC Exported Functions Group4:
Interrupt functions ------------------------*/
void RTC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t RTC_GetINTStatus(uint32_t FlagMask);
void RTC_ClearINTStatus(uint32_t FlagMask);
/* RTC Exported Functions Group5:
Wake-up functions --------------------------*/
void RTC_WKUSecondsConfig(uint8_t nPeriod);
void RTC_WKUMinutesConfig(uint8_t nPeriod);
void RTC_WKUHoursConfig(uint8_t nPeriod);
void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK);
void RTC_WAKE_ITV(uint8_t nType);
void RTC_WAKE_SITV(uint8_t nPeriod);
uint32_t RTC_GetWKUCounterValue(void);
/* RTC Exported Functions Group6:
MISC functions -----------------------------*/
void RTC_PrescalerConfig(uint32_t Prescaler);
void RTC_PLLDIVConfig(uint32_t DIVSource,uint32_t nfrequency);
void RTC_PLLDIVOutputCmd(uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_RTC_H */
/*********************************** END OF FILE ******************************/

212
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/**
******************************************************************************
* @file lib_spi.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief SPI library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_SPI_H
#define __LIB_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Mode;
uint32_t SPH;
uint32_t SPO;
uint32_t ClockDivision;
uint32_t CSNSoft;
uint32_t SWAP;
} SPI_InitType;
/************** Bits definition for SPIx_CTRL register ******************/
#define SPI_CTRL_SCKSEL_0 (0x1U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000001 */
#define SPI_CTRL_SCKSEL_1 (0x2U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000002 */
#define SPI_CTRL_SCKSEL_2 (0x4U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000004 */
/************** Bits definition for SPIx_TXSTS register ******************/
#define SPI_TXSTS_TXFFLAG_0 (0x1U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000001 */
#define SPI_TXSTS_TXFFLAG_1 (0x2U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000002 */
#define SPI_TXSTS_TXFFLAG_2 (0x4U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000004 */
#define SPI_TXSTS_TXFFLAG_3 (0x8U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000008 */
#define SPI_TXSTS_TXFLEV_0 (0x1U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000010 */
#define SPI_TXSTS_TXFLEV_1 (0x2U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000020 */
#define SPI_TXSTS_TXFLEV_2 (0x4U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000040 */
/************** Bits definition for SPIx_TXDAT register ******************/
/************** Bits definition for SPIx_RXSTS register ******************/
#define SPI_RXSTS_RXFFLAG_0 (0x1U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000001 */
#define SPI_RXSTS_RXFFLAG_1 (0x2U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000002 */
#define SPI_RXSTS_RXFFLAG_2 (0x4U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000004 */
#define SPI_RXSTS_RXFFLAG_3 (0x8U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000008 */
#define SPI_RXSTS_RXFLEV_0 (0x1U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000010 */
#define SPI_RXSTS_RXFLEV_1 (0x2U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000020 */
#define SPI_RXSTS_RXFLEV_2 (0x4U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000040 */
//Mode
#define SPI_MODE_MASTER 0
#define SPI_MODE_SLAVE SPI_CTRL_MOD
//SPH
#define SPI_SPH_0 0
#define SPI_SPH_1 SPI_CTRL_SCKPHA
//SPO
#define SPI_SPO_0 0
#define SPI_SPO_1 SPI_CTRL_SCKPOL
//ClockDivision
#define SPI_CLKDIV_2 (0)
#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0)
#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2)
//CSNSoft
#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO
#define SPI_CSNSOFT_DISABLE 0
//SWAP
#define SPI_SWAP_ENABLE SPI_CTRL_SWAP
#define SPI_SWAP_DISABLE 0
//INT
#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN)
#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN)
//status
#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF)
#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY)
#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR)
#define SPI_STS_DMATXDONE (0x80000000|SPI_TXSTS_DMATXDONE)
#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF)
#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL)
#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV)
#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY)
#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF)
#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE)
#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF)
#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE)
//TXFLEV
#define SPI_TXFLEV_0 (0)
#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0)
#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
//RXFLEV
#define SPI_RXFLEV_0 (0)
#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2)
#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0)
/* Private macros ------------------------------------------------------------*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE))
#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1))
#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1))
#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\
((__CLKDIV__) == SPI_CLKDIV_4) ||\
((__CLKDIV__) == SPI_CLKDIV_8) ||\
((__CLKDIV__) == SPI_CLKDIV_16) ||\
((__CLKDIV__) == SPI_CLKDIV_32) ||\
((__CLKDIV__) == SPI_CLKDIV_64) ||\
((__CLKDIV__) == SPI_CLKDIV_128))
#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE))
#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE))
#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\
(((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U))
#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\
((__STSR__) == SPI_STS_TXEMPTY) ||\
((__STSR__) == SPI_STS_TXFUR) ||\
((__STSR__) == SPI_STS_DMATXDONE) ||\
((__STSR__) == SPI_STS_RXFULL) ||\
((__STSR__) == SPI_STS_RXFOV) ||\
((__STSR__) == SPI_STS_BSY) ||\
((__STSR__) == SPI_STS_RFF) ||\
((__STSR__) == SPI_STS_RNE) ||\
((__STSR__) == SPI_STS_TNF) ||\
((__STSR__) == SPI_STS_TFE) ||\
((__STSR__) == SPI_STS_RXIF))
#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) != 0U) &&\
(((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) == 0U))
#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\
((__TXFLEV__) == SPI_TXFLEV_1) ||\
((__TXFLEV__) == SPI_TXFLEV_2) ||\
((__TXFLEV__) == SPI_TXFLEV_3) ||\
((__TXFLEV__) == SPI_TXFLEV_4) ||\
((__TXFLEV__) == SPI_TXFLEV_5) ||\
((__TXFLEV__) == SPI_TXFLEV_6) ||\
((__TXFLEV__) == SPI_TXFLEV_7))
#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\
((__RXFLEV__) == SPI_RXFLEV_1) ||\
((__RXFLEV__) == SPI_RXFLEV_2) ||\
((__RXFLEV__) == SPI_RXFLEV_3) ||\
((__RXFLEV__) == SPI_RXFLEV_4) ||\
((__RXFLEV__) == SPI_RXFLEV_5) ||\
((__RXFLEV__) == SPI_RXFLEV_6) ||\
((__RXFLEV__) == SPI_RXFLEV_7))
/****************************** SPI Instances *********************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/* Exported Functions ------------------------------------------------------- */
/* SPI Exported Functions Group1:
(De)Initialization -------------------------*/
void SPI_DeviceInit(SPI_Type *SPIx);
void SPI_Init(SPI_Type *SPIx, SPI_InitType *InitStruct);
void SPI_StructInit(SPI_InitType *InitStruct);
/* SPI Exported Functions Group2:
Interrupt (flag) ---------------------------*/
void SPI_INTConfig(SPI_Type *SPIx, uint32_t INTMask, uint32_t NewState);
uint8_t SPI_GetStatus(SPI_Type *SPIx, uint32_t Status);
void SPI_ClearStatus(SPI_Type *SPIx, uint32_t Status);
/* SPI Exported Functions Group3:
Transfer datas -----------------------------*/
void SPI_SendData(SPI_Type *SPIx, uint8_t ch);
uint8_t SPI_ReceiveData(SPI_Type *SPIx);
/* SPI Exported Functions Group4:
MISC Configuration -------------------------*/
void SPI_Cmd(SPI_Type *SPIx, uint32_t NewState);
void SPI_TransmitFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel);
void SPI_ReceiveFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel);
uint8_t SPI_GetTransmitFIFOLevel(SPI_Type *SPIx);
uint8_t SPI_GetReceiveFIFOLevel(SPI_Type *SPIx);
void SPI_SmartModeCmd(SPI_Type *SPIx, uint32_t NewState);
void SPI_OverWriteModeCmd(SPI_Type *SPIx, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_SPI_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_tmr.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Timer library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_TMR_H
#define __LIB_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Period;
uint32_t ClockSource;
uint32_t EXTGT;
} TMR_InitType;
//ClockSource
#define TMR_CLKSRC_INTERNAL 0
#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK
//ClockGate
#define TMR_EXTGT_DISABLE 0
#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN
/* Private macros ------------------------------------------------------------*/
#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL))
#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE))
/****************************** TMR Instances *********************************/
#define IS_TMR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TMR0) || \
((INSTANCE) == TMR1) || \
((INSTANCE) == TMR2) || \
((INSTANCE) == TMR3))
/* Exported Functions ------------------------------------------------------- */
/* Timer Exported Functions Group1:
(De)Initialization ----------------------*/
void TMR_DeInit(TMR_Type *TMRx);
void TMR_Init(TMR_Type *TMRx, TMR_InitType *InitStruct);
void TMR_StructInit(TMR_InitType *InitStruct);
/* Timer Exported Functions Group2:
Interrupt (flag) -------------------------*/
void TMR_INTConfig(TMR_Type *TMRx, uint32_t NewState);
uint8_t TMR_GetINTStatus(TMR_Type *TMRx);
void TMR_ClearINTStatus(TMR_Type *TMRx);
/* Timer Exported Functions Group3:
MISC Configuration -----------------------*/
void TMR_Cmd(TMR_Type *TMRx, uint32_t NewState);
uint32_t TMR_GetCurrentValue(TMR_Type *TMRx);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_TMR_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_u32k.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief UART 32K library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_U32K_H
#define __LIB_U32K_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Debsel;
uint32_t Parity;
uint32_t FirstBit;
uint32_t AutoCal;
uint32_t Baudrate;
uint32_t LineSel;
} U32K_InitType;
/************** Bits definition for U32Kx_CTRL0 register ******************/
#define U32K_CTRL0_PMODE_EVEN (0x0U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000000 */
#define U32K_CTRL0_PMODE_ODD (0x1U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000010 */
#define U32K_CTRL0_PMODE_0 (0x2U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000020 */
#define U32K_CTRL0_PMODE_1 (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */
#define U32K_CTRL0_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000000 */
#define U32K_CTRL0_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000040 */
#define U32K_CTRL0_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000080 */
#define U32K_CTRL0_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */
/************** Bits definition for U32Kx_CTRL1 register ******************/
#define U32K_CTRL1_RXSEL_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000000 */
#define U32K_CTRL1_RXSEL_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000010 */
#define U32K_CTRL1_RXSEL_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000020 */
#define U32K_CTRL1_RXSEL_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */
//Debsel
#define U32K_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos)
#define U32K_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos)
#define U32K_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos)
#define U32K_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos)
//Parity
#define U32K_PARITY_EVEN (0x1U << U32K_CTRL0_PMODE_Pos)
#define U32K_PARITY_ODD (0x3U << U32K_CTRL0_PMODE_Pos)
#define U32K_PARITY_0 (0x5U << U32K_CTRL0_PMODE_Pos)
#define U32K_PARITY_1 (0x7U << U32K_CTRL0_PMODE_Pos)
#define U32K_PARITY_NONE (0x0U << U32K_CTRL0_PMODE_Pos)
//FirstBit
#define U32K_FIRSTBIT_LSB 0
#define U32K_FIRSTBIT_MSB (0x1U << U32K_CTRL0_MSB_Pos)
//AutoCal
#define U32K_AUTOCAL_ON 0
#define U32K_AUTOCAL_OFF (0x1U << U32K_CTRL0_ACOFF_Pos)
//Line
#define U32K_LINE_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos)
#define U32K_LINE_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos)
#define U32K_LINE_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos)
#define U32K_LINE_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos)
//INT
#define U32K_INT_RXOV (0x1U << U32K_CTRL1_RXOVIE_Pos)
#define U32K_INT_RXPE (0x1U << U32K_CTRL1_RXPEIE_Pos)
#define U32K_INT_RX (0x1U << U32K_CTRL1_RXIE_Pos)
#define U32K_INT_Msk (U32K_INT_RXOV \
|U32K_INT_RXPE \
|U32K_INT_RX)
//INT Status
#define U32K_INTSTS_RXOV (0x1U << U32K_STS_RXOV_Pos)
#define U32K_INTSTS_RXPE (0x1U << U32K_STS_RXPE_Pos)
#define U32K_INTSTS_RX (0x1U << U32K_STS_RXIF_Pos)
#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \
|U32K_INTSTS_RXPE \
|U32K_INTSTS_RX)
//WKUMode
#define U32K_WKUMOD_RX 0 // Wake-up when receive data
#define U32K_WKUMOD_PC (0x1U << U32K_CTRL0_WKUMODE_Pos) // Wake-up when receive data and parity/stop bit correct
/****************************** U32K Instances ********************************/
#define IS_U32K_ALL_INSTANCE(INSTANCE) (((INSTANCE) == U32K0) || \
((INSTANCE) == U32K1))
/* Private macros ------------------------------------------------------------*/
#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\
((__DEBSEL__) == U32K_DEBSEL_1) ||\
((__DEBSEL__) == U32K_DEBSEL_2) ||\
((__DEBSEL__) == U32K_DEBSEL_3))
#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\
((__PARITY__) == U32K_PARITY_ODD) ||\
((__PARITY__) == U32K_PARITY_0) ||\
((__PARITY__) == U32K_PARITY_1) ||\
((__PARITY__) == U32K_PARITY_NONE))
#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B))
#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB))
#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF))
#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\
((__LINE__) == U32K_LINE_RX1) ||\
((__LINE__) == U32K_LINE_RX2) ||\
((__LINE__) == U32K_LINE_RX3))
#define IS_U32K_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\
((__BAUDRATE__) <= 14400UL))
#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\
(((__INT__) & ~U32K_INT_Msk) == 0U))
#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\
((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\
((__INTFLAGR__) == U32K_INTSTS_RX))
#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U))
#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC))
/* Exported Functions ------------------------------------------------------- */
/* U32K Exported Functions Group1:
(De)Initialization -----------------------*/
void U32K_DeInit(U32K_Type *U32Kx);
void U32K_Init(U32K_Type *U32Kx, U32K_InitType *InitStruct);
void U32K_StructInit(U32K_InitType *InitStruct);
/* U32K Exported Functions Group2:
Interrupt (flag) configure ---------------*/
void U32K_INTConfig(U32K_Type *U32Kx, uint32_t INTMask, uint8_t NewState);
uint8_t U32K_GetINTStatus(U32K_Type *U32Kx, uint32_t INTMask);
void U32K_ClearINTStatus(U32K_Type *U32Kx, uint32_t INTMask);
/* U32K Exported Functions Group3:
Receive datas -----------------------------*/
uint8_t U32K_ReceiveData(U32K_Type *U32Kx);
/* U32K Exported Functions Group4:
MISC Configuration -------- ---------------*/
void U32K_BaudrateConfig(U32K_Type *U32Kx, uint32_t BaudRate);
void U32K_Cmd(U32K_Type *U32Kx, uint32_t NewState);
void U32K_LineConfig(U32K_Type *U32Kx, uint32_t Line);
void U32K_WKUModeConfig(U32K_Type *U32Kx, uint32_t WKUMode);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_U32K_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_uart.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief UART library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_UART_H
#define __LIB_UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//UART Init struct
typedef struct
{
uint32_t Mode;
uint32_t Parity;
uint32_t FirstBit;
uint32_t Baudrate;
} UART_InitType;
//Mode
#define UART_MODE_RX (0x1U << UART_CTRL_RXEN_Pos)
#define UART_MODE_TX (0x1U << UART_CTRL_TXEN_Pos)
#define UART_MODE_OFF 0
#define UART_MODE_Msk (UART_MODE_RX | UART_MODE_TX)
//Parity
#define UART_PARITY_EVEN (0x1U << UART_CTRL2_PMODE_Pos)
#define UART_PARITY_ODD (0x3U << UART_CTRL2_PMODE_Pos)
#define UART_PARITY_0 (0x5U << UART_CTRL2_PMODE_Pos)
#define UART_PARITY_1 (0x7U << UART_CTRL2_PMODE_Pos)
#define UART_PARITY_NONE (0x0U << UART_CTRL2_PMODE_Pos)
//FirstBit
#define UART_FIRSTBIT_LSB 0
#define UART_FIRSTBIT_MSB (0x1U << UART_CTRL2_MSB_Pos)
//UART Configration Information struct
typedef struct
{
uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable
uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable
uint32_t Baudrate; //The value of current budrate
uint8_t Parity; //0:1+8+1 mode; 1: Even parity; 3:Odd parity; 5: parity bit=0; 7: parity bit=1;
uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first
} UART_ConfigINFOType;
//status
#define UART_FLAG_DMATXDONE (0x1U << UART_STATE_DMATXDONE_Pos)
#define UART_FLAG_RXPARITY (0x1U << UART_STATE_RXPSTS_Pos)
#define UART_FLAG_TXDONE (0x1U << UART_STATE_TXDONE_Pos)
#define UART_FLAG_RXPE (0x1U << UART_STATE_RXPE_Pos)
#define UART_FLAG_RXOV (0x1U << UART_STATE_RXOV_Pos)
#define UART_FLAG_TXOV (0x1U << UART_STATE_TXOV_Pos)
#define UART_FLAG_RXFULL (0x1U << UART_STATE_RXFULL_Pos)
#define UART_FLAG_RCMsk (UART_FLAG_DMATXDONE \
|UART_FLAG_TXDONE \
|UART_FLAG_RXPE \
|UART_FLAG_RXOV \
|UART_FLAG_RXFULL \
|UART_FLAG_TXOV)
//interrupt
#define UART_INT_TXDONE (0x1U << UART_CTRL_TXDONEIE_Pos)
#define UART_INT_RXPE (0x1U << UART_CTRL_RXPEIE_Pos)
#define UART_INT_RXOV (0x1U << UART_CTRL_RXOVIE_Pos)
#define UART_INT_TXOV (0x1U << UART_CTRL_TXOVIE_Pos)
#define UART_INT_RX (0x1U << UART_CTRL_RXIE_Pos)
#define UART_INT_Msk (UART_INT_TXDONE \
|UART_INT_RXPE \
|UART_INT_RXOV \
|UART_INT_TXOV \
|UART_INT_RX)
//INTStatus
#define UART_INTSTS_TXDONE (0x1U << UART_INTSTS_TXDONEIF_Pos)
#define UART_INTSTS_RXPE (0x1U << UART_INTSTS_RXPEIF_Pos)
#define UART_INTSTS_RXOV (0x1U << UART_INTSTS_RXOVIF_Pos)
#define UART_INTSTS_TXOV (0x1U << UART_INTSTS_TXOVIF_Pos)
#define UART_INTSTS_RX (0x1U << UART_INTSTS_RXIF_Pos)
#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \
|UART_INTSTS_RXPE \
|UART_INTSTS_RXOV \
|UART_INTSTS_TXOV \
|UART_INTSTS_RX)
/* Private macros ------------------------------------------------------------*/
#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)))
#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\
((__PARITY__) == UART_PARITY_ODD) ||\
((__PARITY__) == UART_PARITY_0) ||\
((__PARITY__) == UART_PARITY_1) ||\
((__PARITY__) == UART_PARITY_NONE))
#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\
((__FIRSTBIT__) == UART_FIRSTBIT_MSB))
#define IS_UART_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\
((__BAUDRATE__) <= 819200UL))
#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_DMATXDONE) ||\
((__FLAGR__) == UART_FLAG_RXPARITY) ||\
((__FLAGR__) == UART_FLAG_TXDONE) ||\
((__FLAGR__) == UART_FLAG_RXPE) ||\
((__FLAGR__) == UART_FLAG_RXOV) ||\
((__FLAGR__) == UART_FLAG_TXOV) ||\
((__FLAGR__) == UART_FLAG_RXFULL))
#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\
(((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U))
#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\
(((__INT__) & ~UART_INT_Msk) == 0U))
#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\
((__INTFLAGR__) == UART_INTSTS_RXPE) ||\
((__INTFLAGR__) == UART_INTSTS_RXOV) ||\
((__INTFLAGR__) == UART_INTSTS_TXOV) ||\
((__INTFLAGR__) == UART_INTSTS_RX))
#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U))
/****************************** UART Instances ********************************/
#define IS_UART_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UART0) || \
((INSTANCE) == UART1) || \
((INSTANCE) == UART2) || \
((INSTANCE) == UART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/* Exported Functions ------------------------------------------------------- */
/* UART Exported Functions Group1:
Initialization and functions --------------*/
void UART_DeInit(UART_Type *UARTx);
void UART_Init(UART_Type *UARTx, UART_InitType *InitStruct);
void UART_StructInit(UART_InitType *InitStruct);
/* UART Exported Functions Group2:
(Interrupt) Flag --------------------------*/
uint8_t UART_GetFlag(UART_Type *UARTx, uint32_t FlagMask);
void UART_ClearFlag(UART_Type *UARTx, uint32_t FlagMask);
void UART_INTConfig(UART_Type *UARTx, uint32_t INTMask, uint8_t NewState);
uint8_t UART_GetINTStatus(UART_Type *UARTx, uint32_t INTMask);
void UART_ClearINTStatus(UART_Type *UARTx, uint32_t INTMask);
/* UART Exported Functions Group3:
Transfer datas ----------------------------*/
void UART_SendData(UART_Type *UARTx, uint8_t ch);
uint8_t UART_ReceiveData(UART_Type *UARTx);
/* UART Exported Functions Group4:
MISC Configuration ------------------------*/
void UART_BaudrateConfig(UART_Type *UARTx, uint32_t BaudRate);
void UART_Cmd(UART_Type *UARTx, uint32_t Mode, uint32_t NewState);
void UART_GetConfigINFO(UART_Type *UARTx, UART_ConfigINFOType *ConfigInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_UART_H */
/*********************************** END OF FILE ******************************/

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/**
*******************************************************************************
* @file lib_version.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Version library.
*******************************************************************************/
#ifndef __LIB_VERSION_H
#define __LIB_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
/* Exported Functions ------------------------------------------------------- */
/**
* @brief Read receive data register.
* @param None
* @retval Version value
*/
uint16_t Target_GetDriveVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_VERSION_H */
/*********************************** END OF FILE ******************************/

47
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/**
******************************************************************************
* @file lib_wdt.h
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief WDT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_WDT_H
#define __LIB_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define WDT_2_SECS (0x0U << PMU_WDTEN_WDTSEL_Pos)
#define WDT_4_SECS (0x1U << PMU_WDTEN_WDTSEL_Pos)
#define WDT_8_SECS (0x2U << PMU_WDTEN_WDTSEL_Pos)
#define WDT_16_SECS (0x3U << PMU_WDTEN_WDTSEL_Pos)
/* Private macros ------------------------------------------------------------*/
#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\
((__PERIOD__) == WDT_4_SECS) ||\
((__PERIOD__) == WDT_8_SECS) ||\
((__PERIOD__) == WDT_16_SECS))
/* Exported Functions ------------------------------------------------------- */
void WDT_Enable(void);
void WDT_Disable(void);
void WDT_Clear(void);
void WDT_SetPeriod(uint32_t period);
uint16_t WDT_GetCounterValue(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_WDT_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc_tiny.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_adc_tiny.h"
#define ANA_REGF_RSTValue (0U)
/**
* @brief Initializes the Tiny ADC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void TADC_DeInit(void)
{
ANA->REGF = ANA_REGF_RSTValue;
ANA->INTSTS = ANA_INTSTS_INTSTS13;
ANA->INTEN &= ~ANA_INTEN_INTEN13;
ANA->MISC &= ~ANA_MISC_TADCTH;
}
/**
* @brief Fills each TADC_InitStruct member with its default value.
* @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized.
* @retval None
*/
void TADC_StructInit(TADCInitType* TADC_InitStruct)
{
/*--------------- Reset TADC init structure parameters values ---------------*/
/* Initialize the SignalSel member */
TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6;
/* Initialize the ADTREF1 member */
TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9;
/* Initialize the ADTREF2 member */
TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8;
/* Initialize the ADTREF3 member */
TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7;
}
/**
* @brief Initializes Tiny ADC.
* @param TADC_InitStruct
SelADT:
ADCTINY_SIGNALSEL_IOE6
ADCTINY_SIGNALSEL_IOE7
ADTREF1:
ADCTINY_REF1_0_9
ADCTINY_REF1_0_7
ADTREF2:
ADCTINY_REF2_1_8
ADCTINY_REF2_1_6
ADTREF3:
ADCTINY_REF3_2_7
ADCTINY_REF3_2_5
* @retval None
*/
void TADC_Init(TADCInitType* TADC_InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel));
assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1));
assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2));
assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3));
tmp = ANA->REGF;
tmp &= ~(ANA_REGF_ADTSEL \
|ANA_REGF_ADTREF1SEL\
|ANA_REGF_ADTREF2SEL\
|ANA_REGF_ADTREF3SEL);
tmp |= (TADC_InitStruct->SignalSel \
|TADC_InitStruct->ADTREF1\
|TADC_InitStruct->ADTREF2\
|TADC_InitStruct->ADTREF3);
ANA->REGF = tmp;
}
/**
* @brief Enables or disables Tiny ADC .
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->REGF |= ANA_REGF_ADTPDN;
else
ANA->REGF &= ~ANA_REGF_ADTPDN;
}
/**
* @brief Gets Tiny ADC output value.
* @param None
* @retval Output of Tiny ADC(0 ~ 3).
*/
uint8_t TADC_GetOutput(void)
{
return ((ANA->CMPOUT & ANA_CMPOUT_TADCO) >> ANA_CMPOUT_TADCO_Pos);
}
/**
* @brief Configures Tiny ADC interrupt threshold.
* @param THSel:
ADCTINY_THSEL_0
ADCTINY_THSEL_1
ADCTINY_THSEL_2
ADCTINY_THSEL_3
* @retval None.
*/
void TADC_IntTHConfig(uint32_t THSel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_THSEL(THSel));
tmp = ANA->MISC;
tmp &= ~ANA_MISC_TADCTH;
tmp |= THSel;
ANA->MISC = tmp;
}
/**
* @brief Enables or disables Tiny ADC interrupt.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_INTConfig(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->INTEN |= ANA_INTEN_INTEN13;
else
ANA->INTEN &= ~ANA_INTEN_INTEN13;
}
/**
* @brief Gets Tiny ADC interrupt status.
* @param None
* @retval Interrupt status.
*/
uint8_t TADC_GetINTStatus(void)
{
if (ANA->INTSTS & ANA_INTSTS_INTSTS13)
return 1;
else
return 0;
}
/**
* @brief Clears Tiny ADC interrupt status.
* @param None
* @retval None
*/
void TADC_ClearINTStatus(void)
{
ANA->INTSTS = ANA_INTSTS_INTSTS13;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_ana.h"
/**
* @brief Gets analog status.
* @param StatusMask:
ANA_STATUS_AVCCLV
ANA_STATUS_VDCINDROP
ANA_STATUS_VDDALARM
ANA_STATUS_COMP2
ANA_STATUS_COMP1
ANA_STATUS_LOCKL
ANA_STATUS_LOCKH
* @retval Analog status
*/
uint8_t ANA_GetStatus(uint32_t StatusMask)
{
/* Check parameters */
assert_parameters(IS_ANA_STATUS(StatusMask));
if (ANA->CMPOUT & StatusMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Gets analog interrupt status.
* @param IntMask:
ANA_INT_UPPER_TH3
ANA_INT_LOWER_TH3
ANA_INT_UPPER_TH2
ANA_INT_LOWER_TH2
ANA_INT_UPPER_TH1
ANA_INT_LOWER_TH1
ANA_INT_UPPER_TH0
ANA_INT_LOWER_TH0
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SLPFAIL_VDCIN
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval interrupt status.
*/
uint8_t ANA_GetINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSR(IntMask));
if (ANA->INTSTS&IntMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clears analog interrupt status.
* @param IntMask:status to clear, can use the '|' operator.
ANA_INT_UPPER_TH3
ANA_INT_LOWER_TH3
ANA_INT_UPPER_TH2
ANA_INT_LOWER_TH2
ANA_INT_UPPER_TH1
ANA_INT_LOWER_TH1
ANA_INT_UPPER_TH0
ANA_INT_LOWER_TH0
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SLPFAIL_VDCIN
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval None
*/
void ANA_ClearINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSC(IntMask));
ANA->INTSTS = IntMask;
}
/**
* @brief Enables or disables analog interrupt.
* @param IntMask:status to clear, can use the '|' operator.
ANA_INT_UPPER_TH3
ANA_INT_LOWER_TH3
ANA_INT_UPPER_TH2
ANA_INT_LOWER_TH2
ANA_INT_UPPER_TH1
ANA_INT_LOWER_TH1
ANA_INT_UPPER_TH0
ANA_INT_LOWER_TH0
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SLPFAIL_VDCIN
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
NewState:
ENABLE
DISABLE
* @retval None
*/
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ANA_INT(IntMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = ANA->INTEN;
if (NewState == ENABLE)
{
tmp |= IntMask;
}
else
{
tmp &= ~IntMask;
}
ANA->INTEN = tmp;
}
/*********************************** END OF FILE ******************************/

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bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_clk.c Normal file
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bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/lib_cmp.c Normal file
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