Merge pull request #4971 from ze9hyr/acm32f030

add acm32f030 bsp

.github/workflows/action.yml

@@ -29,6 +29,7 @@ jobs:
       fail-fast: false
       matrix:
        legs:
+         - {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/Copyright_Notice.md

@@ -10,6 +10,16 @@ The peripheral library or firmware library of the chip manufacturer is authorize
 
 ## BSP's License and Coyright:
 
+### acm32f0x0-nucleo
+
+License:  bsd-new
+
+Copyright: Copyright (c) 2021, AisinoChip
+
+Path:
+
+- bsp/acm32f0x0-nucleo/libraries
+
 ### apollo2
 
 License:  bsd-new

bsp/acm32f0x0-nucleo/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/acm32f0x0-nucleo/Kconfig

@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_ACM32F0
+    bool
+    select ARCH_ARM_CORTEX_M0
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"
+

bsp/acm32f0x0-nucleo/README.md

@@ -0,0 +1,58 @@
+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F0x0芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F0X0系列      |
+|CPU                       | ARM Cortex-M0      |
+|主频                      | 64MHz              |
+|片内SRAM                  | 32K                |
+|片内Flash                 | 128K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F0](www.aisinochip.com/index.php/product/child1/id/217.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f0x0-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=iar`或`scons --target=mdk5`生成IAR或是keil工程，再使用相应的工具进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PD15 ---> PIN: 0, 1...63  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+| WDT           |     支持     |              WDT/IWDT                 |
+| ADC           |     支持     |                                       |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/32.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/32.html

bsp/acm32f0x0-nucleo/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
+

bsp/acm32f0x0-nucleo/SConstruct

@@ -0,0 +1,52 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
+

bsp/acm32f0x0-nucleo/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/acm32f0x0-nucleo/applications/main.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    1     /* PA1 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+    }
+}
+

bsp/acm32f0x0-nucleo/drivers/Kconfig

@@ -0,0 +1,237 @@
+menu "Hardware Drivers Config"
+
+config SOC_ACM32F070RBT7
+    bool
+    select SOC_SERIES_ACM32F0
+    select RT_USING_COMPONENTS_INIT
+    default y
+
+config SOC_SRAM_START_ADDR
+    hex
+    default 0x20000000
+
+config SOC_SRAM_SIZE
+    hex
+    default 0x20
+
+config SOC_FLASH_START_ADDR
+    hex
+    default 0x00000000
+
+config SOC_FLASH_SIZE
+    hex
+    default 0x80
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menu "Hardware GPIO"
+        config BSP_USING_GPIO1
+            bool "Enable GPIOAB"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO2
+            bool "Enable GPIOCD"
+            default y
+            select RT_USING_PIN
+    endmenu
+
+    config BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+    menu "Hardware UART"
+        config BSP_USING_UART1
+            bool "Enable UART1 (PA9/PA10)"
+            default y
+            select RT_USING_SERIAL
+
+        config BSP_USING_UART2
+            bool "Enable UART2 (PA2/PA3)"
+            default y
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART2
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART3
+            bool "Enable UART3 (PC4/PC5)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART3
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART3_TX_USING_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+    endmenu
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    menu "Hardware I2C"
+        config BSP_USING_I2C1
+            bool "Enable I2C1"
+            default n
+            select RT_USING_I2C
+        config BSP_USING_I2C2
+            bool "Enable I2C2"
+            default n
+            select RT_USING_I2C
+    endmenu
+
+    menu "Hardware CAN"
+        config BSP_USING_CAN1
+            bool "Enable CAN1"
+            default n
+            select RT_USING_CAN
+    endmenu
+
+    menu "Hardware TIMER"
+        config BSP_USING_TIM1
+            bool "Enable Timer1"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM3
+            bool "Enable Timer3"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM6
+            bool "Enable Timer6"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM14
+            bool "Enable Timer14"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM15
+            bool "Enable Timer15"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM16
+            bool "Enable Timer16"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM17
+            bool "Enable Timer17"
+            default n
+            select RT_USING_HWTIMER
+    endmenu
+
+    menu "Hardware WDT"
+        config BSP_USING_WDT
+            bool "Enable Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+        config BSP_USING_IWDT
+            bool "Enable Independent Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+    endmenu
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        default n
+
+    menu "Hardware SPI"
+        config BSP_USING_SPI1
+            bool "Enable SPI1"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI1
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI2
+            bool "Enable SPI2"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI2
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                default n
+        endif
+    endmenu
+
+    menu "Hardware CRYPTO"
+        config BSP_USING_CRC
+            select RT_HWCRYPTO_USING_CRC
+            bool "Enable CRC"
+            default n
+            select RT_USING_HWCRYPTO
+        config BSP_USING_AES
+            select RT_HWCRYPTO_USING_AES
+            bool "Enable AES"
+            default n
+            select RT_USING_HWCRYPTO
+
+        config BSP_USING_HRNG
+            select RT_HWCRYPTO_USING_RNG
+            bool "Enable HRNG"
+            default n
+            select RT_USING_HWCRYPTO
+    endmenu
+
+    config BSP_USING_CMP
+        bool "Enable Analog Voltage Comparer"
+        default n
+
+    config BSP_USING_OPA
+        bool "Enable Operational Amplifier"
+        default n
+
+    config BSP_USING_TKEY
+        bool "Enable Touch Key"
+        select RT_USING_TOUCH
+        default n
+
+    config BSP_USING_RPMU
+        bool "Enable RTC PMU"
+        select RT_USING_PM
+        default n
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+

bsp/acm32f0x0-nucleo/drivers/SConscript

@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
+
+

bsp/acm32f0x0-nucleo/drivers/board.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "rtconfig.h"
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/acm32f0x0-nucleo/drivers/board.h

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-27     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/acm32f0x0-nucleo/drivers/drv_adc.c

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   first implementation
+ */
+
+#include <board.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define     ADC_NAME        "adc"
+
+#if defined(BSP_USING_ADC)
+
+struct acm32_adc
+{
+    ADC_HandleTypeDef       handle;
+    struct rt_adc_device    acm32_adc_device;
+};
+
+static struct acm32_adc acm32_adc_obj = {0};
+
+static rt_err_t acm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    struct acm32_adc *adcObj = RT_NULL;
+
+    RT_ASSERT(device != RT_NULL);
+
+    adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device);
+
+    if (enabled)
+    {
+        /* channel enabled */
+        if (0 != (adcObj->handle.Init.ChannelEn & (1 << channel)))
+        {
+            return RT_EOK;
+        }
+
+        adcObj->handle.Instance = ADC;
+        adcObj->handle.Init.ClockDiv = ADC_CLOCK_DIV8;
+        adcObj->handle.Init.ConConvMode = ADC_CONCONVMODE_DISABLE;
+        adcObj->handle.Init.JChannelMode = ADC_JCHANNELMODE_DISABLE;
+        adcObj->handle.Init.DiffMode = ADC_DIFFMODE_DISABLE;
+        adcObj->handle.Init.DMAMode = ADC_DMAMODE_DISABLE;
+        adcObj->handle.Init.OverMode = ADC_OVERMODE_DISABLE;
+        adcObj->handle.Init.OverSampMode = ADC_OVERSAMPMODE_DISABLE;
+        adcObj->handle.Init.AnalogWDGEn = ADC_ANALOGWDGEN_DISABLE;
+        adcObj->handle.Init.ExTrigMode.ExTrigSel = ADC_SOFTWARE_START;
+        adcObj->handle.Init.ChannelEn |= 1 << channel;
+
+        HAL_ADC_Init(&adcObj->handle);
+
+        adcObj->handle.ChannelNum ++;
+    }
+    else
+    {
+        /* channel disabled */
+        if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel)))
+        {
+            return RT_EOK;
+        }
+        adcObj->handle.Init.ChannelEn &= ~(1 << channel);
+        adcObj->handle.ChannelNum --;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t acm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    struct acm32_adc *adcObj = RT_NULL;
+    ADC_ChannelConfTypeDef channelConf = {0};
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+    if (channel > ADC_CHANNEL_15)
+    {
+        return -RT_ERROR;
+    }
+    *value = RT_UINT32_MAX;
+    adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device);
+
+    /* channel disabled */
+    if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel)))
+    {
+        return -RT_ERROR;
+    }
+
+    channelConf.Channel = channel;
+    channelConf.RjMode = 0;
+    channelConf.Sq = ADC_SEQUENCE_SQ1;
+    channelConf.Smp = ADC_SMP_CLOCK_320;
+    HAL_ADC_ConfigChannel(&adcObj->handle, &channelConf);
+
+    if (HAL_OK != HAL_ADC_Polling(&adcObj->handle, (uint32_t *)value, 1, 100))
+    {
+        return -RT_ERROR;
+    }
+    *value &= ~(HAL_ADC_EOC_FLAG);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops acm_adc_ops =
+{
+    .enabled = acm32_adc_enabled,
+    .convert = acm32_get_adc_value,
+};
+
+static int acm32_adc_init(void)
+{
+    return rt_hw_adc_register(&acm32_adc_obj.acm32_adc_device,
+                              ADC_NAME,
+                              &acm_adc_ops,
+                              RT_NULL);
+}
+INIT_BOARD_EXPORT(acm32_adc_init);
+
+#endif /* BSP_USING_ADC */
+

bsp/acm32f0x0-nucleo/drivers/drv_gpio.c

@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-08-26     AisinoChip        first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtconfig.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+
+#include <rtdevice.h>
+
+#define __ACM32_PIN(index, gpio, gpio_index)                                \
+    {                                                                       \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                            \
+    }
+
+#define __ACM32_PIN_RESERVE                                                 \
+    {                                                                       \
+        -1, 0, 0                                                            \
+    }
+
+/* ACM32 GPIO driver */
+struct pin_index
+{
+    int             index;
+    enum_GPIOx_t    gpio;
+    uint32_t        pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t         line;
+    EXTI_HandleTypeDef  handle;
+};
+
+static const struct pin_index pins[] =
+{
+#if defined(BSP_USING_GPIO1)
+    __ACM32_PIN(0,   A, 0),
+    __ACM32_PIN(1,   A, 1),
+    __ACM32_PIN(2,   A, 2),
+    __ACM32_PIN(3,   A, 3),
+    __ACM32_PIN(4,   A, 4),
+    __ACM32_PIN(5,   A, 5),
+    __ACM32_PIN(6,   A, 6),
+    __ACM32_PIN(7,   A, 7),
+    __ACM32_PIN(8,   A, 8),
+    __ACM32_PIN(9,   A, 9),
+    __ACM32_PIN(10,  A, 10),
+    __ACM32_PIN(11,  A, 11),
+    __ACM32_PIN(12,  A, 12),
+    __ACM32_PIN(13,  A, 13),
+    __ACM32_PIN(14,  A, 14),
+    __ACM32_PIN(15,  A, 15),
+    __ACM32_PIN(16,  B, 0),
+    __ACM32_PIN(17,  B, 1),
+    __ACM32_PIN(18,  B, 2),
+    __ACM32_PIN(19,  B, 3),
+    __ACM32_PIN(20,  B, 4),
+    __ACM32_PIN(21,  B, 5),
+    __ACM32_PIN(22,  B, 6),
+    __ACM32_PIN(23,  B, 7),
+    __ACM32_PIN(24,  B, 8),
+    __ACM32_PIN(25,  B, 9),
+    __ACM32_PIN(26,  B, 10),
+    __ACM32_PIN(27,  B, 11),
+    __ACM32_PIN(28,  B, 12),
+    __ACM32_PIN(29,  B, 13),
+    __ACM32_PIN(30,  B, 14),
+    __ACM32_PIN(31,  B, 15),
+#if defined(BSP_USING_GPIO2)
+    __ACM32_PIN(32,  C, 0),
+    __ACM32_PIN(33,  C, 1),
+    __ACM32_PIN(34,  C, 2),
+    __ACM32_PIN(35,  C, 3),
+    __ACM32_PIN(36,  C, 4),
+    __ACM32_PIN(37,  C, 5),
+    __ACM32_PIN(38,  C, 6),
+    __ACM32_PIN(39,  C, 7),
+    __ACM32_PIN(40,  C, 8),
+    __ACM32_PIN(41,  C, 9),
+    __ACM32_PIN(42,  C, 10),
+    __ACM32_PIN(43,  C, 11),
+    __ACM32_PIN(44,  C, 12),
+    __ACM32_PIN(45,  C, 13),
+    __ACM32_PIN(46,  C, 14),
+    __ACM32_PIN(47,  C, 15),
+    __ACM32_PIN(48,  D, 0),
+    __ACM32_PIN(49,  D, 1),
+    __ACM32_PIN(50,  D, 2),
+    __ACM32_PIN(51,  D, 3),
+    __ACM32_PIN(52,  D, 4),
+    __ACM32_PIN(53,  D, 5),
+    __ACM32_PIN(54,  D, 6),
+    __ACM32_PIN(55,  D, 7),
+    __ACM32_PIN(56,  D, 8),
+    __ACM32_PIN(57,  D, 9),
+    __ACM32_PIN(58,  D, 10),
+    __ACM32_PIN(59,  D, 11),
+    __ACM32_PIN(60,  D, 12),
+    __ACM32_PIN(61,  D, 13),
+    __ACM32_PIN(62,  D, 14),
+    __ACM32_PIN(63,  D, 15),
+#endif /* defined(BSP_USING_GPIO2) */
+#endif /* defined(BSP_USING_GPIO1) */
+};
+
+static struct pin_irq_map pin_irq_map[] =
+{
+    {EXTI_LINE_0,  {0}},
+    {EXTI_LINE_1,  {0}},
+    {EXTI_LINE_2,  {0}},
+    {EXTI_LINE_3,  {0}},
+    {EXTI_LINE_4,  {0}},
+    {EXTI_LINE_5,  {0}},
+    {EXTI_LINE_6,  {0}},
+    {EXTI_LINE_7,  {0}},
+    {EXTI_LINE_8,  {0}},
+    {EXTI_LINE_9,  {0}},
+    {EXTI_LINE_10, {0}},
+    {EXTI_LINE_11, {0}},
+    {EXTI_LINE_12, {0}},
+    {EXTI_LINE_13, {0}},
+    {EXTI_LINE_14, {0}},
+    {EXTI_LINE_15, {0}},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void acm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
+}
+
+static int acm32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = HAL_GPIO_ReadPin(index->gpio, index->pin);
+
+    return value;
+}
+
+static void acm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.Pin = index->pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+
+    /* special PIN process */
+    __HAL_RTC_PC13_DIGIT();
+
+    HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+}
+
+#define     PIN2INDEX(pin)      ((pin) % 16)
+
+static rt_err_t acm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t acm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t acm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+    irqmap = &pin_irq_map[irqindex];
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.Pin = index->pin;
+        GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+
+        irqmap->handle.u32_Line = irqmap->line;
+        irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.Pull = GPIO_PULLUP;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.Pull = GPIO_NOPULL;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
+            break;
+        }
+        HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+
+        irqmap->handle.u32_GPIOSel = pin / 16;
+
+        HAL_EXTI_SetConfigLine(&irqmap->handle);
+
+        pin_irq_enable_mask |= 1 << irqindex;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        EXTI->IENR &= ~irqmap->line;
+        EXTI->EENR &= ~irqmap->line;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _acm32_pin_ops =
+{
+    acm32_pin_mode,
+    acm32_pin_write,
+    acm32_pin_read,
+    acm32_pin_attach_irq,
+    acm32_pin_dettach_irq,
+    acm32_pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+void EXTI_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < 16; i++)
+    {
+        if (EXTI->PDR & pin_irq_map[i].line)
+        {
+            EXTI->PDR = pin_irq_map[i].line;
+            pin_irq_hdr(i);
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_PIN */
+

bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c

@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-26     AisinoChip   first version
+ */
+
+#include <board.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef BSP_USING_TIM
+#include "tim_config.h"
+
+#ifdef RT_USING_HWTIMER
+enum
+{
+#ifdef BSP_USING_TIM1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM3
+    TIM3_INDEX,
+#endif
+#ifdef BSP_USING_TIM6
+    TIM6_INDEX,
+#endif
+#ifdef BSP_USING_TIM14
+    TIM14_INDEX,
+#endif
+#ifdef BSP_USING_TIM15
+    TIM15_INDEX,
+#endif
+#ifdef BSP_USING_TIM16
+    TIM16_INDEX,
+#endif
+#ifdef BSP_USING_TIM17
+    TIM17_INDEX,
+#endif
+};
+
+struct acm32_hwtimer
+{
+    rt_hwtimer_t            time_device;
+    TIM_HandleTypeDef       tim_handle;
+    IRQn_Type               tim_irqn;
+    char                    *name;
+};
+
+static struct acm32_hwtimer acm32_hwtimer_obj[] =
+{
+#ifdef BSP_USING_TIM1
+    TIM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM3
+    TIM3_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM6
+    TIM6_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM14
+    TIM14_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM15
+    TIM15_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM16
+    TIM16_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM17
+    TIM17_CONFIG,
+#endif
+};
+
+static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
+{
+    rt_uint32_t timer_clock = 0;
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+    if (state)
+    {
+        tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+        /* time init */
+        timer_clock = System_Get_APBClock();
+        if (System_Get_SystemClock() != System_Get_APBClock())  /* if hclk/pclk != 1, then timer clk = pclk * 2 */
+        {
+            timer_clock =  System_Get_APBClock() << 1;
+        }
+
+        tim->Init.Period            = (timer->freq) - 1;
+        tim->Init.Prescaler         = (timer_clock / timer->freq) - 1 ;
+
+        tim->Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1;
+        if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
+        {
+            tim->Init.CounterMode   = TIM_COUNTERMODE_UP;
+        }
+        else
+        {
+            tim->Init.CounterMode   = TIM_COUNTERMODE_DOWN;
+        }
+        tim->Init.RepetitionCounter = 0;
+        tim->Init.ARRPreLoadEn = TIM_ARR_PRELOAD_ENABLE;
+
+        HAL_TIMER_MSP_Init(tim);
+        HAL_TIMER_Base_Init(tim);
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    /* set tim cnt */
+    tim->Instance->CNT = 0;
+    /* set tim arr */
+    tim->Instance->ARR = t - 1;
+
+    if (opmode == HWTIMER_MODE_ONESHOT)
+    {
+        /* set timer to single mode */
+        SET_BIT(tim->Instance->CR1, BIT3);
+    }
+    else
+    {
+        /* set timer to period mode */
+        CLEAR_BIT(tim->Instance->CR1, BIT3);
+    }
+
+    /* enable IRQ */
+    HAL_TIM_ENABLE_IT(tim, TIMER_INT_EN_UPD);
+
+    /* start timer */
+    HAL_TIMER_Base_Start(tim->Instance);
+
+    return RT_EOK;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    /* stop timer */
+    HAL_TIMER_Base_Stop(tim->Instance);
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(arg != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint32_t freq;
+        rt_uint32_t timer_clock;
+        rt_uint16_t val;
+
+        /* set timer frequence */
+        freq = *((rt_uint32_t *)arg);
+
+        timer_clock = System_Get_APBClock();
+        if (System_Get_SystemClock() != System_Get_APBClock())  /* if hclk/pclk != 1, then timer clk = pclk * 2 */
+        {
+            timer_clock =  System_Get_APBClock() << 1;
+        }
+
+        val = timer_clock / freq;
+        tim->Instance->PSC = val - 1;
+
+        /* Update frequency value */
+        tim->Instance->CR1 = BIT2;  /* CEN=0, URS=1, OPM = 0 */
+        tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
+    }
+    break;
+    default:
+    {
+        result = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return result;
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    return ((TIM_HandleTypeDef *)timer->parent.user_data)->Instance->CNT;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static const struct rt_hwtimer_ops _ops =
+{
+    .init = timer_init,
+    .start = timer_start,
+    .stop = timer_stop,
+    .count_get = timer_counter_get,
+    .control = timer_ctrl,
+};
+
+#ifdef BSP_USING_TIM1
+void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* interrupt service routine */
+    if (TIM1->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM1_INDEX].time_device);
+    }
+
+    TIM1->SR = 0;   /* write 0 to clear hardware flag */
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIM3
+void TIM3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (TIM3->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM3_INDEX].time_device);
+    }
+
+    TIM3->SR = 0;   /* write 0 to clear hardware flag */
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIM6
+void TIM6_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* interrupt service routine */
+    if (TIM6->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM6_INDEX].time_device);
+    }
+    TIM6->SR = 0;   /* write 0 to clear hardware flag */
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM14
+void TIM14_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* interrupt service routine */
+    if (TIM14->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM14_INDEX].time_device);
+    }
+    TIM14->SR = 0;   /* write 0 to clear hardware flag */
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM15
+void TIM15_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* interrupt service routine */
+    if (TIM15->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM15_INDEX].time_device);
+    }
+    TIM15->SR = 0;   /* write 0 to clear hardware flag */
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM16
+void TIM16_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (TIM16->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM16_INDEX].time_device);
+    }
+    TIM16->SR = 0;   /* write 0 to clear hardware flag */
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM17
+void TIM17_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (TIM17->SR & TIMER_SR_UIF)
+    {
+        rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM17_INDEX].time_device);
+    }
+    TIM17->SR = 0;   /* write 0 to clear hardware flag */
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+static int acm32_hwtimer_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(acm32_hwtimer_obj) / sizeof(acm32_hwtimer_obj[0]); i++)
+    {
+        acm32_hwtimer_obj[i].time_device.info = &_info;
+        acm32_hwtimer_obj[i].time_device.ops  = &_ops;
+        result = rt_device_hwtimer_register(&acm32_hwtimer_obj[i].time_device,
+                                            acm32_hwtimer_obj[i].name,
+                                            &acm32_hwtimer_obj[i].tim_handle);
+        if (result != RT_EOK)
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(acm32_hwtimer_init);
+
+#endif /* RT_USING_HWTIMER */
+#endif /* BSP_USING_TIM */
+

bsp/acm32f0x0-nucleo/drivers/drv_wdt.c

@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-08-25     AisinoChip        First Version
+ */
+
+#include <board.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+
+#ifdef RT_USING_WDT
+#include "board.h"
+
+struct acm32_wdt_obj
+{
+    union
+    {
+        WDT_HandleTypeDef       wdt;
+        IWDT_HandleTypeDef      iwdt;
+    } handle;
+    rt_uint16_t             is_start;
+    rt_uint16_t             type;
+    rt_watchdog_t           watchdog;
+};
+
+#define TYPE_WDT         0
+#define TYPE_IWDT        1
+#define IWDT_FREQ        (32000)
+
+#ifdef BSP_USING_WDT
+    #define WDT_NAME        "wdt"
+    static struct acm32_wdt_obj acm32_wdt;
+#endif
+
+#ifdef BSP_USING_IWDT
+    #define IWDT_NAME       "iwdt"
+    static struct acm32_wdt_obj acm32_iwdt;
+#endif
+
+static struct rt_watchdog_ops ops;
+
+rt_inline rt_base_t calc_wdt_divisor_load(rt_uint32_t freq, rt_uint32_t sec, rt_uint32_t *divisor, rt_uint32_t *load)
+{
+    rt_uint32_t freqMaxSec = 0;
+    rt_uint32_t minFreqDiv = WDT_DIVISOR_NONE;
+
+    freqMaxSec = RT_UINT32_MAX / freq;
+
+    while (minFreqDiv <= WDT_DIVISOR_128)
+    {
+        if (sec < freqMaxSec)
+        {
+            break;
+        }
+        minFreqDiv ++;
+        freqMaxSec = RT_UINT32_MAX / freq * (1 << minFreqDiv);
+    }
+
+    if (minFreqDiv > WDT_DIVISOR_128)
+    {
+        return -1;
+    }
+
+    *divisor = minFreqDiv;
+    *load = sec * (freq >> minFreqDiv);
+    return 0;
+}
+
+rt_inline rt_base_t calc_iwdt_divisor_load(rt_uint32_t freq, rt_uint32_t sec, rt_uint32_t *divisor, rt_uint32_t *load)
+{
+    rt_uint32_t minFreqDiv = IWDT_CLOCK_PRESCALER_4;
+    rt_uint32_t freqMaxMs = 0;
+
+    freqMaxMs = IWDT_RELOAD_MAX_VALUE * 1000 / (freq >> (2 + minFreqDiv));
+
+    while (minFreqDiv <= IWDT_CLOCK_PRESCALER_256)
+    {
+        if (sec * 1000 < freqMaxMs)
+        {
+            break;
+        }
+        minFreqDiv ++;
+        freqMaxMs = IWDT_RELOAD_MAX_VALUE * 1000 / (freq >> (2 + minFreqDiv));
+    }
+
+    if (minFreqDiv > IWDT_CLOCK_PRESCALER_256)
+    {
+        return -1;
+    }
+
+    *divisor = minFreqDiv;
+    if (sec < 1000)
+    {
+        *load = (sec * 1000) * IWDT_RELOAD_MAX_VALUE / freqMaxMs;
+    }
+    else
+    {
+        *load = (sec) * IWDT_RELOAD_MAX_VALUE / freqMaxMs / 1000;
+    }
+    return 0;
+}
+
+rt_inline rt_uint32_t calc_wdt_timeout(rt_uint32_t freq, rt_uint32_t divisor, rt_uint32_t count)
+{
+    /* 1 / ( freq / (1<<divisor) ) * (count) */
+    return (rt_uint32_t)(((rt_uint64_t)count) * (1 << divisor) / (freq));
+}
+
+rt_inline rt_uint32_t calc_iwdt_timeout(rt_uint32_t freq, rt_uint32_t divisor, rt_uint32_t count)
+{
+    /* (freq >> (2+divisor)) / IWDT_RELOAD_MAX_VALUE * count */
+    return count / (freq >> (2 + divisor));
+}
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    struct acm32_wdt_obj *wdtObj = NULL;
+    rt_uint32_t timer_clk_hz;
+    rt_uint32_t divisor, load;
+
+    RT_ASSERT(wdt != RT_NULL);
+
+    wdtObj = rt_container_of(wdt, struct acm32_wdt_obj, watchdog);
+    timer_clk_hz = System_Get_APBClock();
+
+    switch (cmd)
+    {
+    /* feed the watchdog */
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            HAL_WDT_Feed(&wdtObj->handle.wdt);
+        }
+        else
+        {
+            HAL_IWDT_Kick_Watchdog_Wait_For_Done(&wdtObj->handle.iwdt);
+        }
+        break;
+    /* set watchdog timeout, seconds */
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            if (calc_wdt_divisor_load(timer_clk_hz, (*((rt_uint32_t *)arg)), &divisor, &load))
+            {
+                return -RT_ERROR;
+            }
+            wdtObj->handle.wdt.Init.WDTDivisor = (WDT_DIVISOR)divisor;
+            wdtObj->handle.wdt.Init.WDTLoad = load;
+            HAL_WDT_Init(&wdtObj->handle.wdt);
+        }
+        else
+        {
+            if (calc_iwdt_divisor_load(IWDT_FREQ, (*((rt_uint32_t *)arg)), &divisor, &load))
+            {
+                return -RT_ERROR;
+            }
+            wdtObj->handle.iwdt.Instance = IWDT;
+            wdtObj->handle.iwdt.Init.Prescaler = divisor;
+            wdtObj->handle.iwdt.Init.Reload = load;
+        }
+
+        if (wdtObj->is_start)
+        {
+            if (TYPE_WDT == wdtObj->type)
+            {
+                HAL_WDT_Init(&wdtObj->handle.wdt);
+            }
+            else
+            {
+                HAL_IWDT_Init(&wdtObj->handle.iwdt);
+            }
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            (*((rt_uint32_t *)arg)) = calc_wdt_timeout(timer_clk_hz,
+                                      wdtObj->handle.wdt.Init.WDTDivisor,
+                                      wdtObj->handle.wdt.Instance->COUNT);
+        }
+        else
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            (*((rt_uint32_t *)arg)) = calc_wdt_timeout(timer_clk_hz,
+                                      wdtObj->handle.wdt.Init.WDTDivisor,
+                                      wdtObj->handle.wdt.Init.WDTLoad);
+        }
+        else
+        {
+            (*((rt_uint32_t *)arg)) = calc_iwdt_timeout(IWDT_FREQ,
+                                      wdtObj->handle.iwdt.Init.Prescaler,
+                                      wdtObj->handle.iwdt.Init.Reload);
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            wdtObj->handle.wdt.Instance = WDT;
+            wdtObj->handle.wdt.Init.WDTMode = WDT_MODE_RST;
+            wdtObj->handle.wdt.Init.WDTINTCLRTIME = 0xffff;
+            HAL_WDT_Init(&wdtObj->handle.wdt);
+            HAL_WDT_Start(&wdtObj->handle.wdt);
+        }
+        else
+        {
+            wdtObj->handle.iwdt.Instance->CMDR = IWDT_ENABLE_COMMAND;
+            wdtObj->handle.iwdt.Init.Window = IWDT_RELOAD_MAX_VALUE;  /* window function disabled when window >= reload */
+            wdtObj->handle.iwdt.Init.Wakeup = IWDT_RELOAD_MAX_VALUE;  /* wakeup function disabled when wakeup >= reload */
+            HAL_IWDT_Init(&wdtObj->handle.iwdt);
+        }
+        wdtObj->is_start = 1;
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        if (TYPE_WDT == wdtObj->type)
+        {
+            HAL_WDT_Stop(&wdtObj->handle.wdt);
+        }
+        else
+        {
+            wdtObj->handle.iwdt.Instance->CMDR = IWDT_DISABLE_COMMAND;
+        }
+        wdtObj->is_start = 0;
+        break;
+    default:
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int rt_wdt_init(void)
+{
+    ops.init = &wdt_init;
+    ops.control = &wdt_control;
+
+#ifdef BSP_USING_WDT
+    acm32_wdt.type = TYPE_WDT;
+    acm32_wdt.is_start = 0;
+    acm32_wdt.watchdog.ops = &ops;
+    if (rt_hw_watchdog_register(&acm32_wdt.watchdog, WDT_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+#endif
+#ifdef BSP_USING_IWDT
+    acm32_iwdt.type = TYPE_IWDT;
+    acm32_iwdt.is_start = 0;
+    acm32_iwdt.watchdog.ops = &ops;
+    if (rt_hw_watchdog_register(&acm32_iwdt.watchdog, IWDT_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_wdt_init);
+
+#endif /* RT_USING_WDT */
+

bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.lds

@@ -0,0 +1,155 @@
+/*
+ * linker script for ACM32F030 with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 128k /* 128KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 32k  /* 32KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > ROM = 8
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } > RAM
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } > RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+

bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.sct

@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/acm32f0x0-nucleo/drivers/tim_config.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-26     AisinoChip   first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM1
+#ifndef TIM1_CONFIG
+#define TIM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .tim_irqn                = TIM1_BRK_UP_TRG_COM_IRQn,    \
+       .name                    = "timer1",     \
+    }
+#endif /* TIM1_CONFIG */
+#endif /* BSP_USING_TIM1 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM6
+#ifndef TIM6_CONFIG
+#define TIM6_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM6,         \
+       .tim_irqn                = TIM6_IRQn,    \
+       .name                    = "timer6",     \
+    }
+#endif /* TIM6_CONFIG */
+#endif /* BSP_USING_TIM6 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM14,         \
+       .tim_irqn                = TIM14_IRQn,    \
+       .name                    = "timer14",     \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM15,         \
+       .tim_irqn                = TIM15_IRQn,    \
+       .name                    = "timer15",     \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM16,         \
+       .tim_irqn                = TIM16_IRQn,    \
+       .name                    = "timer16",     \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM17,         \
+       .tim_irqn                = TIM17_IRQn,    \
+       .name                    = "timer17",     \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/acm32f0x0-nucleo/drivers/uart_config.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */

bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmFunc.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmInstr.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0.s

@@ -0,0 +1,215 @@
+;* File Name          : Startup_ACM32F0x0.s
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F0x0 Devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the SC000 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+
+Stack_Size      EQU     0x00000800
+Heap_Size       EQU     0x00000000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT __Vectors
+
+__Vectors
+                DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler 
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler                  ; 0:  WDT_IRQHandler    
+                DCD     RTC_IRQHandler                  ; 1:  RTC_IRQHandler 
+                DCD     EFC_IRQHandler                  ; 2:  EFC_IRQHandler 
+                DCD     GPIOAB_IRQHandler               ; 3:  GPIOAB_IRQHandler 
+                DCD     GPIOCD_IRQHandler               ; 4:  GPIOCD_IRQHandler
+                DCD     EXTI_IRQHandler                 ; 5:  EXTI_IRQHandler 
+                DCD     SRAM_PARITY_IRQHandler          ; 6:  SRAM_PARITY_IRQHandler
+                DCD     CLKRDY_IRQHandler               ; 7:  CLKRDY_IRQHandler
+                DCD     LCD_IRQHandler                  ; 8:  LCD_IRQHandler
+                DCD     DMA_IRQHandler                  ; 9:  DMA_IRQHandler
+                DCD     UART3_IRQHandler                ; 10: UART3_IRQHandler
+                DCD     TKEY_IRQHandler                 ; 11: TKEY_IRQHandler
+                DCD     ADC_IRQHandler                  ; 12: ADC_IRQHandler
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler  ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler
+                DCD     TIM1_CC_IRQHandler              ; 14: TIM1_CC_IRQHandler
+                DCD     RSV_IRQHandler                  ; 15: Reserved
+                DCD     TIM3_IRQHandler                 ; 16: TIM3_IRQHandler 
+                DCD     TIM6_IRQHandler                 ; 17: TIM6_IRQHandler
+                DCD     RSV_IRQHandler                  ; 18: Reserved
+                DCD     TIM14_IRQHandler                ; 19: TIM14_IRQHandler
+                DCD     TIM15_IRQHandler                ; 20: TIM15_IRQHandler 
+                DCD     TIM16_IRQHandler                ; 21: TIM16_IRQHandler   
+                DCD     TIM17_IRQHandler                ; 22: TIM17_IRQHandler   
+                DCD     I2C1_IRQHandler                 ; 23: I2C1_IRQHandler    
+                DCD     I2C2_IRQHandler                 ; 24: I2C2_IRQHandler     
+                DCD     SPI1_IRQHandler                 ; 25: SPI1_IRQHandler    
+                DCD     SPI2_IRQHandler                 ; 26: SPI2_IRQHandler    
+                DCD     UART1_IRQHandler                ; 27: UART1_IRQHandler   
+                DCD     UART2_IRQHandler                ; 28: UART2_IRQHandler      
+                DCD     LPUART_IRQHandler               ; 29: LPUART_IRQHandler
+                DCD     CAN1_IRQHandler                 ; 30: CAN1_IRQHandler
+                DCD     AES_IRQHandler                  ; 31: AES_IRQHandler 
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler     PROC
+                  EXPORT  Reset_Handler             [WEAK]
+                  IMPORT  __main
+                  LDR     R0, =__main
+                  BX      R0
+                  ENDP
+
+
+NMI_Handler       PROC
+                  EXPORT  NMI_Handler               [WEAK]
+                  B       .
+                  ENDP
+HardFault_Handler PROC
+                  EXPORT  HardFault_Handler         [WEAK]
+                  B       .
+                  ENDP
+MemManage_Handler PROC
+                  EXPORT  MemManage_Handler         [WEAK]
+                  B       .
+                  ENDP
+SVC_Handler       PROC
+                  EXPORT  SVC_Handler               [WEAK]
+                  B       .
+                  ENDP
+PendSV_Handler    PROC
+                  EXPORT  PendSV_Handler            [WEAK]
+                  B       .
+                  ENDP
+SysTick_Handler   PROC
+                  EXPORT  SysTick_Handler           [WEAK]
+                  B       .
+                  ENDP
+
+Default_Handler PROC
+                EXPORT   WDT_IRQHandler                 [WEAK]
+                EXPORT   RTC_IRQHandler                 [WEAK]
+                EXPORT   EFC_IRQHandler                 [WEAK]
+                EXPORT   GPIOAB_IRQHandler              [WEAK]
+                EXPORT   GPIOCD_IRQHandler              [WEAK]
+                EXPORT   EXTI_IRQHandler                [WEAK]
+                EXPORT   SRAM_PARITY_IRQHandler         [WEAK]
+                EXPORT   CLKRDY_IRQHandler              [WEAK]
+                EXPORT   LCD_IRQHandler                 [WEAK]
+                EXPORT   DMA_IRQHandler                 [WEAK]
+                EXPORT   UART3_IRQHandler               [WEAK]
+                EXPORT   TKEY_IRQHandler                [WEAK]
+                EXPORT   ADC_IRQHandler                 [WEAK]
+                EXPORT   TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT   TIM1_CC_IRQHandler             [WEAK]
+                EXPORT   TIM3_IRQHandler                [WEAK]
+                EXPORT   TIM6_IRQHandler                [WEAK]
+                EXPORT   TIM14_IRQHandler               [WEAK]
+                EXPORT   TIM15_IRQHandler               [WEAK]
+                EXPORT   TIM16_IRQHandler               [WEAK]
+                EXPORT   TIM17_IRQHandler               [WEAK]
+                EXPORT   I2C1_IRQHandler                [WEAK]
+                EXPORT   I2C2_IRQHandler                [WEAK]
+                EXPORT   SPI1_IRQHandler                [WEAK]
+                EXPORT   SPI2_IRQHandler                [WEAK]
+                EXPORT   UART1_IRQHandler               [WEAK]
+                EXPORT   UART2_IRQHandler               [WEAK]
+                EXPORT   LPUART_IRQHandler              [WEAK]
+                EXPORT   CAN1_IRQHandler                [WEAK]
+                EXPORT   AES_IRQHandler                 [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+WDT_IRQHandler
+RTC_IRQHandler
+EFC_IRQHandler
+GPIOAB_IRQHandler
+GPIOCD_IRQHandler
+EXTI_IRQHandler
+SRAM_PARITY_IRQHandler
+CLKRDY_IRQHandler
+LCD_IRQHandler
+DMA_IRQHandler
+UART3_IRQHandler
+TKEY_IRQHandler
+ADC_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+LPUART_IRQHandler
+CAN1_IRQHandler
+AES_IRQHandler
+RSV_IRQHandler
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+                 
+                IF      :DEF:__MICROLIB
+                 
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                 
+                ELSE
+                 
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+                 
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                END

bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_gcc.s

@@ -0,0 +1,279 @@
+/*******************************************************************************
+;* File Name          : Startup_ACM32F0x0_gcc.s
+;* Version            : V1.0.0
+;* Date               : 2021
+;* Description        : ACM32F0x0 Devices vector table for GCC toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the SC000 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************/
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2, #4]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+/* Call the clock system intitialization function.*/
+  /* bl  SystemInit */
+/* Call the application's entry point.*/
+  bl entry
+LoopForever:
+    b LoopForever
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word 0
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+
+  /* External Interrupts */
+  .word WDT_IRQHandler                  /* 0:  WDT_IRQHandler   */
+  .word RTC_IRQHandler                  /* 1:  RTC_IRQHandler    */
+  .word EFC_IRQHandler                  /* 2:  EFC_IRQHandler    */
+  .word GPIOAB_IRQHandler               /* 3:  GPIOAB_IRQHandler */
+  .word GPIOCD_IRQHandler               /* 4:  GPIOCD_IRQHandler */
+  .word EXTI_IRQHandler                 /* 5:  EXTI_IRQHandler   */
+  .word SRAM_PARITY_IRQHandler          /* 6:  SRAM_PARITY_IRQHandler */
+  .word CLKRDY_IRQHandler               /* 7:  CLKRDY_IRQHandler */
+  .word LCD_IRQHandler                  /* 8:  LCD_IRQHandler    */
+  .word DMA_IRQHandler                  /* 9:  DMA_IRQHandler    */
+  .word UART3_IRQHandler                /* 10: UART3_IRQHandler  */
+  .word TKEY_IRQHandler                 /* 11: TKEY_IRQHandler   */
+  .word ADC_IRQHandler                  /* 12: ADC_IRQHandler    */
+  .word TIM1_BRK_UP_TRG_COM_IRQHandler  /* 13: TIM1_BRK_UP_TRG_COM_IRQHandler */
+  .word TIM1_CC_IRQHandler              /* 14: TIM1_CC_IRQHandler */
+  .word RSV_IRQHandler                  /* 15: Reserved          */
+  .word TIM3_IRQHandler                 /* 16: TIM3_IRQHandler   */
+  .word TIM6_IRQHandler                 /* 17: TIM6_IRQHandler   */
+  .word RSV_IRQHandler                  /* 18: Reserved          */
+  .word TIM14_IRQHandler                /* 19: TIM14_IRQHandler  */
+  .word TIM15_IRQHandler                /* 20: TIM15_IRQHandler  */
+  .word TIM16_IRQHandler                /* 21: TIM16_IRQHandler  */
+  .word TIM17_IRQHandler                /* 22: TIM17_IRQHandler  */
+  .word I2C1_IRQHandler                 /* 23: I2C1_IRQHandler   */
+  .word I2C2_IRQHandler                 /* 24: I2C2_IRQHandler   */
+  .word SPI1_IRQHandler                 /* 25: SPI1_IRQHandler   */
+  .word SPI2_IRQHandler                 /* 26: SPI2_IRQHandler   */
+  .word UART1_IRQHandler                /* 27: UART1_IRQHandler  */
+  .word UART2_IRQHandler                /* 28: UART2_IRQHandler  */
+  .word LPUART_IRQHandler               /* 29: LPUART_IRQHandler */
+  .word CAN1_IRQHandler                 /* 30: CAN1_IRQHandler   */
+  .word AES_IRQHandler                  /* 31: AES_IRQHandler    */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WDT_IRQHandler
+  .thumb_set WDT_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak EFC_IRQHandler
+  .thumb_set EFC_IRQHandler,Default_Handler
+
+  .weak GPIOAB_IRQHandler
+  .thumb_set GPIOAB_IRQHandler,Default_Handler
+
+  .weak GPIOCD_IRQHandler
+  .thumb_set GPIOCD_IRQHandler,Default_Handler
+
+  .weak EXTI_IRQHandler
+  .thumb_set EXTI_IRQHandler,Default_Handler
+
+  .weak SRAM_PARITY_IRQHandler
+  .thumb_set SRAM_PARITY_IRQHandler,Default_Handler
+
+  .weak CLKRDY_IRQHandler
+  .thumb_set CLKRDY_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler
+
+  .weak DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Default_Handler
+
+  .weak UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Default_Handler
+
+  .weak TKEY_IRQHandler
+  .thumb_set TKEY_IRQHandler,Default_Handler
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Default_Handler
+
+  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak RSV_IRQHandler
+  .thumb_set RSV_IRQHandler,Default_Handler
+
+  .weak TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak I2C1_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Default_Handler
+
+  .weak UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Default_Handler
+
+  .weak LPUART_IRQHandler
+  .thumb_set LPUART_IRQHandler,Default_Handler
+
+  .weak CAN1_IRQHandler
+  .thumb_set CAN1_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT AisinoChip *****END OF FILE****/

bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_iar.s

@@ -0,0 +1,278 @@
+;* File Name          : Startup_ACM32F0x0.s
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F0x0 Devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the SC000 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                  ; Reset Handler
+
+        DCD     NMI_Handler                    ; NMI Handler
+        DCD     HardFault_Handler              ; Hard Fault Handler
+        DCD     MemManage_Handler              ; MemManage_Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     SVC_Handler                    ; SVCall Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     PendSV_Handler                 ; PendSV Handler
+        DCD     SysTick_Handler                ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WDT_IRQHandler                  ; 0:  WDT_IRQHandler
+        DCD     RTC_IRQHandler                  ; 1:  RTC_IRQHandler
+        DCD     EFC_IRQHandler                  ; 2:  EFC_IRQHandler
+        DCD     GPIOAB_IRQHandler               ; 3:  GPIOAB_IRQHandler
+        DCD     GPIOCD_IRQHandler               ; 4:  GPIOCD_IRQHandler
+        DCD     EXTI_IRQHandler                 ; 5:  EXTI_IRQHandler
+        DCD     SRAM_PARITY_IRQHandler          ; 6:  SRAM_PARITY_IRQHandler
+        DCD     CLKRDY_IRQHandler               ; 7:  CLKRDY_IRQHandler
+        DCD     LCD_IRQHandler                  ; 8:  LCD_IRQHandler
+        DCD     DMA_IRQHandler                  ; 9:  DMA_IRQHandler
+        DCD     UART3_IRQHandler                ; 10: UART3_IRQHandler
+        DCD     TKEY_IRQHandler                 ; 11: TKEY_IRQHandler
+        DCD     ADC_IRQHandler                  ; 12: ADC_IRQHandler
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler  ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler
+        DCD     TIM1_CC_IRQHandler              ; 14: TIM1_CC_IRQHandler
+        DCD     RSV_IRQHandler                  ; 15: Reserved
+        DCD     TIM3_IRQHandler                 ; 16: TIM3_IRQHandler
+        DCD     TIM6_IRQHandler                 ; 17: TIM6_IRQHandler
+        DCD     RSV_IRQHandler                  ; 18: Reserved
+        DCD     TIM14_IRQHandler                ; 19: TIM14_IRQHandler
+        DCD     TIM15_IRQHandler                ; 20: TIM15_IRQHandler
+        DCD     TIM16_IRQHandler                ; 21: TIM16_IRQHandler
+        DCD     TIM17_IRQHandler                ; 22: TIM17_IRQHandler
+        DCD     I2C1_IRQHandler                 ; 23: I2C1_IRQHandler
+        DCD     I2C2_IRQHandler                 ; 24: I2C2_IRQHandler
+        DCD     SPI1_IRQHandler                 ; 25: SPI1_IRQHandler
+        DCD     SPI2_IRQHandler                 ; 26: SPI2_IRQHandler
+        DCD     UART1_IRQHandler                ; 27: UART1_IRQHandler
+        DCD     UART2_IRQHandler                ; 28: UART2_IRQHandler
+        DCD     LPUART_IRQHandler               ; 29: LPUART_IRQHandler
+        DCD     CAN1_IRQHandler                 ; 30: CAN1_IRQHandler
+        DCD     AES_IRQHandler                  ; 31: AES_IRQHandler
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK EFC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EFC_IRQHandler
+        B EFC_IRQHandler
+
+        PUBWEAK GPIOAB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOAB_IRQHandler
+        B GPIOAB_IRQHandler
+
+        PUBWEAK GPIOCD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOCD_IRQHandler
+        B GPIOCD_IRQHandler
+
+        PUBWEAK EXTI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI_IRQHandler
+        B EXTI_IRQHandler
+
+        PUBWEAK SRAM_PARITY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SRAM_PARITY_IRQHandler
+        B SRAM_PARITY_IRQHandler
+
+        PUBWEAK CLKRDY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CLKRDY_IRQHandler
+        B CLKRDY_IRQHandler
+
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK TKEY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TKEY_IRQHandler
+        B TKEY_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK LPUART_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART_IRQHandler
+        B LPUART_IRQHandler
+
+        PUBWEAK CAN1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_IRQHandler
+        B CAN1_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RSV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RSV_IRQHandler
+        B RSV_IRQHandler
+
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h

@@ -0,0 +1,170 @@
+/*
+  ******************************************************************************
+  * @file    ACM32Fxx_HAL.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   HAL Config header file.
+  ******************************************************************************
+*/
+#ifndef __ACM32FXX_HAL_H__
+#define __ACM32FXX_HAL_H__
+#ifdef __GNUC__
+#define  __weak __attribute__((weak))
+#endif
+/*
+    Uncomment the line below according to the target device used in your application
+*/
+   #define ACM32F0X0       /*!< ACM32F0x0xx */
+/* #define ACM32FP0X */    /*!< ACM32FP0xxx */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(ACM32F0X0)
+    #include "ACM32F0x0.h"
+#elif defined(ACM32FP0X)
+    #include "ACM32FP0X.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+/**
+  * @}
+  */
+
+
+/*
+ * @brief  HAL Status structures definition
+ */
+typedef enum
+{
+    HAL_OK       = 0x00U,
+    HAL_ERROR    = 0x01U,
+    HAL_BUSY     = 0x02U,
+    HAL_TIMEOUT  = 0x03U
+}HAL_StatusTypeDef;
+
+/* USE FULL ASSERT */
+#define USE_FULL_ASSERT    (1)
+
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDT_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_EFLASH_MODULE_ENABLED
+#define HAL_OPA_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_LPUART_MODULE_ENABLED
+#define HAL_WDT_MODULE_ENABLED
+#define HAL_FSUSB_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+//#define HAL_SYSTICK_ENABLED
+#define HAL_CRC_ENABLED
+#define HAL_TKEY_MODULE_ENABLED
+#define HAL_AES_ENABLED
+#define HAL_HRNG_ENABLED
+#define HAL_DIV_ENABLED
+
+#include "System_ACM32F0x0.h"
+
+#ifdef HAL_DMA_MODULE_ENABLED
+    #include "HAL_DMA.h"
+#endif
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+    #include "HAL_GPIO.h"
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+    #include "HAL_UART.h"
+    #include "HAL_UART_EX.h"
+#endif
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    #include "HAL_ADC.h"
+#endif
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+    #include "HAL_EXTI.h"
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+    #include "HAL_I2C.h"
+#endif
+
+
+#ifdef HAL_RTC_MODULE_ENABLED
+    #include "HAL_RTC.h"
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+    #include "HAL_SPI.h"
+#endif
+
+#ifdef HAL_IWDT_MODULE_ENABLED
+    #include "HAL_IWDT.h"
+#endif
+
+#ifdef HAL_EFLASH_MODULE_ENABLED
+    #include "HAL_EFLASH.h"
+    #include "HAL_EFlash_EX.h"
+#endif
+
+#ifdef HAL_OPA_MODULE_ENABLED
+    #include "HAL_OPA.h"
+#endif
+
+#ifdef HAL_COMP_MODULE_ENABLED
+    #include "HAL_COMP.h"
+#endif
+
+#ifdef HAL_CAN_MODULE_ENABLED
+    #include "HAL_CAN.h"
+#endif
+
+#ifdef HAL_LPUART_MODULE_ENABLED
+    #include "HAL_LPUART.h"
+#endif
+
+#ifdef HAL_WDT_MODULE_ENABLED
+    #include "HAL_WDT.h"
+#endif
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+    #include "HAL_TIMER.h"
+    #include "HAL_TIMER_EX.h"
+#endif
+#ifdef HAL_LCD_MODULE_ENABLED
+    #include "HAL_LCD.h"
+#endif
+
+
+#ifdef HAL_TKEY_MODULE_ENABLED
+    #include "HAL_TKEY.h"
+#endif
+#ifdef HAL_CRC_ENABLED
+#include  "HAL_CRC.h"
+#endif
+
+#ifdef  HAL_AES_ENABLED
+#include  "HAL_AES.h"
+#endif
+
+#ifdef HAL_HRNG_ENABLED
+#include "HAL_HRNG.h"
+#endif
+
+#ifdef HAL_DIV_ENABLED
+#include "HAL_DIV.h"
+#endif
+
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h

@@ -0,0 +1,83 @@
+/***********************************************************************
+ * Copyright (c)  2008 - 2016, Shanghai AisinoChip Co.,Ltd .
+ * All rights reserved.
+ * Filename    : aes.h
+ * Description : aes driver header file
+ * Author(s)   : Eric
+ * version     : V1.0
+ * Modify date : 2016-03-24
+ ***********************************************************************/
+#ifndef __AES_H__
+#define __AES_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define AES_ENCRYPTION          1
+#define AES_DECRYPTION          0
+#define AES_ECB_MODE            0
+#define AES_CBC_MODE            1
+#define AES_SWAP_ENABLE         1
+#define AES_SWAP_DISABLE        0
+
+#define AES_NORMAL_MODE     0x12345678
+#define AES_SECURITY_MODE   0
+
+#define AES_KEY_128     0
+#define AES_KEY_192     1
+#define AES_KEY_256     2
+
+#define AES_FAIL   0x00
+#define AES_PASS   0xa59ada68
+
+/******************************************************************************
+Name:      HAL_AES_Set_Key
+Function:  set aes key for encryption and decryption
+Input:
+           keyin     --    pointer to buffer of key
+           swap_en   --    AES_SWAP_ENABLE, AES_SWAP_DISABLE
+Return:    None
+*******************************************************************************/
+void HAL_AES_Set_Key(UINT32 *keyin, UINT8 key_len, UINT8 swap_en);
+void HAL_AES_Set_Key_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en);
+
+
+/******************************************************************************
+
+Name:        HAL_Aes_Crypt
+Function:    Function for des encryption and decryption
+Input:
+             indata            --  pointer to buffer of input
+             outdata           --  pointer to buffer of result
+             block_len         --  block(128bit) length for des cryption
+             operation         --  AES_ENCRYPTION,AES_DECRYPTION
+             mode              --  AES_ECB_MODE, AES_CBC_MODE,
+             iv                --  initial vector for CBC mode
+             security_mode     --  AES_NORMAL_MODE, AES_SECURITY_MDOE，
+Return:      None
+
+*******************************************************************************/
+UINT32 HAL_AES_Crypt(
+    UINT32 *indata,
+    UINT32 *outdata,
+    UINT32 block_len,
+    UINT8  operation,
+    UINT8  mode,
+    UINT32 *iv,
+    UINT32 security_mode
+);
+
+
+UINT32 HAL_AES_Crypt_U8(
+    UINT8 *indata,
+    UINT8 *outdata,
+    UINT32 block_len,
+    UINT8  operation,
+    UINT8  mode,
+    UINT8 *iv,
+    UINT32 security_mode
+);
+
+#endif
+/******************************************************************************
+ * end of file
+*******************************************************************************/

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h

@@ -0,0 +1,393 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Can.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CAN_H__
+#define __HAL_CAN_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/**
+  * @}
+  */
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+/******************************************************************************/
+/*                                    (CAN)                                   */
+/******************************************************************************/
+
+/****************  Bit definition for CAN MOD register  ***********************/
+#define CAN_MOD_RM                      BIT0
+#define CAN_MOD_LOM                     BIT1
+#define CAN_MOD_STM                     BIT2
+#define CAN_MOD_AFM                     BIT3
+#define CAN_MOD_SM                      BIT4
+/****************  Bit definition for CAN CMR register  ***********************/
+#define CAN_CMR_TR                      BIT0
+#define CAN_CMR_AT                      BIT1
+#define CAN_CMR_RRB                     BIT2
+#define CAN_CMR_CDO                     BIT3
+#define CAN_CMR_SRR                     BIT4
+/****************  Bit definition for CAN SR register  ***********************/
+#define CAN_SR_RBS                      BIT0
+#define CAN_SR_DOS                      BIT1
+#define CAN_SR_TBS                      BIT2
+#define CAN_SR_TCS                      BIT3
+#define CAN_SR_RS                       BIT4
+#define CAN_SR_TS                       BIT5
+#define CAN_SR_ES                       BIT6
+#define CAN_SR_BS                       BIT7
+/****************  Bit definition for CAN IR register  ***********************/
+#define CAN_IR_RI                       BIT0
+#define CAN_IR_TI                       BIT1
+#define CAN_IR_EI                       BIT2
+#define CAN_IR_DOI                      BIT3
+#define CAN_IR_WUI                      BIT4
+#define CAN_IR_EPI                      BIT5
+#define CAN_IR_ALI                      BIT6
+#define CAN_IR_BEI                      BIT7
+/****************  Bit definition for CAN IER register  ***********************/
+#define CAN_IER_RIE                     BIT0
+#define CAN_IER_TIE                     BIT1
+#define CAN_IER_EIE                     BIT2
+#define CAN_IER_DOIE                    BIT3
+#define CAN_IER_WUIE                    BIT4
+#define CAN_IER_EPIE                    BIT5
+#define CAN_IER_ALIE                    BIT6
+#define CAN_IER_BEIE                    BIT7
+
+/**
+  * @brief  CAN  init structure definition
+  */
+typedef struct
+{
+    uint32_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of
+                                @ref CAN_mode  e.g:CAN_Mode_Normal   CAN_Mode_Normal*/
+
+    uint32_t CAN_SJW;          /*!< Specifies the maximum number of time quanta
+                                the CAN hardware is allowed to lengthen or
+                                shorten a bit to perform resynchronization.
+                                This parameter can be a value of
+                                @ref CAN_SJW  e.g:CAN_SJW_1tq--CAN_SJW_4tq*/
+
+    uint32_t CAN_BRP ;          /*!< Specifies the number of time quanta in Bit
+                                Segment 1. This parameter can be a value between 0 and 63 */
+
+    uint32_t CAN_TSEG1;          /*!< Specifies the number of time quanta in Bit
+                                Segment 1. This parameter can be a value of
+                                @ref CAN_TSEG1  e.g: CAN_TSEG1_1tq-CAN_TSEG1_16tq*/
+
+    uint32_t CAN_TSEG2;          /*!< Specifies the number of time quanta in Bit
+                                Segment 2.This parameter can be a value of
+                                @ref CAN_TSEG2  e.g:CAN_TSEG1_1tq-CAN_TSEG16_tq*/
+
+    uint32_t CAN_SAM ;           /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of
+                                @ref CAN_SAM e.g:CAN_SAM_1time  CAN_SAM_3time*/
+} CAN_InitTypeDef;
+
+
+/**
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+    uint32_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                        This parameter can be a value of
+                                        @ref CAN_filter_mode  e.g:CAN_FilterMode_Dual    CAN_FilterMode_Single*/
+
+    uint32_t CAN_FilterId1;             /*!< Specifies the filter identification number
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+
+    uint32_t CAN_FilterId2;             /*!< Specifies the filter identification number
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+
+    uint32_t CAN_FilterMaskId1;         /*!< Specifies the filter identification mask number
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+
+    uint32_t CAN_FilterMaskId2;         /*!< Specifies the filter identification mask number
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+} CAN_FilterInitTypeDef;
+
+
+
+/**
+  * @brief  CAN RxTxMessege structure definition
+  */
+typedef struct
+{
+    uint32_t StdId;                     /*!< Specifies the standard identifier.
+                                        This parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t ExtId;                     /*!< Specifies the extended identifier.
+                                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    uint32_t IDE;                        /*!< Specifies the type of identifier for the message that
+                                        will be transmitted. This parameter can be a value
+                                        of @ref CAN_identifier_type  e.g: CAN_Id_Standard  CAN_Id_Extended*/
+
+    uint32_t RTR;                        /*!< Specifies the type of frame for the message that will
+                                        be transmitted. This parameter can be a value of
+                                        @ref CAN_remote_transmission    e.g: CAN_RTR_Data  CAN_RTR_Remote */
+
+    uint32_t DLC;                        /*!< Specifies the length of the frame that will be
+                                        transmitted. This parameter can be a value between 0 to 8 */
+
+    uint8_t Data[8];                    /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
+} CanTxRxMsg;
+
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct __CAN_HandleTypeDef
+{
+    CAN_TypeDef         *Instance;                 /*!< Register base address */
+
+    CAN_InitTypeDef      Init;                      /*!< CAN required parameters */
+
+    CanTxRxMsg          *RxMessage;                 /*!< CAN RxMessage */
+
+    void (*CAN_ReceiveIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN  ReceiveIT complete callback */
+
+    void (*CAN_TransmitIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN TransmitIT complete callback */
+
+} CAN_HandleTypeDef;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
+
+/** @defgroup CAN_identifier_type
+  * @{
+  */
+
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000001)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+/** @defgroup CAN_remote_transmission
+  * @{
+  */
+
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000001)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+/** @defgroup CAN_TxRxMessege
+  * @{
+  */
+
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_SR_RBS)  || ((FLAG) == CAN_SR_DOS)   || \
+                               ((FLAG) == CAN_SR_TBS)  || ((FLAG) == CAN_SR_TCS)   || \
+                               ((FLAG) == CAN_SR_RS)  || ((FLAG) == CAN_SR_TS)  || \
+                               ((FLAG) == CAN_SR_ES)  || ((FLAG) == CAN_SR_BS))
+
+#define IS_CAN_BRP(BRP)     (((BRP) <= 63))
+
+/**
+  * @defgroup CAN_Mode
+  * @{
+  */
+#define CAN_Mode_Normal         ((uint8_t)0x00) /*!< Normal mode */
+#define CAN_Mode_SlefTest       ((uint8_t)0x01) /*!< SlefTest mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||\
+                            ((MODE) == CAN_Mode_SlefTest))
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Operating_Mode
+  * @{
+  */
+#define CAN_OperatingMode_Normal           ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Listen           ((uint8_t)0x02) /*!< Listen mode */
+#define CAN_OperatingMode_SelfTest           ((uint8_t)0x04) /*!< Listen mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x10) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+                                    ((MODE) == CAN_OperatingMode_Sleep)|| \
+                                    ((MODE) == CAN_OperatingMode_SelfTest)|| \
+                                    ((MODE) == CAN_OperatingMode_Listen))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_SAM
+  * @{
+  */
+
+#define CAN_SAM_1time       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SAM_3time       ((uint8_t)0x01)  /*!< 2 time quantum */
+
+#define IS_CAN_SAM(SAM)     (((SAM) == CAN_SAM_1time) || ((SAM) == CAN_SAM_3time))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width
+  * @{
+  */
+
+#define CAN_SJW_1tq         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq         ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+    /** @defgroup CAN_time_quantum_in_bit_segment_1
+  * @{
+  */
+
+#define CAN_TSEG1_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG1_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG1_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG1_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG1_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG1_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG1_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG1_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_TSEG1_9tq       ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_TSEG1_10tq      ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_TSEG1_11tq      ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_TSEG1_12tq      ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_TSEG1_13tq      ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_TSEG1_14tq      ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_TSEG1_15tq      ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_TSEG1_16tq      ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_TSEG1(TSEG1) ((TSEG1) <= CAN_TSEG1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+  * @{
+  */
+
+#define CAN_TSEG2_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG2_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG2_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG2_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG2_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG2_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG2_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG2_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define IS_CAN_TSEG2(TSEG) ((TSEG) <= CAN_TSEG2_8tq)
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_filter_mode
+  * @{
+  */
+#define CAN_FilterMode_Dual         ((uint8_t)0x00)  /*!< identifier list mode */
+#define CAN_FilterMode_Single       ((uint8_t)0x01)  /*!< identifier/mask mode */
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_Dual) || \
+                                  ((MODE) == CAN_FilterMode_Single))
+
+    /**
+  * @}
+  */
+
+/** @defgroup CAN_ErrorCode
+  * @{
+  */
+#define CAN_ErrorType_ErrCode         ((uint8_t)0xC0)  /*!< identifier list mode */
+#define CAN_ErrorType_Direction       ((uint8_t)0x20)  /*!< identifier/mask mode */
+#define CAN_ErrorType_SegCode            ((uint8_t)0x1F)  /*!< identifier/mask mode */
+#define IS_CAN_ErrorType(ErrorType) (((ErrorType) == CAN_ErrorType_ErrCode) || \
+                                    ((ErrorType) == CAN_ErrorType_Direction)|| \
+                                    ((ErrorType) == CAN_ErrorType_SegCode))
+/**
+  * @}
+  */
+/* Initialization and Configuration functions *********************************/
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+
+/* Transmit functions *********************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage);
+
+void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan);
+
+/* Receive functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+/* Operation modes functions **************************************************/
+HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode);
+
+void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Error Code management functions **********************************/
+int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type);
+
+int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h

@@ -0,0 +1,216 @@
+/*
+  ******************************************************************************
+  * @file    HAL_COMP.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_COMP_H__
+#define __HAL_COMP_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define COMP1        (0x01)
+#define COMP2        (0x02)
+
+/****************  Bit definition for COMP_CR1 and COMP_CR2 register  **************************/
+#define COMP_CR_LOCK                            (BIT31)
+#define COMP_CR_BLANKTIME_POS                   (29U)
+#define COMP_CR_BLANKTIME_MASK                  (BIT30|BIT29)
+#define COMP_CR_CRV_CFG_POS                     (25U)
+#define COMP_CR_CRV_CFG_MASK                    (BIT28|BIT27|BIT26|BIT25)
+#define COMP_CR_CRV_SEL                         (BIT24)
+#define COMP_CR_CRV_EN                          (BIT23)
+#define COMP_CR_WINMODE                         (BIT22)
+#define COMP_CR_WINOUT                          (BIT21)
+#define COMP_CR_POLARITY                        (BIT20)
+#define COMP_CR_FLTEN                           (BIT19)
+#define COMP_CR_FLTTIME_POS                     (16U)
+#define COMP_CR_FLTTIME_MASK                    (BIT18|BIT17|BIT16)
+#define COMP_CR_BLANKSEL_POS                    (12U)
+#define COMP_CR_BLANKSEL_MASK                   (BIT15|BIT14|BIT13|BIT12)
+#define COMP_CR_INPSEL_POS                      (8U)
+#define COMP_CR_INPSEL_MASK                     (BIT11|BIT10|BIT9|BIT8)
+#define COMP_CR_INMSEL_POS                      (4U)
+#define COMP_CR_INMSEL_MASK                     (BIT7|BIT6|BIT5|BIT4)
+#define COMP_CR_HYS_POS                         (1U)
+#define COMP_CR_HYS_MASK                        (BIT3|BIT2|BIT1)
+#define COMP_CR_EN                              (BIT0)
+
+/****************  Bit definition for COMP_SR register  **************************/
+#define COMP_SR_VCOUT2_ORG                      (BIT3)
+#define COMP_SR_VCOUT1_ORG                      (BIT2)
+#define COMP_SR_VCOUT2                          (BIT1)
+#define COMP_SR_VCOUT1                          (BIT0)
+
+/**
+  * @brief  COMP Configuration Structure definition
+  */
+typedef struct
+{
+    uint8_t             Comparator;        /*!< Specify witch comparator be selected */
+    uint32_t            Crv_En;
+    uint32_t            BlankTime;
+    uint32_t            Crv_Sel;
+    uint32_t            Crv_Cfg;
+    uint32_t            WinMode;
+    uint32_t            WinOut;
+    uint32_t            Polarity;
+    uint32_t            FltEn;
+    uint32_t            FltTime;
+    uint32_t            BlankSel;
+    uint32_t            InPSel;
+    uint32_t            InMSel;
+    uint32_t            HYS;
+}COMP_InitTypeDef;
+
+/**
+  * @brief  COMP handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  uint8_t            OutputLevel_Org; /*!< COMP OutputLevel original */
+  uint8_t            OutputLevel;     /*!< COMP OutputLevel with filter */
+} COMP_HandleTypeDef;
+
+#define COMP_CR_CRV_EN_DISABLE           (0U)
+#define COMP_CR_CRV_EN_ENABLE            (1U)
+
+#define COMP_CR_CRV_SEL_AVDD             (0U)
+#define COMP_CR_CRV_SEL_VREF             (1U)
+
+#define COMP_CR1_WINMODE_COMP1_INPSEL           (0U)
+#define COMP_CR1_WINMODE_COMP2_INPSEL           (1U)
+
+#define COMP_CR2_WINMODE_COMP2_INPSEL           (0U)
+#define COMP_CR2_WINMODE_COMP1_INPSEL           (1U)
+
+#define COMP_CR1_WINOUT_VCOUT1                 (0U)
+#define COMP_CR2_WINOUT_VCOUT2                 (0U)
+#define COMP_CR_WINOUT_VCOUT12                 (1U)
+
+#define COMP_CR_POLARITY_P                     (0U)
+#define COMP_CR_POLARITY_N                     (1U)
+
+#define COMP_CR_FLTEN_DISABLE                  (0U)
+#define COMP_CR_FLTEN_ENABLE                   (1U)
+
+#define COMP_CR_FLTTIME_1_CLK                  (0U)
+#define COMP_CR_FLTTIME_2_CLK                  (1U)
+#define COMP_CR_FLTTIME_4_CLK                  (2U)
+#define COMP_CR_FLTTIME_16_CLK                 (3U)
+#define COMP_CR_FLTTIME_64_CLK                 (4U)
+#define COMP_CR_FLTTIME_256_CLK                (5U)
+#define COMP_CR_FLTTIME_1024_CLK               (6U)
+#define COMP_CR_FLTTIME_4095_CLK               (7U)
+
+#define COMP_CR_BLANKTIME_32_CLK               (0U)
+#define COMP_CR_BLANKTIME_64_CLK               (1U)
+#define COMP_CR_BLANKTIME_128_CLK              (2U)
+#define COMP_CR_BLANKTIME_256_CLK              (3U)
+
+#define COMP_CR_BLANKSEL_NONE                  (0U)
+#define COMP_CR_BLANKSEL_1                     (1U)
+#define COMP_CR_BLANKSEL_2                     (2U)
+#define COMP_CR_BLANKSEL_3                     (4U)
+#define COMP_CR_BLANKSEL_4                     (8U)
+
+#define COMP_CR_INPSEL_0                      (0U)
+#define COMP_CR_INPSEL_1                      (1U)
+#define COMP_CR_INPSEL_2                      (2U)
+
+#define COMP_CR_INMSEL_0                      (0U)
+#define COMP_CR_INMSEL_1                      (1U)
+#define COMP_CR_INMSEL_2                      (2U)
+#define COMP_CR_INMSEL_3                      (3U)
+
+#define COMP_CR_HYS_DISABLE                   (0U)
+#define COMP_CR_HYS_1                         (4U)
+#define COMP_CR_HYS_2                         (5U)
+#define COMP_CR_HYS_3                         (6U)
+#define COMP_CR_HYS_4                         (7U)
+
+/******************************** COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE)    ((INSTANCE) == COMP)
+#define IS_COMP_ALL_COMP(_COMP)     (((_COMP) == COMP1) || \
+                                  ((_COMP) == COMP2))
+
+#define IS_COMP_ALL_CRV_EN(_CRV_EN)        (((_CRV_EN) == COMP_CR_CRV_EN_DISABLE) || \
+                                           ((_CRV_EN) == COMP_CR_CRV_EN_ENABLE))
+
+#define IS_COMP_ALL_CRV_SEL(_CRV_SEL)      (((_CRV_SEL) == COMP_CR_CRV_SEL_AVDD) || \
+                                           ((_CRV_SEL) == COMP_CR_CRV_SEL_VREF))
+
+#define IS_COMP_ALL_CRV_CFG(_CRV_CFG)      ((_CRV_CFG) <= 15U)
+
+#define IS_COMP_ALL_WINMODE(WINMODE)       (((WINMODE) == COMP_CR1_WINMODE_COMP1_INPSEL) || \
+                                           ((WINMODE) == COMP_CR1_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP1_INPSEL))
+
+#define IS_COMP_ALL_WINOUT(_WINOUT)        (((_WINOUT) == COMP_CR1_WINOUT_VCOUT1) || \
+                                           ((_WINOUT) == COMP_CR2_WINOUT_VCOUT2) || \
+                                           ((_WINOUT) == COMP_CR_WINOUT_VCOUT12))
+
+#define IS_COMP_ALL_POLARITY(POLARITY)     (((POLARITY) == COMP_CR_POLARITY_N) || \
+                                           ((POLARITY) == COMP_CR_POLARITY_P))
+
+#define IS_COMP_ALL_FLTEN(FLTEN)           (((FLTEN) == COMP_CR_FLTEN_DISABLE) || \
+                                           ((FLTEN) == COMP_CR_FLTEN_ENABLE))
+
+#define IS_COMP_ALL_FLTTIME(FLTTIME)       (((FLTTIME) == COMP_CR_FLTTIME_1_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_2_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_16_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_64_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_256_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_1024_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4095_CLK))
+
+#define IS_COMP_ALL_BLANKTIME(BLANKTIME)   (((BLANKTIME) == COMP_CR_BLANKTIME_32_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_64_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_128_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_256_CLK))
+
+#define IS_COMP_ALL_BLANKSEL(BLANKSEL)     (((BLANKSEL) == COMP_CR_BLANKSEL_NONE) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_1) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_2) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_3) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_4))
+
+#define IS_COMP_ALL_INPSEL(INPSEL)         (((INPSEL) == COMP_CR_INPSEL_0) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_1) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_2))
+
+#define IS_COMP_ALL_INMSEL(INMSEL)         (((INMSEL) == COMP_CR_INMSEL_0 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_1 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_2 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_3 ))
+
+#define IS_COMP_ALL_HYS(_HYS)              (((_HYS) == COMP_CR_HYS_DISABLE) || \
+                                           ((_HYS) == COMP_CR_HYS_1) || \
+                                           ((_HYS) == COMP_CR_HYS_2) || \
+                                           ((_HYS) == COMP_CR_HYS_3) || \
+                                           ((_HYS) == COMP_CR_HYS_4))
+
+/* Function */
+void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+
+#endif
+
+
+
+
+

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h

@@ -0,0 +1,154 @@
+/*
+  ******************************************************************************
+  * @file    HAL_CRC.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CRC_H__
+#define __HAL_CRC_H__
+#include  "ACM32Fxx_HAL.h"
+
+/** @defgroup CRC POLY Reverse
+  * @{
+  */
+ #define CRC_POLY_REV_EN                    (0x00000400U)    /*!< Poly Reverse Enable */
+ #define CRC_POLY_REV_DIS                   (0x00000000U)    /*!< Poly Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC OUTXOR Reverse
+  * @{
+  */
+ #define CRC_OUTXOR_REV_EN                   (0x00000200U)    /*!< OUTXOR Reverse Enable */
+ #define CRC_OUTXOR_REV_DIS                  (0x00000000U)    /*!< OUTXOR Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC INIT Reverse
+  * @{
+  */
+ #define CRC_INIT_REV_EN                     (0x00000100U)    /*!< INIT Reverse Enable */
+ #define CRC_INIT_REV_DIS                    (0x00000000U)    /*!< INIT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RSLT Reverse
+  * @{
+  */
+ #define CRC_RSLT_REV_EN                     (0x00000080U)    /*!< RSLT Reverse Enable */
+ #define CRC_RSLT_REV_DIS                    (0x00000000U)    /*!< RSLT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC DATA Reverse
+  * @{
+  */
+ #define CRC_DATA_REV_DISABLE                (0x00000000U)    /*!< DATA Reverse Disable */
+ #define CRC_DATA_REV_BY_BYTE                (0x00000020U)    /*!< DATA Reverse By Byte */
+ #define CRC_DATA_REV_BY_HALFWORD            (0x00000040U)    /*!< DATA Reverse By HalfWord */
+ #define CRC_DATA_REV_BY_WORD                (0x00000060U)    /*!< DATA Reverse By Word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Poly Len
+  * @{
+  */
+ #define CRC_POLTY_LEN_32                    (0x00000000U)    /*!< POLY len = 32bit */
+ #define CRC_POLTY_LEN_16                    (0x00000008U)    /*!< POLY len = 16bit */
+ #define CRC_POLTY_LEN_8                     (0x00000010U)    /*!< POLY len = 8bit  */
+ #define CRC_POLTY_LEN_7                     (0x00000018U)    /*!< POLY len = 7bit  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Data Len
+  * @{
+  */
+ #define CRC_DATA_LEN_1B                    (0x00000000U)    /*!< DATA len = 1 Byte */
+ #define CRC_DATA_LEN_2B                    (0x00000002U)    /*!< DATA len = 2 Byte */
+ #define CRC_DATA_LEN_3B                    (0x00000004U)    /*!< DATA len = 3 Byte */
+ #define CRC_DATA_LEN_4B                    (0x00000006U)    /*!< DATA len = 4 Byte */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RST
+  * @{
+  */
+ #define CRC_RST_EN                          (0x00000001U)    /*!< RST CRC_DATA To CRC_INIT */
+ #define CRC_RST_DIS                         (0x00000000U)    /*!< RST CRC_DATA To CRC_INIT */
+
+/**
+  * @}
+  */
+
+/*
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+    uint32_t PolyRev;                  /*!< Specifies if the Poly is reversed in CRC
+                                            This parameter can be a value of @ref CRC POLY Reverse. */
+    uint32_t OutxorRev;                /*!< Specifies if the Outxor is reversed in CRC
+                                            This parameter can be a value of @ref CRC OUTXOR Reverse. */
+    uint32_t InitRev;                  /*!< Specifies if the Init is reversed in CRC
+                                            This parameter can be a value of @ref CRC INIT Reverse. */
+    uint32_t RsltRev;                  /*!< Specifies if the Result is reversed in CRC
+                                            This parameter can be a value of @ref CRC RSLT Reverse. */
+    uint32_t DataRev;                  /*!< Specifies if the Data is reversed in CRC
+                                            This parameter can be a value of @ref CRC DATA Reverse. */
+    uint32_t PolyLen;                  /*!< Specifies the Poly Len in CRC
+                                            This parameter can be a value of @ref CRC Poly Len. */
+    uint32_t DataLen;                  /*!< Specifies the Data Len in CRC
+                                            This parameter can be a value of @ref CRC Data Len. */
+    uint32_t RST;                      /*!< Specifies if CRC is reset
+                                            This parameter can be a value of @ref CRC RST. */
+
+    uint32_t InitData;                 /*!< This member configures the InitData. */
+
+    uint32_t OutXorData;               /*!< This member configures the OutXorData. */
+
+    uint32_t PolyData;                 /*!< This member configures the PolyData. */
+
+    uint32_t FData;                    /*!< This member configures the FData. */
+
+}CRC_InitTypeDef;
+
+/*
+ * @brief  UART handle Structure definition
+ */
+typedef struct
+{
+    CRC_TypeDef           *Instance;                /*!< CRC registers base address  */
+
+    CRC_InitTypeDef        Init;                    /*!< CRC calculate parameters  */
+
+    uint8_t* CRC_Data_Buff;                         /*!< CRC databuff base address */
+
+    uint32_t CRC_Data_Len;                          /*!< amount of CRC data to be calculated */
+
+}CRC_HandleTypeDef;
+
+
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc: CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc);
+
+
+#endif
+
+
+
+

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DIV.h

@@ -0,0 +1,24 @@
+#ifndef _HAL_DIV_H_
+#define _HAL_DIV_H_
+
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************
+* function   : hardwareNN_Div_q32
+* Description: Computes q = b div c and a = b mod c.
+               cDigits must be 1, and *c < 0xffffffff
+* input :      UINT32 *b -- input b databuffer
+               UINT32 *c -- input c databuffer
+* output:      UINT32 *q -- quotient of result
+               UINT32 *a -- remainder of result
+
+* return:      none
+************************************************************************/
+void HAL_DIV_Q32(UINT32 *q,UINT32 *a,UINT32 *b,UINT32 bDigits,UINT32 *c,UINT32 cDigits);
+
+
+
+#endif
+
+
+

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h

@@ -0,0 +1,278 @@
+/*
+  ******************************************************************************
+  * @file    HAL_DMA.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_DMA_H__
+#define __HAL_DMA_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define DMA_CHANNEL_NUM     (5)
+
+/** @defgroup DMA_DATA_FLOW
+ *  @{
+ */
+#define    DMA_DATA_FLOW_M2M    (0x00000000)
+#define    DMA_DATA_FLOW_M2P    (0x00000800)
+#define    DMA_DATA_FLOW_P2M    (0x00001000)
+/**
+  * @}
+  */
+
+
+/** @defgroup REQUEST_ID
+ *  @{
+ */
+#define    REG_M2M                        (0)
+
+#define    REQ0_ADC                       (0)
+#define    REQ1_SPI1_SEND                 (1)
+#define    REQ2_SPI1_RECV                 (2)
+#define    REQ3_SPI2_SEND                 (3)
+#define    REQ4_SPI2_RECV                 (4)
+#define    REQ5_UART1_SEND                (5)
+#define    REQ6_UART1_RECV                (6)
+#define    REQ7_UART2_SEND                (7)
+#define    REQ8_UART2_RECV                (8)
+#define    REQ9_I2C1_SEND                 (9)
+#define    REQ10_I2C1_RECV                (10)
+#define    REQ11_I2C2_SEND                (11)
+#define    REQ12_I2C2_RECV                (12)
+#define    REQ13_TIM1_CH1                 (13)
+#define    REQ14_TIM1_CH2                 (14)
+#define    REQ15_TIM1_CH3                 (15)
+#define    REQ16_TIM1_CH4                 (16)
+#define    REQ17_TIM1_UP                  (17)
+#define    REQ18_TIM1_TRIG_COM            (18)
+#define    REQ19_TIM3_CH3                 (19)
+#define    REQ20_TIM3_CH4_OR_UP           (20)
+#define    REQ21_TIM3_CH1_OR_TRIG         (21)
+#define    REQ22_TIM3_CH2_LCDFRAME        (22)
+#define    REQ23_TIM6_UP                  (23)
+#define    REQ24_TIM15_CH1_UP_TRIG_COM    (24)
+#define    REQ25_TIM15_CH2                (25)
+#define    REQ26_TIM16_CH1_UP             (26)
+#define    REQ27_UART3_SEND               (27)
+#define    REQ28_TIM17_CH1_UP             (28)
+#define    REQ29_UART3_RECV               (29)
+#define    REQ30_LPUART_SEND              (30)
+#define    REQ31_LPUART_RECV              (31)
+
+#define    REQ_MAX_LIMIT                  (32)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SOURCE_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_SOURCE_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_SOURCE_ADDR_INCREASE_ENABLE     (0x04000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_DST_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_DST_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_DST_ADDR_INCREASE_ENABLE     (0x08000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SRC_WIDTH
+ *  @{
+ */
+#define    DMA_SRC_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_SRC_WIDTH_HALF_WORD    (0x00040000)    /* 16bit */
+#define    DMA_SRC_WIDTH_WORD         (0x00080000)    /* 36bit */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_DST_WIDTH
+ *  @{
+ */
+#define    DMA_DST_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_DST_WIDTH_HALF_WORD    (0x00200000)    /* 16bit */
+#define    DMA_DST_WIDTH_WORD         (0x00400000)    /* 36bit */
+/**
+  * @}
+  */
+
+
+
+ /** @defgroup DMA_MODE DMA MODE
+ *  @{
+ */
+#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR                  0x00000001U                  /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA burst length Structure definition
+  */
+typedef enum
+{
+    DMA_BURST_LENGTH_1   = 0,
+    DMA_BURST_LENGTH_4   = 1,
+    DMA_BURST_LENGTH_8   = 2,
+    DMA_BURST_LENGTH_16  = 3,
+    DMA_BURST_LENGTH_32  = 4,
+    DMA_BURST_LENGTH_64  = 5,
+    DMA_BURST_LENGTH_128 = 6,
+    DMA_BURST_LENGTH_256 = 7,
+}DMA_BURST_LENGTH;
+
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+    uint32_t Mode;                  /* This parameter can be a value of @ref DMA_MODE */
+
+    uint32_t Data_Flow;             /* This parameter can be a value of @ref DMA_DATA_FLOW */
+
+    uint32_t Request_ID;            /* This parameter can be a value of @ref REQUEST_ID */
+
+    uint32_t Source_Inc;            /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */
+
+    uint32_t Desination_Inc;        /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */
+
+    uint32_t Source_Width;          /* This parameter can be a value of @ref DMA_SRC_WIDTH */
+
+    uint32_t Desination_Width;      /* This parameter can be a value of @ref DMA_DST_WIDTH */
+
+}DMA_InitParaTypeDef;
+
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct
+{
+    DMA_Channel_TypeDef    *Instance;    /* DMA registers base address */
+
+    DMA_InitParaTypeDef     Init;        /* DMA initialization parameters */
+
+    void (*DMA_ITC_Callback)(void);      /* DMA transfer complete callback */
+
+    void (*DMA_IE_Callback)(void);       /* DMA error complete callback */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @brief  DMA Link List Item Structure
+  */
+typedef struct DMA_NextLink
+{
+    uint32_t SrcAddr;               /* source address */
+
+    uint32_t DstAddr;               /* desination address */
+
+    struct DMA_NextLink *Next;      /* Next Link */
+
+    uint32_t Control;               /* Control */
+
+}DMA_LLI_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == DMA_Channel0) || \
+                                          ((INSTANCE) == DMA_Channel1) || \
+                                          ((INSTANCE) == DMA_Channel2) || \
+                                          ((INSTANCE) == DMA_Channel3) || \
+                                          ((INSTANCE) == DMA_Channel4))
+
+#define IS_DMA_DATA_FLOW(DATA_FLOW)      (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \
+                                          ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \
+                                          ((DATA_FLOW) == DMA_DATA_FLOW_P2M))
+
+#define IS_DMA_REQUEST_ID(REQUEST_ID)     ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false)
+
+#define IS_DMA_SRC_WIDTH(WIDTH)          (((WIDTH) == DMA_SRC_WIDTH_BYTE)      || \
+                                          ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \
+                                          ((WIDTH) == DMA_SRC_WIDTH_WORD))
+
+#define IS_DMA_DST_WIDTH(WIDTH)          (((WIDTH) == DMA_DST_WIDTH_BYTE)      || \
+                                          ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \
+                                          ((WIDTH) == DMA_DST_WIDTH_WORD))
+/**
+  * @}
+  */
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                    (DMA)                                   */
+/******************************************************************************/
+
+/****************  Bit definition for DMA CONFIG register  ***********************/
+#define DMA_CONFIG_M2ENDIAN             BIT2
+#define DMA_CONFIG_M1ENDIAN             BIT1
+#define DMA_CONFIG_EN                   BIT0
+
+/****************  Bit definition for DMA Channel CTRL register  ***********************/
+#define DMA_CHANNEL_CTRL_ITC     BIT31
+#define DMA_CHANNEL_CTRL_DI      BIT27
+#define DMA_CHANNEL_CTRL_SI      BIT26
+
+
+/****************  Bit definition for DMA Channel CONFIG register  ***********************/
+#define DMA_CHANNEL_CONFIG_HALT                 BIT18
+#define DMA_CHANNEL_CONFIG_ACTIVE               BIT17
+#define DMA_CHANNEL_CONFIG_LOCK                 BIT16
+#define DMA_CHANNEL_CONFIG_ITC                  BIT15
+#define DMA_CHANNEL_CONFIG_IE                   BIT14
+#define DMA_CHANNEL_CONFIG_FLOW_CTRL           (BIT11|BIT12|BIT13)
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH         (BIT6|BIT7|BIT8|BIT9|BIT10)
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS     (6)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH          (BIT1|BIT2|BIT3|BIT4|BIT5)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS      (1)
+#define DMA_CHANNEL_CONFIG_EN                   BIT0
+
+
+/* Exported functions --------------------------------------------------------*/
+
+#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_)    (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_)
+
+/* HAL_DMA_IRQHandler */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Init */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_DeInit */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Abort */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_GetState */
+HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFLASH.h

@@ -0,0 +1,41 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EFlash HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_H__
+#define __HAL_EFlash_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define EFLASH_PAGE_SIZE    (512UL)
+
+#define HAL_EFLASH_READ_WORD(Addr)        (*(volatile uint32_t *)(Addr))    // Read By Word
+#define HAL_EFLASH_READ_HALFWORD(Addr)    (*(volatile uint16_t *)(Addr))    // Read By Half Word
+#define HAL_EFLASH_READ_BYTE(Addr)        (*(volatile uint8_t *)(Addr))     // Read By Byte
+
+/********************  Bit definition for EFC_CTRL register  ******************/
+#define EFC_CTRL_CHIP_ERASE_MODE        (1 << 2)
+#define EFC_CTRL_PAGE_ERASE_MODE        (1 << 1)
+#define EFC_CTRL_PROGRAM_MODE           (1 << 0)
+
+#define EFLASH_RD_WAIT_POS   7
+/********************  Bit definition for EFC_STATUS register  ***************/
+#define EFC_STATUS_EFLASH_RDY           (1 << 0)
+
+#define SET_EFC_RD_WAIT(wait)     {EFC->CTRL   = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}
+
+/* Exported functions --------------------------------------------------------*/
+
+/* HAL_EFlash_Init */
+void HAL_EFlash_Init(uint32_t fu32_freq);
+/* HAL_EFlash_ErasePage */
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word */
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h

@@ -0,0 +1,26 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);
+
+/* HAL_EFlash_ErasePage_EX */
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word_EX */
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h

@@ -0,0 +1,166 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EXTI_H__
+#define __HAL_EXTI_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                (0x000001)
+#define EXTI_LINE_1                (0x000002)
+#define EXTI_LINE_2                (0x000004)
+#define EXTI_LINE_3                (0x000008)
+#define EXTI_LINE_4                (0x000010)
+#define EXTI_LINE_5                (0x000020)
+#define EXTI_LINE_6                (0x000040)
+#define EXTI_LINE_7                (0x000080)
+#define EXTI_LINE_8                (0x000100)
+#define EXTI_LINE_9                (0x000200)
+#define EXTI_LINE_10               (0x000300)
+#define EXTI_LINE_11               (0x000400)
+#define EXTI_LINE_12               (0x001000)
+#define EXTI_LINE_13               (0x002000)
+#define EXTI_LINE_14               (0x004000)
+#define EXTI_LINE_15               (0x008000)
+#define EXTI_LINE_16               (0x010000)
+#define EXTI_LINE_17               (0x020000)
+#define EXTI_LINE_18               (0x040000)
+#define EXTI_LINE_19               (0x080000)
+#define EXTI_LINE_20               (0x100000)
+#define EXTI_LINE_21               (0x200000)
+#define EXTI_LINE_22               (0x400000)
+#define EXTI_LINE_23               (0x800000)
+#define EXTI_LINE_MASK             (0xFFFFFFU)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_INTERRUPT         (0x00000001)
+#define EXTI_MODE_EVENT             (0x00000002)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_RISING                 (0x00000001)
+#define EXTI_TRIGGER_FALLING                (0x00000002)
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#define EXTI_GPIOE                          0x00000004u
+#define EXTI_GPIOF                          0x00000005u
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Line;        /*!< The Exti line to be configured. This parameter
+                                   can be a value of @ref EXTI_Line */
+    uint32_t u32_Mode;        /*!< The Exit Mode to be configured for a core.
+                                   This parameter can be a combination of @ref EXTI_Mode */
+    uint32_t u32_Trigger;     /*!< The Exti Trigger to be configured. This parameter
+                                   can be a value of @ref EXTI_Trigger */
+    uint32_t u32_GPIOSel;     /*!< The Exti GPIO multiplexer selection to be configured.
+                                   This parameter is only possible for line 0 to 15. It
+                                   can be a value of @ref EXTI_GPIOSel */
+}EXTI_HandleTypeDef;
+
+
+/** @defgroup  EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_ALL_LINE(LINE)    ( (LINE) | (EXTI_LINE_MASK) )
+
+#define IS_EXTI_MODE(__MODE__)     (((__MODE__) == EXTI_MODE_INTERRUPT) || \
+                                    ((__MODE__) == EXTI_MODE_EVENT))
+
+#define IS_EXTI_TRIGGER(__TRIGGER__)     (((__TRIGGER__) == EXTI_TRIGGER_RISING)  || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIOSEL(__GPIOSEL__)     (((__GPIOSEL__) == EXTI_GPIOA) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOB) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOC) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOD) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOE) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOF))
+/**
+  * @}
+  */
+
+/** @brief  __HAL_EXTI_LINE_IT_ENABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__)    (EXTI->IENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_IT_DISABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__)    (EXTI->IENR &= ~(__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_ENABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__)    (EXTI->EENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_DISABLE
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__)    (EXTI->EENR &= ~(__LINE__))
+
+
+/* HAL_EXTI_IRQHandler */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart);
+
+/* HAL_EXTI_SetConfigLine */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_SoftTrigger */
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_GetPending */
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearPending */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearAllPending */
+void HAL_EXTI_ClearAllPending(void);
+
+#endif
+

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h

@@ -0,0 +1,210 @@
+/*
+  ******************************************************************************
+  * @file    HAL_GPIO.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_GPIO_H__
+#define __HAL_GPIO_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_mode GPIO mode
+  * @{
+  */
+#define  GPIO_MODE_INPUT                    (0x00010000u)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                (0x00010001u)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                (0x00011002u)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                    (0x00000003u)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                    (0x00001004u)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                   (0x00000005u)   /*!< Analog Mode                           */
+#define  GPIO_MODE_IT_RISING                (0x10010000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING               (0x10010001u)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING        (0x10010002u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_HIGH_LEVEL            (0x10010003u)   /*!< External Interrupt Mode with high level trigger detection  */
+#define  GPIO_MODE_IT_LOW_LEVEL             (0x10010004u)   /*!< External Interrupt Mode with low level trigger detection  */
+
+#define  GPIO_MODE_OD_MASK                  (0x00001000u)   /*!< OD Mode Mask                          */
+#define  GPIO_MODE_IO_MASK                  (0x00010000u)   /*!< Use GPIO Function Mask                */
+#define  GPIO_MODE_IT_MASK                  (0x10000000u)   /*!< GPIO interrupt Mask                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_pull GPIO pull
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIOEx_function_selection GPIO pull
+  * @{
+  */
+#define  GPIO_FUNCTION_0        (0x00000000u)
+#define  GPIO_FUNCTION_1        (0x00000001u)
+#define  GPIO_FUNCTION_2        (0x00000002u)
+#define  GPIO_FUNCTION_3        (0x00000003u)
+#define  GPIO_FUNCTION_4        (0x00000004u)
+#define  GPIO_FUNCTION_5        (0x00000005u)
+#define  GPIO_FUNCTION_6        (0x00000006u)
+#define  GPIO_FUNCTION_7        (0x00000007u)
+#define  GPIO_FUNCTION_8        (0x00000008u)
+#define  GPIO_FUNCTION_9        (0x00000009u)
+/**
+  * @}
+  */
+
+
+
+/** @defgroup GPIOx Index
+  * @{
+  */
+typedef enum
+{
+    GPIOA,
+    GPIOB,
+    GPIOC,
+    GPIOD,
+}enum_GPIOx_t;
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO Bit SET and Bit RESET enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_PIN_CLEAR = 0u,
+  GPIO_PIN_SET   = 1u,
+}enum_PinState_t;
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief   GPIO Init structure definition
+ */
+typedef struct
+{
+    uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_pins */
+
+    uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_mode */
+
+    uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                              This parameter can be a value of @ref GPIO_pull */
+
+    uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                               This parameter can be a value of @ref GPIOEx_function_selection */
+} GPIO_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) )
+
+#define IS_GPIO_PIN(__PIN__)           ((((uint32_t)(__PIN__) &  GPIO_PIN_MASK) != 0x00u) &&\
+                                        (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+
+#define IS_GPIO_MODE(__MODE__)         (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                        ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                        ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                        ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                        ((__MODE__) == GPIO_MODE_IT_HIGH_LEVEL)      ||\
+                                        ((__MODE__) == GPIO_MODE_IT_LOW_LEVEL)       ||\
+                                        ((__MODE__) == GPIO_MODE_ANALOG))
+
+
+
+
+#define IS_GPIO_PULL(__PULL__)         (((__PULL__) == GPIO_NOPULL)   ||\
+                                        ((__PULL__) == GPIO_PULLUP)   ||\
+                                        ((__PULL__) == GPIO_PULLDOWN))
+
+#define IS_GPIO_PIN_ACTION(ACTION)     (((ACTION) == GPIO_PIN_CLEAR) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_FUNCTION(__FUNCTION__)    (((__FUNCTION__) == GPIO_FUNCTION_0) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_1) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_2) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_3) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_4) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_5) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_6) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_7) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_8) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_9))
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* HAL_GPIO_IRQHandler */
+void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+/* HAL_GPIO_Init */
+void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init);
+
+/* HAL_GPIO_DeInit */
+void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_AnalogEnable */
+void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_WritePin */
+void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState);
+
+/* HAL_GPIO_ReadPin */
+enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h

@@ -0,0 +1,45 @@
+/***********************************************************************
+ * Copyright (c)  2008 - 2016, Shanghai AisinoChip Co.,Ltd .
+ * All rights reserved.
+ * Filename    : HAL_HRNG.h
+ * Description : hrng header file
+ * Author(s)   : Eric
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+#ifndef __HAL_HRNG_H__
+#define __HAL_HRNG_H__
+#include "ACM32Fxx_HAL.h"
+
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Initial
+* Description    : intial hrng module
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Initial(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Source_Disable
+* Description    : disable hrng source
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Source_Disable(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng
+* Description    : get random number
+* Input          : byte_len :  the byte length of random number
+* Output         : *hdata   :  the start address of random number the size must be 16bytes
+* Return         : 0: hrng data is ok; 1: hrng data is bad
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len);
+
+#endif
+
+
+

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h

@@ -0,0 +1,253 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2C.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_I2C_H__
+#define __HAL_I2C_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for I2C CR register  ********************/
+#define I2C_CR_STOPF_INTEN                  BIT20
+#define I2C_CR_RX_ADDR3_INTEN               BIT19
+#define I2C_CR_DMA_EN                       BIT18
+#define I2C_CR_TXE_SEL                      BIT17
+#define I2C_CR_MARLO_INTEN                  BIT16
+#define I2C_CR_TX_AUTO_EN                   BIT15
+#define I2C_CR_OD_MODE                      BIT14
+#define I2C_CR_RX_ADDR2_INT_EN              BIT12
+#define I2C_CR_OVR_INT_EN                   BIT11
+#define I2C_CR_RXNE_INT_EN                  BIT10
+#define I2C_CR_TXE_INT_EN                   BIT9
+#define I2C_CR_RX_ADDR1_INT_EN              BIT8
+#define I2C_CR_MTF_INT_EN                   BIT7
+#define I2C_CR_TACK                         BIT6
+#define I2C_CR_STOP                         BIT5
+#define I2C_CR_START                        BIT4
+#define I2C_CR_TX                           BIT3
+#define I2C_CR_MASTER                       BIT2
+#define I2C_CR_NOSTRETCH                    BIT1
+#define I2C_CR_MEN                          BIT0
+
+/****************  Bit definition for I2C SR register  ********************/
+#define I2C_SR_TIMEOUTBF                    BIT16
+#define I2C_SR_TIMEOUTAF                    BIT15
+#define I2C_SR_RX_ADDR3                     BIT14
+#define I2C_SR_RX_ADDR2                     BIT12
+#define I2C_SR_OVR                          BIT11
+#define I2C_SR_RXNE                         BIT10
+#define I2C_SR_TXE                          BIT9
+#define I2C_SR_RX_ADDR1                     BIT8
+#define I2C_SR_MTF                          BIT7
+#define I2C_SR_MARLO                        BIT6
+#define I2C_SR_TX_RX_FLAG                   BIT5
+#define I2C_SR_BUS_BUSY                     BIT4
+#define I2C_SR_SRW                          BIT3
+#define I2C_SR_STOPF                        BIT2
+#define I2C_SR_STARTF                       BIT1
+#define I2C_SR_RACK                         BIT0
+
+/**************  Bit definition for I2C SLAVE ADDR2/3 register  **************/
+#define I2C_ADDR3_EN                        BIT8
+#define I2C_ADDR2_EN                        BIT0
+
+/**************  Bit definition for I2C TIMEOUT register  **************/
+#define I2C_TIMEOUT_EXTEN                   BIT31
+#define I2C_TOUTB_INTEN                     BIT30
+#define I2C_EXT_MODE                        BIT29
+#define I2C_TIMEOUT_TIMOUTEN                BIT15
+#define I2C_TOUTA_INTEN                     BIT14
+
+/** @defgroup I2C_MODE
+ *  @{
+ */
+#define    I2C_MODE_SLAVE     (0U)
+#define    I2C_MODE_MASTER    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup CLOCK_SPEED
+ *  @{
+ */
+#define    CLOCK_SPEED_STANDARD     (100000U)
+#define    CLOCK_SPEED_FAST         (400000U)
+#define    CLOCK_SPEED_FAST_PLUS    (1000000U)
+/**
+  * @}
+  */
+
+
+/** @defgroup TX_AUTO_EN
+ *  @{
+ */
+#define    TX_AUTO_EN_DISABLE    (0U)
+#define    TX_AUTO_EN_ENABLE     (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup NO_STRETCH_MODE
+ *  @{
+ */
+#define    NO_STRETCH_MODE_STRETCH      (0U)
+#define    NO_STRETCH_MODE_NOSTRETCH    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup SLAVE State machine
+ *  @{
+ */
+#define    SLAVE_RX_STATE_IDLE         (0U)
+#define    SLAVE_RX_STATE_RECEIVING    (1U)
+#define    SLAVE_TX_STATE_IDLE         (0U)
+#define    SLAVE_TX_STATE_SENDING      (1U)
+/**
+  * @}
+  */
+
+ /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0U)
+#define I2C_MEMADD_SIZE_16BIT           (1U)
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+  * @{
+  */
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+/**
+  * @brief  I2C Configuration Structure definition
+  */
+
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR) & (__FLAG__))  == (__FLAG__) ) ? 1 : 0)
+
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef struct
+{
+    uint32_t  I2C_Mode;               /* This parameter can be a value of @ref I2C_MODE */
+
+    uint32_t  Tx_Auto_En;             /* This parameter can be a value of @ref TX_AUTO_EN */
+
+    uint32_t  No_Stretch_Mode;        /* This parameter can be a value of @ref NO_STRETCH_MODE */
+
+    uint32_t  Own_Address;            /* This parameter can be a 7-bit address */
+
+    uint32_t  Clock_Speed;            /* This parameter can be a value of @ref CLOCK_SPEED */
+} I2C_InitTypeDef;
+
+/******************************** Check I2C Parameter *******************************/
+#define IS_I2C_ALL_MODE(I2C_MODE)    (((I2C_MODE) == I2C_MODE_SLAVE) || \
+                                      ((I2C_MODE) == I2C_MODE_MASTER))
+
+#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED)    (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U))
+
+#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN)      (((TX_AUTO_EN) == TX_AUTO_EN_DISABLE) || \
+                                            ((TX_AUTO_EN) == TX_AUTO_EN_ENABLE))
+
+#define IS_I2C_STRETCH_EN(STRETCH_EN)    (((STRETCH_EN) == NO_STRETCH_MODE_STRETCH) || \
+                                          ((STRETCH_EN) == NO_STRETCH_MODE_NOSTRETCH))
+
+/**
+  * @brief  I2C handle Structure definition
+  */
+typedef struct
+{
+    I2C_TypeDef         *Instance;         /* I2C registers base address */
+
+    I2C_InitTypeDef      Init;             /* I2C communication parameters */
+
+    uint32_t               Slave_RxState;    /* I2C Slave state machine */
+    uint32_t               Slave_TxState;    /* I2C Slave state machine */
+
+    uint8_t               *Rx_Buffer;        /* I2C Rx Buffer */
+    uint8_t               *Tx_Buffer;        /* I2C Tx Buffer */
+
+    uint32_t               Rx_Size;          /* I2C Rx Size */
+    uint32_t               Tx_Size;          /* I2C Tx Size */
+
+    uint32_t               Rx_Count;         /* I2C Rx Count */
+    uint32_t               Tx_Count;         /* I2C Tx Count */
+
+    DMA_HandleTypeDef   *HDMA_Rx;          /* I2C Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* I2C Tx DMA handle parameters */
+
+    void (*I2C_STOPF_Callback)(void);      /* I2C STOP flag interrupt callback */
+
+}I2C_HandleTypeDef;
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
+
+/* Function : HAL_I2C_IRQHandler */
+void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspInit */
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspDeInit */
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Init */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_DeInit */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Master_Transmit */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Master_Receive */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Transmit */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Receive */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Transmit_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+
+/* Function : HAL_I2C_Slave_Receive_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Receive_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Transmit_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Mem_Write */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Mem_Read */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_GetSlaveRxState */
+uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_GetSlaveTxState */
+uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c);
+
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h

@@ -0,0 +1,57 @@
+
+/***********************************************************************
+ * Filename    : HAL_IWDT.h
+ * Description : IHAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17
+ ***********************************************************************/
+
+#ifndef __HAL_IWDT_H__
+#define __HAL_IWDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for IWDT register  ***********************/
+
+
+/*----------------------macro definition------------------------*/
+#define IWDT_ENABLE_COMMAND  (0xCCCCU)
+#define IWDT_DISABLE_COMMAND (0xEF01ABCD)
+#define IWDT_WRITE_ENABLE_COMMAND  (0x5555U)
+#define IWDT_WAKEUP_ENABLE_COMMAND  (0x6666U)
+#define IWDT_WAKEUP_DISABLE_COMMAND  (0x9999U)
+#define IWDT_RELOAD_COMMAND  (0xAAAAU)
+
+#define IWDT_RELOAD_MAX_VALUE  (0x0FFFU)
+
+/*----------------------type definition------------------------*/
+typedef enum _IWDT_CLOCK_PRESCALER{
+    IWDT_CLOCK_PRESCALER_4   = 0,
+    IWDT_CLOCK_PRESCALER_8   = 1,
+    IWDT_CLOCK_PRESCALER_16  = 2,
+    IWDT_CLOCK_PRESCALER_32  = 3,
+    IWDT_CLOCK_PRESCALER_64  = 4,
+    IWDT_CLOCK_PRESCALER_128 = 5,
+    IWDT_CLOCK_PRESCALER_256 = 6,
+}IWDT_CLOCK_PRESCALER;
+
+typedef struct
+{
+    uint32_t Prescaler;
+    uint32_t Reload;
+    uint32_t Window;
+    uint32_t Wakeup;
+} IWDT_InitTypeDef;
+
+typedef struct
+{
+    IWDT_TypeDef                 *Instance;  /*!< Register base address    */
+    IWDT_InitTypeDef             Init;       /*!< IWDT required parameters */
+} IWDT_HandleTypeDef;
+
+
+ HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt);
+ HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt);
+#endif

bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_LCD.h

@@ -0,0 +1,442 @@
+/*
+  ******************************************************************************
+  * @file    HAL_LCD.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of lcd HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_LCD_H__
+#define __HAL_LCD_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR0 register  *********************/
+#define LCD_CR0_LCDEN_Pos              (0U)
+#define LCD_CR0_LCDEN_Msk             (0x1UL << LCD_CR0_LCDEN_Pos)
+#define LCD_CR0_LCDEN                 LCD_CR0_LCDEN_Msk
+
+#define LCD_CR0_LCDCLK_Pos             (1U)
+#define LCD_CR0_LCDCLK_Msk             (0x7UL << LCD_CR0_LCDCLK_Pos)
+#define LCD_CR0_LCDCLK                  LCD_CR0_LCDCLK_Msk
+#define LCD_CR0_LCDCLK_0               (0x1UL << LCD_CR0_LCDCLK_Pos)
+#define LCD_CR0_LCDCLK_1               (0x2UL << LCD_CR0_LCDCLK_Pos)
+
+#define LCD_CR0_STATIC_Pos            (4U)
+#define LCD_CR0_STATIC_Msk            (0x1UL << LCD_CR0_STATIC_Pos)
+#define LCD_CR0_STATIC                LCD_CR0_STATIC_Msk
+
+#define LCD_CR0_BIAS_Pos             (5U)
+#define LCD_CR0_BIAS_Msk             (0x3UL << LCD_CR0_BIAS_Pos)
+#define LCD_CR0_BIAS                 LCD_CR0_BIAS_Msk
+#define LCD_CR0_BIAS_0               (0x1UL << LCD_CR0_BIAS_Pos)
+#define LCD_CR0_BIAS_1               (0x2UL << LCD_CR0_BIAS_Pos)
+
+#define LCD_CR0_DUTY_Pos             (7U)
+#define LCD_CR0_DUTY_Msk             (0x7UL << LCD_CR0_DUTY_Pos)
+#define LCD_CR0_DUTY                 LCD_CR0_DUTY_Msk
+#define LCD_CR0_DUTY_0               (0x1UL << LCD_CR0_DUTY_Pos)
+#define LCD_CR0_DUTY_1               (0x2UL << LCD_CR0_DUTY_Pos)
+#define LCD_CR0_DUTY_2               (0x4UL << LCD_CR0_DUTY_Pos)
+
+#define LCD_CR0_MOD_Pos             (11U)
+#define LCD_CR0_MOD_Msk             (0x3UL << LCD_CR0_MOD_Pos)
+#define LCD_CR0_MOD                 LCD_CR0_MOD_Msk
+#define LCD_CR0_MOD_0               (0x1UL << LCD_CR0_MOD_Pos)
+#define LCD_CR0_MOD_1               (0x2UL << LCD_CR0_MOD_Pos)
+
+#define LCD_CR0_CONTRAST_Pos             (13U)
+#define LCD_CR0_CONTRAST_Msk             (0xfUL << LCD_CR0_CONTRAST_Pos)
+#define LCD_CR0_CONTRAST                 LCD_CR0_CONTRAST_Msk
+#define LCD_CR0_CONTRAST_0               (0x1UL << LCD_CR0_CONTRAST_Pos)
+#define LCD_CR0_CONTRAST_1               (0x2UL << LCD_CR0_CONTRAST_Pos)
+#define LCD_CR0_CONTRAST_2               (0x4UL << LCD_CR0_CONTRAST_Pos)
+#define LCD_CR0_CONTRAST_3               (0x8UL << LCD_CR0_CONTRAST_Pos)
+
+#define LCD_CR0_WSEL_Pos                (17U)
+#define LCD_CR0_WSEL_Msk                (0x1UL << LCD_CR0_WSEL_Pos)
+#define LCD_CR0_WSEL                     LCD_CR0_WSEL_Msk
+
+/*******************  Bit definition for LCD_CR1 register  *********************/
+#define LCD_CR1_BLINKCNT_Pos             (0U)
+#define LCD_CR1_BLINKCNT_Msk             (0x3FUL << LCD_CR1_BLINKCNT_Pos)
+#define LCD_CR1_BLINKCNT                  LCD_CR1_BLINKCNT_Msk
+
+
+#define LCD_CR1_BLINKEN_Pos             (6U)
+#define LCD_CR1_BLINKEN_Msk             (0x1UL << LCD_CR1_BLINKEN_Pos)
+#define LCD_CR1_BLINKEN                  LCD_CR1_BLINKEN_Msk
+
+#define LCD_CR1_MODE_Pos             (8U)
+#define LCD_CR1_MODE_Msk             (0x1UL << LCD_CR1_MODE_Pos)
+#define LCD_CR1_MODE                  LCD_CR1_MODE_Msk
+
+#define LCD_CR1_IE_Pos             (9U)
+#define LCD_CR1_IE_Msk             (0x1UL << LCD_CR1_IE_Pos)
+#define LCD_CR1_IE                  LCD_CR1_IE_Msk
+
+#define LCD_CR1_DMAEN_Pos             (10U)
+#define LCD_CR1_DMAEN_Msk             (0x1UL << LCD_CR1_DMAEN_Pos)
+#define LCD_CR1_DMAEN                  LCD_CR1_DMAEN_Msk
+
+#define LCD_CR1_INTF_Pos             (11U)
+#define LCD_CR1_INTF_Msk             (0x1UL << LCD_CR1_INTF_Pos)
+#define LCD_CR1_INTF                  LCD_CR1_INTF_Msk
+
+#define LCD_CR1_FCC_Pos             (12U)
+#define LCD_CR1_FCC_Msk             (0x1UL << LCD_CR1_FCC_Pos)
+#define LCD_CR1_FCC                  LCD_CR1_FCC_Msk
+
+#define LCD_CR1_MODSEL_Pos             (13U)
+#define LCD_CR1_MODSEL_Msk             (0x3UL << LCD_CR1_MODSEL_Pos)
+#define LCD_CR1_MODSEL                  LCD_CR1_MODSEL_Msk
+#define LCD_CR1_MODSEL_0               (0x1UL << LCD_CR1_MODSEL_Pos)
+#define LCD_CR1_MODSEL_1               (0x2UL << LCD_CR1_MODSEL_Pos)
+
+#define LCD_CR1_RSEL_Pos             (15U)
+#define LCD_CR1_RSEL_Msk             (0x1UL << LCD_CR1_RSEL_Pos)
+#define LCD_CR1_RSEL                  LCD_CR1_RSEL_Msk
+
+#define LCD_CR1_PON_Pos              (13U)
+#define LCD_CR1_PON_Msk              (0x3fUL << LCD_CR1_PON_Pos)
+#define LCD_CR1_PON                  LCD_CR1_PON_Msk
+
+/*******************  Bit definition for LCD_CR1 register  *********************/
+#define LCD_INTCLR_INTF_Pos             (10U)
+#define LCD_INTCLR_INTF_Msk             (0x1UL << LCD_INTCLR_INTF_Pos)
+#define LCD_INTCLR_INTFT                  LCD_INTCLR_INTF_Msk
+
+
+
+/**
+  * @brief LCD SegCom Init structure definition
+  */
+typedef struct
+{
+    uint32_t SEG0_31;      /*!< Configures the SEG0 to SEG31 Enable or Disable.
+                            This parameter can be a value between 0x0 and 0xFFFFFFFF */
+    union{
+            uint32_t SEG32_39_COM0_8;   /*!< Configures the SEG32-35 and COM0-8 Enable or Disable.
+                                        This parameter can be a value between 0x0 and 0xFFF */
+            struct
+            {
+                uint32_t SEG32_35      :4;  /*!< Configures the SEG32-35 Enable or Disable.
+                                            This parameter can be a value between 0x0 and 0xF */
+                uint32_t SEG36_COM7    :1;  /*!< Configures the SEG36/COM7 Enable or Disable.  */
+                uint32_t SEG37_COM6    :1;  /*!< Configures the SEG37/COM6 Enable or Disable.  */
+                uint32_t SEG38_COM5    :1;  /*!< Configures the SEG38/COM5 Enable or Disable.  */
+                uint32_t SEG39_COM4    :1;  /*!< Configures the SEG39/COM4 Enable or Disable.  */
+                uint32_t COM0_3        :4;  /*!< Configures the COM0-3 Enable or Disable.
+                                            This parameter can be a value between 0x0 and 0xF */
+            }SEGCOM_bit;
+    }Stc_SEG32_39_COM0_8;
+}LCD_SegComInitTypeDef;
+
+
+/**
+  * @brief LCD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t PONTime;         /*!< Configures the Pulse ON duration time.
+                            This parameter can be a value between 0x00 and 0x3F */
+  uint32_t BiasRes;        /*!< Configures the LCD BiasRes.
+                                 This parameter can be one value of @ref BiasRes */
+  uint32_t DriveMod;    /*!< Configures the LCD DriveMod.
+                                 This parameter can be one value of @ref DriveMod */
+  uint32_t FastCharge;     /*!< Configures the LCD FastCharge.
+                                 This parameter can be one value of @ref FastCharge */
+  uint32_t Contrast;        /*!< Configures the LCD Contrast.
+                                 This parameter can be one value of @ref LCD_Contrast */
+
+}LCD_InResInitTypeDef;
+/**
+  * @brief LCD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Duty;            /*!< Configures the LCD Duty.
+                                 This parameter can be one value of @ref LCD_Duty */
+  uint32_t Bias;            /*!< Configures the LCD Bias.
+                                 This parameter can be one value of @ref LCD_Bias */
+  uint32_t Driving_Waveform; /*!< Configures the LCD Drive Waveform.
+                                 This parameter can be one value of @ref Driving_Waveform */
+
+  uint32_t BiasSrc;                  /*!< Configures the LCD Bias Src.
+                                 This parameter can be one value of @ref BiasSrc*/
+
+  uint32_t DisplayMode;      /*!< Configures the LCD DisplayMode.
+                                 This parameter can be one value of @ref DisplayMode*/
+
+  uint32_t StaticPower;   /*!< Configures the LCD StaticPower.
+                                 This parameter can be one value of @ref StaticPower*/
+
+  uint32_t LCDFrequency;  /*!< Configures the LCD LCDFrequency.
+                                 This parameter can be one value of @ref LCDFrequency*/
+
+  uint32_t BlinkEN;           /*!< Configures the LCD BlinkEN.
+                                 This parameter can be one value of @ref BlinkEN */
+
+  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
+                            This parameter can be a value between 0x00 and 0x3F */
+}LCD_InitTypeDef;
+
+
+/**
+  * @brief  LCD handle Structure definition
+  */
+typedef struct
+{
+  LCD_TypeDef                   *Instance;  /* LCD registers base address */
+
+  LCD_InitTypeDef               Init;       /* LCD communication parameters */
+
+  DMA_HandleTypeDef           *DMA_Handle;                 /*!< UART Rx DMA handle parameters */
+}LCD_HandleTypeDef;
+
+
+#define IS_LCD_PERIPH(PERIPH) (((PERIPH) == LCD))
+
+/** @defgroup LCD_Duty LCD Duty
+  * @{
+  */
+
+#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000U)                                     /*!< Static duty */
+#define LCD_DUTY_1_2                    LCD_CR0_DUTY_0                                            /*!< 1/2 duty    */
+#define LCD_DUTY_1_3                    LCD_CR0_DUTY_1                                            /*!< 1/3 duty    */
+#define LCD_DUTY_1_4                    ((LCD_CR0_DUTY_1 | LCD_CR0_DUTY_0))                         /*!< 1/4 duty    */
+#define LCD_DUTY_1_6                    ((LCD_CR0_DUTY_2 | LCD_CR0_DUTY_0))                         /*!< 1/6 duty    */
+#define LCD_DUTY_1_8                    ((LCD_CR0_DUTY_2 | LCD_CR0_DUTY_1 | LCD_CR0_DUTY_0))      /*!< 1/8 duty    */
+
+#define IS_LCD_DUTY(DUTY)      (((DUTY) == LCD_DUTY_STATIC)  || \
+                               ((DUTY) == LCD_DUTY_1_2)     || \
+                               ((DUTY) == LCD_DUTY_1_3)     || \
+                               ((DUTY) == LCD_DUTY_1_4)     || \
+                               ((DUTY) == LCD_DUTY_1_6)     || \
+                               ((DUTY) == LCD_DUTY_1_8))
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+
+/** @defgroup LCD_Bias LCD Bias
+  * @{
+  */
+
+#define LCD_BIAS_1_4                    ((uint32_t)0x00000000U) /*!< 1/4 Bias */
+#define LCD_BIAS_1_2                    LCD_CR0_BIAS_0           /*!< 1/2 Bias */
+#define LCD_BIAS_1_3                    LCD_CR0_BIAS_1           /*!< 1/3 Bias */
+
+#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
+                               ((__BIAS__) == LCD_BIAS_1_2) || \
+                               ((__BIAS__) == LCD_BIAS_1_3))
+/**
+  * @}
+  */
+
+ /** @defgroup Driving_Waveform  Driving_Waveform
+  * @{
+  */
+
+#define LCD_Driving_Waveform_A                    ((uint32_t)0x00000000U) /*!< A类波形*/
+#define LCD_Driving_Waveform_B                     LCD_CR0_WSEL           /*!< B类波形 */
+#define IS_LCD_Driving_Waveform(__Driving_Waveform__)         (((__Driving_Waveform__) == LCD_Driving_Waveform_A) || \
+                                                                ((__Driving_Waveform__) == LCD_Driving_Waveform_B))
+/**
+  * @}
+  */
+
+  /** @defgroup BiasSrc
+  * @{
+  */
+
+#define LCD_BiasSrc_InRes_Seg31_35_Normal                   ((uint32_t)0x00000000U) /*!< LCD Bias来源：内部电阻分压，且SEG31-35可以作为SEG/IO*/
+#define LCD_BiasSrc_InRes_Seg31_35_Cap                      LCD_CR0_MOD_0           /*!< LCD Bias来源：内部电阻分压，且SEG31-35用于外接电容滤波，SEG/IO功能关闭 */
+#define LCD_BiasSrc_ExRes_Seg31_35_Cap                      LCD_CR0_MOD_1           /*!< LCD Bias来源：外部电阻分压，且SEG31-35用于外接分压电阻和滤波电容，SEG/IO功能关闭 */
+#define IS_LCD_BiasSrc(__BiasSrc__)                         (((__BiasSrc__) == LCD_BiasSrc_InRes_Seg31_35_Normal) || \
+                                                          ((__BiasSrc__) == LCD_BiasSrc_InRes_Seg31_35_Cap)||\
+                                                          ((__BiasSrc__) == LCD_BiasSrc_ExRes_Seg31_35_Cap))
+/**
+  * @}
+  */
+
+  /** @defgroup DisplayMode
+  * @{
+  */
+
+#define LCD_DisplayMode_0                        ((uint32_t)0x00000000U) /*!< LCD RAM显示模式0*/
+#define LCD_DisplayMode_1                          LCD_CR1_MODE           /*!< LCD RAM显示模式1 */
+#define IS_LCD_DisplayMode(__DisplayMode__)                         (((__DisplayMode__) == LCD_DisplayMode_0)||\
+                                                                    ((__DisplayMode__) == LCD_DisplayMode_1))
+/**
+  * @}
+  */
+
+
+    /** @defgroup StaticPower
+  * @{
+  */
+
+#define LCD_StaticPower_NormalPower                                 ((uint32_t)0x00000000U) /*!< LCD RAM显示模式0*/
+#define LCD_StaticPower_LowPower                                     LCD_CR0_STATIC           /*!< LCD RAM显示模式1 */
+#define IS_LCD_StaticPower(__StaticPower__)                         (((__StaticPower__) == LCD_StaticPower_NormalPower) || \
+                                                                    ((__StaticPower__) == LCD_StaticPower_LowPower))
+/**
+  * @}
+  */
+
+
+/** @defgroup LCDFrequency
+  * @{
+  */
+
+#define LCD_LCDFrequency_64HZ                                    ((uint32_t)0x00000000U)           /*!< LCD扫描频率选择*/
+#define LCD_LCDFrequency_128HZ                                     LCD_CR0_LCDCLK_0           /*!< LCD扫描频率选择 */
+#define LCD_LCDFrequency_256HZ                                     LCD_CR0_LCDCLK_1           /*!< LCD扫描频率选择 */
+#define LCD_LCDFrequency_512HZ                                     ((LCD_CR0_LCDCLK_0 | LCD_CR0_LCDCLK_1))           /*!< LCD扫描频率选择*/
+#define IS_LCD_LCDFrequency(__LCDFrequency__)                      (((__LCDFrequency__) == LCD_LCDFrequency_64HZ) || \
+                                                                    ((__LCDFrequency__) == LCD_LCDFrequency_128HZ)||\
+                                                                    ((__LCDFrequency__) == LCD_LCDFrequency_256HZ)||\
+                                                                    ((__LCDFrequency__) == LCD_LCDFrequency_512HZ))
+/**
+  * @}
+  */
+
+ /** @defgroup BlinkEN
+  * @{
+  */
+#define LCD_BlinkEN_Disable                                 ((uint32_t)0x00000000U)     /*!<LCD闪屏配置使能*/
+#define LCD_BlinkEN_Enable                                     LCD_CR1_BLINKEN           /*!< LCD闪屏配置使能 */
+#define IS_LCD_BlinkEN(__BlinkEN__)                         (((__BlinkEN__) == LCD_BlinkEN_Disable) || \
+                                                             ((__BlinkEN__) == LCD_BlinkEN_Enable))
+/**
+  * @}
+  */
+#define IS_LCD_BlinkFrequency(__BlinkFrequency__)           ((__BlinkFrequency__)<= ((uint8_t)0x3F)) /*!<LCD闪屏配置*/
+
+ /** @defgroup BiasRes
+  * @{
+  */
+#define LCD_BiasRes_240k                                    ((uint32_t)0x00000000U)     /*!<LCD闪屏配置使能*/
+#define LCD_BiasRes_4M                                       LCD_CR1_RSEL           /*!< LCD闪屏配置使能 */
+#define IS_LCD_BiasRes(__BiasRes__)                         (((__BiasRes__) == LCD_BiasRes_240k) || \
+                                                             ((__BiasRes__) == LCD_BiasRes_4M))
+/**
+  * @}
+  */
+
+  /** @defgroup DriveMod
+  * @{
+  */
+#define LCD_DriveMod_Res240k4M                                    ((uint32_t)0x00000000U)     /*!<LCD闪屏配置使能*/
+#define LCD_DriveMod_Res60k                                       LCD_CR1_MODSEL_0           /*!< LCD闪屏配置使能 */
+#define LCD_DriveMod_FC                                        LCD_CR1_MODSEL_1           /*!< LCD闪屏配置使能 */
+#define IS_LCD_DriveMod(__DriveMod__)                         (((__DriveMod__) == LCD_DriveMod_Res240k4M) || \
+                                                             ((__DriveMod__) == LCD_DriveMod_Res60k)|| \
+                                                             ((__DriveMod__) == LCD_DriveMod_FC))
+/**
+  * @}
+  */
+
+
+ /** @defgroup FastCharge
+  * @{
+  */
+#define LCD_FastCharge_Disable                                 ((uint32_t)0x00000000U)     /*!<LCD闪屏配置使能*/
+#define LCD_FastCharge_Enable                                     LCD_CR1_FCC           /*!< LCD闪屏配置使能 */
+#define IS_LCD_FastCharge(__FastCharge__)                         (((__FastCharge__) == LCD_FastCharge_Disable) || \
+                                                                    ((__FastCharge__) == LCD_FastCharge_Enable))
+/**
+  * @}
+  */
+
+ /** @defgroup LCD_Contrast
+  * @{
+  */
+#define LCD_Contrast_531VDD                                     ((uint32_t)0x00000000U)    /*!<LCD对比度调整*/
+#define LCD_Contrast_562VDD                                       (LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_593VDD                                       (LCD_CR0_CONTRAST_1)
+#define LCD_Contrast_623VDD                                       (LCD_CR0_CONTRAST_1|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_654VDD                                        (LCD_CR0_CONTRAST_2)
+#define LCD_Contrast_686VDD                                        (LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_717VDD                                        (LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_1)
+#define LCD_Contrast_748VDD                                        (LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_1|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_778VDD                                        (LCD_CR0_CONTRAST_3)
+#define LCD_Contrast_810VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_840VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_1)
+#define LCD_Contrast_871VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_1|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_903VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_2)
+#define LCD_Contrast_939VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_0)
+#define LCD_Contrast_969VDD                                        (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_1)
+#define LCD_Contrast_1000VDD                                       (LCD_CR0_CONTRAST_3|LCD_CR0_CONTRAST_2|LCD_CR0_CONTRAST_1|LCD_CR0_CONTRAST_0)
+
+#define IS_LCD_Contrast(__Contrast__)                         (((__Contrast__) == LCD_Contrast_531VDD) || \
+                                                             ((__Contrast__) == LCD_Contrast_562VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_593VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_623VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_654VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_686VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_717VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_748VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_778VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_810VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_840VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_871VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_903VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_939VDD)|| \
+                                                             ((__Contrast__) == LCD_Contrast_969VDD)| \
+                                                             ((__Contrast__) == LCD_Contrast_1000VDD))
+
+
+/**
+  * @}
+  */
+
+#define IS_LCD_PONTime(__PONTime__)                         ((__PONTime__) <= ((uint32_t)0x3F))
+
+/**
+  * @}
+  */
+
+
+void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
+
+void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
+
+HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
+
+HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
+
+HAL_StatusTypeDef HAL_LCD_InResConfig(LCD_HandleTypeDef *hlcd,LCD_InResInitTypeDef* LCD_InResInitStruct);
+
+HAL_StatusTypeDef HAL_LCD_SegComConfig(LCD_HandleTypeDef *hlcd,LCD_SegComInitTypeDef *SegCom);
+
+HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t LCDRAMIndex, uint32_t Data);
+
+HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
+
+HAL_StatusTypeDef HAL_LCD_Start_DMA(LCD_HandleTypeDef *hlcd, uint32_t *pData, uint32_t Length);
+
+HAL_StatusTypeDef HAL_LCD_Stop_DMA(LCD_HandleTypeDef *hlcd);
+
+void HAL_LCD_IRQHandler(LCD_HandleTypeDef *hlcd);
+
+#endif